linux/drivers/parisc/iosapic.c
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   1/*
   2** I/O Sapic Driver - PCI interrupt line support
   3**
   4**      (c) Copyright 1999 Grant Grundler
   5**      (c) Copyright 1999 Hewlett-Packard Company
   6**
   7**      This program is free software; you can redistribute it and/or modify
   8**      it under the terms of the GNU General Public License as published by
   9**      the Free Software Foundation; either version 2 of the License, or
  10**      (at your option) any later version.
  11**
  12** The I/O sapic driver manages the Interrupt Redirection Table which is
  13** the control logic to convert PCI line based interrupts into a Message
  14** Signaled Interrupt (aka Transaction Based Interrupt, TBI).
  15**
  16** Acronyms
  17** --------
  18** HPA  Hard Physical Address (aka MMIO address)
  19** IRQ  Interrupt ReQuest. Implies Line based interrupt.
  20** IRT  Interrupt Routing Table (provided by PAT firmware)
  21** IRdT Interrupt Redirection Table. IRQ line to TXN ADDR/DATA
  22**      table which is implemented in I/O SAPIC.
  23** ISR  Interrupt Service Routine. aka Interrupt handler.
  24** MSI  Message Signaled Interrupt. PCI 2.2 functionality.
  25**      aka Transaction Based Interrupt (or TBI).
  26** PA   Precision Architecture. HP's RISC architecture.
  27** RISC Reduced Instruction Set Computer.
  28**
  29**
  30** What's a Message Signalled Interrupt?
  31** -------------------------------------
  32** MSI is a write transaction which targets a processor and is similar
  33** to a processor write to memory or MMIO. MSIs can be generated by I/O
  34** devices as well as processors and require *architecture* to work.
  35**
  36** PA only supports MSI. So I/O subsystems must either natively generate
  37** MSIs (e.g. GSC or HP-PB) or convert line based interrupts into MSIs
  38** (e.g. PCI and EISA).  IA64 supports MSIs via a "local SAPIC" which
  39** acts on behalf of a processor.
  40**
  41** MSI allows any I/O device to interrupt any processor. This makes
  42** load balancing of the interrupt processing possible on an SMP platform.
  43** Interrupts are also ordered WRT to DMA data.  It's possible on I/O
  44** coherent systems to completely eliminate PIO reads from the interrupt
  45** path. The device and driver must be designed and implemented to
  46** guarantee all DMA has been issued (issues about atomicity here)
  47** before the MSI is issued. I/O status can then safely be read from
  48** DMA'd data by the ISR.
  49**
  50**
  51** PA Firmware
  52** -----------
  53** PA-RISC platforms have two fundamentally different types of firmware.
  54** For PCI devices, "Legacy" PDC initializes the "INTERRUPT_LINE" register
  55** and BARs similar to a traditional PC BIOS.
  56** The newer "PAT" firmware supports PDC calls which return tables.
  57** PAT firmware only initializes the PCI Console and Boot interface.
  58** With these tables, the OS can program all other PCI devices.
  59**
  60** One such PAT PDC call returns the "Interrupt Routing Table" (IRT).
  61** The IRT maps each PCI slot's INTA-D "output" line to an I/O SAPIC
  62** input line.  If the IRT is not available, this driver assumes
  63** INTERRUPT_LINE register has been programmed by firmware. The latter
  64** case also means online addition of PCI cards can NOT be supported
  65** even if HW support is present.
  66**
  67** All platforms with PAT firmware to date (Oct 1999) use one Interrupt
  68** Routing Table for the entire platform.
  69**
  70** Where's the iosapic?
  71** --------------------
  72** I/O sapic is part of the "Core Electronics Complex". And on HP platforms
  73** it's integrated as part of the PCI bus adapter, "lba".  So no bus walk
  74** will discover I/O Sapic. I/O Sapic driver learns about each device
  75** when lba driver advertises the presence of the I/O sapic by calling
  76** iosapic_register().
  77**
  78**
  79** IRQ handling notes
  80** ------------------
  81** The IO-SAPIC can indicate to the CPU which interrupt was asserted.
  82** So, unlike the GSC-ASIC and Dino, we allocate one CPU interrupt per
  83** IO-SAPIC interrupt and call the device driver's handler directly.
  84** The IO-SAPIC driver hijacks the CPU interrupt handler so it can
  85** issue the End Of Interrupt command to the IO-SAPIC.
  86**
  87** Overview of exported iosapic functions
  88** --------------------------------------
  89** (caveat: code isn't finished yet - this is just the plan)
  90**
  91** iosapic_init:
  92**   o initialize globals (lock, etc)
  93**   o try to read IRT. Presence of IRT determines if this is
  94**     a PAT platform or not.
  95**
  96** iosapic_register():
  97**   o create iosapic_info instance data structure
  98**   o allocate vector_info array for this iosapic
  99**   o initialize vector_info - read corresponding IRdT?
 100**
 101** iosapic_xlate_pin: (only called by fixup_irq for PAT platform)
 102**   o intr_pin = read cfg (INTERRUPT_PIN);
 103**   o if (device under PCI-PCI bridge)
 104**               translate slot/pin
 105**
 106** iosapic_fixup_irq:
 107**   o if PAT platform (IRT present)
 108**         intr_pin = iosapic_xlate_pin(isi,pcidev):
 109**         intr_line = find IRT entry(isi, PCI_SLOT(pcidev), intr_pin)
 110**         save IRT entry into vector_info later
 111**         write cfg INTERRUPT_LINE (with intr_line)?
 112**     else
 113**         intr_line = pcidev->irq
 114**         IRT pointer = NULL
 115**     endif
 116**   o locate vector_info (needs: isi, intr_line)
 117**   o allocate processor "irq" and get txn_addr/data
 118**   o request_irq(processor_irq,  iosapic_interrupt, vector_info,...)
 119**
 120** iosapic_enable_irq:
 121**   o clear any pending IRQ on that line
 122**   o enable IRdT - call enable_irq(vector[line]->processor_irq)
 123**   o write EOI in case line is already asserted.
 124**
 125** iosapic_disable_irq:
 126**   o disable IRdT - call disable_irq(vector[line]->processor_irq)
 127*/
 128
 129
 130/* FIXME: determine which include files are really needed */
 131#include <linux/types.h>
 132#include <linux/kernel.h>
 133#include <linux/spinlock.h>
 134#include <linux/pci.h>
 135#include <linux/init.h>
 136#include <linux/slab.h>
 137#include <linux/interrupt.h>
 138
 139#include <asm/byteorder.h>      /* get in-line asm for swab */
 140#include <asm/pdc.h>
 141#include <asm/pdcpat.h>
 142#include <asm/page.h>
 143#include <asm/system.h>
 144#include <asm/io.h>             /* read/write functions */
 145#ifdef CONFIG_SUPERIO
 146#include <asm/superio.h>
 147#endif
 148
 149#include <asm/ropes.h>
 150#include "./iosapic_private.h"
 151
 152#define MODULE_NAME "iosapic"
 153
 154/* "local" compile flags */
 155#undef PCI_BRIDGE_FUNCS
 156#undef DEBUG_IOSAPIC
 157#undef DEBUG_IOSAPIC_IRT
 158
 159
 160#ifdef DEBUG_IOSAPIC
 161#define DBG(x...) printk(x)
 162#else /* DEBUG_IOSAPIC */
 163#define DBG(x...)
 164#endif /* DEBUG_IOSAPIC */
 165
 166#ifdef DEBUG_IOSAPIC_IRT
 167#define DBG_IRT(x...) printk(x)
 168#else
 169#define DBG_IRT(x...)
 170#endif
 171
 172#ifdef CONFIG_64BIT
 173#define COMPARE_IRTE_ADDR(irte, hpa)    ((irte)->dest_iosapic_addr == (hpa))
 174#else
 175#define COMPARE_IRTE_ADDR(irte, hpa)    \
 176                ((irte)->dest_iosapic_addr == ((hpa) | 0xffffffff00000000ULL))
 177#endif
 178
 179#define IOSAPIC_REG_SELECT              0x00
 180#define IOSAPIC_REG_WINDOW              0x10
 181#define IOSAPIC_REG_EOI                 0x40
 182
 183#define IOSAPIC_REG_VERSION             0x1
 184
 185#define IOSAPIC_IRDT_ENTRY(idx)         (0x10+(idx)*2)
 186#define IOSAPIC_IRDT_ENTRY_HI(idx)      (0x11+(idx)*2)
 187
 188static inline unsigned int iosapic_read(void __iomem *iosapic, unsigned int reg)
 189{
 190        writel(reg, iosapic + IOSAPIC_REG_SELECT);
 191        return readl(iosapic + IOSAPIC_REG_WINDOW);
 192}
 193
 194static inline void iosapic_write(void __iomem *iosapic, unsigned int reg, u32 val)
 195{
 196        writel(reg, iosapic + IOSAPIC_REG_SELECT);
 197        writel(val, iosapic + IOSAPIC_REG_WINDOW);
 198}
 199
 200#define IOSAPIC_VERSION_MASK    0x000000ff
 201#define IOSAPIC_VERSION(ver)    ((int) (ver & IOSAPIC_VERSION_MASK))
 202
 203#define IOSAPIC_MAX_ENTRY_MASK          0x00ff0000
 204#define IOSAPIC_MAX_ENTRY_SHIFT         0x10
 205#define IOSAPIC_IRDT_MAX_ENTRY(ver)     \
 206        (int) (((ver) & IOSAPIC_MAX_ENTRY_MASK) >> IOSAPIC_MAX_ENTRY_SHIFT)
 207
 208/* bits in the "low" I/O Sapic IRdT entry */
 209#define IOSAPIC_IRDT_ENABLE       0x10000
 210#define IOSAPIC_IRDT_PO_LOW       0x02000
 211#define IOSAPIC_IRDT_LEVEL_TRIG   0x08000
 212#define IOSAPIC_IRDT_MODE_LPRI    0x00100
 213
 214/* bits in the "high" I/O Sapic IRdT entry */
 215#define IOSAPIC_IRDT_ID_EID_SHIFT              0x10
 216
 217
 218static DEFINE_SPINLOCK(iosapic_lock);
 219
 220static inline void iosapic_eoi(void __iomem *addr, unsigned int data)
 221{
 222        __raw_writel(data, addr);
 223}
 224
 225/*
 226** REVISIT: future platforms may have more than one IRT.
 227** If so, the following three fields form a structure which
 228** then be linked into a list. Names are chosen to make searching
 229** for them easy - not necessarily accurate (eg "cell").
 230**
 231** Alternative: iosapic_info could point to the IRT it's in.
 232** iosapic_register() could search a list of IRT's.
 233*/
 234static struct irt_entry *irt_cell;
 235static size_t irt_num_entry;
 236
 237static struct irt_entry *iosapic_alloc_irt(int num_entries)
 238{
 239        unsigned long a;
 240
 241        /* The IRT needs to be 8-byte aligned for the PDC call. 
 242         * Normally kmalloc would guarantee larger alignment, but
 243         * if CONFIG_DEBUG_SLAB is enabled, then we can get only
 244         * 4-byte alignment on 32-bit kernels
 245         */
 246        a = (unsigned long)kmalloc(sizeof(struct irt_entry) * num_entries + 8, GFP_KERNEL);
 247        a = (a + 7UL) & ~7UL;
 248        return (struct irt_entry *)a;
 249}
 250
 251/**
 252 * iosapic_load_irt - Fill in the interrupt routing table
 253 * @cell_num: The cell number of the CPU we're currently executing on
 254 * @irt: The address to place the new IRT at
 255 * @return The number of entries found
 256 *
 257 * The "Get PCI INT Routing Table Size" option returns the number of 
 258 * entries in the PCI interrupt routing table for the cell specified 
 259 * in the cell_number argument.  The cell number must be for a cell 
 260 * within the caller's protection domain.
 261 *
 262 * The "Get PCI INT Routing Table" option returns, for the cell 
 263 * specified in the cell_number argument, the PCI interrupt routing 
 264 * table in the caller allocated memory pointed to by mem_addr.
 265 * We assume the IRT only contains entries for I/O SAPIC and
 266 * calculate the size based on the size of I/O sapic entries.
 267 *
 268 * The PCI interrupt routing table entry format is derived from the
 269 * IA64 SAL Specification 2.4.   The PCI interrupt routing table defines
 270 * the routing of PCI interrupt signals between the PCI device output
 271 * "pins" and the IO SAPICs' input "lines" (including core I/O PCI
 272 * devices).  This table does NOT include information for devices/slots
 273 * behind PCI to PCI bridges. See PCI to PCI Bridge Architecture Spec.
 274 * for the architected method of routing of IRQ's behind PPB's.
 275 */
 276
 277
 278static int __init
 279iosapic_load_irt(unsigned long cell_num, struct irt_entry **irt)
 280{
 281        long status;              /* PDC return value status */
 282        struct irt_entry *table;  /* start of interrupt routing tbl */
 283        unsigned long num_entries = 0UL;
 284
 285        BUG_ON(!irt);
 286
 287        if (is_pdc_pat()) {
 288                /* Use pat pdc routine to get interrupt routing table size */
 289                DBG("calling get_irt_size (cell %ld)\n", cell_num);
 290                status = pdc_pat_get_irt_size(&num_entries, cell_num);
 291                DBG("get_irt_size: %ld\n", status);
 292
 293                BUG_ON(status != PDC_OK);
 294                BUG_ON(num_entries == 0);
 295
 296                /*
 297                ** allocate memory for interrupt routing table
 298                ** This interface isn't really right. We are assuming
 299                ** the contents of the table are exclusively
 300                ** for I/O sapic devices.
 301                */
 302                table = iosapic_alloc_irt(num_entries);
 303                if (table == NULL) {
 304                        printk(KERN_WARNING MODULE_NAME ": read_irt : can "
 305                                        "not alloc mem for IRT\n");
 306                        return 0;
 307                }
 308
 309                /* get PCI INT routing table */
 310                status = pdc_pat_get_irt(table, cell_num);
 311                DBG("pdc_pat_get_irt: %ld\n", status);
 312                WARN_ON(status != PDC_OK);
 313        } else {
 314                /*
 315                ** C3000/J5000 (and similar) platforms with Sprockets PDC
 316                ** will return exactly one IRT for all iosapics.
 317                ** So if we have one, don't need to get it again.
 318                */
 319                if (irt_cell)
 320                        return 0;
 321
 322                /* Should be using the Elroy's HPA, but it's ignored anyway */
 323                status = pdc_pci_irt_size(&num_entries, 0);
 324                DBG("pdc_pci_irt_size: %ld\n", status);
 325
 326                if (status != PDC_OK) {
 327                        /* Not a "legacy" system with I/O SAPIC either */
 328                        return 0;
 329                }
 330
 331                BUG_ON(num_entries == 0);
 332
 333                table = iosapic_alloc_irt(num_entries);
 334                if (!table) {
 335                        printk(KERN_WARNING MODULE_NAME ": read_irt : can "
 336                                        "not alloc mem for IRT\n");
 337                        return 0;
 338                }
 339
 340                /* HPA ignored by this call too. */
 341                status = pdc_pci_irt(num_entries, 0, table);
 342                BUG_ON(status != PDC_OK);
 343        }
 344
 345        /* return interrupt table address */
 346        *irt = table;
 347
 348#ifdef DEBUG_IOSAPIC_IRT
 349{
 350        struct irt_entry *p = table;
 351        int i;
 352
 353        printk(MODULE_NAME " Interrupt Routing Table (cell %ld)\n", cell_num);
 354        printk(MODULE_NAME " start = 0x%p num_entries %ld entry_size %d\n",
 355                table,
 356                num_entries,
 357                (int) sizeof(struct irt_entry));
 358
 359        for (i = 0 ; i < num_entries ; i++, p++) {
 360                printk(MODULE_NAME " %02x %02x %02x %02x %02x %02x %02x %02x %08x%08x\n",
 361                p->entry_type, p->entry_length, p->interrupt_type,
 362                p->polarity_trigger, p->src_bus_irq_devno, p->src_bus_id,
 363                p->src_seg_id, p->dest_iosapic_intin,
 364                ((u32 *) p)[2],
 365                ((u32 *) p)[3]
 366                );
 367        }
 368}
 369#endif /* DEBUG_IOSAPIC_IRT */
 370
 371        return num_entries;
 372}
 373
 374
 375
 376void __init iosapic_init(void)
 377{
 378        unsigned long cell = 0;
 379
 380        DBG("iosapic_init()\n");
 381
 382#ifdef __LP64__
 383        if (is_pdc_pat()) {
 384                int status;
 385                struct pdc_pat_cell_num cell_info;
 386
 387                status = pdc_pat_cell_get_number(&cell_info);
 388                if (status == PDC_OK) {
 389                        cell = cell_info.cell_num;
 390                }
 391        }
 392#endif
 393
 394        /* get interrupt routing table for this cell */
 395        irt_num_entry = iosapic_load_irt(cell, &irt_cell);
 396        if (irt_num_entry == 0)
 397                irt_cell = NULL;        /* old PDC w/o iosapic */
 398}
 399
 400
 401/*
 402** Return the IRT entry in case we need to look something else up.
 403*/
 404static struct irt_entry *
 405irt_find_irqline(struct iosapic_info *isi, u8 slot, u8 intr_pin)
 406{
 407        struct irt_entry *i = irt_cell;
 408        int cnt;        /* track how many entries we've looked at */
 409        u8 irq_devno = (slot << IRT_DEV_SHIFT) | (intr_pin-1);
 410
 411        DBG_IRT("irt_find_irqline() SLOT %d pin %d\n", slot, intr_pin);
 412
 413        for (cnt=0; cnt < irt_num_entry; cnt++, i++) {
 414
 415                /*
 416                ** Validate: entry_type, entry_length, interrupt_type
 417                **
 418                ** Difference between validate vs compare is the former
 419                ** should print debug info and is not expected to "fail"
 420                ** on current platforms.
 421                */
 422                if (i->entry_type != IRT_IOSAPIC_TYPE) {
 423                        DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d type %d\n", i, cnt, i->entry_type);
 424                        continue;
 425                }
 426                
 427                if (i->entry_length != IRT_IOSAPIC_LENGTH) {
 428                        DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry %d  length %d\n", i, cnt, i->entry_length);
 429                        continue;
 430                }
 431
 432                if (i->interrupt_type != IRT_VECTORED_INTR) {
 433                        DBG_IRT(KERN_WARNING MODULE_NAME ":find_irqline(0x%p): skipping entry  %d interrupt_type %d\n", i, cnt, i->interrupt_type);
 434                        continue;
 435                }
 436
 437                if (!COMPARE_IRTE_ADDR(i, isi->isi_hpa))
 438                        continue;
 439
 440                if ((i->src_bus_irq_devno & IRT_IRQ_DEVNO_MASK) != irq_devno)
 441                        continue;
 442
 443                /*
 444                ** Ignore: src_bus_id and rc_seg_id correlate with
 445                **         iosapic_info->isi_hpa on HP platforms.
 446                **         If needed, pass in "PFA" (aka config space addr)
 447                **         instead of slot.
 448                */
 449
 450                /* Found it! */
 451                return i;
 452        }
 453
 454        printk(KERN_WARNING MODULE_NAME ": 0x%lx : no IRT entry for slot %d, pin %d\n",
 455                        isi->isi_hpa, slot, intr_pin);
 456        return NULL;
 457}
 458
 459
 460/*
 461** xlate_pin() supports the skewing of IRQ lines done by subsidiary bridges.
 462** Legacy PDC already does this translation for us and stores it in INTR_LINE.
 463**
 464** PAT PDC needs to basically do what legacy PDC does:
 465** o read PIN
 466** o adjust PIN in case device is "behind" a PPB
 467**     (eg 4-port 100BT and SCSI/LAN "Combo Card")
 468** o convert slot/pin to I/O SAPIC input line.
 469**
 470** HP platforms only support:
 471** o one level of skewing for any number of PPBs
 472** o only support PCI-PCI Bridges.
 473*/
 474static struct irt_entry *
 475iosapic_xlate_pin(struct iosapic_info *isi, struct pci_dev *pcidev)
 476{
 477        u8 intr_pin, intr_slot;
 478
 479        pci_read_config_byte(pcidev, PCI_INTERRUPT_PIN, &intr_pin);
 480
 481        DBG_IRT("iosapic_xlate_pin(%s) SLOT %d pin %d\n",
 482                pcidev->slot_name, PCI_SLOT(pcidev->devfn), intr_pin);
 483
 484        if (intr_pin == 0) {
 485                /* The device does NOT support/use IRQ lines.  */
 486                return NULL;
 487        }
 488
 489        /* Check if pcidev behind a PPB */
 490        if (pcidev->bus->parent) {
 491                /* Convert pcidev INTR_PIN into something we
 492                ** can lookup in the IRT.
 493                */
 494#ifdef PCI_BRIDGE_FUNCS
 495                /*
 496                ** Proposal #1:
 497                **
 498                ** call implementation specific translation function
 499                ** This is architecturally "cleaner". HP-UX doesn't
 500                ** support other secondary bus types (eg. E/ISA) directly.
 501                ** May be needed for other processor (eg IA64) architectures
 502                ** or by some ambitous soul who wants to watch TV.
 503                */
 504                if (pci_bridge_funcs->xlate_intr_line) {
 505                        intr_pin = pci_bridge_funcs->xlate_intr_line(pcidev);
 506                }
 507#else   /* PCI_BRIDGE_FUNCS */
 508                struct pci_bus *p = pcidev->bus;
 509                /*
 510                ** Proposal #2:
 511                ** The "pin" is skewed ((pin + dev - 1) % 4).
 512                **
 513                ** This isn't very clean since I/O SAPIC must assume:
 514                **   - all platforms only have PCI busses.
 515                **   - only PCI-PCI bridge (eg not PCI-EISA, PCI-PCMCIA)
 516                **   - IRQ routing is only skewed once regardless of
 517                **     the number of PPB's between iosapic and device.
 518                **     (Bit3 expansion chassis follows this rule)
 519                **
 520                ** Advantage is it's really easy to implement.
 521                */
 522                intr_pin = pci_swizzle_interrupt_pin(pcidev, intr_pin);
 523#endif /* PCI_BRIDGE_FUNCS */
 524
 525                /*
 526                 * Locate the host slot of the PPB.
 527                 */
 528                while (p->parent->parent)
 529                        p = p->parent;
 530
 531                intr_slot = PCI_SLOT(p->self->devfn);
 532        } else {
 533                intr_slot = PCI_SLOT(pcidev->devfn);
 534        }
 535        DBG_IRT("iosapic_xlate_pin:  bus %d slot %d pin %d\n",
 536                                pcidev->bus->secondary, intr_slot, intr_pin);
 537
 538        return irt_find_irqline(isi, intr_slot, intr_pin);
 539}
 540
 541static void iosapic_rd_irt_entry(struct vector_info *vi , u32 *dp0, u32 *dp1)
 542{
 543        struct iosapic_info *isp = vi->iosapic;
 544        u8 idx = vi->irqline;
 545
 546        *dp0 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY(idx));
 547        *dp1 = iosapic_read(isp->addr, IOSAPIC_IRDT_ENTRY_HI(idx));
 548}
 549
 550
 551static void iosapic_wr_irt_entry(struct vector_info *vi, u32 dp0, u32 dp1)
 552{
 553        struct iosapic_info *isp = vi->iosapic;
 554
 555        DBG_IRT("iosapic_wr_irt_entry(): irq %d hpa %lx 0x%x 0x%x\n",
 556                vi->irqline, isp->isi_hpa, dp0, dp1);
 557
 558        iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY(vi->irqline), dp0);
 559
 560        /* Read the window register to flush the writes down to HW  */
 561        dp0 = readl(isp->addr+IOSAPIC_REG_WINDOW);
 562
 563        iosapic_write(isp->addr, IOSAPIC_IRDT_ENTRY_HI(vi->irqline), dp1);
 564
 565        /* Read the window register to flush the writes down to HW  */
 566        dp1 = readl(isp->addr+IOSAPIC_REG_WINDOW);
 567}
 568
 569/*
 570** set_irt prepares the data (dp0, dp1) according to the vector_info
 571** and target cpu (id_eid).  dp0/dp1 are then used to program I/O SAPIC
 572** IRdT for the given "vector" (aka IRQ line).
 573*/
 574static void
 575iosapic_set_irt_data( struct vector_info *vi, u32 *dp0, u32 *dp1)
 576{
 577        u32 mode = 0;
 578        struct irt_entry *p = vi->irte;
 579
 580        if ((p->polarity_trigger & IRT_PO_MASK) == IRT_ACTIVE_LO)
 581                mode |= IOSAPIC_IRDT_PO_LOW;
 582
 583        if (((p->polarity_trigger >> IRT_EL_SHIFT) & IRT_EL_MASK) == IRT_LEVEL_TRIG)
 584                mode |= IOSAPIC_IRDT_LEVEL_TRIG;
 585
 586        /*
 587        ** IA64 REVISIT
 588        ** PA doesn't support EXTINT or LPRIO bits.
 589        */
 590
 591        *dp0 = mode | (u32) vi->txn_data;
 592
 593        /*
 594        ** Extracting id_eid isn't a real clean way of getting it.
 595        ** But the encoding is the same for both PA and IA64 platforms.
 596        */
 597        if (is_pdc_pat()) {
 598                /*
 599                ** PAT PDC just hands it to us "right".
 600                ** txn_addr comes from cpu_data[x].txn_addr.
 601                */
 602                *dp1 = (u32) (vi->txn_addr);
 603        } else {
 604                /* 
 605                ** eg if base_addr == 0xfffa0000),
 606                **    we want to get 0xa0ff0000.
 607                **
 608                ** eid  0x0ff00000 -> 0x00ff0000
 609                ** id   0x000ff000 -> 0xff000000
 610                */
 611                *dp1 = (((u32)vi->txn_addr & 0x0ff00000) >> 4) |
 612                        (((u32)vi->txn_addr & 0x000ff000) << 12);
 613        }
 614        DBG_IRT("iosapic_set_irt_data(): 0x%x 0x%x\n", *dp0, *dp1);
 615}
 616
 617
 618static struct vector_info *iosapic_get_vector(unsigned int irq)
 619{
 620        struct irq_desc *desc = irq_to_desc(irq);
 621
 622        return desc->chip_data;
 623}
 624
 625static void iosapic_disable_irq(unsigned int irq)
 626{
 627        unsigned long flags;
 628        struct vector_info *vi = iosapic_get_vector(irq);
 629        u32 d0, d1;
 630
 631        spin_lock_irqsave(&iosapic_lock, flags);
 632        iosapic_rd_irt_entry(vi, &d0, &d1);
 633        d0 |= IOSAPIC_IRDT_ENABLE;
 634        iosapic_wr_irt_entry(vi, d0, d1);
 635        spin_unlock_irqrestore(&iosapic_lock, flags);
 636}
 637
 638static void iosapic_enable_irq(unsigned int irq)
 639{
 640        struct vector_info *vi = iosapic_get_vector(irq);
 641        u32 d0, d1;
 642
 643        /* data is initialized by fixup_irq */
 644        WARN_ON(vi->txn_irq  == 0);
 645
 646        iosapic_set_irt_data(vi, &d0, &d1);
 647        iosapic_wr_irt_entry(vi, d0, d1);
 648
 649#ifdef DEBUG_IOSAPIC_IRT
 650{
 651        u32 *t = (u32 *) ((ulong) vi->eoi_addr & ~0xffUL);
 652        printk("iosapic_enable_irq(): regs %p", vi->eoi_addr);
 653        for ( ; t < vi->eoi_addr; t++)
 654                printk(" %x", readl(t));
 655        printk("\n");
 656}
 657
 658printk("iosapic_enable_irq(): sel ");
 659{
 660        struct iosapic_info *isp = vi->iosapic;
 661
 662        for (d0=0x10; d0<0x1e; d0++) {
 663                d1 = iosapic_read(isp->addr, d0);
 664                printk(" %x", d1);
 665        }
 666}
 667printk("\n");
 668#endif
 669
 670        /*
 671         * Issuing I/O SAPIC an EOI causes an interrupt IFF IRQ line is
 672         * asserted.  IRQ generally should not be asserted when a driver
 673         * enables their IRQ. It can lead to "interesting" race conditions
 674         * in the driver initialization sequence.
 675         */
 676        DBG(KERN_DEBUG "enable_irq(%d): eoi(%p, 0x%x)\n", irq,
 677                        vi->eoi_addr, vi->eoi_data);
 678        iosapic_eoi(vi->eoi_addr, vi->eoi_data);
 679}
 680
 681/*
 682 * PARISC only supports PCI devices below I/O SAPIC.
 683 * PCI only supports level triggered in order to share IRQ lines.
 684 * ergo I/O SAPIC must always issue EOI on parisc.
 685 *
 686 * i386/ia64 support ISA devices and have to deal with
 687 * edge-triggered interrupts too.
 688 */
 689static void iosapic_end_irq(unsigned int irq)
 690{
 691        struct vector_info *vi = iosapic_get_vector(irq);
 692        DBG(KERN_DEBUG "end_irq(%d): eoi(%p, 0x%x)\n", irq,
 693                        vi->eoi_addr, vi->eoi_data);
 694        iosapic_eoi(vi->eoi_addr, vi->eoi_data);
 695        cpu_end_irq(irq);
 696}
 697
 698static unsigned int iosapic_startup_irq(unsigned int irq)
 699{
 700        iosapic_enable_irq(irq);
 701        return 0;
 702}
 703
 704#ifdef CONFIG_SMP
 705static int iosapic_set_affinity_irq(unsigned int irq,
 706                                     const struct cpumask *dest)
 707{
 708        struct vector_info *vi = iosapic_get_vector(irq);
 709        u32 d0, d1, dummy_d0;
 710        unsigned long flags;
 711        int dest_cpu;
 712
 713        dest_cpu = cpu_check_affinity(irq, dest);
 714        if (dest_cpu < 0)
 715                return -1;
 716
 717        cpumask_copy(irq_desc[irq].affinity, cpumask_of(dest_cpu));
 718        vi->txn_addr = txn_affinity_addr(irq, dest_cpu);
 719
 720        spin_lock_irqsave(&iosapic_lock, flags);
 721        /* d1 contains the destination CPU, so only want to set that
 722         * entry */
 723        iosapic_rd_irt_entry(vi, &d0, &d1);
 724        iosapic_set_irt_data(vi, &dummy_d0, &d1);
 725        iosapic_wr_irt_entry(vi, d0, d1);
 726        spin_unlock_irqrestore(&iosapic_lock, flags);
 727
 728        return 0;
 729}
 730#endif
 731
 732static struct irq_chip iosapic_interrupt_type = {
 733        .name    =      "IO-SAPIC-level",
 734        .startup =      iosapic_startup_irq,
 735        .shutdown =     iosapic_disable_irq,
 736        .enable =       iosapic_enable_irq,
 737        .disable =      iosapic_disable_irq,
 738        .ack =          cpu_ack_irq,
 739        .end =          iosapic_end_irq,
 740#ifdef CONFIG_SMP
 741        .set_affinity = iosapic_set_affinity_irq,
 742#endif
 743};
 744
 745int iosapic_fixup_irq(void *isi_obj, struct pci_dev *pcidev)
 746{
 747        struct iosapic_info *isi = isi_obj;
 748        struct irt_entry *irte = NULL;  /* only used if PAT PDC */
 749        struct vector_info *vi;
 750        int isi_line;   /* line used by device */
 751
 752        if (!isi) {
 753                printk(KERN_WARNING MODULE_NAME ": hpa not registered for %s\n",
 754                        pci_name(pcidev));
 755                return -1;
 756        }
 757
 758#ifdef CONFIG_SUPERIO
 759        /*
 760         * HACK ALERT! (non-compliant PCI device support)
 761         *
 762         * All SuckyIO interrupts are routed through the PIC's on function 1.
 763         * But SuckyIO OHCI USB controller gets an IRT entry anyway because
 764         * it advertises INT D for INT_PIN.  Use that IRT entry to get the
 765         * SuckyIO interrupt routing for PICs on function 1 (*BLEECCHH*).
 766         */
 767        if (is_superio_device(pcidev)) {
 768                /* We must call superio_fixup_irq() to register the pdev */
 769                pcidev->irq = superio_fixup_irq(pcidev);
 770
 771                /* Don't return if need to program the IOSAPIC's IRT... */
 772                if (PCI_FUNC(pcidev->devfn) != SUPERIO_USB_FN)
 773                        return pcidev->irq;
 774        }
 775#endif /* CONFIG_SUPERIO */
 776
 777        /* lookup IRT entry for isi/slot/pin set */
 778        irte = iosapic_xlate_pin(isi, pcidev);
 779        if (!irte) {
 780                printk("iosapic: no IRTE for %s (IRQ not connected?)\n",
 781                                pci_name(pcidev));
 782                return -1;
 783        }
 784        DBG_IRT("iosapic_fixup_irq(): irte %p %x %x %x %x %x %x %x %x\n",
 785                irte,
 786                irte->entry_type,
 787                irte->entry_length,
 788                irte->polarity_trigger,
 789                irte->src_bus_irq_devno,
 790                irte->src_bus_id,
 791                irte->src_seg_id,
 792                irte->dest_iosapic_intin,
 793                (u32) irte->dest_iosapic_addr);
 794        isi_line = irte->dest_iosapic_intin;
 795
 796        /* get vector info for this input line */
 797        vi = isi->isi_vector + isi_line;
 798        DBG_IRT("iosapic_fixup_irq:  line %d vi 0x%p\n", isi_line, vi);
 799
 800        /* If this IRQ line has already been setup, skip it */
 801        if (vi->irte)
 802                goto out;
 803
 804        vi->irte = irte;
 805
 806        /*
 807         * Allocate processor IRQ
 808         *
 809         * XXX/FIXME The txn_alloc_irq() code and related code should be
 810         * moved to enable_irq(). That way we only allocate processor IRQ
 811         * bits for devices that actually have drivers claiming them.
 812         * Right now we assign an IRQ to every PCI device present,
 813         * regardless of whether it's used or not.
 814         */
 815        vi->txn_irq = txn_alloc_irq(8);
 816
 817        if (vi->txn_irq < 0)
 818                panic("I/O sapic: couldn't get TXN IRQ\n");
 819
 820        /* enable_irq() will use txn_* to program IRdT */
 821        vi->txn_addr = txn_alloc_addr(vi->txn_irq);
 822        vi->txn_data = txn_alloc_data(vi->txn_irq);
 823
 824        vi->eoi_addr = isi->addr + IOSAPIC_REG_EOI;
 825        vi->eoi_data = cpu_to_le32(vi->txn_data);
 826
 827        cpu_claim_irq(vi->txn_irq, &iosapic_interrupt_type, vi);
 828
 829 out:
 830        pcidev->irq = vi->txn_irq;
 831
 832        DBG_IRT("iosapic_fixup_irq() %d:%d %x %x line %d irq %d\n",
 833                PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn),
 834                pcidev->vendor, pcidev->device, isi_line, pcidev->irq);
 835
 836        return pcidev->irq;
 837}
 838
 839
 840/*
 841** squirrel away the I/O Sapic Version
 842*/
 843static unsigned int
 844iosapic_rd_version(struct iosapic_info *isi)
 845{
 846        return iosapic_read(isi->addr, IOSAPIC_REG_VERSION);
 847}
 848
 849
 850/*
 851** iosapic_register() is called by "drivers" with an integrated I/O SAPIC.
 852** Caller must be certain they have an I/O SAPIC and know its MMIO address.
 853**
 854**      o allocate iosapic_info and add it to the list
 855**      o read iosapic version and squirrel that away
 856**      o read size of IRdT.
 857**      o allocate and initialize isi_vector[]
 858**      o allocate irq region
 859*/
 860void *iosapic_register(unsigned long hpa)
 861{
 862        struct iosapic_info *isi = NULL;
 863        struct irt_entry *irte = irt_cell;
 864        struct vector_info *vip;
 865        int cnt;        /* track how many entries we've looked at */
 866
 867        /*
 868         * Astro based platforms can only support PCI OLARD if they implement
 869         * PAT PDC.  Legacy PDC omits LBAs with no PCI devices from the IRT.
 870         * Search the IRT and ignore iosapic's which aren't in the IRT.
 871         */
 872        for (cnt=0; cnt < irt_num_entry; cnt++, irte++) {
 873                WARN_ON(IRT_IOSAPIC_TYPE != irte->entry_type);
 874                if (COMPARE_IRTE_ADDR(irte, hpa))
 875                        break;
 876        }
 877
 878        if (cnt >= irt_num_entry) {
 879                DBG("iosapic_register() ignoring 0x%lx (NOT FOUND)\n", hpa);
 880                return NULL;
 881        }
 882
 883        isi = kzalloc(sizeof(struct iosapic_info), GFP_KERNEL);
 884        if (!isi) {
 885                BUG();
 886                return NULL;
 887        }
 888
 889        isi->addr = ioremap_nocache(hpa, 4096);
 890        isi->isi_hpa = hpa;
 891        isi->isi_version = iosapic_rd_version(isi);
 892        isi->isi_num_vectors = IOSAPIC_IRDT_MAX_ENTRY(isi->isi_version) + 1;
 893
 894        vip = isi->isi_vector = (struct vector_info *)
 895                kzalloc(sizeof(struct vector_info) * isi->isi_num_vectors, GFP_KERNEL);
 896        if (vip == NULL) {
 897                kfree(isi);
 898                return NULL;
 899        }
 900
 901        for (cnt=0; cnt < isi->isi_num_vectors; cnt++, vip++) {
 902                vip->irqline = (unsigned char) cnt;
 903                vip->iosapic = isi;
 904        }
 905        return isi;
 906}
 907
 908
 909#ifdef DEBUG_IOSAPIC
 910
 911static void
 912iosapic_prt_irt(void *irt, long num_entry)
 913{
 914        unsigned int i, *irp = (unsigned int *) irt;
 915
 916
 917        printk(KERN_DEBUG MODULE_NAME ": Interrupt Routing Table (%lx entries)\n", num_entry);
 918
 919        for (i=0; i<num_entry; i++, irp += 4) {
 920                printk(KERN_DEBUG "%p : %2d %.8x %.8x %.8x %.8x\n",
 921                                        irp, i, irp[0], irp[1], irp[2], irp[3]);
 922        }
 923}
 924
 925
 926static void
 927iosapic_prt_vi(struct vector_info *vi)
 928{
 929        printk(KERN_DEBUG MODULE_NAME ": vector_info[%d] is at %p\n", vi->irqline, vi);
 930        printk(KERN_DEBUG "\t\tstatus:   %.4x\n", vi->status);
 931        printk(KERN_DEBUG "\t\ttxn_irq:  %d\n",  vi->txn_irq);
 932        printk(KERN_DEBUG "\t\ttxn_addr: %lx\n", vi->txn_addr);
 933        printk(KERN_DEBUG "\t\ttxn_data: %lx\n", vi->txn_data);
 934        printk(KERN_DEBUG "\t\teoi_addr: %p\n",  vi->eoi_addr);
 935        printk(KERN_DEBUG "\t\teoi_data: %x\n",  vi->eoi_data);
 936}
 937
 938
 939static void
 940iosapic_prt_isi(struct iosapic_info *isi)
 941{
 942        printk(KERN_DEBUG MODULE_NAME ": io_sapic_info at %p\n", isi);
 943        printk(KERN_DEBUG "\t\tisi_hpa:       %lx\n", isi->isi_hpa);
 944        printk(KERN_DEBUG "\t\tisi_status:    %x\n", isi->isi_status);
 945        printk(KERN_DEBUG "\t\tisi_version:   %x\n", isi->isi_version);
 946        printk(KERN_DEBUG "\t\tisi_vector:    %p\n", isi->isi_vector);
 947}
 948#endif /* DEBUG_IOSAPIC */
 949