linux/drivers/media/video/cx231xx/cx231xx-avcore.c
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   1/*
   2   cx231xx_avcore.c - driver for Conexant Cx23100/101/102
   3                      USB video capture devices
   4
   5   Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
   6
   7   This program contains the specific code to control the avdecoder chip and
   8   other related usb control functions for cx231xx based chipset.
   9
  10   This program is free software; you can redistribute it and/or modify
  11   it under the terms of the GNU General Public License as published by
  12   the Free Software Foundation; either version 2 of the License, or
  13   (at your option) any later version.
  14
  15   This program is distributed in the hope that it will be useful,
  16   but WITHOUT ANY WARRANTY; without even the implied warranty of
  17   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18   GNU General Public License for more details.
  19
  20   You should have received a copy of the GNU General Public License
  21   along with this program; if not, write to the Free Software
  22   Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23 */
  24
  25#include <linux/init.h>
  26#include <linux/list.h>
  27#include <linux/module.h>
  28#include <linux/kernel.h>
  29#include <linux/bitmap.h>
  30#include <linux/usb.h>
  31#include <linux/i2c.h>
  32#include <linux/mm.h>
  33#include <linux/mutex.h>
  34
  35#include <media/v4l2-common.h>
  36#include <media/v4l2-ioctl.h>
  37#include <media/v4l2-chip-ident.h>
  38
  39#include "cx231xx.h"
  40
  41/******************************************************************************
  42                        -: BLOCK ARRANGEMENT :-
  43        I2S block ----------------------|
  44        [I2S audio]                     |
  45                                        |
  46        Analog Front End --> Direct IF -|-> Cx25840 --> Audio
  47        [video & audio]                 |   [Audio]
  48                                        |
  49                                        |-> Cx25840 --> Video
  50                                            [Video]
  51
  52*******************************************************************************/
  53
  54/******************************************************************************
  55 *                    A F E - B L O C K    C O N T R O L   functions          *
  56 *                              [ANALOG FRONT END]                            *
  57 ******************************************************************************/
  58static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
  59{
  60        return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
  61                                        saddr, 2, data, 1);
  62}
  63
  64static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
  65{
  66        int status;
  67        u32 temp = 0;
  68
  69        status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
  70                                        saddr, 2, &temp, 1);
  71        *data = (u8) temp;
  72        return status;
  73}
  74
  75int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
  76{
  77        int status = 0;
  78        u8 temp = 0;
  79        u8 afe_power_status = 0;
  80        int i = 0;
  81
  82        /* super block initialize */
  83        temp = (u8) (ref_count & 0xff);
  84        status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
  85        if (status < 0)
  86                return status;
  87
  88        status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
  89        if (status < 0)
  90                return status;
  91
  92        temp = (u8) ((ref_count & 0x300) >> 8);
  93        temp |= 0x40;
  94        status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
  95        if (status < 0)
  96                return status;
  97
  98        status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
  99        if (status < 0)
 100                return status;
 101
 102        /* enable pll     */
 103        while (afe_power_status != 0x18) {
 104                status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
 105                if (status < 0) {
 106                        cx231xx_info(
 107                        ": Init Super Block failed in send cmd\n");
 108                        break;
 109                }
 110
 111                status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
 112                afe_power_status &= 0xff;
 113                if (status < 0) {
 114                        cx231xx_info(
 115                        ": Init Super Block failed in receive cmd\n");
 116                        break;
 117                }
 118                i++;
 119                if (i == 10) {
 120                        cx231xx_info(
 121                        ": Init Super Block force break in loop !!!!\n");
 122                        status = -1;
 123                        break;
 124                }
 125        }
 126
 127        if (status < 0)
 128                return status;
 129
 130        /* start tuning filter */
 131        status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
 132        if (status < 0)
 133                return status;
 134
 135        msleep(5);
 136
 137        /* exit tuning */
 138        status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
 139
 140        return status;
 141}
 142
 143int cx231xx_afe_init_channels(struct cx231xx *dev)
 144{
 145        int status = 0;
 146
 147        /* power up all 3 channels, clear pd_buffer */
 148        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
 149        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
 150        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
 151
 152        /* Enable quantizer calibration */
 153        status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
 154
 155        /* channel initialize, force modulator (fb) reset */
 156        status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
 157        status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
 158        status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
 159
 160        /* start quantilizer calibration  */
 161        status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
 162        status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
 163        status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
 164        msleep(5);
 165
 166        /* exit modulator (fb) reset */
 167        status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
 168        status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
 169        status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
 170
 171        /* enable the pre_clamp in each channel for single-ended input */
 172        status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
 173        status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
 174        status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
 175
 176        /* use diode instead of resistor, so set term_en to 0, res_en to 0  */
 177        status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 178                                   ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
 179        status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 180                                   ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
 181        status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
 182                                   ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
 183
 184        /* dynamic element matching off */
 185        status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
 186        status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
 187        status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
 188
 189        return status;
 190}
 191
 192int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
 193{
 194        u8 c_value = 0;
 195        int status = 0;
 196
 197        status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
 198        c_value &= (~(0x50));
 199        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
 200
 201        return status;
 202}
 203
 204/*
 205        The Analog Front End in Cx231xx has 3 channels. These
 206        channels are used to share between different inputs
 207        like tuner, s-video and composite inputs.
 208
 209        channel 1 ----- pin 1  to pin4(in reg is 1-4)
 210        channel 2 ----- pin 5  to pin8(in reg is 5-8)
 211        channel 3 ----- pin 9 to pin 12(in reg is 9-11)
 212*/
 213int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
 214{
 215        u8 ch1_setting = (u8) input_mux;
 216        u8 ch2_setting = (u8) (input_mux >> 8);
 217        u8 ch3_setting = (u8) (input_mux >> 16);
 218        int status = 0;
 219        u8 value = 0;
 220
 221        if (ch1_setting != 0) {
 222                status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
 223                value &= (!INPUT_SEL_MASK);
 224                value |= (ch1_setting - 1) << 4;
 225                value &= 0xff;
 226                status = afe_write_byte(dev, ADC_INPUT_CH1, value);
 227        }
 228
 229        if (ch2_setting != 0) {
 230                status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
 231                value &= (!INPUT_SEL_MASK);
 232                value |= (ch2_setting - 1) << 4;
 233                value &= 0xff;
 234                status = afe_write_byte(dev, ADC_INPUT_CH2, value);
 235        }
 236
 237        /* For ch3_setting, the value to put in the register is
 238           7 less than the input number */
 239        if (ch3_setting != 0) {
 240                status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
 241                value &= (!INPUT_SEL_MASK);
 242                value |= (ch3_setting - 1) << 4;
 243                value &= 0xff;
 244                status = afe_write_byte(dev, ADC_INPUT_CH3, value);
 245        }
 246
 247        return status;
 248}
 249
 250int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
 251{
 252        int status = 0;
 253
 254        /*
 255        * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
 256        * Currently, only baseband works.
 257        */
 258
 259        switch (mode) {
 260        case AFE_MODE_LOW_IF:
 261                /* SetupAFEforLowIF();  */
 262                break;
 263        case AFE_MODE_BASEBAND:
 264                status = cx231xx_afe_setup_AFE_for_baseband(dev);
 265                break;
 266        case AFE_MODE_EU_HI_IF:
 267                /* SetupAFEforEuHiIF(); */
 268                break;
 269        case AFE_MODE_US_HI_IF:
 270                /* SetupAFEforUsHiIF(); */
 271                break;
 272        case AFE_MODE_JAPAN_HI_IF:
 273                /* SetupAFEforJapanHiIF(); */
 274                break;
 275        }
 276
 277        if ((mode != dev->afe_mode) &&
 278                (dev->video_input == CX231XX_VMUX_TELEVISION))
 279                status = cx231xx_afe_adjust_ref_count(dev,
 280                                                     CX231XX_VMUX_TELEVISION);
 281
 282        dev->afe_mode = mode;
 283
 284        return status;
 285}
 286
 287int cx231xx_afe_update_power_control(struct cx231xx *dev,
 288                                        enum AV_MODE avmode)
 289{
 290        u8 afe_power_status = 0;
 291        int status = 0;
 292
 293        switch (dev->model) {
 294        case CX231XX_BOARD_CNXT_RDE_250:
 295        case CX231XX_BOARD_CNXT_RDU_250:
 296                if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 297                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 298                                                FLD_PWRDN_ENABLE_PLL)) {
 299                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
 300                                                        FLD_PWRDN_TUNING_BIAS |
 301                                                        FLD_PWRDN_ENABLE_PLL);
 302                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 303                                                        &afe_power_status);
 304                                if (status < 0)
 305                                        break;
 306                        }
 307
 308                        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 309                                                        0x00);
 310                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 311                                                        0x00);
 312                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 313                                                        0x00);
 314                } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 315                        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 316                                                        0x70);
 317                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 318                                                        0x70);
 319                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 320                                                        0x70);
 321
 322                        status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 323                                                  &afe_power_status);
 324                        afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 325                                                FLD_PWRDN_PD_BIAS |
 326                                                FLD_PWRDN_PD_TUNECK;
 327                        status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 328                                                   afe_power_status);
 329                } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 330                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 331                                                FLD_PWRDN_ENABLE_PLL)) {
 332                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
 333                                                        FLD_PWRDN_TUNING_BIAS |
 334                                                        FLD_PWRDN_ENABLE_PLL);
 335                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 336                                                        &afe_power_status);
 337                                if (status < 0)
 338                                        break;
 339                        }
 340
 341                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 342                                                0x00);
 343                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 344                                                0x00);
 345                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 346                                                0x00);
 347                } else {
 348                        cx231xx_info("Invalid AV mode input\n");
 349                        status = -1;
 350                }
 351                break;
 352        default:
 353                if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
 354                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 355                                                FLD_PWRDN_ENABLE_PLL)) {
 356                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
 357                                                        FLD_PWRDN_TUNING_BIAS |
 358                                                        FLD_PWRDN_ENABLE_PLL);
 359                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 360                                                        &afe_power_status);
 361                                if (status < 0)
 362                                        break;
 363                        }
 364
 365                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 366                                                        0x40);
 367                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 368                                                        0x40);
 369                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 370                                                        0x00);
 371                } else if (avmode == POLARIS_AVMODE_DIGITAL) {
 372                        status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 373                                                        0x70);
 374                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 375                                                        0x70);
 376                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 377                                                        0x70);
 378
 379                        status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 380                                                       &afe_power_status);
 381                        afe_power_status |= FLD_PWRDN_PD_BANDGAP |
 382                                                FLD_PWRDN_PD_BIAS |
 383                                                FLD_PWRDN_PD_TUNECK;
 384                        status |= afe_write_byte(dev, SUP_BLK_PWRDN,
 385                                                        afe_power_status);
 386                } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
 387                        while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
 388                                                FLD_PWRDN_ENABLE_PLL)) {
 389                                status = afe_write_byte(dev, SUP_BLK_PWRDN,
 390                                                        FLD_PWRDN_TUNING_BIAS |
 391                                                        FLD_PWRDN_ENABLE_PLL);
 392                                status |= afe_read_byte(dev, SUP_BLK_PWRDN,
 393                                                        &afe_power_status);
 394                                if (status < 0)
 395                                        break;
 396                        }
 397
 398                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
 399                                                        0x00);
 400                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
 401                                                        0x00);
 402                        status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
 403                                                        0x40);
 404                } else {
 405                        cx231xx_info("Invalid AV mode input\n");
 406                        status = -1;
 407                }
 408        }                       /* switch  */
 409
 410        return status;
 411}
 412
 413int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
 414{
 415        u8 input_mode = 0;
 416        u8 ntf_mode = 0;
 417        int status = 0;
 418
 419        dev->video_input = video_input;
 420
 421        if (video_input == CX231XX_VMUX_TELEVISION) {
 422                status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
 423                status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
 424                                        &ntf_mode);
 425        } else {
 426                status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
 427                status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
 428                                        &ntf_mode);
 429        }
 430
 431        input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
 432
 433        switch (input_mode) {
 434        case SINGLE_ENDED:
 435                dev->afe_ref_count = 0x23C;
 436                break;
 437        case LOW_IF:
 438                dev->afe_ref_count = 0x24C;
 439                break;
 440        case EU_IF:
 441                dev->afe_ref_count = 0x258;
 442                break;
 443        case US_IF:
 444                dev->afe_ref_count = 0x260;
 445                break;
 446        default:
 447                break;
 448        }
 449
 450        status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
 451
 452        return status;
 453}
 454
 455/******************************************************************************
 456 *     V I D E O / A U D I O    D E C O D E R    C O N T R O L   functions    *
 457 ******************************************************************************/
 458static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
 459{
 460        return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 461                                        saddr, 2, data, 1);
 462}
 463
 464static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
 465{
 466        int status;
 467        u32 temp = 0;
 468
 469        status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 470                                        saddr, 2, &temp, 1);
 471        *data = (u8) temp;
 472        return status;
 473}
 474
 475static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
 476{
 477        return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 478                                        saddr, 2, data, 4);
 479}
 480
 481static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
 482{
 483        return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
 484                                        saddr, 2, data, 4);
 485}
 486
 487int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
 488{
 489        int status = 0;
 490
 491        switch (INPUT(input)->type) {
 492        case CX231XX_VMUX_COMPOSITE1:
 493        case CX231XX_VMUX_SVIDEO:
 494                if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 495                    (dev->power_mode != POLARIS_AVMODE_ENXTERNAL_AV)) {
 496                        /* External AV */
 497                        status = cx231xx_set_power_mode(dev,
 498                                        POLARIS_AVMODE_ENXTERNAL_AV);
 499                        if (status < 0) {
 500                                cx231xx_errdev("%s: set_power_mode : Failed to"
 501                                                " set Power - errCode [%d]!\n",
 502                                                __func__, status);
 503                                return status;
 504                        }
 505                }
 506                status = cx231xx_set_decoder_video_input(dev,
 507                                                         INPUT(input)->type,
 508                                                         INPUT(input)->vmux);
 509                break;
 510        case CX231XX_VMUX_TELEVISION:
 511        case CX231XX_VMUX_CABLE:
 512                if ((dev->current_pcb_config.type == USB_BUS_POWER) &&
 513                    (dev->power_mode != POLARIS_AVMODE_ANALOGT_TV)) {
 514                        /* Tuner */
 515                        status = cx231xx_set_power_mode(dev,
 516                                                POLARIS_AVMODE_ANALOGT_TV);
 517                        if (status < 0) {
 518                                cx231xx_errdev("%s: set_power_mode:Failed"
 519                                        " to set Power - errCode [%d]!\n",
 520                                        __func__, status);
 521                                return status;
 522                        }
 523                }
 524                status = cx231xx_set_decoder_video_input(dev,
 525                                                        CX231XX_VMUX_COMPOSITE1,
 526                                                        INPUT(input)->vmux);
 527                break;
 528        default:
 529                cx231xx_errdev("%s: set_power_mode : Unknown Input %d !\n",
 530                     __func__, INPUT(input)->type);
 531                break;
 532        }
 533
 534        /* save the selection */
 535        dev->video_input = input;
 536
 537        return status;
 538}
 539
 540int cx231xx_set_decoder_video_input(struct cx231xx *dev,
 541                                u8 pin_type, u8 input)
 542{
 543        int status = 0;
 544        u32 value = 0;
 545
 546        if (pin_type != dev->video_input) {
 547                status = cx231xx_afe_adjust_ref_count(dev, pin_type);
 548                if (status < 0) {
 549                        cx231xx_errdev("%s: adjust_ref_count :Failed to set"
 550                                "AFE input mux - errCode [%d]!\n",
 551                                __func__, status);
 552                        return status;
 553                }
 554        }
 555
 556        /* call afe block to set video inputs */
 557        status = cx231xx_afe_set_input_mux(dev, input);
 558        if (status < 0) {
 559                cx231xx_errdev("%s: set_input_mux :Failed to set"
 560                                " AFE input mux - errCode [%d]!\n",
 561                                __func__, status);
 562                return status;
 563        }
 564
 565        switch (pin_type) {
 566        case CX231XX_VMUX_COMPOSITE1:
 567                status = vid_blk_read_word(dev, AFE_CTRL, &value);
 568                value |= (0 << 13) | (1 << 4);
 569                value &= ~(1 << 5);
 570
 571                /* set [24:23] [22:15] to 0  */
 572                value &= (~(0x1ff8000));
 573                /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0  */
 574                value |= 0x1000000;
 575                status = vid_blk_write_word(dev, AFE_CTRL, value);
 576
 577                status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 578                value |= (1 << 7);
 579                status = vid_blk_write_word(dev, OUT_CTRL1, value);
 580
 581                /* Set vip 1.1 output mode */
 582                status = cx231xx_read_modify_write_i2c_dword(dev,
 583                                                        VID_BLK_I2C_ADDRESS,
 584                                                        OUT_CTRL1,
 585                                                        FLD_OUT_MODE,
 586                                                        OUT_MODE_VIP11);
 587
 588                /* Tell DIF object to go to baseband mode  */
 589                status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 590                if (status < 0) {
 591                        cx231xx_errdev("%s: cx231xx_dif set to By pass"
 592                                                   " mode- errCode [%d]!\n",
 593                                __func__, status);
 594                        return status;
 595                }
 596
 597                /* Read the DFE_CTRL1 register */
 598                status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 599
 600                /* enable the VBI_GATE_EN */
 601                value |= FLD_VBI_GATE_EN;
 602
 603                /* Enable the auto-VGA enable */
 604                value |= FLD_VGA_AUTO_EN;
 605
 606                /* Write it back */
 607                status = vid_blk_write_word(dev, DFE_CTRL1, value);
 608
 609                /* Disable auto config of registers */
 610                status = cx231xx_read_modify_write_i2c_dword(dev,
 611                                        VID_BLK_I2C_ADDRESS,
 612                                        MODE_CTRL, FLD_ACFG_DIS,
 613                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
 614
 615                /* Set CVBS input mode */
 616                status = cx231xx_read_modify_write_i2c_dword(dev,
 617                        VID_BLK_I2C_ADDRESS,
 618                        MODE_CTRL, FLD_INPUT_MODE,
 619                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
 620                break;
 621        case CX231XX_VMUX_SVIDEO:
 622                /* Disable the use of  DIF */
 623
 624                status = vid_blk_read_word(dev, AFE_CTRL, &value);
 625
 626                /* set [24:23] [22:15] to 0 */
 627                value &= (~(0x1ff8000));
 628                /* set FUNC_MODE[24:23] = 2
 629                IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
 630                value |= 0x1000010;
 631                status = vid_blk_write_word(dev, AFE_CTRL, value);
 632
 633                /* Tell DIF object to go to baseband mode */
 634                status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
 635                if (status < 0) {
 636                        cx231xx_errdev("%s: cx231xx_dif set to By pass"
 637                                                   " mode- errCode [%d]!\n",
 638                                __func__, status);
 639                        return status;
 640                }
 641
 642                /* Read the DFE_CTRL1 register */
 643                status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 644
 645                /* enable the VBI_GATE_EN */
 646                value |= FLD_VBI_GATE_EN;
 647
 648                /* Enable the auto-VGA enable */
 649                value |= FLD_VGA_AUTO_EN;
 650
 651                /* Write it back */
 652                status = vid_blk_write_word(dev, DFE_CTRL1, value);
 653
 654                /* Disable auto config of registers  */
 655                status =  cx231xx_read_modify_write_i2c_dword(dev,
 656                                        VID_BLK_I2C_ADDRESS,
 657                                        MODE_CTRL, FLD_ACFG_DIS,
 658                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
 659
 660                /* Set YC input mode */
 661                status = cx231xx_read_modify_write_i2c_dword(dev,
 662                        VID_BLK_I2C_ADDRESS,
 663                        MODE_CTRL,
 664                        FLD_INPUT_MODE,
 665                        cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
 666
 667                /* Chroma to ADC2 */
 668                status = vid_blk_read_word(dev, AFE_CTRL, &value);
 669                value |= FLD_CHROMA_IN_SEL;     /* set the chroma in select */
 670
 671                /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
 672                   This sets them to use video
 673                   rather than audio.  Only one of the two will be in use. */
 674                value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
 675
 676                status = vid_blk_write_word(dev, AFE_CTRL, value);
 677
 678                status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
 679                break;
 680        case CX231XX_VMUX_TELEVISION:
 681        case CX231XX_VMUX_CABLE:
 682        default:
 683                switch (dev->model) {
 684                case CX231XX_BOARD_CNXT_RDE_250:
 685                case CX231XX_BOARD_CNXT_RDU_250:
 686                        /* Disable the use of  DIF   */
 687
 688                        status = vid_blk_read_word(dev, AFE_CTRL, &value);
 689                        value |= (0 << 13) | (1 << 4);
 690                        value &= ~(1 << 5);
 691
 692                        /* set [24:23] [22:15] to 0 */
 693                        value &= (~(0x1FF8000));
 694                        /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
 695                        value |= 0x1000000;
 696                        status = vid_blk_write_word(dev, AFE_CTRL, value);
 697
 698                        status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 699                        value |= (1 << 7);
 700                        status = vid_blk_write_word(dev, OUT_CTRL1, value);
 701
 702                        /* Set vip 1.1 output mode */
 703                        status = cx231xx_read_modify_write_i2c_dword(dev,
 704                                                        VID_BLK_I2C_ADDRESS,
 705                                                        OUT_CTRL1, FLD_OUT_MODE,
 706                                                        OUT_MODE_VIP11);
 707
 708                        /* Tell DIF object to go to baseband mode */
 709                        status = cx231xx_dif_set_standard(dev,
 710                                                          DIF_USE_BASEBAND);
 711                        if (status < 0) {
 712                                cx231xx_errdev("%s: cx231xx_dif set to By pass"
 713                                                " mode- errCode [%d]!\n",
 714                                                __func__, status);
 715                                return status;
 716                        }
 717
 718                        /* Read the DFE_CTRL1 register */
 719                        status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 720
 721                        /* enable the VBI_GATE_EN */
 722                        value |= FLD_VBI_GATE_EN;
 723
 724                        /* Enable the auto-VGA enable */
 725                        value |= FLD_VGA_AUTO_EN;
 726
 727                        /* Write it back */
 728                        status = vid_blk_write_word(dev, DFE_CTRL1, value);
 729
 730                        /* Disable auto config of registers */
 731                        status = cx231xx_read_modify_write_i2c_dword(dev,
 732                                        VID_BLK_I2C_ADDRESS,
 733                                        MODE_CTRL, FLD_ACFG_DIS,
 734                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
 735
 736                        /* Set CVBS input mode */
 737                        status = cx231xx_read_modify_write_i2c_dword(dev,
 738                                VID_BLK_I2C_ADDRESS,
 739                                MODE_CTRL, FLD_INPUT_MODE,
 740                                cx231xx_set_field(FLD_INPUT_MODE,
 741                                                INPUT_MODE_CVBS_0));
 742                        break;
 743                default:
 744                        /* Enable the DIF for the tuner */
 745
 746                        /* Reinitialize the DIF */
 747                        status = cx231xx_dif_set_standard(dev, dev->norm);
 748                        if (status < 0) {
 749                                cx231xx_errdev("%s: cx231xx_dif set to By pass"
 750                                                " mode- errCode [%d]!\n",
 751                                                __func__, status);
 752                                return status;
 753                        }
 754
 755                        /* Make sure bypass is cleared */
 756                        status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
 757
 758                        /* Clear the bypass bit */
 759                        value &= ~FLD_DIF_DIF_BYPASS;
 760
 761                        /* Enable the use of the DIF block */
 762                        status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
 763
 764                        /* Read the DFE_CTRL1 register */
 765                        status = vid_blk_read_word(dev, DFE_CTRL1, &value);
 766
 767                        /* Disable the VBI_GATE_EN */
 768                        value &= ~FLD_VBI_GATE_EN;
 769
 770                        /* Enable the auto-VGA enable, AGC, and
 771                           set the skip count to 2 */
 772                        value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
 773
 774                        /* Write it back */
 775                        status = vid_blk_write_word(dev, DFE_CTRL1, value);
 776
 777                        /* Wait until AGC locks up */
 778                        msleep(1);
 779
 780                        /* Disable the auto-VGA enable AGC */
 781                        value &= ~(FLD_VGA_AUTO_EN);
 782
 783                        /* Write it back */
 784                        status = vid_blk_write_word(dev, DFE_CTRL1, value);
 785
 786                        /* Enable Polaris B0 AGC output */
 787                        status = vid_blk_read_word(dev, PIN_CTRL, &value);
 788                        value |= (FLD_OEF_AGC_RF) |
 789                                 (FLD_OEF_AGC_IFVGA) |
 790                                 (FLD_OEF_AGC_IF);
 791                        status = vid_blk_write_word(dev, PIN_CTRL, value);
 792
 793                        /* Set vip 1.1 output mode */
 794                        status = cx231xx_read_modify_write_i2c_dword(dev,
 795                                                VID_BLK_I2C_ADDRESS,
 796                                                OUT_CTRL1, FLD_OUT_MODE,
 797                                                OUT_MODE_VIP11);
 798
 799                        /* Disable auto config of registers */
 800                        status = cx231xx_read_modify_write_i2c_dword(dev,
 801                                        VID_BLK_I2C_ADDRESS,
 802                                        MODE_CTRL, FLD_ACFG_DIS,
 803                                        cx231xx_set_field(FLD_ACFG_DIS, 1));
 804
 805                        /* Set CVBS input mode */
 806                        status = cx231xx_read_modify_write_i2c_dword(dev,
 807                                VID_BLK_I2C_ADDRESS,
 808                                MODE_CTRL, FLD_INPUT_MODE,
 809                                cx231xx_set_field(FLD_INPUT_MODE,
 810                                                INPUT_MODE_CVBS_0));
 811
 812                        /* Set some bits in AFE_CTRL so that channel 2 or 3
 813                         * is ready to receive audio */
 814                        /* Clear clamp for channels 2 and 3      (bit 16-17) */
 815                        /* Clear droop comp                      (bit 19-20) */
 816                        /* Set VGA_SEL (for audio control)       (bit 7-8) */
 817                        status = vid_blk_read_word(dev, AFE_CTRL, &value);
 818
 819                        value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
 820
 821                        status = vid_blk_write_word(dev, AFE_CTRL, value);
 822                        break;
 823
 824                }
 825                break;
 826        }
 827
 828        /* Set raw VBI mode */
 829        status = cx231xx_read_modify_write_i2c_dword(dev,
 830                                VID_BLK_I2C_ADDRESS,
 831                                OUT_CTRL1, FLD_VBIHACTRAW_EN,
 832                                cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
 833
 834        status = vid_blk_read_word(dev, OUT_CTRL1, &value);
 835        if (value & 0x02) {
 836                value |= (1 << 19);
 837                status = vid_blk_write_word(dev, OUT_CTRL1, value);
 838        }
 839
 840        return status;
 841}
 842
 843/*
 844 * Handle any video-mode specific overrides that are different
 845 * on a per video standards basis after touching the MODE_CTRL
 846 * register which resets many values for autodetect
 847 */
 848int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
 849{
 850        int status = 0;
 851
 852        cx231xx_info("do_mode_ctrl_overrides : 0x%x\n",
 853                     (unsigned int)dev->norm);
 854
 855        /* Change the DFE_CTRL3 bp_percent to fix flagging */
 856        status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
 857
 858        if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
 859                cx231xx_info("do_mode_ctrl_overrides NTSC\n");
 860
 861                /* Move the close caption lines out of active video,
 862                   adjust the active video start point */
 863                status = cx231xx_read_modify_write_i2c_dword(dev,
 864                                                        VID_BLK_I2C_ADDRESS,
 865                                                        VERT_TIM_CTRL,
 866                                                        FLD_VBLANK_CNT, 0x18);
 867                status = cx231xx_read_modify_write_i2c_dword(dev,
 868                                                        VID_BLK_I2C_ADDRESS,
 869                                                        VERT_TIM_CTRL,
 870                                                        FLD_VACTIVE_CNT,
 871                                                        0x1E6000);
 872                status = cx231xx_read_modify_write_i2c_dword(dev,
 873                                                        VID_BLK_I2C_ADDRESS,
 874                                                        VERT_TIM_CTRL,
 875                                                        FLD_V656BLANK_CNT,
 876                                                        0x1E000000);
 877
 878                status = cx231xx_read_modify_write_i2c_dword(dev,
 879                                                        VID_BLK_I2C_ADDRESS,
 880                                                        HORIZ_TIM_CTRL,
 881                                                        FLD_HBLANK_CNT,
 882                                                        cx231xx_set_field
 883                                                        (FLD_HBLANK_CNT, 0x79));
 884        } else if (dev->norm & V4L2_STD_SECAM) {
 885                cx231xx_info("do_mode_ctrl_overrides SECAM\n");
 886                status =  cx231xx_read_modify_write_i2c_dword(dev,
 887                                                        VID_BLK_I2C_ADDRESS,
 888                                                        VERT_TIM_CTRL,
 889                                                        FLD_VBLANK_CNT, 0x24);
 890                /* Adjust the active video horizontal start point */
 891                status = cx231xx_read_modify_write_i2c_dword(dev,
 892                                                        VID_BLK_I2C_ADDRESS,
 893                                                        HORIZ_TIM_CTRL,
 894                                                        FLD_HBLANK_CNT,
 895                                                        cx231xx_set_field
 896                                                        (FLD_HBLANK_CNT, 0x85));
 897        } else {
 898                cx231xx_info("do_mode_ctrl_overrides PAL\n");
 899                status = cx231xx_read_modify_write_i2c_dword(dev,
 900                                                        VID_BLK_I2C_ADDRESS,
 901                                                        VERT_TIM_CTRL,
 902                                                        FLD_VBLANK_CNT, 0x24);
 903                /* Adjust the active video horizontal start point */
 904                status = cx231xx_read_modify_write_i2c_dword(dev,
 905                                                        VID_BLK_I2C_ADDRESS,
 906                                                        HORIZ_TIM_CTRL,
 907                                                        FLD_HBLANK_CNT,
 908                                                        cx231xx_set_field
 909                                                        (FLD_HBLANK_CNT, 0x85));
 910        }
 911
 912        return status;
 913}
 914
 915int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
 916{
 917        int status = 0;
 918        enum AUDIO_INPUT ainput = AUDIO_INPUT_LINE;
 919
 920        switch (INPUT(input)->amux) {
 921        case CX231XX_AMUX_VIDEO:
 922                ainput = AUDIO_INPUT_TUNER_TV;
 923                break;
 924        case CX231XX_AMUX_LINE_IN:
 925                status = cx231xx_i2s_blk_set_audio_input(dev, input);
 926                ainput = AUDIO_INPUT_LINE;
 927                break;
 928        default:
 929                break;
 930        }
 931
 932        status = cx231xx_set_audio_decoder_input(dev, ainput);
 933
 934        return status;
 935}
 936
 937int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
 938                                    enum AUDIO_INPUT audio_input)
 939{
 940        u32 dwval;
 941        int status;
 942        u8 gen_ctrl;
 943        u32 value = 0;
 944
 945        /* Put it in soft reset   */
 946        status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
 947        gen_ctrl |= 1;
 948        status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
 949
 950        switch (audio_input) {
 951        case AUDIO_INPUT_LINE:
 952                /* setup AUD_IO control from Merlin paralle output */
 953                value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
 954                                          AUD_CHAN_SRC_PARALLEL);
 955                status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
 956
 957                /* setup input to Merlin, SRC2 connect to AC97
 958                   bypass upsample-by-2, slave mode, sony mode, left justify
 959                   adr 091c, dat 01000000 */
 960                status = vid_blk_read_word(dev, AC97_CTL, &dwval);
 961
 962                status = vid_blk_write_word(dev, AC97_CTL,
 963                                           (dwval | FLD_AC97_UP2X_BYPASS));
 964
 965                /* select the parallel1 and SRC3 */
 966                status = vid_blk_write_word(dev, BAND_OUT_SEL,
 967                                cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
 968                                cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
 969                                cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
 970
 971                /* unmute all, AC97 in, independence mode
 972                   adr 08d0, data 0x00063073 */
 973                status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
 974
 975                /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
 976                status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
 977                status = vid_blk_write_word(dev, PATH1_VOL_CTL,
 978                                           (dwval | FLD_PATH1_AVC_THRESHOLD));
 979
 980                /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
 981                status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
 982                status = vid_blk_write_word(dev, PATH1_SC_CTL,
 983                                           (dwval | FLD_PATH1_SC_THRESHOLD));
 984                break;
 985
 986        case AUDIO_INPUT_TUNER_TV:
 987        default:
 988
 989                /* Setup SRC sources and clocks */
 990                status = vid_blk_write_word(dev, BAND_OUT_SEL,
 991                        cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00)         |
 992                        cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01)        |
 993                        cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00)         |
 994                        cx231xx_set_field(FLD_SRC5_CLK_SEL, 0x02)        |
 995                        cx231xx_set_field(FLD_SRC4_IN_SEL, 0x02)         |
 996                        cx231xx_set_field(FLD_SRC4_CLK_SEL, 0x03)        |
 997                        cx231xx_set_field(FLD_SRC3_IN_SEL, 0x00)         |
 998                        cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x00)        |
 999                        cx231xx_set_field(FLD_BASEBAND_BYPASS_CTL, 0x00) |
1000                        cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03)        |
1001                        cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00)         |
1002                        cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02)   |
1003                        cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1004
1005                /* Setup the AUD_IO control */
1006                status = vid_blk_write_word(dev, AUD_IO_CTRL,
1007                        cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00)  |
1008                        cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00)   |
1009                        cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1010                        cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1011                        cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1012
1013                status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1014
1015                /* setAudioStandard(_audio_standard); */
1016
1017                status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1018                switch (dev->model) {
1019                case CX231XX_BOARD_CNXT_RDE_250:
1020                case CX231XX_BOARD_CNXT_RDU_250:
1021                        status = cx231xx_read_modify_write_i2c_dword(dev,
1022                                        VID_BLK_I2C_ADDRESS,
1023                                        CHIP_CTRL,
1024                                        FLD_SIF_EN,
1025                                        cx231xx_set_field(FLD_SIF_EN, 1));
1026                        break;
1027                default:
1028                        break;
1029                }
1030                break;
1031
1032        case AUDIO_INPUT_TUNER_FM:
1033                /*  use SIF for FM radio
1034                   setupFM();
1035                   setAudioStandard(_audio_standard);
1036                 */
1037                break;
1038
1039        case AUDIO_INPUT_MUTE:
1040                status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1041                break;
1042        }
1043
1044        /* Take it out of soft reset */
1045        status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1046        gen_ctrl &= ~1;
1047        status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1048
1049        return status;
1050}
1051
1052/* Set resolution of the video */
1053int cx231xx_resolution_set(struct cx231xx *dev)
1054{
1055        /* set horzontal scale */
1056        int status = vid_blk_write_word(dev, HSCALE_CTRL, dev->hscale);
1057        if (status)
1058                return status;
1059
1060        /* set vertical scale */
1061        return vid_blk_write_word(dev, VSCALE_CTRL, dev->vscale);
1062}
1063
1064/******************************************************************************
1065 *                    C H I P Specific  C O N T R O L   functions             *
1066 ******************************************************************************/
1067int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1068{
1069        u32 value;
1070        int status = 0;
1071
1072        status = vid_blk_read_word(dev, PIN_CTRL, &value);
1073        value |= (~dev->board.ctl_pin_status_mask);
1074        status = vid_blk_write_word(dev, PIN_CTRL, value);
1075
1076        return status;
1077}
1078
1079int cx231xx_set_agc_analog_digital_mux_select(struct cx231xx *dev,
1080                                              u8 analog_or_digital)
1081{
1082        int status = 0;
1083
1084        /* first set the direction to output */
1085        status = cx231xx_set_gpio_direction(dev,
1086                                            dev->board.
1087                                            agc_analog_digital_select_gpio, 1);
1088
1089        /* 0 - demod ; 1 - Analog mode */
1090        status = cx231xx_set_gpio_value(dev,
1091                                   dev->board.agc_analog_digital_select_gpio,
1092                                   analog_or_digital);
1093
1094        return status;
1095}
1096
1097int cx231xx_enable_i2c_for_tuner(struct cx231xx *dev, u8 I2CIndex)
1098{
1099        u8 value[4] = { 0, 0, 0, 0 };
1100        int status = 0;
1101
1102        cx231xx_info("Changing the i2c port for tuner to %d\n", I2CIndex);
1103
1104        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER,
1105                                       PWR_CTL_EN, value, 4);
1106        if (status < 0)
1107                return status;
1108
1109        if (I2CIndex == I2C_1) {
1110                if (value[0] & I2C_DEMOD_EN) {
1111                        value[0] &= ~I2C_DEMOD_EN;
1112                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1113                                                   PWR_CTL_EN, value, 4);
1114                }
1115        } else {
1116                if (!(value[0] & I2C_DEMOD_EN)) {
1117                        value[0] |= I2C_DEMOD_EN;
1118                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1119                                                   PWR_CTL_EN, value, 4);
1120                }
1121        }
1122
1123        return status;
1124
1125}
1126
1127/******************************************************************************
1128 *                 D I F - B L O C K    C O N T R O L   functions             *
1129 ******************************************************************************/
1130int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1131                                          u32 function_mode, u32 standard)
1132{
1133        int status = 0;
1134
1135        if (mode == V4L2_TUNER_RADIO) {
1136                /* C2HH */
1137                /* lo if big signal */
1138                status = cx231xx_reg_mask_write(dev,
1139                                VID_BLK_I2C_ADDRESS, 32,
1140                                AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1141                /* FUNC_MODE = DIF */
1142                status = cx231xx_reg_mask_write(dev,
1143                                VID_BLK_I2C_ADDRESS, 32,
1144                                AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1145                /* IF_MODE */
1146                status = cx231xx_reg_mask_write(dev,
1147                                VID_BLK_I2C_ADDRESS, 32,
1148                                AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1149                /* no inv */
1150                status = cx231xx_reg_mask_write(dev,
1151                                VID_BLK_I2C_ADDRESS, 32,
1152                                AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1153        } else if (standard != DIF_USE_BASEBAND) {
1154                if (standard & V4L2_STD_MN) {
1155                        /* lo if big signal */
1156                        status = cx231xx_reg_mask_write(dev,
1157                                        VID_BLK_I2C_ADDRESS, 32,
1158                                        AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1159                        /* FUNC_MODE = DIF */
1160                        status = cx231xx_reg_mask_write(dev,
1161                                        VID_BLK_I2C_ADDRESS, 32,
1162                                        AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1163                                        function_mode);
1164                        /* IF_MODE */
1165                        status = cx231xx_reg_mask_write(dev,
1166                                        VID_BLK_I2C_ADDRESS, 32,
1167                                        AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1168                        /* no inv */
1169                        status = cx231xx_reg_mask_write(dev,
1170                                        VID_BLK_I2C_ADDRESS, 32,
1171                                        AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1172                        /* 0x124, AUD_CHAN1_SRC = 0x3 */
1173                        status = cx231xx_reg_mask_write(dev,
1174                                        VID_BLK_I2C_ADDRESS, 32,
1175                                        AUD_IO_CTRL, 0, 31, 0x00000003);
1176                } else if ((standard == V4L2_STD_PAL_I) |
1177                        (standard & V4L2_STD_SECAM)) {
1178                        /* C2HH setup */
1179                        /* lo if big signal */
1180                        status = cx231xx_reg_mask_write(dev,
1181                                        VID_BLK_I2C_ADDRESS, 32,
1182                                        AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1183                        /* FUNC_MODE = DIF */
1184                        status = cx231xx_reg_mask_write(dev,
1185                                        VID_BLK_I2C_ADDRESS, 32,
1186                                        AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1187                                        function_mode);
1188                        /* IF_MODE */
1189                        status = cx231xx_reg_mask_write(dev,
1190                                        VID_BLK_I2C_ADDRESS, 32,
1191                                        AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1192                        /* no inv */
1193                        status = cx231xx_reg_mask_write(dev,
1194                                        VID_BLK_I2C_ADDRESS, 32,
1195                                        AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1196                } else {
1197                        /* default PAL BG */
1198                        /* C2HH setup */
1199                        /* lo if big signal */
1200                        status = cx231xx_reg_mask_write(dev,
1201                                        VID_BLK_I2C_ADDRESS, 32,
1202                                        AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1203                        /* FUNC_MODE = DIF */
1204                        status = cx231xx_reg_mask_write(dev,
1205                                        VID_BLK_I2C_ADDRESS, 32,
1206                                        AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1207                                        function_mode);
1208                        /* IF_MODE */
1209                        status = cx231xx_reg_mask_write(dev,
1210                                        VID_BLK_I2C_ADDRESS, 32,
1211                                        AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1212                        /* no inv */
1213                        status = cx231xx_reg_mask_write(dev,
1214                                        VID_BLK_I2C_ADDRESS, 32,
1215                                        AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1216                }
1217        }
1218
1219        return status;
1220}
1221
1222int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1223{
1224        int status = 0;
1225        u32 dif_misc_ctrl_value = 0;
1226        u32 func_mode = 0;
1227
1228        cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1229
1230        status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1231        if (standard != DIF_USE_BASEBAND)
1232                dev->norm = standard;
1233
1234        switch (dev->model) {
1235        case CX231XX_BOARD_CNXT_RDE_250:
1236        case CX231XX_BOARD_CNXT_RDU_250:
1237                func_mode = 0x03;
1238                break;
1239        default:
1240                func_mode = 0x01;
1241        }
1242
1243        status = cx231xx_dif_configure_C2HH_for_low_IF(dev, dev->active_mode,
1244                                                  func_mode, standard);
1245
1246        if (standard == DIF_USE_BASEBAND) {     /* base band */
1247                /* There is a different SRC_PHASE_INC value
1248                   for baseband vs. DIF */
1249                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1250                status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1251                                                &dif_misc_ctrl_value);
1252                dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1253                status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1254                                                dif_misc_ctrl_value);
1255        } else if (standard & V4L2_STD_PAL_D) {
1256                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1257                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1258                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1259                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1260                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1261                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1262                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1263                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
1264                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1265                                           DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1266                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1267                                           DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1268                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1269                                           DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1270                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1271                                           DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1272                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1273                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
1274                                           0x26001700);
1275                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1276                                           DIF_AGC_RF_CURRENT, 0, 31,
1277                                           0x00002660);
1278                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1279                                           DIF_VIDEO_AGC_CTRL, 0, 31,
1280                                           0x72500800);
1281                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1282                                           DIF_VID_AUD_OVERRIDE, 0, 31,
1283                                           0x27000100);
1284                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1285                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1286                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1287                                           DIF_COMP_FLT_CTRL, 0, 31,
1288                                           0x00000000);
1289                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1290                                           DIF_SRC_PHASE_INC, 0, 31,
1291                                           0x1befbf06);
1292                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1293                                           DIF_SRC_GAIN_CONTROL, 0, 31,
1294                                           0x000035e8);
1295                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1296                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1297                /* Save the Spec Inversion value */
1298                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1299                dif_misc_ctrl_value |= 0x3a023F11;
1300        } else if (standard & V4L2_STD_PAL_I) {
1301                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1302                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1303                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1304                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1305                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1306                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1307                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1308                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
1309                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1310                                           DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1311                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1312                                           DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1313                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1314                                           DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1315                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1316                                           DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1317                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1318                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
1319                                           0x26001700);
1320                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1321                                           DIF_AGC_RF_CURRENT, 0, 31,
1322                                           0x00002660);
1323                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1324                                           DIF_VIDEO_AGC_CTRL, 0, 31,
1325                                           0x72500800);
1326                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1327                                           DIF_VID_AUD_OVERRIDE, 0, 31,
1328                                           0x27000100);
1329                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1330                                           DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1331                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1332                                           DIF_COMP_FLT_CTRL, 0, 31,
1333                                           0x00000000);
1334                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1335                                           DIF_SRC_PHASE_INC, 0, 31,
1336                                           0x1befbf06);
1337                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1338                                           DIF_SRC_GAIN_CONTROL, 0, 31,
1339                                           0x000035e8);
1340                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1341                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1342                /* Save the Spec Inversion value */
1343                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1344                dif_misc_ctrl_value |= 0x3a033F11;
1345        } else if (standard & V4L2_STD_PAL_M) {
1346                /* improved Low Frequency Phase Noise */
1347                status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1348                status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1349                status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1350                status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1351                status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1352                status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1353                                                0x26001700);
1354                status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1355                                                0x00002660);
1356                status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1357                                                0x72500800);
1358                status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1359                                                0x27000100);
1360                status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1361                status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1362                                                0x009f50c1);
1363                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1364                                                0x1befbf06);
1365                status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1366                                                0x000035e8);
1367                status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1368                                                0x00000000);
1369                /* Save the Spec Inversion value */
1370                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1371                dif_misc_ctrl_value |= 0x3A0A3F10;
1372        } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1373                /* improved Low Frequency Phase Noise */
1374                status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1375                status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1376                status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1377                status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1378                status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1379                status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1380                                                0x26001700);
1381                status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1382                                                0x00002660);
1383                status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1384                                                0x72500800);
1385                status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1386                                                0x27000100);
1387                status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1388                                                0x012c405d);
1389                status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1390                                                0x009f50c1);
1391                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1392                                                0x1befbf06);
1393                status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1394                                                0x000035e8);
1395                status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1396                                                0x00000000);
1397                /* Save the Spec Inversion value */
1398                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1399                dif_misc_ctrl_value = 0x3A093F10;
1400        } else if (standard &
1401                  (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1402                   V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1403
1404                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1405                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1406                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1407                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1408                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1409                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1410                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1411                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
1412                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1413                                           DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1414                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1415                                           DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1416                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1417                                           DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1418                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1419                                           DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1420                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1421                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
1422                                           0x26001700);
1423                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1424                                           DIF_AGC_RF_CURRENT, 0, 31,
1425                                           0x00002660);
1426                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1427                                           DIF_VID_AUD_OVERRIDE, 0, 31,
1428                                           0x27000100);
1429                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1430                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1431                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1432                                           DIF_COMP_FLT_CTRL, 0, 31,
1433                                           0x00000000);
1434                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1435                                           DIF_SRC_PHASE_INC, 0, 31,
1436                                           0x1befbf06);
1437                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1438                                           DIF_SRC_GAIN_CONTROL, 0, 31,
1439                                           0x000035e8);
1440                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1441                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1442                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1443                                           DIF_VIDEO_AGC_CTRL, 0, 31,
1444                                           0xf4000000);
1445
1446                /* Save the Spec Inversion value */
1447                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1448                dif_misc_ctrl_value |= 0x3a023F11;
1449        } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1450                /* Is it SECAM_L1? */
1451                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1452                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1453                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1454                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1455                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1456                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1457                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1458                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
1459                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1460                                           DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1461                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1462                                           DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1463                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1464                                           DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1465                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1466                                           DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1467                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1468                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
1469                                           0x26001700);
1470                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1471                                           DIF_AGC_RF_CURRENT, 0, 31,
1472                                           0x00002660);
1473                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1474                                           DIF_VID_AUD_OVERRIDE, 0, 31,
1475                                           0x27000100);
1476                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1477                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1478                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1479                                           DIF_COMP_FLT_CTRL, 0, 31,
1480                                           0x00000000);
1481                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1482                                           DIF_SRC_PHASE_INC, 0, 31,
1483                                           0x1befbf06);
1484                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1485                                           DIF_SRC_GAIN_CONTROL, 0, 31,
1486                                           0x000035e8);
1487                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1488                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1489                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1490                                           DIF_VIDEO_AGC_CTRL, 0, 31,
1491                                           0xf2560000);
1492
1493                /* Save the Spec Inversion value */
1494                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1495                dif_misc_ctrl_value |= 0x3a023F11;
1496
1497        } else if (standard & V4L2_STD_NTSC_M) {
1498                /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1499                   V4L2_STD_NTSC_M_JP (Japan,  0 IRE Setup) */
1500
1501                /* For NTSC the centre frequency of video coming out of
1502                   sidewinder is around 7.1MHz or 3.6MHz depending on the
1503                   spectral inversion. so for a non spectrally inverted channel
1504                   the pll freq word is 0x03420c49
1505                 */
1506
1507                status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
1508                status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
1509                status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
1510                status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1511                status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
1512                status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1513                                                0x26001700);
1514                status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1515                                                0x00002660);
1516                status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1517                                                0x04000800);
1518                status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1519                                                0x27000100);
1520                status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
1521
1522                status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1523                                                0x009f50c1);
1524                status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1525                                                0x1befbf06);
1526                status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1527                                                0x000035e8);
1528
1529                status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
1530                status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
1531                                                0xC2262600);
1532                status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
1533
1534                /* Save the Spec Inversion value */
1535                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1536                dif_misc_ctrl_value |= 0x3a003F10;
1537        } else {
1538                /* default PAL BG */
1539                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1540                                           DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1541                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1542                                           DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1543                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1544                                           DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1545                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1546                                           DIF_PLL_CTRL3, 0, 31, 0x00008800);
1547                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1548                                           DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1549                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1550                                           DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1551                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1552                                           DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1553                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1554                                           DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1555                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1556                                           DIF_AGC_IF_INT_CURRENT, 0, 31,
1557                                           0x26001700);
1558                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1559                                           DIF_AGC_RF_CURRENT, 0, 31,
1560                                           0x00002660);
1561                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1562                                           DIF_VIDEO_AGC_CTRL, 0, 31,
1563                                           0x72500800);
1564                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1565                                           DIF_VID_AUD_OVERRIDE, 0, 31,
1566                                           0x27000100);
1567                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1568                                           DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1569                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1570                                           DIF_COMP_FLT_CTRL, 0, 31,
1571                                           0x00A653A8);
1572                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1573                                           DIF_SRC_PHASE_INC, 0, 31,
1574                                           0x1befbf06);
1575                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1576                                           DIF_SRC_GAIN_CONTROL, 0, 31,
1577                                           0x000035e8);
1578                status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1579                                           DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1580                /* Save the Spec Inversion value */
1581                dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1582                dif_misc_ctrl_value |= 0x3a013F11;
1583        }
1584
1585        /* The AGC values should be the same for all standards,
1586           AUD_SRC_SEL[19] should always be disabled    */
1587        dif_misc_ctrl_value &= ~FLD_DIF_AUD_SRC_SEL;
1588
1589        /* It is still possible to get Set Standard calls even when we
1590           are in FM mode.
1591           This is done to override the value for FM. */
1592        if (dev->active_mode == V4L2_TUNER_RADIO)
1593                dif_misc_ctrl_value = 0x7a080000;
1594
1595        /* Write the calculated value for misc ontrol register      */
1596        status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
1597
1598        return status;
1599}
1600
1601int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1602{
1603        int status = 0;
1604        u32 dwval;
1605
1606        /* Set the RF and IF k_agc values to 3 */
1607        status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1608        dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1609        dwval |= 0x33000000;
1610
1611        status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1612
1613        return status;
1614}
1615
1616int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1617{
1618        int status = 0;
1619        u32 dwval;
1620
1621        /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1622         * SECAM L/B/D standards */
1623        status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1624        dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1625
1626        if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
1627                         V4L2_STD_SECAM_D))
1628                dwval |= 0x88000000;
1629        else
1630                dwval |= 0x44000000;
1631
1632        status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1633
1634        return status;
1635}
1636
1637/******************************************************************************
1638 *                  I 2 S - B L O C K    C O N T R O L   functions            *
1639 ******************************************************************************/
1640int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
1641{
1642        int status = 0;
1643        u32 value;
1644
1645        status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1646                                       CH_PWR_CTRL1, 1, &value, 1);
1647        /* enables clock to delta-sigma and decimation filter */
1648        value |= 0x80;
1649        status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1650                                        CH_PWR_CTRL1, 1, value, 1);
1651        /* power up all channel */
1652        status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1653                                        CH_PWR_CTRL2, 1, 0x00, 1);
1654
1655        return status;
1656}
1657
1658int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
1659                                        enum AV_MODE avmode)
1660{
1661        int status = 0;
1662        u32 value = 0;
1663
1664        if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
1665                status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1666                                          CH_PWR_CTRL2, 1, &value, 1);
1667                value |= 0xfe;
1668                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1669                                                CH_PWR_CTRL2, 1, value, 1);
1670        } else {
1671                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1672                                                CH_PWR_CTRL2, 1, 0x00, 1);
1673        }
1674
1675        return status;
1676}
1677
1678/* set i2s_blk for audio input types */
1679int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
1680{
1681        int status = 0;
1682
1683        switch (audio_input) {
1684        case CX231XX_AMUX_LINE_IN:
1685                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1686                                                CH_PWR_CTRL2, 1, 0x00, 1);
1687                status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1688                                                CH_PWR_CTRL1, 1, 0x80, 1);
1689                break;
1690        case CX231XX_AMUX_VIDEO:
1691        default:
1692                break;
1693        }
1694
1695        dev->ctl_ainput = audio_input;
1696
1697        return status;
1698}
1699
1700/******************************************************************************
1701 *                  P O W E R      C O N T R O L   functions                  *
1702 ******************************************************************************/
1703int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1704{
1705        u8 value[4] = { 0, 0, 0, 0 };
1706        u32 tmp = 0;
1707        int status = 0;
1708
1709        if (dev->power_mode != mode)
1710                dev->power_mode = mode;
1711        else {
1712                cx231xx_info(" setPowerMode::mode = %d, No Change req.\n",
1713                             mode);
1714                return 0;
1715        }
1716
1717        cx231xx_info(" setPowerMode::mode = %d\n", mode);
1718
1719        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1720                                       4);
1721        if (status < 0)
1722                return status;
1723
1724        tmp = *((u32 *) value);
1725
1726        switch (mode) {
1727        case POLARIS_AVMODE_ENXTERNAL_AV:
1728
1729                tmp &= (~PWR_MODE_MASK);
1730
1731                tmp |= PWR_AV_EN;
1732                value[0] = (u8) tmp;
1733                value[1] = (u8) (tmp >> 8);
1734                value[2] = (u8) (tmp >> 16);
1735                value[3] = (u8) (tmp >> 24);
1736                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1737                                                PWR_CTL_EN, value, 4);
1738                msleep(PWR_SLEEP_INTERVAL);
1739
1740                tmp |= PWR_ISO_EN;
1741                value[0] = (u8) tmp;
1742                value[1] = (u8) (tmp >> 8);
1743                value[2] = (u8) (tmp >> 16);
1744                value[3] = (u8) (tmp >> 24);
1745                status =
1746                    cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1747                                           value, 4);
1748                msleep(PWR_SLEEP_INTERVAL);
1749
1750                tmp |= POLARIS_AVMODE_ENXTERNAL_AV;
1751                value[0] = (u8) tmp;
1752                value[1] = (u8) (tmp >> 8);
1753                value[2] = (u8) (tmp >> 16);
1754                value[3] = (u8) (tmp >> 24);
1755                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1756                                                PWR_CTL_EN, value, 4);
1757
1758                /* reset state of xceive tuner */
1759                dev->xc_fw_load_done = 0;
1760                break;
1761
1762        case POLARIS_AVMODE_ANALOGT_TV:
1763
1764                tmp &= (~PWR_DEMOD_EN);
1765                tmp |= (I2C_DEMOD_EN);
1766                value[0] = (u8) tmp;
1767                value[1] = (u8) (tmp >> 8);
1768                value[2] = (u8) (tmp >> 16);
1769                value[3] = (u8) (tmp >> 24);
1770                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1771                                                PWR_CTL_EN, value, 4);
1772                msleep(PWR_SLEEP_INTERVAL);
1773
1774                if (!(tmp & PWR_TUNER_EN)) {
1775                        tmp |= (PWR_TUNER_EN);
1776                        value[0] = (u8) tmp;
1777                        value[1] = (u8) (tmp >> 8);
1778                        value[2] = (u8) (tmp >> 16);
1779                        value[3] = (u8) (tmp >> 24);
1780                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1781                                                        PWR_CTL_EN, value, 4);
1782                        msleep(PWR_SLEEP_INTERVAL);
1783                }
1784
1785                if (!(tmp & PWR_AV_EN)) {
1786                        tmp |= PWR_AV_EN;
1787                        value[0] = (u8) tmp;
1788                        value[1] = (u8) (tmp >> 8);
1789                        value[2] = (u8) (tmp >> 16);
1790                        value[3] = (u8) (tmp >> 24);
1791                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1792                                                        PWR_CTL_EN, value, 4);
1793                        msleep(PWR_SLEEP_INTERVAL);
1794                }
1795                if (!(tmp & PWR_ISO_EN)) {
1796                        tmp |= PWR_ISO_EN;
1797                        value[0] = (u8) tmp;
1798                        value[1] = (u8) (tmp >> 8);
1799                        value[2] = (u8) (tmp >> 16);
1800                        value[3] = (u8) (tmp >> 24);
1801                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1802                                                        PWR_CTL_EN, value, 4);
1803                        msleep(PWR_SLEEP_INTERVAL);
1804                }
1805
1806                if (!(tmp & POLARIS_AVMODE_ANALOGT_TV)) {
1807                        tmp |= POLARIS_AVMODE_ANALOGT_TV;
1808                        value[0] = (u8) tmp;
1809                        value[1] = (u8) (tmp >> 8);
1810                        value[2] = (u8) (tmp >> 16);
1811                        value[3] = (u8) (tmp >> 24);
1812                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1813                                                        PWR_CTL_EN, value, 4);
1814                        msleep(PWR_SLEEP_INTERVAL);
1815                }
1816
1817                if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1818                    (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1819                        /* tuner path to channel 1 from port 3 */
1820                        cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1821
1822                        if (dev->cx231xx_reset_analog_tuner)
1823                                dev->cx231xx_reset_analog_tuner(dev);
1824                }
1825                break;
1826
1827        case POLARIS_AVMODE_DIGITAL:
1828                if (!(tmp & PWR_TUNER_EN)) {
1829                        tmp |= (PWR_TUNER_EN);
1830                        value[0] = (u8) tmp;
1831                        value[1] = (u8) (tmp >> 8);
1832                        value[2] = (u8) (tmp >> 16);
1833                        value[3] = (u8) (tmp >> 24);
1834                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1835                                                        PWR_CTL_EN, value, 4);
1836                        msleep(PWR_SLEEP_INTERVAL);
1837                }
1838                if (!(tmp & PWR_AV_EN)) {
1839                        tmp |= PWR_AV_EN;
1840                        value[0] = (u8) tmp;
1841                        value[1] = (u8) (tmp >> 8);
1842                        value[2] = (u8) (tmp >> 16);
1843                        value[3] = (u8) (tmp >> 24);
1844                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1845                                                        PWR_CTL_EN, value, 4);
1846                        msleep(PWR_SLEEP_INTERVAL);
1847                }
1848                if (!(tmp & PWR_ISO_EN)) {
1849                        tmp |= PWR_ISO_EN;
1850                        value[0] = (u8) tmp;
1851                        value[1] = (u8) (tmp >> 8);
1852                        value[2] = (u8) (tmp >> 16);
1853                        value[3] = (u8) (tmp >> 24);
1854                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1855                                                        PWR_CTL_EN, value, 4);
1856                        msleep(PWR_SLEEP_INTERVAL);
1857                }
1858
1859                tmp |= POLARIS_AVMODE_DIGITAL | I2C_DEMOD_EN;
1860                value[0] = (u8) tmp;
1861                value[1] = (u8) (tmp >> 8);
1862                value[2] = (u8) (tmp >> 16);
1863                value[3] = (u8) (tmp >> 24);
1864                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1865                                                PWR_CTL_EN, value, 4);
1866                msleep(PWR_SLEEP_INTERVAL);
1867
1868                if (!(tmp & PWR_DEMOD_EN)) {
1869                        tmp |= PWR_DEMOD_EN;
1870                        value[0] = (u8) tmp;
1871                        value[1] = (u8) (tmp >> 8);
1872                        value[2] = (u8) (tmp >> 16);
1873                        value[3] = (u8) (tmp >> 24);
1874                        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1875                                                        PWR_CTL_EN, value, 4);
1876                        msleep(PWR_SLEEP_INTERVAL);
1877                }
1878
1879                if ((dev->model == CX231XX_BOARD_CNXT_RDE_250) ||
1880                    (dev->model == CX231XX_BOARD_CNXT_RDU_250)) {
1881                        /* tuner path to channel 1 from port 3 */
1882                        cx231xx_enable_i2c_for_tuner(dev, I2C_3);
1883
1884                        if (dev->cx231xx_reset_analog_tuner)
1885                                dev->cx231xx_reset_analog_tuner(dev);
1886                }
1887                break;
1888
1889        default:
1890                break;
1891        }
1892
1893        msleep(PWR_SLEEP_INTERVAL);
1894
1895        /* For power saving, only enable Pwr_resetout_n
1896           when digital TV is selected. */
1897        if (mode == POLARIS_AVMODE_DIGITAL) {
1898                tmp |= PWR_RESETOUT_EN;
1899                value[0] = (u8) tmp;
1900                value[1] = (u8) (tmp >> 8);
1901                value[2] = (u8) (tmp >> 16);
1902                value[3] = (u8) (tmp >> 24);
1903                status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER,
1904                                                PWR_CTL_EN, value, 4);
1905                msleep(PWR_SLEEP_INTERVAL);
1906        }
1907
1908        /* update power control for afe */
1909        status = cx231xx_afe_update_power_control(dev, mode);
1910
1911        /* update power control for i2s_blk */
1912        status = cx231xx_i2s_blk_update_power_control(dev, mode);
1913
1914        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
1915                                       4);
1916        cx231xx_info(" The data of PWR_CTL_EN register 0x74"
1917                                 "=0x%0x,0x%0x,0x%0x,0x%0x\n",
1918                     value[0], value[1], value[2], value[3]);
1919
1920        return status;
1921}
1922
1923int cx231xx_power_suspend(struct cx231xx *dev)
1924{
1925        u8 value[4] = { 0, 0, 0, 0 };
1926        u32 tmp = 0;
1927        int status = 0;
1928
1929        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN,
1930                                       value, 4);
1931        if (status > 0)
1932                return status;
1933
1934        tmp = *((u32 *) value);
1935        tmp &= (~PWR_MODE_MASK);
1936
1937        value[0] = (u8) tmp;
1938        value[1] = (u8) (tmp >> 8);
1939        value[2] = (u8) (tmp >> 16);
1940        value[3] = (u8) (tmp >> 24);
1941        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, PWR_CTL_EN,
1942                                        value, 4);
1943
1944        return status;
1945}
1946
1947/******************************************************************************
1948 *                  S T R E A M    C O N T R O L   functions                  *
1949 ******************************************************************************/
1950int cx231xx_start_stream(struct cx231xx *dev, u32 ep_mask)
1951{
1952        u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1953        u32 tmp = 0;
1954        int status = 0;
1955
1956        cx231xx_info("cx231xx_start_stream():: ep_mask = %x\n", ep_mask);
1957        status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET,
1958                                       value, 4);
1959        if (status < 0)
1960                return status;
1961
1962        tmp = *((u32 *) value);
1963        tmp |= ep_mask;
1964        value[0] = (u8) tmp;
1965        value[1] = (u8) (tmp >> 8);
1966        value[2] = (u8) (tmp >> 16);
1967        value[3] = (u8) (tmp >> 24);
1968
1969        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1970                                        value, 4);
1971
1972        return status;
1973}
1974
1975int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask)
1976{
1977        u8 value[4] = { 0x0, 0x0, 0x0, 0x0 };
1978        u32 tmp = 0;
1979        int status = 0;
1980
1981        cx231xx_info("cx231xx_stop_stream():: ep_mask = %x\n", ep_mask);
1982        status =
1983            cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, EP_MODE_SET, value, 4);
1984        if (status < 0)
1985                return status;
1986
1987        tmp = *((u32 *) value);
1988        tmp &= (~ep_mask);
1989        value[0] = (u8) tmp;
1990        value[1] = (u8) (tmp >> 8);
1991        value[2] = (u8) (tmp >> 16);
1992        value[3] = (u8) (tmp >> 24);
1993
1994        status = cx231xx_write_ctrl_reg(dev, VRT_SET_REGISTER, EP_MODE_SET,
1995                                        value, 4);
1996
1997        return status;
1998}
1999
2000int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2001{
2002        int status = 0;
2003
2004        if (dev->udev->speed == USB_SPEED_HIGH) {
2005                switch (media_type) {
2006                case 81: /* audio */
2007                        cx231xx_info("%s: Audio enter HANC\n", __func__);
2008                        status =
2009                            cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
2010                        break;
2011
2012                case 2: /* vbi */
2013                        cx231xx_info("%s: set vanc registers\n", __func__);
2014                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x300);
2015                        break;
2016
2017                case 3: /* sliced cc */
2018                        cx231xx_info("%s: set hanc registers\n", __func__);
2019                        status =
2020                            cx231xx_mode_register(dev, TS_MODE_REG, 0x1300);
2021                        break;
2022
2023                case 0: /* video */
2024                        cx231xx_info("%s: set video registers\n", __func__);
2025                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2026                        break;
2027
2028                case 4: /* ts1 */
2029                        cx231xx_info("%s: set ts1 registers\n", __func__);
2030                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2031                        status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2032                        break;
2033                case 6: /* ts1 parallel mode */
2034                        cx231xx_info("%s: set ts1 parrallel mode registers\n",
2035                                     __func__);
2036                        status = cx231xx_mode_register(dev, TS_MODE_REG, 0x100);
2037                        status = cx231xx_mode_register(dev, TS1_CFG_REG, 0x400);
2038                        break;
2039                }
2040        } else {
2041                status = cx231xx_mode_register(dev, TS_MODE_REG, 0x101);
2042        }
2043
2044        return status;
2045}
2046
2047int cx231xx_capture_start(struct cx231xx *dev, int start, u8 media_type)
2048{
2049        int rc = -1;
2050        u32 ep_mask = -1;
2051        struct pcb_config *pcb_config;
2052
2053        /* get EP for media type */
2054        pcb_config = (struct pcb_config *)&dev->current_pcb_config;
2055
2056        if (pcb_config->config_num == 1) {
2057                switch (media_type) {
2058                case 0: /* Video */
2059                        ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2060                        break;
2061                case 1: /* Audio */
2062                        ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2063                        break;
2064                case 2: /* Vbi */
2065                        ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2066                        break;
2067                case 3: /* Sliced_cc */
2068                        ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2069                        break;
2070                case 4: /* ts1 */
2071                case 6: /* ts1 parallel mode */
2072                        ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2073                        break;
2074                case 5: /* ts2 */
2075                        ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2076                        break;
2077                }
2078
2079        } else if (pcb_config->config_num > 1) {
2080                switch (media_type) {
2081                case 0: /* Video */
2082                        ep_mask = ENABLE_EP4;   /* ep4  [00:1000] */
2083                        break;
2084                case 1: /* Audio */
2085                        ep_mask = ENABLE_EP3;   /* ep3  [00:0100] */
2086                        break;
2087                case 2: /* Vbi */
2088                        ep_mask = ENABLE_EP5;   /* ep5 [01:0000] */
2089                        break;
2090                case 3: /* Sliced_cc */
2091                        ep_mask = ENABLE_EP6;   /* ep6 [10:0000] */
2092                        break;
2093                case 4: /* ts1 */
2094                case 6: /* ts1 parallel mode */
2095                        ep_mask = ENABLE_EP1;   /* ep1 [00:0001] */
2096                        break;
2097                case 5: /* ts2 */
2098                        ep_mask = ENABLE_EP2;   /* ep2 [00:0010] */
2099                        break;
2100                }
2101
2102        }
2103
2104        if (start) {
2105                rc = cx231xx_initialize_stream_xfer(dev, media_type);
2106
2107                if (rc < 0)
2108                        return rc;
2109
2110                /* enable video capture */
2111                if (ep_mask > 0)
2112                        rc = cx231xx_start_stream(dev, ep_mask);
2113        } else {
2114                /* disable video capture */
2115                if (ep_mask > 0)
2116                        rc = cx231xx_stop_stream(dev, ep_mask);
2117        }
2118
2119        if (dev->mode == CX231XX_ANALOG_MODE)
2120                ;/* do any in Analog mode */
2121        else
2122                ;/* do any in digital mode */
2123
2124        return rc;
2125}
2126EXPORT_SYMBOL_GPL(cx231xx_capture_start);
2127
2128/*****************************************************************************
2129*                   G P I O   B I T control functions                        *
2130******************************************************************************/
2131int cx231xx_set_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2132{
2133        int status = 0;
2134
2135        status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 0);
2136
2137        return status;
2138}
2139
2140int cx231xx_get_gpio_bit(struct cx231xx *dev, u32 gpio_bit, u8 * gpio_val)
2141{
2142        int status = 0;
2143
2144        status = cx231xx_send_gpio_cmd(dev, gpio_bit, gpio_val, 4, 0, 1);
2145
2146        return status;
2147}
2148
2149/*
2150* cx231xx_set_gpio_direction
2151*      Sets the direction of the GPIO pin to input or output
2152*
2153* Parameters :
2154*      pin_number : The GPIO Pin number to program the direction for
2155*                   from 0 to 31
2156*      pin_value : The Direction of the GPIO Pin under reference.
2157*                      0 = Input direction
2158*                      1 = Output direction
2159*/
2160int cx231xx_set_gpio_direction(struct cx231xx *dev,
2161                               int pin_number, int pin_value)
2162{
2163        int status = 0;
2164        u32 value = 0;
2165
2166        /* Check for valid pin_number - if 32 , bail out */
2167        if (pin_number >= 32)
2168                return -EINVAL;
2169
2170        /* input */
2171        if (pin_value == 0)
2172                value = dev->gpio_dir & (~(1 << pin_number));   /* clear */
2173        else
2174                value = dev->gpio_dir | (1 << pin_number);
2175
2176        status = cx231xx_set_gpio_bit(dev, value, (u8 *) &dev->gpio_val);
2177
2178        /* cache the value for future */
2179        dev->gpio_dir = value;
2180
2181        return status;
2182}
2183
2184/*
2185* cx231xx_set_gpio_value
2186*      Sets the value of the GPIO pin to Logic high or low. The Pin under
2187*      reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2188*
2189* Parameters :
2190*      pin_number : The GPIO Pin number to program the direction for
2191*      pin_value : The value of the GPIO Pin under reference.
2192*                      0 = set it to 0
2193*                      1 = set it to 1
2194*/
2195int cx231xx_set_gpio_value(struct cx231xx *dev, int pin_number, int pin_value)
2196{
2197        int status = 0;
2198        u32 value = 0;
2199
2200        /* Check for valid pin_number - if 0xFF , bail out */
2201        if (pin_number >= 32)
2202                return -EINVAL;
2203
2204        /* first do a sanity check - if the Pin is not output, make it output */
2205        if ((dev->gpio_dir & (1 << pin_number)) == 0x00) {
2206                /* It was in input mode */
2207                value = dev->gpio_dir | (1 << pin_number);
2208                dev->gpio_dir = value;
2209                status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2210                                              (u8 *) &dev->gpio_val);
2211                value = 0;
2212        }
2213
2214        if (pin_value == 0)
2215                value = dev->gpio_val & (~(1 << pin_number));
2216        else
2217                value = dev->gpio_val | (1 << pin_number);
2218
2219        /* store the value */
2220        dev->gpio_val = value;
2221
2222        /* toggle bit0 of GP_IO */
2223        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2224
2225        return status;
2226}
2227
2228/*****************************************************************************
2229*                      G P I O I2C related functions                         *
2230******************************************************************************/
2231int cx231xx_gpio_i2c_start(struct cx231xx *dev)
2232{
2233        int status = 0;
2234
2235        /* set SCL to output 1 ; set SDA to output 1 */
2236        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2237        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2238        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2239        dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2240
2241        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2242        if (status < 0)
2243                return -EINVAL;
2244
2245        /* set SCL to output 1; set SDA to output 0 */
2246        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2247        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2248
2249        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2250        if (status < 0)
2251                return -EINVAL;
2252
2253        /* set SCL to output 0; set SDA to output 0      */
2254        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2255        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2256
2257        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2258        if (status < 0)
2259                return -EINVAL;
2260
2261        return status;
2262}
2263
2264int cx231xx_gpio_i2c_end(struct cx231xx *dev)
2265{
2266        int status = 0;
2267
2268        /* set SCL to output 0; set SDA to output 0      */
2269        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2270        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2271
2272        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2273        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2274
2275        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2276        if (status < 0)
2277                return -EINVAL;
2278
2279        /* set SCL to output 1; set SDA to output 0      */
2280        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2281        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2282
2283        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2284        if (status < 0)
2285                return -EINVAL;
2286
2287        /* set SCL to input ,release SCL cable control
2288           set SDA to input ,release SDA cable control */
2289        dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2290        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2291
2292        status =
2293            cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2294        if (status < 0)
2295                return -EINVAL;
2296
2297        return status;
2298}
2299
2300int cx231xx_gpio_i2c_write_byte(struct cx231xx *dev, u8 data)
2301{
2302        int status = 0;
2303        u8 i;
2304
2305        /* set SCL to output ; set SDA to output */
2306        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2307        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2308
2309        for (i = 0; i < 8; i++) {
2310                if (((data << i) & 0x80) == 0) {
2311                        /* set SCL to output 0; set SDA to output 0     */
2312                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2313                        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2314                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2315                                                      (u8 *)&dev->gpio_val);
2316
2317                        /* set SCL to output 1; set SDA to output 0     */
2318                        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2319                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2320                                                      (u8 *)&dev->gpio_val);
2321
2322                        /* set SCL to output 0; set SDA to output 0     */
2323                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2324                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2325                                                      (u8 *)&dev->gpio_val);
2326                } else {
2327                        /* set SCL to output 0; set SDA to output 1     */
2328                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2329                        dev->gpio_val |= 1 << dev->board.tuner_sda_gpio;
2330                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2331                                                      (u8 *)&dev->gpio_val);
2332
2333                        /* set SCL to output 1; set SDA to output 1     */
2334                        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2335                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2336                                                      (u8 *)&dev->gpio_val);
2337
2338                        /* set SCL to output 0; set SDA to output 1     */
2339                        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2340                        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2341                                                      (u8 *)&dev->gpio_val);
2342                }
2343        }
2344        return status;
2345}
2346
2347int cx231xx_gpio_i2c_read_byte(struct cx231xx *dev, u8 * buf)
2348{
2349        u8 value = 0;
2350        int status = 0;
2351        u32 gpio_logic_value = 0;
2352        u8 i;
2353
2354        /* read byte */
2355        for (i = 0; i < 8; i++) {       /* send write I2c addr */
2356
2357                /* set SCL to output 0; set SDA to input */
2358                dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2359                status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2360                                              (u8 *)&dev->gpio_val);
2361
2362                /* set SCL to output 1; set SDA to input */
2363                dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2364                status = cx231xx_set_gpio_bit(dev, dev->gpio_dir,
2365                                              (u8 *)&dev->gpio_val);
2366
2367                /* get SDA data bit */
2368                gpio_logic_value = dev->gpio_val;
2369                status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2370                                              (u8 *)&dev->gpio_val);
2371                if ((dev->gpio_val & (1 << dev->board.tuner_sda_gpio)) != 0)
2372                        value |= (1 << (8 - i - 1));
2373
2374                dev->gpio_val = gpio_logic_value;
2375        }
2376
2377        /* set SCL to output 0,finish the read latest SCL signal.
2378           !!!set SDA to input, never to modify SDA direction at
2379           the same times */
2380        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2381        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2382
2383        /* store the value */
2384        *buf = value & 0xff;
2385
2386        return status;
2387}
2388
2389int cx231xx_gpio_i2c_read_ack(struct cx231xx *dev)
2390{
2391        int status = 0;
2392        u32 gpio_logic_value = 0;
2393        int nCnt = 10;
2394        int nInit = nCnt;
2395
2396        /* clock stretch; set SCL to input; set SDA to input;
2397           get SCL value till SCL = 1 */
2398        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2399        dev->gpio_dir &= ~(1 << dev->board.tuner_scl_gpio);
2400
2401        gpio_logic_value = dev->gpio_val;
2402        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2403
2404        do {
2405                msleep(2);
2406                status = cx231xx_get_gpio_bit(dev, dev->gpio_dir,
2407                                              (u8 *)&dev->gpio_val);
2408                nCnt--;
2409        } while (((dev->gpio_val &
2410                          (1 << dev->board.tuner_scl_gpio)) == 0) &&
2411                         (nCnt > 0));
2412
2413        if (nCnt == 0)
2414                cx231xx_info("No ACK after %d msec -GPIO I2C failed!",
2415                             nInit * 10);
2416
2417        /*
2418         * readAck
2419         * through clock stretch, slave has given a SCL signal,
2420         * so the SDA data can be directly read.
2421         */
2422        status = cx231xx_get_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2423
2424        if ((dev->gpio_val & 1 << dev->board.tuner_sda_gpio) == 0) {
2425                dev->gpio_val = gpio_logic_value;
2426                dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2427                status = 0;
2428        } else {
2429                dev->gpio_val = gpio_logic_value;
2430                dev->gpio_val |= (1 << dev->board.tuner_sda_gpio);
2431        }
2432
2433        /* read SDA end, set the SCL to output 0, after this operation,
2434           SDA direction can be changed. */
2435        dev->gpio_val = gpio_logic_value;
2436        dev->gpio_dir |= (1 << dev->board.tuner_scl_gpio);
2437        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2438        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2439
2440        return status;
2441}
2442
2443int cx231xx_gpio_i2c_write_ack(struct cx231xx *dev)
2444{
2445        int status = 0;
2446
2447        /* set SDA to ouput */
2448        dev->gpio_dir |= 1 << dev->board.tuner_sda_gpio;
2449        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2450
2451        /* set SCL = 0 (output); set SDA = 0 (output) */
2452        dev->gpio_val &= ~(1 << dev->board.tuner_sda_gpio);
2453        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2454        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2455
2456        /* set SCL = 1 (output); set SDA = 0 (output) */
2457        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2458        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2459
2460        /* set SCL = 0 (output); set SDA = 0 (output) */
2461        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2462        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2463
2464        /* set SDA to input,and then the slave will read data from SDA. */
2465        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2466        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2467
2468        return status;
2469}
2470
2471int cx231xx_gpio_i2c_write_nak(struct cx231xx *dev)
2472{
2473        int status = 0;
2474
2475        /* set scl to output ; set sda to input */
2476        dev->gpio_dir |= 1 << dev->board.tuner_scl_gpio;
2477        dev->gpio_dir &= ~(1 << dev->board.tuner_sda_gpio);
2478        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2479
2480        /* set scl to output 0; set sda to input */
2481        dev->gpio_val &= ~(1 << dev->board.tuner_scl_gpio);
2482        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2483
2484        /* set scl to output 1; set sda to input */
2485        dev->gpio_val |= 1 << dev->board.tuner_scl_gpio;
2486        status = cx231xx_set_gpio_bit(dev, dev->gpio_dir, (u8 *)&dev->gpio_val);
2487
2488        return status;
2489}
2490
2491/*****************************************************************************
2492*                      G P I O I2C related functions                         *
2493******************************************************************************/
2494/* cx231xx_gpio_i2c_read
2495 * Function to read data from gpio based I2C interface
2496 */
2497int cx231xx_gpio_i2c_read(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2498{
2499        int status = 0;
2500        int i = 0;
2501
2502        /* get the lock */
2503        mutex_lock(&dev->gpio_i2c_lock);
2504
2505        /* start */
2506        status = cx231xx_gpio_i2c_start(dev);
2507
2508        /* write dev_addr */
2509        status = cx231xx_gpio_i2c_write_byte(dev, (dev_addr << 1) + 1);
2510
2511        /* readAck */
2512        status = cx231xx_gpio_i2c_read_ack(dev);
2513
2514        /* read data */
2515        for (i = 0; i < len; i++) {
2516                /* read data */
2517                buf[i] = 0;
2518                status = cx231xx_gpio_i2c_read_byte(dev, &buf[i]);
2519
2520                if ((i + 1) != len) {
2521                        /* only do write ack if we more length */
2522                        status = cx231xx_gpio_i2c_write_ack(dev);
2523                }
2524        }
2525
2526        /* write NAK - inform reads are complete */
2527        status = cx231xx_gpio_i2c_write_nak(dev);
2528
2529        /* write end */
2530        status = cx231xx_gpio_i2c_end(dev);
2531
2532        /* release the lock */
2533        mutex_unlock(&dev->gpio_i2c_lock);
2534
2535        return status;
2536}
2537
2538/* cx231xx_gpio_i2c_write
2539 * Function to write data to gpio based I2C interface
2540 */
2541int cx231xx_gpio_i2c_write(struct cx231xx *dev, u8 dev_addr, u8 * buf, u8 len)
2542{
2543        int status = 0;
2544        int i = 0;
2545
2546        /* get the lock */
2547        mutex_lock(&dev->gpio_i2c_lock);
2548
2549        /* start */
2550        status = cx231xx_gpio_i2c_start(dev);
2551
2552        /* write dev_addr */
2553        status = cx231xx_gpio_i2c_write_byte(dev, dev_addr << 1);
2554
2555        /* read Ack */
2556        status = cx231xx_gpio_i2c_read_ack(dev);
2557
2558        for (i = 0; i < len; i++) {
2559                /* Write data */
2560                status = cx231xx_gpio_i2c_write_byte(dev, buf[i]);
2561
2562                /* read Ack */
2563                status = cx231xx_gpio_i2c_read_ack(dev);
2564        }
2565
2566        /* write End */
2567        status = cx231xx_gpio_i2c_end(dev);
2568
2569        /* release the lock */
2570        mutex_unlock(&dev->gpio_i2c_lock);
2571
2572        return 0;
2573}
2574