linux/arch/powerpc/include/asm/reg_booke.h
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   1/*
   2 * Contains register definitions common to the Book E PowerPC
   3 * specification.  Notice that while the IBM-40x series of CPUs
   4 * are not true Book E PowerPCs, they borrowed a number of features
   5 * before Book E was finalized, and are included here as well.  Unfortunatly,
   6 * they sometimes used different locations than true Book E CPUs did.
   7 */
   8#ifdef __KERNEL__
   9#ifndef __ASM_POWERPC_REG_BOOKE_H__
  10#define __ASM_POWERPC_REG_BOOKE_H__
  11
  12/* Machine State Register (MSR) Fields */
  13#define MSR_GS          (1<<28) /* Guest state */
  14#define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
  15#define MSR_SPE         (1<<25) /* Enable SPE */
  16#define MSR_DWE         (1<<10) /* Debug Wait Enable */
  17#define MSR_UBLE        (1<<10) /* BTB lock enable (e500) */
  18#define MSR_IS          MSR_IR  /* Instruction Space */
  19#define MSR_DS          MSR_DR  /* Data Space */
  20#define MSR_PMM         (1<<2)  /* Performance monitor mark bit */
  21
  22/* Default MSR for kernel mode. */
  23#if defined (CONFIG_40x)
  24#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE)
  25#elif defined(CONFIG_BOOKE)
  26#define MSR_KERNEL      (MSR_ME|MSR_RI|MSR_CE)
  27#endif
  28
  29/* Special Purpose Registers (SPRNs)*/
  30#define SPRN_DECAR      0x036   /* Decrementer Auto Reload Register */
  31#define SPRN_IVPR       0x03F   /* Interrupt Vector Prefix Register */
  32#define SPRN_USPRG0     0x100   /* User Special Purpose Register General 0 */
  33#define SPRN_SPRG4R     0x104   /* Special Purpose Register General 4 Read */
  34#define SPRN_SPRG5R     0x105   /* Special Purpose Register General 5 Read */
  35#define SPRN_SPRG6R     0x106   /* Special Purpose Register General 6 Read */
  36#define SPRN_SPRG7R     0x107   /* Special Purpose Register General 7 Read */
  37#define SPRN_SPRG4W     0x114   /* Special Purpose Register General 4 Write */
  38#define SPRN_SPRG5W     0x115   /* Special Purpose Register General 5 Write */
  39#define SPRN_SPRG6W     0x116   /* Special Purpose Register General 6 Write */
  40#define SPRN_SPRG7W     0x117   /* Special Purpose Register General 7 Write */
  41#define SPRN_DBCR2      0x136   /* Debug Control Register 2 */
  42#define SPRN_IAC3       0x13A   /* Instruction Address Compare 3 */
  43#define SPRN_IAC4       0x13B   /* Instruction Address Compare 4 */
  44#define SPRN_DVC1       0x13E   /* Data Value Compare Register 1 */
  45#define SPRN_DVC2       0x13F   /* Data Value Compare Register 2 */
  46#define SPRN_IVOR0      0x190   /* Interrupt Vector Offset Register 0 */
  47#define SPRN_IVOR1      0x191   /* Interrupt Vector Offset Register 1 */
  48#define SPRN_IVOR2      0x192   /* Interrupt Vector Offset Register 2 */
  49#define SPRN_IVOR3      0x193   /* Interrupt Vector Offset Register 3 */
  50#define SPRN_IVOR4      0x194   /* Interrupt Vector Offset Register 4 */
  51#define SPRN_IVOR5      0x195   /* Interrupt Vector Offset Register 5 */
  52#define SPRN_IVOR6      0x196   /* Interrupt Vector Offset Register 6 */
  53#define SPRN_IVOR7      0x197   /* Interrupt Vector Offset Register 7 */
  54#define SPRN_IVOR8      0x198   /* Interrupt Vector Offset Register 8 */
  55#define SPRN_IVOR9      0x199   /* Interrupt Vector Offset Register 9 */
  56#define SPRN_IVOR10     0x19A   /* Interrupt Vector Offset Register 10 */
  57#define SPRN_IVOR11     0x19B   /* Interrupt Vector Offset Register 11 */
  58#define SPRN_IVOR12     0x19C   /* Interrupt Vector Offset Register 12 */
  59#define SPRN_IVOR13     0x19D   /* Interrupt Vector Offset Register 13 */
  60#define SPRN_IVOR14     0x19E   /* Interrupt Vector Offset Register 14 */
  61#define SPRN_IVOR15     0x19F   /* Interrupt Vector Offset Register 15 */
  62#define SPRN_SPEFSCR    0x200   /* SPE & Embedded FP Status & Control */
  63#define SPRN_BBEAR      0x201   /* Branch Buffer Entry Address Register */
  64#define SPRN_BBTAR      0x202   /* Branch Buffer Target Address Register */
  65#define SPRN_L1CFG0     0x203   /* L1 Cache Configure Register 0 */
  66#define SPRN_L1CFG1     0x204   /* L1 Cache Configure Register 1 */
  67#define SPRN_ATB        0x20E   /* Alternate Time Base */
  68#define SPRN_ATBL       0x20E   /* Alternate Time Base Lower */
  69#define SPRN_ATBU       0x20F   /* Alternate Time Base Upper */
  70#define SPRN_IVOR32     0x210   /* Interrupt Vector Offset Register 32 */
  71#define SPRN_IVOR33     0x211   /* Interrupt Vector Offset Register 33 */
  72#define SPRN_IVOR34     0x212   /* Interrupt Vector Offset Register 34 */
  73#define SPRN_IVOR35     0x213   /* Interrupt Vector Offset Register 35 */
  74#define SPRN_IVOR36     0x214   /* Interrupt Vector Offset Register 36 */
  75#define SPRN_IVOR37     0x215   /* Interrupt Vector Offset Register 37 */
  76#define SPRN_MCSRR0     0x23A   /* Machine Check Save and Restore Register 0 */
  77#define SPRN_MCSRR1     0x23B   /* Machine Check Save and Restore Register 1 */
  78#define SPRN_MCSR       0x23C   /* Machine Check Status Register */
  79#define SPRN_MCAR       0x23D   /* Machine Check Address Register */
  80#define SPRN_DSRR0      0x23E   /* Debug Save and Restore Register 0 */
  81#define SPRN_DSRR1      0x23F   /* Debug Save and Restore Register 1 */
  82#define SPRN_SPRG8      0x25C   /* Special Purpose Register General 8 */
  83#define SPRN_SPRG9      0x25D   /* Special Purpose Register General 9 */
  84#define SPRN_L1CSR2     0x25E   /* L1 Cache Control and Status Register 2 */
  85#define SPRN_MAS0       0x270   /* MMU Assist Register 0 */
  86#define SPRN_MAS1       0x271   /* MMU Assist Register 1 */
  87#define SPRN_MAS2       0x272   /* MMU Assist Register 2 */
  88#define SPRN_MAS3       0x273   /* MMU Assist Register 3 */
  89#define SPRN_MAS4       0x274   /* MMU Assist Register 4 */
  90#define SPRN_MAS5       0x275   /* MMU Assist Register 5 */
  91#define SPRN_MAS6       0x276   /* MMU Assist Register 6 */
  92#define SPRN_PID1       0x279   /* Process ID Register 1 */
  93#define SPRN_PID2       0x27A   /* Process ID Register 2 */
  94#define SPRN_TLB0CFG    0x2B0   /* TLB 0 Config Register */
  95#define SPRN_TLB1CFG    0x2B1   /* TLB 1 Config Register */
  96#define SPRN_EPR        0x2BE   /* External Proxy Register */
  97#define SPRN_CCR1       0x378   /* Core Configuration Register 1 */
  98#define SPRN_ZPR        0x3B0   /* Zone Protection Register (40x) */
  99#define SPRN_MAS7       0x3B0   /* MMU Assist Register 7 */
 100#define SPRN_MMUCR      0x3B2   /* MMU Control Register */
 101#define SPRN_CCR0       0x3B3   /* Core Configuration Register 0 */
 102#define SPRN_EPLC       0x3B3   /* External Process ID Load Context */
 103#define SPRN_EPSC       0x3B4   /* External Process ID Store Context */
 104#define SPRN_SGR        0x3B9   /* Storage Guarded Register */
 105#define SPRN_DCWR       0x3BA   /* Data Cache Write-thru Register */
 106#define SPRN_SLER       0x3BB   /* Little-endian real mode */
 107#define SPRN_SU0R       0x3BC   /* "User 0" real mode (40x) */
 108#define SPRN_DCMP       0x3D1   /* Data TLB Compare Register */
 109#define SPRN_ICDBDR     0x3D3   /* Instruction Cache Debug Data Register */
 110#define SPRN_EVPR       0x3D6   /* Exception Vector Prefix Register */
 111#define SPRN_L1CSR0     0x3F2   /* L1 Cache Control and Status Register 0 */
 112#define SPRN_L1CSR1     0x3F3   /* L1 Cache Control and Status Register 1 */
 113#define SPRN_MMUCSR0    0x3F4   /* MMU Control and Status Register 0 */
 114#define SPRN_MMUCFG     0x3F7   /* MMU Configuration Register */
 115#define SPRN_PIT        0x3DB   /* Programmable Interval Timer */
 116#define SPRN_BUCSR      0x3F5   /* Branch Unit Control and Status */
 117#define SPRN_L2CSR0     0x3F9   /* L2 Data Cache Control and Status Register 0 */
 118#define SPRN_L2CSR1     0x3FA   /* L2 Data Cache Control and Status Register 1 */
 119#define SPRN_DCCR       0x3FA   /* Data Cache Cacheability Register */
 120#define SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 121#define SPRN_SVR        0x3FF   /* System Version Register */
 122
 123/*
 124 * SPRs which have conflicting definitions on true Book E versus classic,
 125 * or IBM 40x.
 126 */
 127#ifdef CONFIG_BOOKE
 128#define SPRN_PID        0x030   /* Process ID */
 129#define SPRN_PID0       SPRN_PID/* Process ID Register 0 */
 130#define SPRN_CSRR0      0x03A   /* Critical Save and Restore Register 0 */
 131#define SPRN_CSRR1      0x03B   /* Critical Save and Restore Register 1 */
 132#define SPRN_DEAR       0x03D   /* Data Error Address Register */
 133#define SPRN_ESR        0x03E   /* Exception Syndrome Register */
 134#define SPRN_PIR        0x11E   /* Processor Identification Register */
 135#define SPRN_DBSR       0x130   /* Debug Status Register */
 136#define SPRN_DBCR0      0x134   /* Debug Control Register 0 */
 137#define SPRN_DBCR1      0x135   /* Debug Control Register 1 */
 138#define SPRN_IAC1       0x138   /* Instruction Address Compare 1 */
 139#define SPRN_IAC2       0x139   /* Instruction Address Compare 2 */
 140#define SPRN_DAC1       0x13C   /* Data Address Compare 1 */
 141#define SPRN_DAC2       0x13D   /* Data Address Compare 2 */
 142#define SPRN_TSR        0x150   /* Timer Status Register */
 143#define SPRN_TCR        0x154   /* Timer Control Register */
 144#endif /* Book E */
 145#ifdef CONFIG_40x
 146#define SPRN_PID        0x3B1   /* Process ID */
 147#define SPRN_DBCR1      0x3BD   /* Debug Control Register 1 */          
 148#define SPRN_ESR        0x3D4   /* Exception Syndrome Register */
 149#define SPRN_DEAR       0x3D5   /* Data Error Address Register */
 150#define SPRN_TSR        0x3D8   /* Timer Status Register */
 151#define SPRN_TCR        0x3DA   /* Timer Control Register */
 152#define SPRN_SRR2       0x3DE   /* Save/Restore Register 2 */
 153#define SPRN_SRR3       0x3DF   /* Save/Restore Register 3 */
 154#define SPRN_DBSR       0x3F0   /* Debug Status Register */             
 155#define SPRN_DBCR0      0x3F2   /* Debug Control Register 0 */
 156#define SPRN_DAC1       0x3F6   /* Data Address Compare 1 */
 157#define SPRN_DAC2       0x3F7   /* Data Address Compare 2 */
 158#define SPRN_CSRR0      SPRN_SRR2 /* Critical Save and Restore Register 0 */
 159#define SPRN_CSRR1      SPRN_SRR3 /* Critical Save and Restore Register 1 */
 160#endif
 161
 162/* Bit definitions for CCR1. */
 163#define CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
 164#define CCR1_TCS        0x00000080 /* Timer Clock Select */
 165
 166/* Bit definitions for the MCSR. */
 167#define MCSR_MCS        0x80000000 /* Machine Check Summary */
 168#define MCSR_IB         0x40000000 /* Instruction PLB Error */
 169#define MCSR_DRB        0x20000000 /* Data Read PLB Error */
 170#define MCSR_DWB        0x10000000 /* Data Write PLB Error */
 171#define MCSR_TLBP       0x08000000 /* TLB Parity Error */
 172#define MCSR_ICP        0x04000000 /* I-Cache Parity Error */
 173#define MCSR_DCSP       0x02000000 /* D-Cache Search Parity Error */
 174#define MCSR_DCFP       0x01000000 /* D-Cache Flush Parity Error */
 175#define MCSR_IMPE       0x00800000 /* Imprecise Machine Check Exception */
 176
 177#ifdef CONFIG_E500
 178#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
 179#define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
 180#define MCSR_DCP_PERR   0x20000000UL /* D-Cache Push Parity Error */
 181#define MCSR_DCPERR     0x10000000UL /* D-Cache Parity Error */
 182#define MCSR_BUS_IAERR  0x00000080UL /* Instruction Address Error */
 183#define MCSR_BUS_RAERR  0x00000040UL /* Read Address Error */
 184#define MCSR_BUS_WAERR  0x00000020UL /* Write Address Error */
 185#define MCSR_BUS_IBERR  0x00000010UL /* Instruction Data Error */
 186#define MCSR_BUS_RBERR  0x00000008UL /* Read Data Bus Error */
 187#define MCSR_BUS_WBERR  0x00000004UL /* Write Data Bus Error */
 188#define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
 189#define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
 190
 191/* e500 parts may set unused bits in MCSR; mask these off */
 192#define MCSR_MASK       (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
 193                        MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
 194                        MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
 195                        MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
 196#endif
 197#ifdef CONFIG_E200
 198#define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
 199#define MCSR_CP_PERR    0x20000000UL /* Cache Push Parity Error */
 200#define MCSR_CPERR      0x10000000UL /* Cache Parity Error */
 201#define MCSR_EXCP_ERR   0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
 202                                        fetch for an exception handler */
 203#define MCSR_BUS_IRERR  0x00000010UL /* Read Bus Error on instruction fetch*/
 204#define MCSR_BUS_DRERR  0x00000008UL /* Read Bus Error on data load */
 205#define MCSR_BUS_WRERR  0x00000004UL /* Write Bus Error on buffered
 206                                        store or cache line push */
 207
 208/* e200 parts may set unused bits in MCSR; mask these off */
 209#define MCSR_MASK       (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
 210                        MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
 211                        MCSR_BUS_WRERR)
 212#endif
 213
 214/* Bit definitions for the DBSR. */
 215/*
 216 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
 217 */
 218#ifdef CONFIG_BOOKE
 219#define DBSR_IC         0x08000000      /* Instruction Completion */
 220#define DBSR_BT         0x04000000      /* Branch Taken */
 221#define DBSR_IRPT       0x02000000      /* Exception Debug Event */
 222#define DBSR_TIE        0x01000000      /* Trap Instruction Event */
 223#define DBSR_IAC1       0x00800000      /* Instr Address Compare 1 Event */
 224#define DBSR_IAC2       0x00400000      /* Instr Address Compare 2 Event */
 225#define DBSR_IAC3       0x00200000      /* Instr Address Compare 3 Event */
 226#define DBSR_IAC4       0x00100000      /* Instr Address Compare 4 Event */
 227#define DBSR_DAC1R      0x00080000      /* Data Addr Compare 1 Read Event */
 228#define DBSR_DAC1W      0x00040000      /* Data Addr Compare 1 Write Event */
 229#define DBSR_DAC2R      0x00020000      /* Data Addr Compare 2 Read Event */
 230#define DBSR_DAC2W      0x00010000      /* Data Addr Compare 2 Write Event */
 231#define DBSR_RET        0x00008000      /* Return Debug Event */
 232#define DBSR_CIRPT      0x00000040      /* Critical Interrupt Taken Event */
 233#define DBSR_CRET       0x00000020      /* Critical Return Debug Event */
 234#endif
 235#ifdef CONFIG_40x
 236#define DBSR_IC         0x80000000      /* Instruction Completion */
 237#define DBSR_BT         0x40000000      /* Branch taken */
 238#define DBSR_IRPT       0x20000000      /* Exception Debug Event */
 239#define DBSR_TIE        0x10000000      /* Trap Instruction debug Event */
 240#define DBSR_IAC1       0x04000000      /* Instruction Address Compare 1 Event */
 241#define DBSR_IAC2       0x02000000      /* Instruction Address Compare 2 Event */
 242#define DBSR_IAC3       0x00080000      /* Instruction Address Compare 3 Event */
 243#define DBSR_IAC4       0x00040000      /* Instruction Address Compare 4 Event */
 244#define DBSR_DAC1R      0x01000000      /* Data Address Compare 1 Read Event */
 245#define DBSR_DAC1W      0x00800000      /* Data Address Compare 1 Write Event */
 246#define DBSR_DAC2R      0x00400000      /* Data Address Compare 2 Read Event */
 247#define DBSR_DAC2W      0x00200000      /* Data Address Compare 2 Write Event */
 248#endif
 249
 250/* Bit definitions related to the ESR. */
 251#define ESR_MCI         0x80000000      /* Machine Check - Instruction */
 252#define ESR_IMCP        0x80000000      /* Instr. Machine Check - Protection */
 253#define ESR_IMCN        0x40000000      /* Instr. Machine Check - Non-config */
 254#define ESR_IMCB        0x20000000      /* Instr. Machine Check - Bus error */
 255#define ESR_IMCT        0x10000000      /* Instr. Machine Check - Timeout */
 256#define ESR_PIL         0x08000000      /* Program Exception - Illegal */
 257#define ESR_PPR         0x04000000      /* Program Exception - Privileged */
 258#define ESR_PTR         0x02000000      /* Program Exception - Trap */
 259#define ESR_FP          0x01000000      /* Floating Point Operation */
 260#define ESR_DST         0x00800000      /* Storage Exception - Data miss */
 261#define ESR_DIZ         0x00400000      /* Storage Exception - Zone fault */
 262#define ESR_ST          0x00800000      /* Store Operation */
 263#define ESR_DLK         0x00200000      /* Data Cache Locking */
 264#define ESR_ILK         0x00100000      /* Instr. Cache Locking */
 265#define ESR_PUO         0x00040000      /* Unimplemented Operation exception */
 266#define ESR_BO          0x00020000      /* Byte Ordering */
 267
 268/* Bit definitions related to the DBCR0. */
 269#if defined(CONFIG_40x)
 270#define DBCR0_EDM       0x80000000      /* External Debug Mode */
 271#define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
 272#define DBCR0_RST       0x30000000      /* all the bits in the RST field */
 273#define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
 274#define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
 275#define DBCR0_RST_CORE  0x10000000      /* Core Reset */
 276#define DBCR0_RST_NONE  0x00000000      /* No Reset */
 277#define DBCR0_IC        0x08000000      /* Instruction Completion */
 278#define DBCR0_ICMP      DBCR0_IC
 279#define DBCR0_BT        0x04000000      /* Branch Taken */
 280#define DBCR0_BRT       DBCR0_BT
 281#define DBCR0_EDE       0x02000000      /* Exception Debug Event */
 282#define DBCR0_IRPT      DBCR0_EDE
 283#define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
 284#define DBCR0_IA1       0x00800000      /* Instr Addr compare 1 enable */
 285#define DBCR0_IAC1      DBCR0_IA1
 286#define DBCR0_IA2       0x00400000      /* Instr Addr compare 2 enable */
 287#define DBCR0_IAC2      DBCR0_IA2
 288#define DBCR0_IA12      0x00200000      /* Instr Addr 1-2 range enable */
 289#define DBCR0_IA12X     0x00100000      /* Instr Addr 1-2 range eXclusive */
 290#define DBCR0_IA3       0x00080000      /* Instr Addr compare 3 enable */
 291#define DBCR0_IAC3      DBCR0_IA3
 292#define DBCR0_IA4       0x00040000      /* Instr Addr compare 4 enable */
 293#define DBCR0_IAC4      DBCR0_IA4
 294#define DBCR0_IA34      0x00020000      /* Instr Addr 3-4 range Enable */
 295#define DBCR0_IA34X     0x00010000      /* Instr Addr 3-4 range eXclusive */
 296#define DBCR0_IA12T     0x00008000      /* Instr Addr 1-2 range Toggle */
 297#define DBCR0_IA34T     0x00004000      /* Instr Addr 3-4 range Toggle */
 298#define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
 299#elif defined(CONFIG_BOOKE)
 300#define DBCR0_EDM       0x80000000      /* External Debug Mode */
 301#define DBCR0_IDM       0x40000000      /* Internal Debug Mode */
 302#define DBCR0_RST       0x30000000      /* all the bits in the RST field */
 303/* DBCR0_RST_* is 44x specific and not followed in fsl booke */
 304#define DBCR0_RST_SYSTEM 0x30000000     /* System Reset */
 305#define DBCR0_RST_CHIP  0x20000000      /* Chip Reset */
 306#define DBCR0_RST_CORE  0x10000000      /* Core Reset */
 307#define DBCR0_RST_NONE  0x00000000      /* No Reset */
 308#define DBCR0_ICMP      0x08000000      /* Instruction Completion */
 309#define DBCR0_IC        DBCR0_ICMP
 310#define DBCR0_BRT       0x04000000      /* Branch Taken */
 311#define DBCR0_BT        DBCR0_BRT
 312#define DBCR0_IRPT      0x02000000      /* Exception Debug Event */
 313#define DBCR0_TDE       0x01000000      /* TRAP Debug Event */
 314#define DBCR0_TIE       DBCR0_TDE
 315#define DBCR0_IAC1      0x00800000      /* Instr Addr compare 1 enable */
 316#define DBCR0_IAC2      0x00400000      /* Instr Addr compare 2 enable */
 317#define DBCR0_IAC3      0x00200000      /* Instr Addr compare 3 enable */
 318#define DBCR0_IAC4      0x00100000      /* Instr Addr compare 4 enable */
 319#define DBCR0_DAC1R     0x00080000      /* DAC 1 Read enable */
 320#define DBCR0_DAC1W     0x00040000      /* DAC 1 Write enable */
 321#define DBCR0_DAC2R     0x00020000      /* DAC 2 Read enable */
 322#define DBCR0_DAC2W     0x00010000      /* DAC 2 Write enable */
 323#define DBCR0_RET       0x00008000      /* Return Debug Event */
 324#define DBCR0_CIRPT     0x00000040      /* Critical Interrupt Taken Event */
 325#define DBCR0_CRET      0x00000020      /* Critical Return Debug Event */
 326#define DBCR0_FT        0x00000001      /* Freeze Timers on debug event */
 327
 328/* Bit definitions related to the DBCR1. */
 329#define DBCR1_IAC12M    0x00800000      /* Instr Addr 1-2 range enable */
 330#define DBCR1_IAC12MX   0x00C00000      /* Instr Addr 1-2 range eXclusive */
 331#define DBCR1_IAC12AT   0x00010000      /* Instr Addr 1-2 range Toggle */
 332#define DBCR1_IAC34M    0x00000080      /* Instr Addr 3-4 range enable */
 333#define DBCR1_IAC34MX   0x000000C0      /* Instr Addr 3-4 range eXclusive */
 334#define DBCR1_IAC34AT   0x00000001      /* Instr Addr 3-4 range Toggle */
 335
 336/* Bit definitions related to the DBCR2. */
 337#define DBCR2_DAC12M    0x00800000      /* DAC 1-2 range enable */
 338#define DBCR2_DAC12MX   0x00C00000      /* DAC 1-2 range eXclusive */
 339#define DBCR2_DAC12A    0x00200000      /* DAC 1-2 Asynchronous */
 340#endif
 341
 342/* Bit definitions related to the TCR. */
 343#define TCR_WP(x)       (((x)&0x3)<<30) /* WDT Period */
 344#define TCR_WP_MASK     TCR_WP(3)
 345#define WP_2_17         0               /* 2^17 clocks */
 346#define WP_2_21         1               /* 2^21 clocks */
 347#define WP_2_25         2               /* 2^25 clocks */
 348#define WP_2_29         3               /* 2^29 clocks */
 349#define TCR_WRC(x)      (((x)&0x3)<<28) /* WDT Reset Control */
 350#define TCR_WRC_MASK    TCR_WRC(3)
 351#define WRC_NONE        0               /* No reset will occur */
 352#define WRC_CORE        1               /* Core reset will occur */
 353#define WRC_CHIP        2               /* Chip reset will occur */
 354#define WRC_SYSTEM      3               /* System reset will occur */
 355#define TCR_WIE         0x08000000      /* WDT Interrupt Enable */
 356#define TCR_PIE         0x04000000      /* PIT Interrupt Enable */
 357#define TCR_DIE         TCR_PIE         /* DEC Interrupt Enable */
 358#define TCR_FP(x)       (((x)&0x3)<<24) /* FIT Period */
 359#define TCR_FP_MASK     TCR_FP(3)
 360#define FP_2_9          0               /* 2^9 clocks */
 361#define FP_2_13         1               /* 2^13 clocks */
 362#define FP_2_17         2               /* 2^17 clocks */
 363#define FP_2_21         3               /* 2^21 clocks */
 364#define TCR_FIE         0x00800000      /* FIT Interrupt Enable */
 365#define TCR_ARE         0x00400000      /* Auto Reload Enable */
 366
 367/* Bit definitions for the TSR. */
 368#define TSR_ENW         0x80000000      /* Enable Next Watchdog */
 369#define TSR_WIS         0x40000000      /* WDT Interrupt Status */
 370#define TSR_WRS(x)      (((x)&0x3)<<28) /* WDT Reset Status */
 371#define WRS_NONE        0               /* No WDT reset occurred */
 372#define WRS_CORE        1               /* WDT forced core reset */
 373#define WRS_CHIP        2               /* WDT forced chip reset */
 374#define WRS_SYSTEM      3               /* WDT forced system reset */
 375#define TSR_PIS         0x08000000      /* PIT Interrupt Status */
 376#define TSR_DIS         TSR_PIS         /* DEC Interrupt Status */
 377#define TSR_FIS         0x04000000      /* FIT Interrupt Status */
 378
 379/* Bit definitions for the DCCR. */
 380#define DCCR_NOCACHE    0               /* Noncacheable */
 381#define DCCR_CACHE      1               /* Cacheable */
 382
 383/* Bit definitions for DCWR. */
 384#define DCWR_COPY       0               /* Copy-back */
 385#define DCWR_WRITE      1               /* Write-through */
 386
 387/* Bit definitions for ICCR. */
 388#define ICCR_NOCACHE    0               /* Noncacheable */
 389#define ICCR_CACHE      1               /* Cacheable */
 390
 391/* Bit definitions for L1CSR0. */
 392#define L1CSR0_CLFC     0x00000100      /* Cache Lock Bits Flash Clear */
 393#define L1CSR0_DCFI     0x00000002      /* Data Cache Flash Invalidate */
 394#define L1CSR0_CFI      0x00000002      /* Cache Flash Invalidate */
 395#define L1CSR0_DCE      0x00000001      /* Data Cache Enable */
 396
 397/* Bit definitions for L1CSR1. */
 398#define L1CSR1_ICLFR    0x00000100      /* Instr Cache Lock Bits Flash Reset */
 399#define L1CSR1_ICFI     0x00000002      /* Instr Cache Flash Invalidate */
 400#define L1CSR1_ICE      0x00000001      /* Instr Cache Enable */
 401
 402/* Bit definitions for L2CSR0. */
 403#define L2CSR0_L2E      0x80000000      /* L2 Cache Enable */
 404#define L2CSR0_L2PE     0x40000000      /* L2 Cache Parity/ECC Enable */
 405#define L2CSR0_L2WP     0x1c000000      /* L2 I/D Way Partioning */
 406#define L2CSR0_L2CM     0x03000000      /* L2 Cache Coherency Mode */
 407#define L2CSR0_L2FI     0x00200000      /* L2 Cache Flash Invalidate */
 408#define L2CSR0_L2IO     0x00100000      /* L2 Cache Instruction Only */
 409#define L2CSR0_L2DO     0x00010000      /* L2 Cache Data Only */
 410#define L2CSR0_L2REP    0x00003000      /* L2 Line Replacement Algo */
 411#define L2CSR0_L2FL     0x00000800      /* L2 Cache Flush */
 412#define L2CSR0_L2LFC    0x00000400      /* L2 Cache Lock Flash Clear */
 413#define L2CSR0_L2LOA    0x00000080      /* L2 Cache Lock Overflow Allocate */
 414#define L2CSR0_L2LO     0x00000020      /* L2 Cache Lock Overflow */
 415
 416/* Bit definitions for MMUCSR0 */
 417#define MMUCSR0_TLB1FI  0x00000002      /* TLB1 Flash invalidate */
 418#define MMUCSR0_TLB0FI  0x00000004      /* TLB0 Flash invalidate */
 419#define MMUCSR0_TLB2FI  0x00000040      /* TLB2 Flash invalidate */
 420#define MMUCSR0_TLB3FI  0x00000020      /* TLB3 Flash invalidate */
 421
 422/* Bit definitions for SGR. */
 423#define SGR_NORMAL      0               /* Speculative fetching allowed. */
 424#define SGR_GUARDED     1               /* Speculative fetching disallowed. */
 425
 426/*
 427 * The IBM-403 is an even more odd special case, as it is much
 428 * older than the IBM-405 series.  We put these down here incase someone
 429 * wishes to support these machines again.
 430 */
 431#ifdef CONFIG_403GCX
 432/* Special Purpose Registers (SPRNs)*/
 433#define SPRN_TBHU       0x3CC   /* Time Base High User-mode */
 434#define SPRN_TBLU       0x3CD   /* Time Base Low User-mode */
 435#define SPRN_CDBCR      0x3D7   /* Cache Debug Control Register */
 436#define SPRN_TBHI       0x3DC   /* Time Base High */
 437#define SPRN_TBLO       0x3DD   /* Time Base Low */
 438#define SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
 439#define SPRN_PBL1       0x3FC   /* Protection Bound Lower 1 */
 440#define SPRN_PBL2       0x3FE   /* Protection Bound Lower 2 */
 441#define SPRN_PBU1       0x3FD   /* Protection Bound Upper 1 */
 442#define SPRN_PBU2       0x3FF   /* Protection Bound Upper 2 */
 443
 444
 445/* Bit definitions for the DBCR. */
 446#define DBCR_EDM        DBCR0_EDM
 447#define DBCR_IDM        DBCR0_IDM
 448#define DBCR_RST(x)     (((x) & 0x3) << 28)
 449#define DBCR_RST_NONE   0
 450#define DBCR_RST_CORE   1
 451#define DBCR_RST_CHIP   2
 452#define DBCR_RST_SYSTEM 3
 453#define DBCR_IC         DBCR0_IC        /* Instruction Completion Debug Evnt */
 454#define DBCR_BT         DBCR0_BT        /* Branch Taken Debug Event */
 455#define DBCR_EDE        DBCR0_EDE       /* Exception Debug Event */
 456#define DBCR_TDE        DBCR0_TDE       /* TRAP Debug Event */
 457#define DBCR_FER        0x00F80000      /* First Events Remaining Mask */
 458#define DBCR_FT         0x00040000      /* Freeze Timers on Debug Event */
 459#define DBCR_IA1        0x00020000      /* Instr. Addr. Compare 1 Enable */
 460#define DBCR_IA2        0x00010000      /* Instr. Addr. Compare 2 Enable */
 461#define DBCR_D1R        0x00008000      /* Data Addr. Compare 1 Read Enable */
 462#define DBCR_D1W        0x00004000      /* Data Addr. Compare 1 Write Enable */
 463#define DBCR_D1S(x)     (((x) & 0x3) << 12)     /* Data Adrr. Compare 1 Size */
 464#define DAC_BYTE        0
 465#define DAC_HALF        1
 466#define DAC_WORD        2
 467#define DAC_QUAD        3
 468#define DBCR_D2R        0x00000800      /* Data Addr. Compare 2 Read Enable */
 469#define DBCR_D2W        0x00000400      /* Data Addr. Compare 2 Write Enable */
 470#define DBCR_D2S(x)     (((x) & 0x3) << 8)      /* Data Addr. Compare 2 Size */
 471#define DBCR_SBT        0x00000040      /* Second Branch Taken Debug Event */
 472#define DBCR_SED        0x00000020      /* Second Exception Debug Event */
 473#define DBCR_STD        0x00000010      /* Second Trap Debug Event */
 474#define DBCR_SIA        0x00000008      /* Second IAC Enable */
 475#define DBCR_SDA        0x00000004      /* Second DAC Enable */
 476#define DBCR_JOI        0x00000002      /* JTAG Serial Outbound Int. Enable */
 477#define DBCR_JII        0x00000001      /* JTAG Serial Inbound Int. Enable */
 478#endif /* 403GCX */
 479#endif /* __ASM_POWERPC_REG_BOOKE_H__ */
 480#endif /* __KERNEL__ */
 481