linux/arch/powerpc/include/asm/mpc52xx_psc.h
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   1/*
   2 * include/asm-ppc/mpc52xx_psc.h
   3 *
   4 * Definitions of consts/structs to drive the Freescale MPC52xx OnChip
   5 * PSCs. Theses are shared between multiple drivers since a PSC can be
   6 * UART, AC97, IR, I2S, ... So this header is in asm-ppc.
   7 *
   8 *
   9 * Maintainer : Sylvain Munaut <tnt@246tNt.com>
  10 *
  11 * Based/Extracted from some header of the 2.4 originally written by
  12 * Dale Farnsworth <dfarnsworth@mvista.com>
  13 *
  14 * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
  15 * Copyright (C) 2003 MontaVista, Software, Inc.
  16 *
  17 * This file is licensed under the terms of the GNU General Public License
  18 * version 2. This program is licensed "as is" without any warranty of any
  19 * kind, whether express or implied.
  20 */
  21
  22#ifndef __ASM_MPC52xx_PSC_H__
  23#define __ASM_MPC52xx_PSC_H__
  24
  25#include <asm/types.h>
  26
  27/* Max number of PSCs */
  28#define MPC52xx_PSC_MAXNUM      6
  29
  30/* Programmable Serial Controller (PSC) status register bits */
  31#define MPC52xx_PSC_SR_CDE      0x0080
  32#define MPC52xx_PSC_SR_RXRDY    0x0100
  33#define MPC52xx_PSC_SR_RXFULL   0x0200
  34#define MPC52xx_PSC_SR_TXRDY    0x0400
  35#define MPC52xx_PSC_SR_TXEMP    0x0800
  36#define MPC52xx_PSC_SR_OE       0x1000
  37#define MPC52xx_PSC_SR_PE       0x2000
  38#define MPC52xx_PSC_SR_FE       0x4000
  39#define MPC52xx_PSC_SR_RB       0x8000
  40
  41/* PSC Command values */
  42#define MPC52xx_PSC_RX_ENABLE           0x0001
  43#define MPC52xx_PSC_RX_DISABLE          0x0002
  44#define MPC52xx_PSC_TX_ENABLE           0x0004
  45#define MPC52xx_PSC_TX_DISABLE          0x0008
  46#define MPC52xx_PSC_SEL_MODE_REG_1      0x0010
  47#define MPC52xx_PSC_RST_RX              0x0020
  48#define MPC52xx_PSC_RST_TX              0x0030
  49#define MPC52xx_PSC_RST_ERR_STAT        0x0040
  50#define MPC52xx_PSC_RST_BRK_CHG_INT     0x0050
  51#define MPC52xx_PSC_START_BRK           0x0060
  52#define MPC52xx_PSC_STOP_BRK            0x0070
  53
  54/* PSC TxRx FIFO status bits */
  55#define MPC52xx_PSC_RXTX_FIFO_ERR       0x0040
  56#define MPC52xx_PSC_RXTX_FIFO_UF        0x0020
  57#define MPC52xx_PSC_RXTX_FIFO_OF        0x0010
  58#define MPC52xx_PSC_RXTX_FIFO_FR        0x0008
  59#define MPC52xx_PSC_RXTX_FIFO_FULL      0x0004
  60#define MPC52xx_PSC_RXTX_FIFO_ALARM     0x0002
  61#define MPC52xx_PSC_RXTX_FIFO_EMPTY     0x0001
  62
  63/* PSC interrupt status/mask bits */
  64#define MPC52xx_PSC_IMR_TXRDY           0x0100
  65#define MPC52xx_PSC_IMR_RXRDY           0x0200
  66#define MPC52xx_PSC_IMR_DB              0x0400
  67#define MPC52xx_PSC_IMR_TXEMP           0x0800
  68#define MPC52xx_PSC_IMR_ORERR           0x1000
  69#define MPC52xx_PSC_IMR_IPC             0x8000
  70
  71/* PSC input port change bits */
  72#define MPC52xx_PSC_CTS                 0x01
  73#define MPC52xx_PSC_DCD                 0x02
  74#define MPC52xx_PSC_D_CTS               0x10
  75#define MPC52xx_PSC_D_DCD               0x20
  76
  77/* PSC acr bits */
  78#define MPC52xx_PSC_IEC_CTS             0x01
  79#define MPC52xx_PSC_IEC_DCD             0x02
  80
  81/* PSC output port bits */
  82#define MPC52xx_PSC_OP_RTS              0x01
  83#define MPC52xx_PSC_OP_RES              0x02
  84
  85/* PSC mode fields */
  86#define MPC52xx_PSC_MODE_5_BITS                 0x00
  87#define MPC52xx_PSC_MODE_6_BITS                 0x01
  88#define MPC52xx_PSC_MODE_7_BITS                 0x02
  89#define MPC52xx_PSC_MODE_8_BITS                 0x03
  90#define MPC52xx_PSC_MODE_BITS_MASK              0x03
  91#define MPC52xx_PSC_MODE_PAREVEN                0x00
  92#define MPC52xx_PSC_MODE_PARODD                 0x04
  93#define MPC52xx_PSC_MODE_PARFORCE               0x08
  94#define MPC52xx_PSC_MODE_PARNONE                0x10
  95#define MPC52xx_PSC_MODE_ERR                    0x20
  96#define MPC52xx_PSC_MODE_FFULL                  0x40
  97#define MPC52xx_PSC_MODE_RXRTS                  0x80
  98
  99#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS        0x00
 100#define MPC52xx_PSC_MODE_ONE_STOP               0x07
 101#define MPC52xx_PSC_MODE_TWO_STOP               0x0f
 102#define MPC52xx_PSC_MODE_TXCTS                  0x10
 103
 104#define MPC52xx_PSC_RFNUM_MASK  0x01ff
 105
 106#define MPC52xx_PSC_SICR_DTS1                   (1 << 29)
 107#define MPC52xx_PSC_SICR_SHDR                   (1 << 28)
 108#define MPC52xx_PSC_SICR_SIM_MASK               (0xf << 24)
 109#define MPC52xx_PSC_SICR_SIM_UART               (0x0 << 24)
 110#define MPC52xx_PSC_SICR_SIM_UART_DCD           (0x8 << 24)
 111#define MPC52xx_PSC_SICR_SIM_CODEC_8            (0x1 << 24)
 112#define MPC52xx_PSC_SICR_SIM_CODEC_16           (0x2 << 24)
 113#define MPC52xx_PSC_SICR_SIM_AC97               (0x3 << 24)
 114#define MPC52xx_PSC_SICR_SIM_SIR                (0x8 << 24)
 115#define MPC52xx_PSC_SICR_SIM_SIR_DCD            (0xc << 24)
 116#define MPC52xx_PSC_SICR_SIM_MIR                (0x5 << 24)
 117#define MPC52xx_PSC_SICR_SIM_FIR                (0x6 << 24)
 118#define MPC52xx_PSC_SICR_SIM_CODEC_24           (0x7 << 24)
 119#define MPC52xx_PSC_SICR_SIM_CODEC_32           (0xf << 24)
 120#define MPC52xx_PSC_SICR_GENCLK                 (1 << 23)
 121#define MPC52xx_PSC_SICR_I2S                    (1 << 22)
 122#define MPC52xx_PSC_SICR_CLKPOL                 (1 << 21)
 123#define MPC52xx_PSC_SICR_SYNCPOL                (1 << 20)
 124#define MPC52xx_PSC_SICR_CELLSLAVE              (1 << 19)
 125#define MPC52xx_PSC_SICR_CELL2XCLK              (1 << 18)
 126#define MPC52xx_PSC_SICR_ESAI                   (1 << 17)
 127#define MPC52xx_PSC_SICR_ENAC97                 (1 << 16)
 128#define MPC52xx_PSC_SICR_SPI                    (1 << 15)
 129#define MPC52xx_PSC_SICR_MSTR                   (1 << 14)
 130#define MPC52xx_PSC_SICR_CPOL                   (1 << 13)
 131#define MPC52xx_PSC_SICR_CPHA                   (1 << 12)
 132#define MPC52xx_PSC_SICR_USEEOF                 (1 << 11)
 133#define MPC52xx_PSC_SICR_DISABLEEOF             (1 << 10)
 134
 135/* Structure of the hardware registers */
 136struct mpc52xx_psc {
 137        u8              mode;           /* PSC + 0x00 */
 138        u8              reserved0[3];
 139        union {                         /* PSC + 0x04 */
 140                u16     status;
 141                u16     clock_select;
 142        } sr_csr;
 143#define mpc52xx_psc_status      sr_csr.status
 144#define mpc52xx_psc_clock_select sr_csr.clock_select
 145        u16             reserved1;
 146        u8              command;        /* PSC + 0x08 */
 147        u8              reserved2[3];
 148        union {                         /* PSC + 0x0c */
 149                u8      buffer_8;
 150                u16     buffer_16;
 151                u32     buffer_32;
 152        } buffer;
 153#define mpc52xx_psc_buffer_8    buffer.buffer_8
 154#define mpc52xx_psc_buffer_16   buffer.buffer_16
 155#define mpc52xx_psc_buffer_32   buffer.buffer_32
 156        union {                         /* PSC + 0x10 */
 157                u8      ipcr;
 158                u8      acr;
 159        } ipcr_acr;
 160#define mpc52xx_psc_ipcr        ipcr_acr.ipcr
 161#define mpc52xx_psc_acr         ipcr_acr.acr
 162        u8              reserved3[3];
 163        union {                         /* PSC + 0x14 */
 164                u16     isr;
 165                u16     imr;
 166        } isr_imr;
 167#define mpc52xx_psc_isr         isr_imr.isr
 168#define mpc52xx_psc_imr         isr_imr.imr
 169        u16             reserved4;
 170        u8              ctur;           /* PSC + 0x18 */
 171        u8              reserved5[3];
 172        u8              ctlr;           /* PSC + 0x1c */
 173        u8              reserved6[3];
 174        /* BitClkDiv field of CCR is byte swapped in
 175         * the hardware for mpc5200/b compatibility */
 176        u32             ccr;            /* PSC + 0x20 */
 177        u32             ac97_slots;     /* PSC + 0x24 */
 178        u32             ac97_cmd;       /* PSC + 0x28 */
 179        u32             ac97_data;      /* PSC + 0x2c */
 180        u8              ivr;            /* PSC + 0x30 */
 181        u8              reserved8[3];
 182        u8              ip;             /* PSC + 0x34 */
 183        u8              reserved9[3];
 184        u8              op1;            /* PSC + 0x38 */
 185        u8              reserved10[3];
 186        u8              op0;            /* PSC + 0x3c */
 187        u8              reserved11[3];
 188        u32             sicr;           /* PSC + 0x40 */
 189        u8              ircr1;          /* PSC + 0x44 */
 190        u8              reserved13[3];
 191        u8              ircr2;          /* PSC + 0x44 */
 192        u8              reserved14[3];
 193        u8              irsdr;          /* PSC + 0x4c */
 194        u8              reserved15[3];
 195        u8              irmdr;          /* PSC + 0x50 */
 196        u8              reserved16[3];
 197        u8              irfdr;          /* PSC + 0x54 */
 198        u8              reserved17[3];
 199};
 200
 201struct mpc52xx_psc_fifo {
 202        u16             rfnum;          /* PSC + 0x58 */
 203        u16             reserved18;
 204        u16             tfnum;          /* PSC + 0x5c */
 205        u16             reserved19;
 206        u32             rfdata;         /* PSC + 0x60 */
 207        u16             rfstat;         /* PSC + 0x64 */
 208        u16             reserved20;
 209        u8              rfcntl;         /* PSC + 0x68 */
 210        u8              reserved21[5];
 211        u16             rfalarm;        /* PSC + 0x6e */
 212        u16             reserved22;
 213        u16             rfrptr;         /* PSC + 0x72 */
 214        u16             reserved23;
 215        u16             rfwptr;         /* PSC + 0x76 */
 216        u16             reserved24;
 217        u16             rflrfptr;       /* PSC + 0x7a */
 218        u16             reserved25;
 219        u16             rflwfptr;       /* PSC + 0x7e */
 220        u32             tfdata;         /* PSC + 0x80 */
 221        u16             tfstat;         /* PSC + 0x84 */
 222        u16             reserved26;
 223        u8              tfcntl;         /* PSC + 0x88 */
 224        u8              reserved27[5];
 225        u16             tfalarm;        /* PSC + 0x8e */
 226        u16             reserved28;
 227        u16             tfrptr;         /* PSC + 0x92 */
 228        u16             reserved29;
 229        u16             tfwptr;         /* PSC + 0x96 */
 230        u16             reserved30;
 231        u16             tflrfptr;       /* PSC + 0x9a */
 232        u16             reserved31;
 233        u16             tflwfptr;       /* PSC + 0x9e */
 234};
 235
 236#define MPC512x_PSC_FIFO_RESET_SLICE    0x80
 237#define MPC512x_PSC_FIFO_ENABLE_SLICE   0x01
 238#define MPC512x_PSC_FIFO_ENABLE_DMA     0x04
 239
 240#define MPC512x_PSC_FIFO_EMPTY          0x1
 241#define MPC512x_PSC_FIFO_FULL           0x2
 242#define MPC512x_PSC_FIFO_ALARM          0x4
 243#define MPC512x_PSC_FIFO_URERR          0x8
 244#define MPC512x_PSC_FIFO_ORERR          0x01
 245#define MPC512x_PSC_FIFO_MEMERROR       0x02
 246
 247struct mpc512x_psc_fifo {
 248        u32             reserved1[10];
 249        u32             txcmd;          /* PSC + 0x80 */
 250        u32             txalarm;        /* PSC + 0x84 */
 251        u32             txsr;           /* PSC + 0x88 */
 252        u32             txisr;          /* PSC + 0x8c */
 253        u32             tximr;          /* PSC + 0x90 */
 254        u32             txcnt;          /* PSC + 0x94 */
 255        u32             txptr;          /* PSC + 0x98 */
 256        u32             txsz;           /* PSC + 0x9c */
 257        u32             reserved2[7];
 258        union {
 259                u8      txdata_8;
 260                u16     txdata_16;
 261                u32     txdata_32;
 262        } txdata;                       /* PSC + 0xbc */
 263#define txdata_8 txdata.txdata_8
 264#define txdata_16 txdata.txdata_16
 265#define txdata_32 txdata.txdata_32
 266        u32             rxcmd;          /* PSC + 0xc0 */
 267        u32             rxalarm;        /* PSC + 0xc4 */
 268        u32             rxsr;           /* PSC + 0xc8 */
 269        u32             rxisr;          /* PSC + 0xcc */
 270        u32             rximr;          /* PSC + 0xd0 */
 271        u32             rxcnt;          /* PSC + 0xd4 */
 272        u32             rxptr;          /* PSC + 0xd8 */
 273        u32             rxsz;           /* PSC + 0xdc */
 274        u32             reserved3[7];
 275        union {
 276                u8      rxdata_8;
 277                u16     rxdata_16;
 278                u32     rxdata_32;
 279        } rxdata;                       /* PSC + 0xfc */
 280#define rxdata_8 rxdata.rxdata_8
 281#define rxdata_16 rxdata.rxdata_16
 282#define rxdata_32 rxdata.rxdata_32
 283};
 284
 285#endif  /* __ASM_MPC52xx_PSC_H__ */
 286