LXR linux/arch/powerpc/include/asm/io.h

   1#ifndef _ASM_POWERPC_IO_H
   2#define _ASM_POWERPC_IO_H
   3#ifdef __KERNEL__
   4
   5/*
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License
   8 * as published by the Free Software Foundation; either version
   9 * 2 of the License, or (at your option) any later version.
  10 */
  11
  12/* Check of existence of legacy devices */
  13extern int check_legacy_ioport(unsigned long base_port);
  14#define I8042_DATA_REG  0x60
  15#define FDC_BASE        0x3f0
  16/* only relevant for PReP */
  17#define _PIDXR          0x279
  18#define _PNPWRP         0xa79
  19#define PNPBIOS_BASE    0xf000
  20
  21#include <linux/device.h>
  22#include <linux/io.h>
  23
  24#include <linux/compiler.h>
  25#include <asm/page.h>
  26#include <asm/byteorder.h>
  27#include <asm/synch.h>
  28#include <asm/delay.h>
  29#include <asm/mmu.h>
  30
  31#include <asm-generic/iomap.h>
  32
  33#ifdef CONFIG_PPC64
  34#include <asm/paca.h>
  35#endif
  36
  37#define SIO_CONFIG_RA   0x398
  38#define SIO_CONFIG_RD   0x399
  39
  40#define SLOW_DOWN_IO
  41
  42/* 32 bits uses slightly different variables for the various IO
  43 * bases. Most of this file only uses _IO_BASE though which we
  44 * define properly based on the platform
  45 */
  46#ifndef CONFIG_PCI
  47#define _IO_BASE        0
  48#define _ISA_MEM_BASE   0
  49#define PCI_DRAM_OFFSET 0
  50#elif defined(CONFIG_PPC32)
  51#define _IO_BASE        isa_io_base
  52#define _ISA_MEM_BASE   isa_mem_base
  53#define PCI_DRAM_OFFSET pci_dram_offset
  54#else
  55#define _IO_BASE        pci_io_base
  56#define _ISA_MEM_BASE   isa_mem_base
  57#define PCI_DRAM_OFFSET 0
  58#endif
  59
  60extern unsigned long isa_io_base;
  61extern unsigned long pci_io_base;
  62extern unsigned long pci_dram_offset;
  63
  64extern resource_size_t isa_mem_base;
  65
  66#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
  67#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
  68#endif
  69
  70/*
  71 *
  72 * Low level MMIO accessors
  73 *
  74 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
  75 * specific and thus shouldn't be used in generic code. The accessors
  76 * provided here are:
  77 *
  78 *      in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
  79 *      out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
  80 *      _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
  81 *
  82 * Those operate directly on a kernel virtual address. Note that the prototype
  83 * for the out_* accessors has the arguments in opposite order from the usual
  84 * linux PCI accessors. Unlike those, they take the address first and the value
  85 * next.
  86 *
  87 * Note: I might drop the _ns suffix on the stream operations soon as it is
  88 * simply normal for stream operations to not swap in the first place.
  89 *
  90 */
  91
  92#ifdef CONFIG_PPC64
  93#define IO_SET_SYNC_FLAG()      do { local_paca->io_sync = 1; } while(0)
  94#else
  95#define IO_SET_SYNC_FLAG()
  96#endif
  97
  98/* gcc 4.0 and older doesn't have 'Z' constraint */
  99#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
 100#define DEF_MMIO_IN_LE(name, size, insn)                                \
 101static inline u##size name(const volatile u##size __iomem *addr)        \
 102{                                                                       \
 103        u##size ret;                                                    \
 104        __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync"    \
 105                : "=r" (ret) : "r" (addr), "m" (*addr) : "memory");     \
 106        return ret;                                                     \
 107}
 108
 109#define DEF_MMIO_OUT_LE(name, size, insn)                               \
 110static inline void name(volatile u##size __iomem *addr, u##size val)    \
 111{                                                                       \
 112        __asm__ __volatile__("sync;"#insn" %1,0,%2"                     \
 113                : "=m" (*addr) : "r" (val), "r" (addr) : "memory");     \
 114        IO_SET_SYNC_FLAG();                                             \
 115}
 116#else /* newer gcc */
 117#define DEF_MMIO_IN_LE(name, size, insn)                                \
 118static inline u##size name(const volatile u##size __iomem *addr)        \
 119{                                                                       \
 120        u##size ret;                                                    \
 121        __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync"     \
 122                : "=r" (ret) : "Z" (*addr) : "memory");                 \
 123        return ret;                                                     \
 124}
 125
 126#define DEF_MMIO_OUT_LE(name, size, insn)                               \
 127static inline void name(volatile u##size __iomem *addr, u##size val)    \
 128{                                                                       \
 129        __asm__ __volatile__("sync;"#insn" %1,%y0"                      \
 130                : "=Z" (*addr) : "r" (val) : "memory");                 \
 131        IO_SET_SYNC_FLAG();                                             \
 132}
 133#endif
 134
 135#define DEF_MMIO_IN_BE(name, size, insn)                                \
 136static inline u##size name(const volatile u##size __iomem *addr)        \
 137{                                                                       \
 138        u##size ret;                                                    \
 139        __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
 140                : "=r" (ret) : "m" (*addr) : "memory");                 \
 141        return ret;                                                     \
 142}
 143
 144#define DEF_MMIO_OUT_BE(name, size, insn)                               \
 145static inline void name(volatile u##size __iomem *addr, u##size val)    \
 146{                                                                       \
 147        __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0"                 \
 148                : "=m" (*addr) : "r" (val) : "memory");                 \
 149        IO_SET_SYNC_FLAG();                                             \
 150}
 151
 152
 153DEF_MMIO_IN_BE(in_8,     8, lbz);
 154DEF_MMIO_IN_BE(in_be16, 16, lhz);
 155DEF_MMIO_IN_BE(in_be32, 32, lwz);
 156DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
 157DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
 158
 159DEF_MMIO_OUT_BE(out_8,     8, stb);
 160DEF_MMIO_OUT_BE(out_be16, 16, sth);
 161DEF_MMIO_OUT_BE(out_be32, 32, stw);
 162DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
 163DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
 164
 165#ifdef __powerpc64__
 166DEF_MMIO_OUT_BE(out_be64, 64, std);
 167DEF_MMIO_IN_BE(in_be64, 64, ld);
 168
 169/* There is no asm instructions for 64 bits reverse loads and stores */
 170static inline u64 in_le64(const volatile u64 __iomem *addr)
 171{
 172        return swab64(in_be64(addr));
 173}
 174
 175static inline void out_le64(volatile u64 __iomem *addr, u64 val)
 176{
 177        out_be64(addr, swab64(val));
 178}
 179#endif /* __powerpc64__ */
 180
 181/*
 182 * Low level IO stream instructions are defined out of line for now
 183 */
 184extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
 185extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
 186extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
 187extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
 188extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
 189extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
 190
 191/* The _ns naming is historical and will be removed. For now, just #define
 192 * the non _ns equivalent names
 193 */
 194#define _insw   _insw_ns
 195#define _insl   _insl_ns
 196#define _outsw  _outsw_ns
 197#define _outsl  _outsl_ns
 198
 199
 200/*
 201 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
 202 */
 203
 204extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
 205extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
 206                           unsigned long n);
 207extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
 208                         unsigned long n);
 209
 210/*
 211 *
 212 * PCI and standard ISA accessors
 213 *
 214 * Those are globally defined linux accessors for devices on PCI or ISA
 215 * busses. They follow the Linux defined semantics. The current implementation
 216 * for PowerPC is as close as possible to the x86 version of these, and thus
 217 * provides fairly heavy weight barriers for the non-raw versions
 218 *
 219 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
 220 * allowing the platform to provide its own implementation of some or all
 221 * of the accessors.
 222 */
 223
 224/*
 225 * Include the EEH definitions when EEH is enabled only so they don't get
 226 * in the way when building for 32 bits
 227 */
 228#ifdef CONFIG_EEH
 229#include <asm/eeh.h>
 230#endif
 231
 232/* Shortcut to the MMIO argument pointer */
 233#define PCI_IO_ADDR     volatile void __iomem *
 234
 235/* Indirect IO address tokens:
 236 *
 237 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
 238 * on all IOs. (Note that this is all 64 bits only for now)
 239 *
 240 * To help platforms who may need to differenciate MMIO addresses in
 241 * their hooks, a bitfield is reserved for use by the platform near the
 242 * top of MMIO addresses (not PIO, those have to cope the hard way).
 243 *
 244 * This bit field is 12 bits and is at the top of the IO virtual
 245 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
 246 *
 247 * The kernel virtual space is thus:
 248 *
 249 *  0xD000000000000000          : vmalloc
 250 *  0xD000080000000000          : PCI PHB IO space
 251 *  0xD000080080000000          : ioremap
 252 *  0xD0000fffffffffff          : end of ioremap region
 253 *
 254 * Since the top 4 bits are reserved as the region ID, we use thus
 255 * the next 12 bits and keep 4 bits available for the future if the
 256 * virtual address space is ever to be extended.
 257 *
 258 * The direct IO mapping operations will then mask off those bits
 259 * before doing the actual access, though that only happen when
 260 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
 261 * mechanism
 262 */
 263
 264#ifdef CONFIG_PPC_INDIRECT_IO
 265#define PCI_IO_IND_TOKEN_MASK   0x0fff000000000000ul
 266#define PCI_IO_IND_TOKEN_SHIFT  48
 267#define PCI_FIX_ADDR(addr)                                              \
 268        ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
 269#define PCI_GET_ADDR_TOKEN(addr)                                        \
 270        (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >>             \
 271                PCI_IO_IND_TOKEN_SHIFT)
 272#define PCI_SET_ADDR_TOKEN(addr, token)                                 \
 273do {                                                                    \
 274        unsigned long __a = (unsigned long)(addr);                      \
 275        __a &= ~PCI_IO_IND_TOKEN_MASK;                                  \
 276        __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT;      \
 277        (addr) = (void __iomem *)__a;                                   \
 278} while(0)
 279#else
 280#define PCI_FIX_ADDR(addr) (addr)
 281#endif
 282
 283
 284/*
 285 * Non ordered and non-swapping "raw" accessors
 286 */
 287
 288static inline unsigned char __raw_readb(const volatile void __iomem *addr)
 289{
 290        return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
 291}
 292static inline unsigned short __raw_readw(const volatile void __iomem *addr)
 293{
 294        return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
 295}
 296static inline unsigned int __raw_readl(const volatile void __iomem *addr)
 297{
 298        return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
 299}
 300static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
 301{
 302        *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
 303}
 304static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
 305{
 306        *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
 307}
 308static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
 309{
 310        *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
 311}
 312
 313#ifdef __powerpc64__
 314static inline unsigned long __raw_readq(const volatile void __iomem *addr)
 315{
 316        return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
 317}
 318static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 319{
 320        *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
 321}
 322#endif /* __powerpc64__ */
 323
 324/*
 325 *
 326 * PCI PIO and MMIO accessors.
 327 *
 328 *
 329 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
 330 * machine checks (which they occasionally do when probing non existing
 331 * IO ports on some platforms, like PowerMac and 8xx).
 332 * I always found it to be of dubious reliability and I am tempted to get
 333 * rid of it one of these days. So if you think it's important to keep it,
 334 * please voice up asap. We never had it for 64 bits and I do not intend
 335 * to port it over
 336 */
 337
 338#ifdef CONFIG_PPC32
 339
 340#define __do_in_asm(name, op)                           \
 341static inline unsigned int name(unsigned int port)      \
 342{                                                       \
 343        unsigned int x;                                 \
 344        __asm__ __volatile__(                           \
 345                "sync\n"                                \
 346                "0:"    op "    %0,0,%1\n"              \
 347                "1:     twi     0,%0,0\n"               \
 348                "2:     isync\n"                        \
 349                "3:     nop\n"                          \
 350                "4:\n"                                  \
 351                ".section .fixup,\"ax\"\n"              \
 352                "5:     li      %0,-1\n"                \
 353                "       b       4b\n"                   \
 354                ".previous\n"                           \
 355                ".section __ex_table,\"a\"\n"           \
 356                "       .align  2\n"                    \
 357                "       .long   0b,5b\n"                \
 358                "       .long   1b,5b\n"                \
 359                "       .long   2b,5b\n"                \
 360                "       .long   3b,5b\n"                \
 361                ".previous"                             \
 362                : "=&r" (x)                             \
 363                : "r" (port + _IO_BASE)                 \
 364                : "memory");                            \
 365        return x;                                       \
 366}
 367
 368#define __do_out_asm(name, op)                          \
 369static inline void name(unsigned int val, unsigned int port) \
 370{                                                       \
 371        __asm__ __volatile__(                           \
 372                "sync\n"                                \
 373                "0:" op " %0,0,%1\n"                    \
 374                "1:     sync\n"                         \
 375                "2:\n"                                  \
 376                ".section __ex_table,\"a\"\n"           \
 377                "       .align  2\n"                    \
 378                "       .long   0b,2b\n"                \
 379                "       .long   1b,2b\n"                \
 380                ".previous"                             \
 381                : : "r" (val), "r" (port + _IO_BASE)    \
 382                : "memory");                            \
 383}
 384
 385__do_in_asm(_rec_inb, "lbzx")
 386__do_in_asm(_rec_inw, "lhbrx")
 387__do_in_asm(_rec_inl, "lwbrx")
 388__do_out_asm(_rec_outb, "stbx")
 389__do_out_asm(_rec_outw, "sthbrx")
 390__do_out_asm(_rec_outl, "stwbrx")
 391
 392#endif /* CONFIG_PPC32 */
 393
 394/* The "__do_*" operations below provide the actual "base" implementation
 395 * for each of the defined acccessor. Some of them use the out_* functions
 396 * directly, some of them still use EEH, though we might change that in the
 397 * future. Those macros below provide the necessary argument swapping and
 398 * handling of the IO base for PIO.
 399 *
 400 * They are themselves used by the macros that define the actual accessors
 401 * and can be used by the hooks if any.
 402 *
 403 * Note that PIO operations are always defined in terms of their corresonding
 404 * MMIO operations. That allows platforms like iSeries who want to modify the
 405 * behaviour of both to only hook on the MMIO version and get both. It's also
 406 * possible to hook directly at the toplevel PIO operation if they have to
 407 * be handled differently
 408 */
 409#define __do_writeb(val, addr)  out_8(PCI_FIX_ADDR(addr), val)
 410#define __do_writew(val, addr)  out_le16(PCI_FIX_ADDR(addr), val)
 411#define __do_writel(val, addr)  out_le32(PCI_FIX_ADDR(addr), val)
 412#define __do_writeq(val, addr)  out_le64(PCI_FIX_ADDR(addr), val)
 413#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
 414#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
 415#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
 416
 417#ifdef CONFIG_EEH
 418#define __do_readb(addr)        eeh_readb(PCI_FIX_ADDR(addr))
 419#define __do_readw(addr)        eeh_readw(PCI_FIX_ADDR(addr))
 420#define __do_readl(addr)        eeh_readl(PCI_FIX_ADDR(addr))
 421#define __do_readq(addr)        eeh_readq(PCI_FIX_ADDR(addr))
 422#define __do_readw_be(addr)     eeh_readw_be(PCI_FIX_ADDR(addr))
 423#define __do_readl_be(addr)     eeh_readl_be(PCI_FIX_ADDR(addr))
 424#define __do_readq_be(addr)     eeh_readq_be(PCI_FIX_ADDR(addr))
 425#else /* CONFIG_EEH */
 426#define __do_readb(addr)        in_8(PCI_FIX_ADDR(addr))
 427#define __do_readw(addr)        in_le16(PCI_FIX_ADDR(addr))
 428#define __do_readl(addr)        in_le32(PCI_FIX_ADDR(addr))
 429#define __do_readq(addr)        in_le64(PCI_FIX_ADDR(addr))
 430#define __do_readw_be(addr)     in_be16(PCI_FIX_ADDR(addr))
 431#define __do_readl_be(addr)     in_be32(PCI_FIX_ADDR(addr))
 432#define __do_readq_be(addr)     in_be64(PCI_FIX_ADDR(addr))
 433#endif /* !defined(CONFIG_EEH) */
 434
 435#ifdef CONFIG_PPC32
 436#define __do_outb(val, port)    _rec_outb(val, port)
 437#define __do_outw(val, port)    _rec_outw(val, port)
 438#define __do_outl(val, port)    _rec_outl(val, port)
 439#define __do_inb(port)          _rec_inb(port)
 440#define __do_inw(port)          _rec_inw(port)
 441#define __do_inl(port)          _rec_inl(port)
 442#else /* CONFIG_PPC32 */
 443#define __do_outb(val, port)    writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
 444#define __do_outw(val, port)    writew(val,(PCI_IO_ADDR)_IO_BASE+port);
 445#define __do_outl(val, port)    writel(val,(PCI_IO_ADDR)_IO_BASE+port);
 446#define __do_inb(port)          readb((PCI_IO_ADDR)_IO_BASE + port);
 447#define __do_inw(port)          readw((PCI_IO_ADDR)_IO_BASE + port);
 448#define __do_inl(port)          readl((PCI_IO_ADDR)_IO_BASE + port);
 449#endif /* !CONFIG_PPC32 */
 450
 451#ifdef CONFIG_EEH
 452#define __do_readsb(a, b, n)    eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
 453#define __do_readsw(a, b, n)    eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
 454#define __do_readsl(a, b, n)    eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
 455#else /* CONFIG_EEH */
 456#define __do_readsb(a, b, n)    _insb(PCI_FIX_ADDR(a), (b), (n))
 457#define __do_readsw(a, b, n)    _insw(PCI_FIX_ADDR(a), (b), (n))
 458#define __do_readsl(a, b, n)    _insl(PCI_FIX_ADDR(a), (b), (n))
 459#endif /* !CONFIG_EEH */
 460#define __do_writesb(a, b, n)   _outsb(PCI_FIX_ADDR(a),(b),(n))
 461#define __do_writesw(a, b, n)   _outsw(PCI_FIX_ADDR(a),(b),(n))
 462#define __do_writesl(a, b, n)   _outsl(PCI_FIX_ADDR(a),(b),(n))
 463
 464#define __do_insb(p, b, n)      readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 465#define __do_insw(p, b, n)      readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 466#define __do_insl(p, b, n)      readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
 467#define __do_outsb(p, b, n)     writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 468#define __do_outsw(p, b, n)     writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 469#define __do_outsl(p, b, n)     writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
 470
 471#define __do_memset_io(addr, c, n)      \
 472                                _memset_io(PCI_FIX_ADDR(addr), c, n)
 473#define __do_memcpy_toio(dst, src, n)   \
 474                                _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
 475
 476#ifdef CONFIG_EEH
 477#define __do_memcpy_fromio(dst, src, n) \
 478                                eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
 479#else /* CONFIG_EEH */
 480#define __do_memcpy_fromio(dst, src, n) \
 481                                _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
 482#endif /* !CONFIG_EEH */
 483
 484#ifdef CONFIG_PPC_INDIRECT_IO
 485#define DEF_PCI_HOOK(x)         x
 486#else
 487#define DEF_PCI_HOOK(x)         NULL
 488#endif
 489
 490/* Structure containing all the hooks */
 491extern struct ppc_pci_io {
 492
 493#define DEF_PCI_AC_RET(name, ret, at, al, space, aa)    ret (*name) at;
 494#define DEF_PCI_AC_NORET(name, at, al, space, aa)       void (*name) at;
 495
 496#include <asm/io-defs.h>
 497
 498#undef DEF_PCI_AC_RET
 499#undef DEF_PCI_AC_NORET
 500
 501} ppc_pci_io;
 502
 503/* The inline wrappers */
 504#define DEF_PCI_AC_RET(name, ret, at, al, space, aa)            \
 505static inline ret name at                                       \
 506{                                                               \
 507        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
 508                return ppc_pci_io.name al;                      \
 509        return __do_##name al;                                  \
 510}
 511
 512#define DEF_PCI_AC_NORET(name, at, al, space, aa)               \
 513static inline void name at                                      \
 514{                                                               \
 515        if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL)              \
 516                ppc_pci_io.name al;                             \
 517        else                                                    \
 518                __do_##name al;                                 \
 519}
 520
 521#include <asm/io-defs.h>
 522
 523#undef DEF_PCI_AC_RET
 524#undef DEF_PCI_AC_NORET
 525
 526/* Some drivers check for the presence of readq & writeq with
 527 * a #ifdef, so we make them happy here.
 528 */
 529#ifdef __powerpc64__
 530#define readq   readq
 531#define writeq  writeq
 532#endif
 533
 534/*
 535 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 536 * access
 537 */
 538#define xlate_dev_mem_ptr(p)    __va(p)
 539
 540/*
 541 * Convert a virtual cached pointer to an uncached pointer
 542 */
 543#define xlate_dev_kmem_ptr(p)   p
 544
 545/*
 546 * We don't do relaxed operations yet, at least not with this semantic
 547 */
 548#define readb_relaxed(addr) readb(addr)
 549#define readw_relaxed(addr) readw(addr)
 550#define readl_relaxed(addr) readl(addr)
 551#define readq_relaxed(addr) readq(addr)
 552
 553#ifdef CONFIG_PPC32
 554#define mmiowb()
 555#else
 556/*
 557 * Enforce synchronisation of stores vs. spin_unlock
 558 * (this does it explicitly, though our implementation of spin_unlock
 559 * does it implicitely too)
 560 */
 561static inline void mmiowb(void)
 562{
 563        unsigned long tmp;
 564
 565        __asm__ __volatile__("sync; li %0,0; stb %0,%1(13)"
 566        : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
 567        : "memory");
 568}
 569#endif /* !CONFIG_PPC32 */
 570
 571static inline void iosync(void)
 572{
 573        __asm__ __volatile__ ("sync" : : : "memory");
 574}
 575
 576/* Enforce in-order execution of data I/O.
 577 * No distinction between read/write on PPC; use eieio for all three.
 578 * Those are fairly week though. They don't provide a barrier between
 579 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
 580 * they only provide barriers between 2 __raw MMIO operations and
 581 * possibly break write combining.
 582 */
 583#define iobarrier_rw() eieio()
 584#define iobarrier_r()  eieio()
 585#define iobarrier_w()  eieio()
 586
 587
 588/*
 589 * output pause versions need a delay at least for the
 590 * w83c105 ide controller in a p610.
 591 */
 592#define inb_p(port)             inb(port)
 593#define outb_p(val, port)       (udelay(1), outb((val), (port)))
 594#define inw_p(port)             inw(port)
 595#define outw_p(val, port)       (udelay(1), outw((val), (port)))
 596#define inl_p(port)             inl(port)
 597#define outl_p(val, port)       (udelay(1), outl((val), (port)))
 598
 599
 600#define IO_SPACE_LIMIT ~(0UL)
 601
 602
 603/**
 604 * ioremap     -   map bus memory into CPU space
 605 * @address:   bus address of the memory
 606 * @size:      size of the resource to map
 607 *
 608 * ioremap performs a platform specific sequence of operations to
 609 * make bus memory CPU accessible via the readb/readw/readl/writeb/
 610 * writew/writel functions and the other mmio helpers. The returned
 611 * address is not guaranteed to be usable directly as a virtual
 612 * address.
 613 *
 614 * We provide a few variations of it:
 615 *
 616 * * ioremap is the standard one and provides non-cacheable guarded mappings
 617 *   and can be hooked by the platform via ppc_md
 618 *
 619 * * ioremap_flags allows to specify the page flags as an argument and can
 620 *   also be hooked by the platform via ppc_md. ioremap_prot is the exact
 621 *   same thing as ioremap_flags.
 622 *
 623 * * ioremap_nocache is identical to ioremap
 624 *
 625 * * iounmap undoes such a mapping and can be hooked
 626 *
 627 * * __ioremap_at (and the pending __iounmap_at) are low level functions to
 628 *   create hand-made mappings for use only by the PCI code and cannot
 629 *   currently be hooked. Must be page aligned.
 630 *
 631 * * __ioremap is the low level implementation used by ioremap and
 632 *   ioremap_flags and cannot be hooked (but can be used by a hook on one
 633 *   of the previous ones)
 634 *
 635 * * __ioremap_caller is the same as above but takes an explicit caller
 636 *   reference rather than using __builtin_return_address(0)
 637 *
 638 * * __iounmap, is the low level implementation used by iounmap and cannot
 639 *   be hooked (but can be used by a hook on iounmap)
 640 *
 641 */
 642extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
 643extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
 644                                   unsigned long flags);
 645#define ioremap_nocache(addr, size)     ioremap((addr), (size))
 646#define ioremap_prot(addr, size, prot)  ioremap_flags((addr), (size), (prot))
 647
 648extern void iounmap(volatile void __iomem *addr);
 649
 650extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
 651                               unsigned long flags);
 652extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
 653                                      unsigned long flags, void *caller);
 654
 655extern void __iounmap(volatile void __iomem *addr);
 656
 657extern void __iomem * __ioremap_at(phys_addr_t pa, void *ea,
 658                                   unsigned long size, unsigned long flags);
 659extern void __iounmap_at(void *ea, unsigned long size);
 660
 661/*
 662 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
 663 * which needs some additional definitions here. They basically allow PIO
 664 * space overall to be 1GB. This will work as long as we never try to use
 665 * iomap to map MMIO below 1GB which should be fine on ppc64
 666 */
 667#define HAVE_ARCH_PIO_SIZE              1
 668#define PIO_OFFSET                      0x00000000UL
 669#define PIO_MASK                        (FULL_IO_SIZE - 1)
 670#define PIO_RESERVED                    (FULL_IO_SIZE)
 671
 672#define mmio_read16be(addr)             readw_be(addr)
 673#define mmio_read32be(addr)             readl_be(addr)
 674#define mmio_write16be(val, addr)       writew_be(val, addr)
 675#define mmio_write32be(val, addr)       writel_be(val, addr)
 676#define mmio_insb(addr, dst, count)     readsb(addr, dst, count)
 677#define mmio_insw(addr, dst, count)     readsw(addr, dst, count)
 678#define mmio_insl(addr, dst, count)     readsl(addr, dst, count)
 679#define mmio_outsb(addr, src, count)    writesb(addr, src, count)
 680#define mmio_outsw(addr, src, count)    writesw(addr, src, count)
 681#define mmio_outsl(addr, src, count)    writesl(addr, src, count)
 682
 683/**
 684 *      virt_to_phys    -       map virtual addresses to physical
 685 *      @address: address to remap
 686 *
 687 *      The returned physical address is the physical (CPU) mapping for
 688 *      the memory address given. It is only valid to use this function on
 689 *      addresses directly mapped or allocated via kmalloc.
 690 *
 691 *      This function does not give bus mappings for DMA transfers. In
 692 *      almost all conceivable cases a device driver should not be using
 693 *      this function
 694 */
 695static inline unsigned long virt_to_phys(volatile void * address)
 696{
 697        return __pa((unsigned long)address);
 698}
 699
 700/**
 701 *      phys_to_virt    -       map physical address to virtual
 702 *      @address: address to remap
 703 *
 704 *      The returned virtual address is a current CPU mapping for
 705 *      the memory address given. It is only valid to use this function on
 706 *      addresses that have a kernel mapping
 707 *
 708 *      This function does not handle bus mappings for DMA transfers. In
 709 *      almost all conceivable cases a device driver should not be using
 710 *      this function
 711 */
 712static inline void * phys_to_virt(unsigned long address)
 713{
 714        return (void *)__va(address);
 715}
 716
 717/*
 718 * Change "struct page" to physical address.
 719 */
 720#define page_to_phys(page)      ((phys_addr_t)page_to_pfn(page) << PAGE_SHIFT)
 721
 722/*
 723 * 32 bits still uses virt_to_bus() for it's implementation of DMA
 724 * mappings se we have to keep it defined here. We also have some old
 725 * drivers (shame shame shame) that use bus_to_virt() and haven't been
 726 * fixed yet so I need to define it here.
 727 */
 728#ifdef CONFIG_PPC32
 729
 730static inline unsigned long virt_to_bus(volatile void * address)
 731{
 732        if (address == NULL)
 733                return 0;
 734        return __pa(address) + PCI_DRAM_OFFSET;
 735}
 736
 737static inline void * bus_to_virt(unsigned long address)
 738{
 739        if (address == 0)
 740                return NULL;
 741        return __va(address - PCI_DRAM_OFFSET);
 742}
 743
 744#define page_to_bus(page)       (page_to_phys(page) + PCI_DRAM_OFFSET)
 745
 746#endif /* CONFIG_PPC32 */
 747
 748/* access ports */
 749#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) |  (_v))
 750#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
 751
 752#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) |  (_v))
 753#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
 754
 755#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) |  (_v))
 756#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
 757
 758/* Clear and set bits in one shot.  These macros can be used to clear and
 759 * set multiple bits in a register using a single read-modify-write.  These
 760 * macros can also be used to set a multiple-bit bit pattern using a mask,
 761 * by specifying the mask in the 'clear' parameter and the new bit pattern
 762 * in the 'set' parameter.
 763 */
 764
 765#define clrsetbits(type, addr, clear, set) \
 766        out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
 767
 768#ifdef __powerpc64__
 769#define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
 770#define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
 771#endif
 772
 773#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
 774#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
 775
 776#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
 777#define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
 778
 779#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
 780
 781void __iomem *devm_ioremap_prot(struct device *dev, resource_size_t offset,
 782                                size_t size, unsigned long flags);
 783
 784#endif /* __KERNEL__ */
 785
 786#endif /* _ASM_POWERPC_IO_H */
 787