linux/arch/powerpc/include/asm/immap_qe.h
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   1/*
   2 * QUICC Engine (QE) Internal Memory Map.
   3 * The Internal Memory Map for devices with QE on them. This
   4 * is the superset of all QE devices (8360, etc.).
   5
   6 * Copyright (C) 2006. Freescale Semicondutor, Inc. All rights reserved.
   7 *
   8 * Authors:     Shlomi Gridish <gridish@freescale.com>
   9 *              Li Yang <leoli@freescale.com>
  10 *
  11 * This program is free software; you can redistribute  it and/or modify it
  12 * under  the terms of  the GNU General  Public License as published by the
  13 * Free Software Foundation;  either version 2 of the  License, or (at your
  14 * option) any later version.
  15 */
  16#ifndef _ASM_POWERPC_IMMAP_QE_H
  17#define _ASM_POWERPC_IMMAP_QE_H
  18#ifdef __KERNEL__
  19
  20#include <linux/kernel.h>
  21#include <asm/io.h>
  22
  23#define QE_IMMAP_SIZE   (1024 * 1024)   /* 1MB from 1MB+IMMR */
  24
  25/* QE I-RAM */
  26struct qe_iram {
  27        __be32  iadd;           /* I-RAM Address Register */
  28        __be32  idata;          /* I-RAM Data Register */
  29        u8      res0[0x78];
  30} __attribute__ ((packed));
  31
  32/* QE Interrupt Controller */
  33struct qe_ic_regs {
  34        __be32  qicr;
  35        __be32  qivec;
  36        __be32  qripnr;
  37        __be32  qipnr;
  38        __be32  qipxcc;
  39        __be32  qipycc;
  40        __be32  qipwcc;
  41        __be32  qipzcc;
  42        __be32  qimr;
  43        __be32  qrimr;
  44        __be32  qicnr;
  45        u8      res0[0x4];
  46        __be32  qiprta;
  47        __be32  qiprtb;
  48        u8      res1[0x4];
  49        __be32  qricr;
  50        u8      res2[0x20];
  51        __be32  qhivec;
  52        u8      res3[0x1C];
  53} __attribute__ ((packed));
  54
  55/* Communications Processor */
  56struct cp_qe {
  57        __be32  cecr;           /* QE command register */
  58        __be32  ceccr;          /* QE controller configuration register */
  59        __be32  cecdr;          /* QE command data register */
  60        u8      res0[0xA];
  61        __be16  ceter;          /* QE timer event register */
  62        u8      res1[0x2];
  63        __be16  cetmr;          /* QE timers mask register */
  64        __be32  cetscr;         /* QE time-stamp timer control register */
  65        __be32  cetsr1;         /* QE time-stamp register 1 */
  66        __be32  cetsr2;         /* QE time-stamp register 2 */
  67        u8      res2[0x8];
  68        __be32  cevter;         /* QE virtual tasks event register */
  69        __be32  cevtmr;         /* QE virtual tasks mask register */
  70        __be16  cercr;          /* QE RAM control register */
  71        u8      res3[0x2];
  72        u8      res4[0x24];
  73        __be16  ceexe1;         /* QE external request 1 event register */
  74        u8      res5[0x2];
  75        __be16  ceexm1;         /* QE external request 1 mask register */
  76        u8      res6[0x2];
  77        __be16  ceexe2;         /* QE external request 2 event register */
  78        u8      res7[0x2];
  79        __be16  ceexm2;         /* QE external request 2 mask register */
  80        u8      res8[0x2];
  81        __be16  ceexe3;         /* QE external request 3 event register */
  82        u8      res9[0x2];
  83        __be16  ceexm3;         /* QE external request 3 mask register */
  84        u8      res10[0x2];
  85        __be16  ceexe4;         /* QE external request 4 event register */
  86        u8      res11[0x2];
  87        __be16  ceexm4;         /* QE external request 4 mask register */
  88        u8      res12[0x3A];
  89        __be32  ceurnr;         /* QE microcode revision number register */
  90        u8      res13[0x244];
  91} __attribute__ ((packed));
  92
  93/* QE Multiplexer */
  94struct qe_mux {
  95        __be32  cmxgcr;         /* CMX general clock route register */
  96        __be32  cmxsi1cr_l;     /* CMX SI1 clock route low register */
  97        __be32  cmxsi1cr_h;     /* CMX SI1 clock route high register */
  98        __be32  cmxsi1syr;      /* CMX SI1 SYNC route register */
  99        __be32  cmxucr[4];      /* CMX UCCx clock route registers */
 100        __be32  cmxupcr;        /* CMX UPC clock route register */
 101        u8      res0[0x1C];
 102} __attribute__ ((packed));
 103
 104/* QE Timers */
 105struct qe_timers {
 106        u8      gtcfr1;         /* Timer 1 and Timer 2 global config register*/
 107        u8      res0[0x3];
 108        u8      gtcfr2;         /* Timer 3 and timer 4 global config register*/
 109        u8      res1[0xB];
 110        __be16  gtmdr1;         /* Timer 1 mode register */
 111        __be16  gtmdr2;         /* Timer 2 mode register */
 112        __be16  gtrfr1;         /* Timer 1 reference register */
 113        __be16  gtrfr2;         /* Timer 2 reference register */
 114        __be16  gtcpr1;         /* Timer 1 capture register */
 115        __be16  gtcpr2;         /* Timer 2 capture register */
 116        __be16  gtcnr1;         /* Timer 1 counter */
 117        __be16  gtcnr2;         /* Timer 2 counter */
 118        __be16  gtmdr3;         /* Timer 3 mode register */
 119        __be16  gtmdr4;         /* Timer 4 mode register */
 120        __be16  gtrfr3;         /* Timer 3 reference register */
 121        __be16  gtrfr4;         /* Timer 4 reference register */
 122        __be16  gtcpr3;         /* Timer 3 capture register */
 123        __be16  gtcpr4;         /* Timer 4 capture register */
 124        __be16  gtcnr3;         /* Timer 3 counter */
 125        __be16  gtcnr4;         /* Timer 4 counter */
 126        __be16  gtevr1;         /* Timer 1 event register */
 127        __be16  gtevr2;         /* Timer 2 event register */
 128        __be16  gtevr3;         /* Timer 3 event register */
 129        __be16  gtevr4;         /* Timer 4 event register */
 130        __be16  gtps;           /* Timer 1 prescale register */
 131        u8 res2[0x46];
 132} __attribute__ ((packed));
 133
 134/* BRG */
 135struct qe_brg {
 136        __be32  brgc[16];       /* BRG configuration registers */
 137        u8      res0[0x40];
 138} __attribute__ ((packed));
 139
 140/* SPI */
 141struct spi {
 142        u8      res0[0x20];
 143        __be32  spmode;         /* SPI mode register */
 144        u8      res1[0x2];
 145        u8      spie;           /* SPI event register */
 146        u8      res2[0x1];
 147        u8      res3[0x2];
 148        u8      spim;           /* SPI mask register */
 149        u8      res4[0x1];
 150        u8      res5[0x1];
 151        u8      spcom;          /* SPI command register */
 152        u8      res6[0x2];
 153        __be32  spitd;          /* SPI transmit data register (cpu mode) */
 154        __be32  spird;          /* SPI receive data register (cpu mode) */
 155        u8      res7[0x8];
 156} __attribute__ ((packed));
 157
 158/* SI */
 159struct si1 {
 160        __be16  siamr1;         /* SI1 TDMA mode register */
 161        __be16  sibmr1;         /* SI1 TDMB mode register */
 162        __be16  sicmr1;         /* SI1 TDMC mode register */
 163        __be16  sidmr1;         /* SI1 TDMD mode register */
 164        u8      siglmr1_h;      /* SI1 global mode register high */
 165        u8      res0[0x1];
 166        u8      sicmdr1_h;      /* SI1 command register high */
 167        u8      res2[0x1];
 168        u8      sistr1_h;       /* SI1 status register high */
 169        u8      res3[0x1];
 170        __be16  sirsr1_h;       /* SI1 RAM shadow address register high */
 171        u8      sitarc1;        /* SI1 RAM counter Tx TDMA */
 172        u8      sitbrc1;        /* SI1 RAM counter Tx TDMB */
 173        u8      sitcrc1;        /* SI1 RAM counter Tx TDMC */
 174        u8      sitdrc1;        /* SI1 RAM counter Tx TDMD */
 175        u8      sirarc1;        /* SI1 RAM counter Rx TDMA */
 176        u8      sirbrc1;        /* SI1 RAM counter Rx TDMB */
 177        u8      sircrc1;        /* SI1 RAM counter Rx TDMC */
 178        u8      sirdrc1;        /* SI1 RAM counter Rx TDMD */
 179        u8      res4[0x8];
 180        __be16  siemr1;         /* SI1 TDME mode register 16 bits */
 181        __be16  sifmr1;         /* SI1 TDMF mode register 16 bits */
 182        __be16  sigmr1;         /* SI1 TDMG mode register 16 bits */
 183        __be16  sihmr1;         /* SI1 TDMH mode register 16 bits */
 184        u8      siglmg1_l;      /* SI1 global mode register low 8 bits */
 185        u8      res5[0x1];
 186        u8      sicmdr1_l;      /* SI1 command register low 8 bits */
 187        u8      res6[0x1];
 188        u8      sistr1_l;       /* SI1 status register low 8 bits */
 189        u8      res7[0x1];
 190        __be16  sirsr1_l;       /* SI1 RAM shadow address register low 16 bits*/
 191        u8      siterc1;        /* SI1 RAM counter Tx TDME 8 bits */
 192        u8      sitfrc1;        /* SI1 RAM counter Tx TDMF 8 bits */
 193        u8      sitgrc1;        /* SI1 RAM counter Tx TDMG 8 bits */
 194        u8      sithrc1;        /* SI1 RAM counter Tx TDMH 8 bits */
 195        u8      sirerc1;        /* SI1 RAM counter Rx TDME 8 bits */
 196        u8      sirfrc1;        /* SI1 RAM counter Rx TDMF 8 bits */
 197        u8      sirgrc1;        /* SI1 RAM counter Rx TDMG 8 bits */
 198        u8      sirhrc1;        /* SI1 RAM counter Rx TDMH 8 bits */
 199        u8      res8[0x8];
 200        __be32  siml1;          /* SI1 multiframe limit register */
 201        u8      siedm1;         /* SI1 extended diagnostic mode register */
 202        u8      res9[0xBB];
 203} __attribute__ ((packed));
 204
 205/* SI Routing Tables */
 206struct sir {
 207        u8      tx[0x400];
 208        u8      rx[0x400];
 209        u8      res0[0x800];
 210} __attribute__ ((packed));
 211
 212/* USB Controller */
 213struct usb_ctlr {
 214        u8      usb_usmod;
 215        u8      usb_usadr;
 216        u8      usb_uscom;
 217        u8      res1[1];
 218        __be16  usb_usep[4];
 219        u8      res2[4];
 220        __be16  usb_usber;
 221        u8      res3[2];
 222        __be16  usb_usbmr;
 223        u8      res4[1];
 224        u8      usb_usbs;
 225        __be16  usb_ussft;
 226        u8      res5[2];
 227        __be16  usb_usfrn;
 228        u8      res6[0x22];
 229} __attribute__ ((packed));
 230
 231/* MCC */
 232struct mcc {
 233        __be32  mcce;           /* MCC event register */
 234        __be32  mccm;           /* MCC mask register */
 235        __be32  mccf;           /* MCC configuration register */
 236        __be32  merl;           /* MCC emergency request level register */
 237        u8      res0[0xF0];
 238} __attribute__ ((packed));
 239
 240/* QE UCC Slow */
 241struct ucc_slow {
 242        __be32  gumr_l;         /* UCCx general mode register (low) */
 243        __be32  gumr_h;         /* UCCx general mode register (high) */
 244        __be16  upsmr;          /* UCCx protocol-specific mode register */
 245        u8      res0[0x2];
 246        __be16  utodr;          /* UCCx transmit on demand register */
 247        __be16  udsr;           /* UCCx data synchronization register */
 248        __be16  ucce;           /* UCCx event register */
 249        u8      res1[0x2];
 250        __be16  uccm;           /* UCCx mask register */
 251        u8      res2[0x1];
 252        u8      uccs;           /* UCCx status register */
 253        u8      res3[0x24];
 254        __be16  utpt;
 255        u8      res4[0x52];
 256        u8      guemr;          /* UCC general extended mode register */
 257} __attribute__ ((packed));
 258
 259/* QE UCC Fast */
 260struct ucc_fast {
 261        __be32  gumr;           /* UCCx general mode register */
 262        __be32  upsmr;          /* UCCx protocol-specific mode register */
 263        __be16  utodr;          /* UCCx transmit on demand register */
 264        u8      res0[0x2];
 265        __be16  udsr;           /* UCCx data synchronization register */
 266        u8      res1[0x2];
 267        __be32  ucce;           /* UCCx event register */
 268        __be32  uccm;           /* UCCx mask register */
 269        u8      uccs;           /* UCCx status register */
 270        u8      res2[0x7];
 271        __be32  urfb;           /* UCC receive FIFO base */
 272        __be16  urfs;           /* UCC receive FIFO size */
 273        u8      res3[0x2];
 274        __be16  urfet;          /* UCC receive FIFO emergency threshold */
 275        __be16  urfset;         /* UCC receive FIFO special emergency
 276                                   threshold */
 277        __be32  utfb;           /* UCC transmit FIFO base */
 278        __be16  utfs;           /* UCC transmit FIFO size */
 279        u8      res4[0x2];
 280        __be16  utfet;          /* UCC transmit FIFO emergency threshold */
 281        u8      res5[0x2];
 282        __be16  utftt;          /* UCC transmit FIFO transmit threshold */
 283        u8      res6[0x2];
 284        __be16  utpt;           /* UCC transmit polling timer */
 285        u8      res7[0x2];
 286        __be32  urtry;          /* UCC retry counter register */
 287        u8      res8[0x4C];
 288        u8      guemr;          /* UCC general extended mode register */
 289} __attribute__ ((packed));
 290
 291struct ucc {
 292        union {
 293                struct  ucc_slow slow;
 294                struct  ucc_fast fast;
 295                u8      res[0x200];     /* UCC blocks are 512 bytes each */
 296        };
 297} __attribute__ ((packed));
 298
 299/* MultiPHY UTOPIA POS Controllers (UPC) */
 300struct upc {
 301        __be32  upgcr;          /* UTOPIA/POS general configuration register */
 302        __be32  uplpa;          /* UTOPIA/POS last PHY address */
 303        __be32  uphec;          /* ATM HEC register */
 304        __be32  upuc;           /* UTOPIA/POS UCC configuration */
 305        __be32  updc1;          /* UTOPIA/POS device 1 configuration */
 306        __be32  updc2;          /* UTOPIA/POS device 2 configuration */
 307        __be32  updc3;          /* UTOPIA/POS device 3 configuration */
 308        __be32  updc4;          /* UTOPIA/POS device 4 configuration */
 309        __be32  upstpa;         /* UTOPIA/POS STPA threshold */
 310        u8      res0[0xC];
 311        __be32  updrs1_h;       /* UTOPIA/POS device 1 rate select */
 312        __be32  updrs1_l;       /* UTOPIA/POS device 1 rate select */
 313        __be32  updrs2_h;       /* UTOPIA/POS device 2 rate select */
 314        __be32  updrs2_l;       /* UTOPIA/POS device 2 rate select */
 315        __be32  updrs3_h;       /* UTOPIA/POS device 3 rate select */
 316        __be32  updrs3_l;       /* UTOPIA/POS device 3 rate select */
 317        __be32  updrs4_h;       /* UTOPIA/POS device 4 rate select */
 318        __be32  updrs4_l;       /* UTOPIA/POS device 4 rate select */
 319        __be32  updrp1;         /* UTOPIA/POS device 1 receive priority low */
 320        __be32  updrp2;         /* UTOPIA/POS device 2 receive priority low */
 321        __be32  updrp3;         /* UTOPIA/POS device 3 receive priority low */
 322        __be32  updrp4;         /* UTOPIA/POS device 4 receive priority low */
 323        __be32  upde1;          /* UTOPIA/POS device 1 event */
 324        __be32  upde2;          /* UTOPIA/POS device 2 event */
 325        __be32  upde3;          /* UTOPIA/POS device 3 event */
 326        __be32  upde4;          /* UTOPIA/POS device 4 event */
 327        __be16  uprp1;
 328        __be16  uprp2;
 329        __be16  uprp3;
 330        __be16  uprp4;
 331        u8      res1[0x8];
 332        __be16  uptirr1_0;      /* Device 1 transmit internal rate 0 */
 333        __be16  uptirr1_1;      /* Device 1 transmit internal rate 1 */
 334        __be16  uptirr1_2;      /* Device 1 transmit internal rate 2 */
 335        __be16  uptirr1_3;      /* Device 1 transmit internal rate 3 */
 336        __be16  uptirr2_0;      /* Device 2 transmit internal rate 0 */
 337        __be16  uptirr2_1;      /* Device 2 transmit internal rate 1 */
 338        __be16  uptirr2_2;      /* Device 2 transmit internal rate 2 */
 339        __be16  uptirr2_3;      /* Device 2 transmit internal rate 3 */
 340        __be16  uptirr3_0;      /* Device 3 transmit internal rate 0 */
 341        __be16  uptirr3_1;      /* Device 3 transmit internal rate 1 */
 342        __be16  uptirr3_2;      /* Device 3 transmit internal rate 2 */
 343        __be16  uptirr3_3;      /* Device 3 transmit internal rate 3 */
 344        __be16  uptirr4_0;      /* Device 4 transmit internal rate 0 */
 345        __be16  uptirr4_1;      /* Device 4 transmit internal rate 1 */
 346        __be16  uptirr4_2;      /* Device 4 transmit internal rate 2 */
 347        __be16  uptirr4_3;      /* Device 4 transmit internal rate 3 */
 348        __be32  uper1;          /* Device 1 port enable register */
 349        __be32  uper2;          /* Device 2 port enable register */
 350        __be32  uper3;          /* Device 3 port enable register */
 351        __be32  uper4;          /* Device 4 port enable register */
 352        u8      res2[0x150];
 353} __attribute__ ((packed));
 354
 355/* SDMA */
 356struct sdma {
 357        __be32  sdsr;           /* Serial DMA status register */
 358        __be32  sdmr;           /* Serial DMA mode register */
 359        __be32  sdtr1;          /* SDMA system bus threshold register */
 360        __be32  sdtr2;          /* SDMA secondary bus threshold register */
 361        __be32  sdhy1;          /* SDMA system bus hysteresis register */
 362        __be32  sdhy2;          /* SDMA secondary bus hysteresis register */
 363        __be32  sdta1;          /* SDMA system bus address register */
 364        __be32  sdta2;          /* SDMA secondary bus address register */
 365        __be32  sdtm1;          /* SDMA system bus MSNUM register */
 366        __be32  sdtm2;          /* SDMA secondary bus MSNUM register */
 367        u8      res0[0x10];
 368        __be32  sdaqr;          /* SDMA address bus qualify register */
 369        __be32  sdaqmr;         /* SDMA address bus qualify mask register */
 370        u8      res1[0x4];
 371        __be32  sdebcr;         /* SDMA CAM entries base register */
 372        u8      res2[0x38];
 373} __attribute__ ((packed));
 374
 375/* Debug Space */
 376struct dbg {
 377        __be32  bpdcr;          /* Breakpoint debug command register */
 378        __be32  bpdsr;          /* Breakpoint debug status register */
 379        __be32  bpdmr;          /* Breakpoint debug mask register */
 380        __be32  bprmrr0;        /* Breakpoint request mode risc register 0 */
 381        __be32  bprmrr1;        /* Breakpoint request mode risc register 1 */
 382        u8      res0[0x8];
 383        __be32  bprmtr0;        /* Breakpoint request mode trb register 0 */
 384        __be32  bprmtr1;        /* Breakpoint request mode trb register 1 */
 385        u8      res1[0x8];
 386        __be32  bprmir;         /* Breakpoint request mode immediate register */
 387        __be32  bprmsr;         /* Breakpoint request mode serial register */
 388        __be32  bpemr;          /* Breakpoint exit mode register */
 389        u8      res2[0x48];
 390} __attribute__ ((packed));
 391
 392/*
 393 * RISC Special Registers (Trap and Breakpoint).  These are described in
 394 * the QE Developer's Handbook.
 395 */
 396struct rsp {
 397        __be32 tibcr[16];       /* Trap/instruction breakpoint control regs */
 398        u8 res0[64];
 399        __be32 ibcr0;
 400        __be32 ibs0;
 401        __be32 ibcnr0;
 402        u8 res1[4];
 403        __be32 ibcr1;
 404        __be32 ibs1;
 405        __be32 ibcnr1;
 406        __be32 npcr;
 407        __be32 dbcr;
 408        __be32 dbar;
 409        __be32 dbamr;
 410        __be32 dbsr;
 411        __be32 dbcnr;
 412        u8 res2[12];
 413        __be32 dbdr_h;
 414        __be32 dbdr_l;
 415        __be32 dbdmr_h;
 416        __be32 dbdmr_l;
 417        __be32 bsr;
 418        __be32 bor;
 419        __be32 bior;
 420        u8 res3[4];
 421        __be32 iatr[4];
 422        __be32 eccr;            /* Exception control configuration register */
 423        __be32 eicr;
 424        u8 res4[0x100-0xf8];
 425} __attribute__ ((packed));
 426
 427struct qe_immap {
 428        struct qe_iram          iram;           /* I-RAM */
 429        struct qe_ic_regs       ic;             /* Interrupt Controller */
 430        struct cp_qe            cp;             /* Communications Processor */
 431        struct qe_mux           qmx;            /* QE Multiplexer */
 432        struct qe_timers        qet;            /* QE Timers */
 433        struct spi              spi[0x2];       /* spi */
 434        struct mcc              mcc;            /* mcc */
 435        struct qe_brg           brg;            /* brg */
 436        struct usb_ctlr         usb;            /* USB */
 437        struct si1              si1;            /* SI */
 438        u8                      res11[0x800];
 439        struct sir              sir;            /* SI Routing Tables */
 440        struct ucc              ucc1;           /* ucc1 */
 441        struct ucc              ucc3;           /* ucc3 */
 442        struct ucc              ucc5;           /* ucc5 */
 443        struct ucc              ucc7;           /* ucc7 */
 444        u8                      res12[0x600];
 445        struct upc              upc1;           /* MultiPHY UTOPIA POS Ctrlr 1*/
 446        struct ucc              ucc2;           /* ucc2 */
 447        struct ucc              ucc4;           /* ucc4 */
 448        struct ucc              ucc6;           /* ucc6 */
 449        struct ucc              ucc8;           /* ucc8 */
 450        u8                      res13[0x600];
 451        struct upc              upc2;           /* MultiPHY UTOPIA POS Ctrlr 2*/
 452        struct sdma             sdma;           /* SDMA */
 453        struct dbg              dbg;            /* 0x104080 - 0x1040FF
 454                                                   Debug Space */
 455        struct rsp              rsp[0x2];       /* 0x104100 - 0x1042FF
 456                                                   RISC Special Registers
 457                                                   (Trap and Breakpoint) */
 458        u8                      res14[0x300];   /* 0x104300 - 0x1045FF */
 459        u8                      res15[0x3A00];  /* 0x104600 - 0x107FFF */
 460        u8                      res16[0x8000];  /* 0x108000 - 0x110000 */
 461        u8                      muram[0xC000];  /* 0x110000 - 0x11C000
 462                                                   Multi-user RAM */
 463        u8                      res17[0x24000]; /* 0x11C000 - 0x140000 */
 464        u8                      res18[0xC0000]; /* 0x140000 - 0x200000 */
 465} __attribute__ ((packed));
 466
 467extern struct qe_immap __iomem *qe_immr;
 468extern phys_addr_t get_qe_base(void);
 469
 470static inline unsigned long immrbar_virt_to_phys(void *address)
 471{
 472        if ( ((u32)address >= (u32)qe_immr) &&
 473                        ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
 474                return (unsigned long)(address - (u32)qe_immr +
 475                                (u32)get_qe_base());
 476        return (unsigned long)virt_to_phys(address);
 477}
 478
 479#endif /* __KERNEL__ */
 480#endif /* _ASM_POWERPC_IMMAP_QE_H */
 481