linux/arch/powerpc/include/asm/cputable.h
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   1#ifndef __ASM_POWERPC_CPUTABLE_H
   2#define __ASM_POWERPC_CPUTABLE_H
   3
   4#define PPC_FEATURE_32                  0x80000000
   5#define PPC_FEATURE_64                  0x40000000
   6#define PPC_FEATURE_601_INSTR           0x20000000
   7#define PPC_FEATURE_HAS_ALTIVEC         0x10000000
   8#define PPC_FEATURE_HAS_FPU             0x08000000
   9#define PPC_FEATURE_HAS_MMU             0x04000000
  10#define PPC_FEATURE_HAS_4xxMAC          0x02000000
  11#define PPC_FEATURE_UNIFIED_CACHE       0x01000000
  12#define PPC_FEATURE_HAS_SPE             0x00800000
  13#define PPC_FEATURE_HAS_EFP_SINGLE      0x00400000
  14#define PPC_FEATURE_HAS_EFP_DOUBLE      0x00200000
  15#define PPC_FEATURE_NO_TB               0x00100000
  16#define PPC_FEATURE_POWER4              0x00080000
  17#define PPC_FEATURE_POWER5              0x00040000
  18#define PPC_FEATURE_POWER5_PLUS         0x00020000
  19#define PPC_FEATURE_CELL                0x00010000
  20#define PPC_FEATURE_BOOKE               0x00008000
  21#define PPC_FEATURE_SMT                 0x00004000
  22#define PPC_FEATURE_ICACHE_SNOOP        0x00002000
  23#define PPC_FEATURE_ARCH_2_05           0x00001000
  24#define PPC_FEATURE_PA6T                0x00000800
  25#define PPC_FEATURE_HAS_DFP             0x00000400
  26#define PPC_FEATURE_POWER6_EXT          0x00000200
  27#define PPC_FEATURE_ARCH_2_06           0x00000100
  28#define PPC_FEATURE_HAS_VSX             0x00000080
  29
  30#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \
  31                                        0x00000040
  32
  33#define PPC_FEATURE_TRUE_LE             0x00000002
  34#define PPC_FEATURE_PPC_LE              0x00000001
  35
  36#ifdef __KERNEL__
  37
  38#include <asm/asm-compat.h>
  39#include <asm/feature-fixups.h>
  40
  41#ifndef __ASSEMBLY__
  42
  43/* This structure can grow, it's real size is used by head.S code
  44 * via the mkdefs mechanism.
  45 */
  46struct cpu_spec;
  47
  48typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  49typedef void (*cpu_restore_t)(void);
  50
  51enum powerpc_oprofile_type {
  52        PPC_OPROFILE_INVALID = 0,
  53        PPC_OPROFILE_RS64 = 1,
  54        PPC_OPROFILE_POWER4 = 2,
  55        PPC_OPROFILE_G4 = 3,
  56        PPC_OPROFILE_FSL_EMB = 4,
  57        PPC_OPROFILE_CELL = 5,
  58        PPC_OPROFILE_PA6T = 6,
  59};
  60
  61enum powerpc_pmc_type {
  62        PPC_PMC_DEFAULT = 0,
  63        PPC_PMC_IBM = 1,
  64        PPC_PMC_PA6T = 2,
  65        PPC_PMC_G4 = 3,
  66};
  67
  68struct pt_regs;
  69
  70extern int machine_check_generic(struct pt_regs *regs);
  71extern int machine_check_4xx(struct pt_regs *regs);
  72extern int machine_check_440A(struct pt_regs *regs);
  73extern int machine_check_e500(struct pt_regs *regs);
  74extern int machine_check_e200(struct pt_regs *regs);
  75
  76/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  77struct cpu_spec {
  78        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  79        unsigned int    pvr_mask;
  80        unsigned int    pvr_value;
  81
  82        char            *cpu_name;
  83        unsigned long   cpu_features;           /* Kernel features */
  84        unsigned int    cpu_user_features;      /* Userland features */
  85        unsigned int    mmu_features;           /* MMU features */
  86
  87        /* cache line sizes */
  88        unsigned int    icache_bsize;
  89        unsigned int    dcache_bsize;
  90
  91        /* number of performance monitor counters */
  92        unsigned int    num_pmcs;
  93        enum powerpc_pmc_type pmc_type;
  94
  95        /* this is called to initialize various CPU bits like L1 cache,
  96         * BHT, SPD, etc... from head.S before branching to identify_machine
  97         */
  98        cpu_setup_t     cpu_setup;
  99        /* Used to restore cpu setup on secondary processors and at resume */
 100        cpu_restore_t   cpu_restore;
 101
 102        /* Used by oprofile userspace to select the right counters */
 103        char            *oprofile_cpu_type;
 104
 105        /* Processor specific oprofile operations */
 106        enum powerpc_oprofile_type oprofile_type;
 107
 108        /* Bit locations inside the mmcra change */
 109        unsigned long   oprofile_mmcra_sihv;
 110        unsigned long   oprofile_mmcra_sipr;
 111
 112        /* Bits to clear during an oprofile exception */
 113        unsigned long   oprofile_mmcra_clear;
 114
 115        /* Name of processor class, for the ELF AT_PLATFORM entry */
 116        char            *platform;
 117
 118        /* Processor specific machine check handling. Return negative
 119         * if the error is fatal, 1 if it was fully recovered and 0 to
 120         * pass up (not CPU originated) */
 121        int             (*machine_check)(struct pt_regs *regs);
 122};
 123
 124extern struct cpu_spec          *cur_cpu_spec;
 125
 126extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
 127
 128extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 129extern void do_feature_fixups(unsigned long value, void *fixup_start,
 130                              void *fixup_end);
 131
 132extern const char *powerpc_base_platform;
 133
 134#endif /* __ASSEMBLY__ */
 135
 136/* CPU kernel features */
 137
 138/* Retain the 32b definitions all use bottom half of word */
 139#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000000000000001)
 140#define CPU_FTR_L2CR                    ASM_CONST(0x0000000000000002)
 141#define CPU_FTR_SPEC7450                ASM_CONST(0x0000000000000004)
 142#define CPU_FTR_ALTIVEC                 ASM_CONST(0x0000000000000008)
 143#define CPU_FTR_TAU                     ASM_CONST(0x0000000000000010)
 144#define CPU_FTR_CAN_DOZE                ASM_CONST(0x0000000000000020)
 145#define CPU_FTR_USE_TB                  ASM_CONST(0x0000000000000040)
 146#define CPU_FTR_L2CSR                   ASM_CONST(0x0000000000000080)
 147#define CPU_FTR_601                     ASM_CONST(0x0000000000000100)
 148#define CPU_FTR_DBELL                   ASM_CONST(0x0000000000000200)
 149#define CPU_FTR_CAN_NAP                 ASM_CONST(0x0000000000000400)
 150#define CPU_FTR_L3CR                    ASM_CONST(0x0000000000000800)
 151#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x0000000000001000)
 152#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x0000000000002000)
 153#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x0000000000004000)
 154#define CPU_FTR_NO_DPM                  ASM_CONST(0x0000000000008000)
 155#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x0000000000020000)
 156#define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
 157#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
 158#define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
 159#define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
 160#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x0000000000800000)
 161#define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x0000000001000000)
 162#define CPU_FTR_SPE                     ASM_CONST(0x0000000002000000)
 163#define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x0000000004000000)
 164#define CPU_FTR_LWSYNC                  ASM_CONST(0x0000000008000000)
 165#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000010000000)
 166#define CPU_FTR_INDEXED_DCR             ASM_CONST(0x0000000020000000)
 167
 168/*
 169 * Add the 64-bit processor unique features in the top half of the word;
 170 * on 32-bit, make the names available but defined to be 0.
 171 */
 172#ifdef __powerpc64__
 173#define LONG_ASM_CONST(x)               ASM_CONST(x)
 174#else
 175#define LONG_ASM_CONST(x)               0
 176#endif
 177
 178#define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
 179#define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
 180#define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
 181#define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
 182#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
 183#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
 184#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
 185#define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
 186#define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
 187#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
 188#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
 189#define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000800000000000)
 190#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0001000000000000)
 191#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0002000000000000)
 192#define CPU_FTR_1T_SEGMENT              LONG_ASM_CONST(0x0004000000000000)
 193#define CPU_FTR_NO_SLBIE_B              LONG_ASM_CONST(0x0008000000000000)
 194#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0010000000000000)
 195#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0020000000000000)
 196#define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0040000000000000)
 197#define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0080000000000000)
 198
 199#ifndef __ASSEMBLY__
 200
 201#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_SLB | \
 202                                 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
 203                                 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
 204
 205/* We only set the altivec features if the kernel was compiled with altivec
 206 * support
 207 */
 208#ifdef CONFIG_ALTIVEC
 209#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 210#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 211#else
 212#define CPU_FTR_ALTIVEC_COMP    0
 213#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 214#endif
 215
 216/* We only set the VSX features if the kernel was compiled with VSX
 217 * support
 218 */
 219#ifdef CONFIG_VSX
 220#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
 221#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
 222#else
 223#define CPU_FTR_VSX_COMP        0
 224#define PPC_FEATURE_HAS_VSX_COMP    0
 225#endif
 226
 227/* We only set the spe features if the kernel was compiled with spe
 228 * support
 229 */
 230#ifdef CONFIG_SPE
 231#define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 232#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 233#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 234#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 235#else
 236#define CPU_FTR_SPE_COMP        0
 237#define PPC_FEATURE_HAS_SPE_COMP    0
 238#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 239#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 240#endif
 241
 242/* We need to mark all pages as being coherent if we're SMP or we have a
 243 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 244 * require it for PCI "streaming/prefetch" to work properly.
 245 * This is also required by 52xx family.
 246 */
 247#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 248        || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
 249        || defined(CONFIG_PPC_MPC52xx)
 250#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 251#else
 252#define CPU_FTR_COMMON                  0
 253#endif
 254
 255/* The powersave features NAP & DOZE seems to confuse BDI when
 256   debugging. So if a BDI is used, disable theses
 257 */
 258#ifndef CONFIG_BDI_SWITCH
 259#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 260#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 261#else
 262#define CPU_FTR_MAYBE_CAN_DOZE  0
 263#define CPU_FTR_MAYBE_CAN_NAP   0
 264#endif
 265
 266#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
 267                     !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
 268                     !defined(CONFIG_BOOKE))
 269
 270#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
 271        CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 272#define CPU_FTRS_603    (CPU_FTR_COMMON | \
 273            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 274            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 275#define CPU_FTRS_604    (CPU_FTR_COMMON | \
 276            CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
 277#define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 278            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 279            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 280#define CPU_FTRS_740    (CPU_FTR_COMMON | \
 281            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 282            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 283            CPU_FTR_PPC_LE)
 284#define CPU_FTRS_750    (CPU_FTR_COMMON | \
 285            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 286            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 287            CPU_FTR_PPC_LE)
 288#define CPU_FTRS_750CL  (CPU_FTRS_750)
 289#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 290#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 291#define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
 292#define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 293#define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 294            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 295            CPU_FTR_ALTIVEC_COMP | \
 296            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 297#define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 298            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 299            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
 300            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 301#define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 302            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 303            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 304            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 305#define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 306            CPU_FTR_USE_TB | \
 307            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 308            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 309            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 310            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 311#define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 312            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 313            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 314            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 315            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 316#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 317            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 318            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 319            CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 320#define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 321            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 322            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 323            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 324            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 325            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 326#define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 327            CPU_FTR_USE_TB | \
 328            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 329            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 330            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 331#define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 332            CPU_FTR_USE_TB | \
 333            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 334            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 335            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 336            CPU_FTR_NEED_PAIRED_STWCX)
 337#define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 338            CPU_FTR_USE_TB | \
 339            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 340            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 341            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 342#define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 343            CPU_FTR_USE_TB | \
 344            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 345            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 346            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 347#define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 348            CPU_FTR_USE_TB | \
 349            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 350            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 351            CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 352#define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 353            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 354#define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 355            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
 356#define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 357            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 358            CPU_FTR_COMMON)
 359#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 360            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 361            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 362#define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_USE_TB)
 363#define CPU_FTRS_8XX    (CPU_FTR_USE_TB)
 364#define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 365#define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 366#define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
 367            CPU_FTR_INDEXED_DCR)
 368#define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 369            CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 370            CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE)
 371#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 372            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 373            CPU_FTR_NOEXECUTE)
 374#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 375            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
 376            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 377#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 378            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 379            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 380            CPU_FTR_DBELL)
 381#define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 382
 383/* 64-bit CPUs */
 384#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 385            CPU_FTR_IABR | CPU_FTR_PPC_LE)
 386#define CPU_FTRS_RS64   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 387            CPU_FTR_IABR | \
 388            CPU_FTR_MMCRA | CPU_FTR_CTRL)
 389#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 390            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 391            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)
 392#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 393            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 394            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
 395            CPU_FTR_CP_USE_DCBTZ)
 396#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 397            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 398            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 399            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 400            CPU_FTR_PURR)
 401#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 402            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 403            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 404            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 405            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 406            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD)
 407#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 408            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 409            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 410            CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
 411            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 412            CPU_FTR_DSCR | CPU_FTR_SAO)
 413#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 414            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 415            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 416            CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
 417            CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
 418            CPU_FTR_UNALIGNED_LD_STD)
 419#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 420            CPU_FTR_PPCAS_ARCH_V2 | \
 421            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
 422            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
 423#define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 424
 425#ifdef __powerpc64__
 426#define CPU_FTRS_POSSIBLE       \
 427            (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |        \
 428            CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 |       \
 429            CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T |           \
 430            CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
 431#else
 432enum {
 433        CPU_FTRS_POSSIBLE =
 434#if CLASSIC_PPC
 435            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 436            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 437            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 438            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 439            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 440            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 441            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 442            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 443            CPU_FTRS_CLASSIC32 |
 444#else
 445            CPU_FTRS_GENERIC_32 |
 446#endif
 447#ifdef CONFIG_8xx
 448            CPU_FTRS_8XX |
 449#endif
 450#ifdef CONFIG_40x
 451            CPU_FTRS_40X |
 452#endif
 453#ifdef CONFIG_44x
 454            CPU_FTRS_44X | CPU_FTRS_440x6 |
 455#endif
 456#ifdef CONFIG_E200
 457            CPU_FTRS_E200 |
 458#endif
 459#ifdef CONFIG_E500
 460            CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
 461#endif
 462            0,
 463};
 464#endif /* __powerpc64__ */
 465
 466#ifdef __powerpc64__
 467#define CPU_FTRS_ALWAYS         \
 468            (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &        \
 469            CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 &       \
 470            CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
 471#else
 472enum {
 473        CPU_FTRS_ALWAYS =
 474#if CLASSIC_PPC
 475            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 476            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 477            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 478            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 479            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 480            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 481            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 482            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 483            CPU_FTRS_CLASSIC32 &
 484#else
 485            CPU_FTRS_GENERIC_32 &
 486#endif
 487#ifdef CONFIG_8xx
 488            CPU_FTRS_8XX &
 489#endif
 490#ifdef CONFIG_40x
 491            CPU_FTRS_40X &
 492#endif
 493#ifdef CONFIG_44x
 494            CPU_FTRS_44X & CPU_FTRS_440x6 &
 495#endif
 496#ifdef CONFIG_E200
 497            CPU_FTRS_E200 &
 498#endif
 499#ifdef CONFIG_E500
 500            CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
 501#endif
 502            CPU_FTRS_POSSIBLE,
 503};
 504#endif /* __powerpc64__ */
 505
 506static inline int cpu_has_feature(unsigned long feature)
 507{
 508        return (CPU_FTRS_ALWAYS & feature) ||
 509               (CPU_FTRS_POSSIBLE
 510                & cur_cpu_spec->cpu_features
 511                & feature);
 512}
 513
 514#endif /* !__ASSEMBLY__ */
 515
 516#endif /* __KERNEL__ */
 517#endif /* __ASM_POWERPC_CPUTABLE_H */
 518