1/* 2 * Contains register definitions common to PowerPC 8xx CPUs. Notice 3 */ 4#ifndef _ASM_POWERPC_REG_8xx_H 5#define _ASM_POWERPC_REG_8xx_H 6 7/* Cache control on the MPC8xx is provided through some additional 8 * special purpose registers. 9 */ 10#define SPRN_IC_CST 560 /* Instruction cache control/status */ 11#define SPRN_IC_ADR 561 /* Address needed for some commands */ 12#define SPRN_IC_DAT 562 /* Read-only data register */ 13#define SPRN_DC_CST 568 /* Data cache control/status */ 14#define SPRN_DC_ADR 569 /* Address needed for some commands */ 15#define SPRN_DC_DAT 570 /* Read-only data register */ 16 17/* Commands. Only the first few are available to the instruction cache. 18*/ 19#define IDC_ENABLE 0x02000000 /* Cache enable */ 20#define IDC_DISABLE 0x04000000 /* Cache disable */ 21#define IDC_LDLCK 0x06000000 /* Load and lock */ 22#define IDC_UNLINE 0x08000000 /* Unlock line */ 23#define IDC_UNALL 0x0a000000 /* Unlock all */ 24#define IDC_INVALL 0x0c000000 /* Invalidate all */ 25 26#define DC_FLINE 0x0e000000 /* Flush data cache line */ 27#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ 28#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ 29#define DC_SLES 0x05000000 /* Set little endian swap mode */ 30#define DC_CLES 0x07000000 /* Clear little endian swap mode */ 31 32/* Status. 33*/ 34#define IDC_ENABLED 0x80000000 /* Cache is enabled */ 35#define IDC_CERR1 0x00200000 /* Cache error 1 */ 36#define IDC_CERR2 0x00100000 /* Cache error 2 */ 37#define IDC_CERR3 0x00080000 /* Cache error 3 */ 38 39#define DC_DFWT 0x40000000 /* Data cache is forced write through */ 40#define DC_LES 0x20000000 /* Caches are little endian mode */ 41 42#endif /* _ASM_POWERPC_REG_8xx_H */ 43