LXR linux/arch/powerpc/include/asm/mmu.h

   1#ifndef _ASM_POWERPC_MMU_H_
   2#define _ASM_POWERPC_MMU_H_
   3#ifdef __KERNEL__
   4
   5#include <asm/asm-compat.h>
   6#include <asm/feature-fixups.h>
   7
   8/*
   9 * MMU features bit definitions
  10 */
  11
  12/*
  13 * First half is MMU families
  14 */
  15#define MMU_FTR_HPTE_TABLE              ASM_CONST(0x00000001)
  16#define MMU_FTR_TYPE_8xx                ASM_CONST(0x00000002)
  17#define MMU_FTR_TYPE_40x                ASM_CONST(0x00000004)
  18#define MMU_FTR_TYPE_44x                ASM_CONST(0x00000008)
  19#define MMU_FTR_TYPE_FSL_E              ASM_CONST(0x00000010)
  20
  21/*
  22 * This is individual features
  23 */
  24
  25/* Enable use of high BAT registers */
  26#define MMU_FTR_USE_HIGH_BATS           ASM_CONST(0x00010000)
  27
  28/* Enable >32-bit physical addresses on 32-bit processor, only used
  29 * by CONFIG_6xx currently as BookE supports that from day 1
  30 */
  31#define MMU_FTR_BIG_PHYS                ASM_CONST(0x00020000)
  32
  33/* Enable use of broadcast TLB invalidations. We don't always set it
  34 * on processors that support it due to other constraints with the
  35 * use of such invalidations
  36 */
  37#define MMU_FTR_USE_TLBIVAX_BCAST       ASM_CONST(0x00040000)
  38
  39/* Enable use of tlbilx invalidate instructions.
  40 */
  41#define MMU_FTR_USE_TLBILX              ASM_CONST(0x00080000)
  42
  43/* This indicates that the processor cannot handle multiple outstanding
  44 * broadcast tlbivax or tlbsync. This makes the code use a spinlock
  45 * around such invalidate forms.
  46 */
  47#define MMU_FTR_LOCK_BCAST_INVAL        ASM_CONST(0x00100000)
  48
  49/* This indicates that the processor doesn't handle way selection
  50 * properly and needs SW to track and update the LRU state.  This
  51 * is specific to an errata on e300c2/c3/c4 class parts
  52 */
  53#define MMU_FTR_NEED_DTLB_SW_LRU        ASM_CONST(0x00200000)
  54
  55#ifndef __ASSEMBLY__
  56#include <asm/cputable.h>
  57
  58static inline int mmu_has_feature(unsigned long feature)
  59{
  60        return (cur_cpu_spec->mmu_features & feature);
  61}
  62
  63extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
  64
  65/* MMU initialization (64-bit only fo now) */
  66extern void early_init_mmu(void);
  67extern void early_init_mmu_secondary(void);
  68
  69#endif /* !__ASSEMBLY__ */
  70
  71
  72#ifdef CONFIG_PPC64
  73/* 64-bit classic hash table MMU */
  74#  include <asm/mmu-hash64.h>
  75#elif defined(CONFIG_PPC_STD_MMU)
  76/* 32-bit classic hash table MMU */
  77#  include <asm/mmu-hash32.h>
  78#elif defined(CONFIG_40x)
  79/* 40x-style software loaded TLB */
  80#  include <asm/mmu-40x.h>
  81#elif defined(CONFIG_44x)
  82/* 44x-style software loaded TLB */
  83#  include <asm/mmu-44x.h>
  84#elif defined(CONFIG_PPC_BOOK3E_MMU)
  85/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
  86#  include <asm/mmu-book3e.h>
  87#elif defined (CONFIG_PPC_8xx)
  88/* Motorola/Freescale 8xx software loaded TLB */
  89#  include <asm/mmu-8xx.h>
  90#endif
  91
  92#endif /* __KERNEL__ */
  93#endif /* _ASM_POWERPC_MMU_H_ */
  94