LXR linux/arch/powerpc/include/asm/cpm1.h

   1/*
   2 * MPC8xx Communication Processor Module.
   3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4 *
   5 * This file contains structures and information for the communication
   6 * processor channels.  Some CPM control and status is available
   7 * throught the MPC8xx internal memory map.  See immap.h for details.
   8 * This file only contains what I need for the moment, not the total
   9 * CPM capabilities.  I (or someone else) will add definitions as they
  10 * are needed.  -- Dan
  11 *
  12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  13 * bytes of the DP RAM and relocates the I2C parameter area to the
  14 * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  15 * or other use.
  16 */
  17#ifndef __CPM1__
  18#define __CPM1__
  19
  20#include <asm/8xx_immap.h>
  21#include <asm/ptrace.h>
  22#include <asm/cpm.h>
  23
  24/* CPM Command register.
  25*/
  26#define CPM_CR_RST      ((ushort)0x8000)
  27#define CPM_CR_OPCODE   ((ushort)0x0f00)
  28#define CPM_CR_CHAN     ((ushort)0x00f0)
  29#define CPM_CR_FLG      ((ushort)0x0001)
  30
  31/* Channel numbers.
  32*/
  33#define CPM_CR_CH_SCC1          ((ushort)0x0000)
  34#define CPM_CR_CH_I2C           ((ushort)0x0001)        /* I2C and IDMA1 */
  35#define CPM_CR_CH_SCC2          ((ushort)0x0004)
  36#define CPM_CR_CH_SPI           ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
  37#define CPM_CR_CH_TIMER         CPM_CR_CH_SPI
  38#define CPM_CR_CH_SCC3          ((ushort)0x0008)
  39#define CPM_CR_CH_SMC1          ((ushort)0x0009)        /* SMC1 / DSP1 */
  40#define CPM_CR_CH_SCC4          ((ushort)0x000c)
  41#define CPM_CR_CH_SMC2          ((ushort)0x000d)        /* SMC2 / DSP2 */
  42
  43#define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  44
  45/* Export the base address of the communication processor registers
  46 * and dual port ram.
  47 */
  48extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
  49
  50#define cpm_dpalloc cpm_muram_alloc
  51#define cpm_dpfree cpm_muram_free
  52#define cpm_dpram_addr cpm_muram_addr
  53#define cpm_dpram_phys cpm_muram_dma
  54
  55extern void cpm_setbrg(uint brg, uint rate);
  56
  57extern void cpm_load_patch(cpm8xx_t *cp);
  58
  59extern void cpm_reset(void);
  60
  61/* Parameter RAM offsets.
  62*/
  63#define PROFF_SCC1      ((uint)0x0000)
  64#define PROFF_IIC       ((uint)0x0080)
  65#define PROFF_SCC2      ((uint)0x0100)
  66#define PROFF_SPI       ((uint)0x0180)
  67#define PROFF_SCC3      ((uint)0x0200)
  68#define PROFF_SMC1      ((uint)0x0280)
  69#define PROFF_SCC4      ((uint)0x0300)
  70#define PROFF_SMC2      ((uint)0x0380)
  71
  72/* Define enough so I can at least use the serial port as a UART.
  73 * The MBX uses SMC1 as the host serial port.
  74 */
  75typedef struct smc_uart {
  76        ushort  smc_rbase;      /* Rx Buffer descriptor base address */
  77        ushort  smc_tbase;      /* Tx Buffer descriptor base address */
  78        u_char  smc_rfcr;       /* Rx function code */
  79        u_char  smc_tfcr;       /* Tx function code */
  80        ushort  smc_mrblr;      /* Max receive buffer length */
  81        uint    smc_rstate;     /* Internal */
  82        uint    smc_idp;        /* Internal */
  83        ushort  smc_rbptr;      /* Internal */
  84        ushort  smc_ibc;        /* Internal */
  85        uint    smc_rxtmp;      /* Internal */
  86        uint    smc_tstate;     /* Internal */
  87        uint    smc_tdp;        /* Internal */
  88        ushort  smc_tbptr;      /* Internal */
  89        ushort  smc_tbc;        /* Internal */
  90        uint    smc_txtmp;      /* Internal */
  91        ushort  smc_maxidl;     /* Maximum idle characters */
  92        ushort  smc_tmpidl;     /* Temporary idle counter */
  93        ushort  smc_brklen;     /* Last received break length */
  94        ushort  smc_brkec;      /* rcv'd break condition counter */
  95        ushort  smc_brkcr;      /* xmt break count register */
  96        ushort  smc_rmask;      /* Temporary bit mask */
  97        char    res1[8];        /* Reserved */
  98        ushort  smc_rpbase;     /* Relocation pointer */
  99} smc_uart_t;
 100
 101/* Function code bits.
 102*/
 103#define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 104
 105/* SMC uart mode register.
 106*/
 107#define SMCMR_REN       ((ushort)0x0001)
 108#define SMCMR_TEN       ((ushort)0x0002)
 109#define SMCMR_DM        ((ushort)0x000c)
 110#define SMCMR_SM_GCI    ((ushort)0x0000)
 111#define SMCMR_SM_UART   ((ushort)0x0020)
 112#define SMCMR_SM_TRANS  ((ushort)0x0030)
 113#define SMCMR_SM_MASK   ((ushort)0x0030)
 114#define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 115#define SMCMR_REVD      SMCMR_PM_EVEN
 116#define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 117#define SMCMR_BS        SMCMR_PEN
 118#define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 119#define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 120#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 121
 122/* SMC2 as Centronics parallel printer.  It is half duplex, in that
 123 * it can only receive or transmit.  The parameter ram values for
 124 * each direction are either unique or properly overlap, so we can
 125 * include them in one structure.
 126 */
 127typedef struct smc_centronics {
 128        ushort  scent_rbase;
 129        ushort  scent_tbase;
 130        u_char  scent_cfcr;
 131        u_char  scent_smask;
 132        ushort  scent_mrblr;
 133        uint    scent_rstate;
 134        uint    scent_r_ptr;
 135        ushort  scent_rbptr;
 136        ushort  scent_r_cnt;
 137        uint    scent_rtemp;
 138        uint    scent_tstate;
 139        uint    scent_t_ptr;
 140        ushort  scent_tbptr;
 141        ushort  scent_t_cnt;
 142        uint    scent_ttemp;
 143        ushort  scent_max_sl;
 144        ushort  scent_sl_cnt;
 145        ushort  scent_character1;
 146        ushort  scent_character2;
 147        ushort  scent_character3;
 148        ushort  scent_character4;
 149        ushort  scent_character5;
 150        ushort  scent_character6;
 151        ushort  scent_character7;
 152        ushort  scent_character8;
 153        ushort  scent_rccm;
 154        ushort  scent_rccr;
 155} smc_cent_t;
 156
 157/* Centronics Status Mask Register.
 158*/
 159#define SMC_CENT_F      ((u_char)0x08)
 160#define SMC_CENT_PE     ((u_char)0x04)
 161#define SMC_CENT_S      ((u_char)0x02)
 162
 163/* SMC Event and Mask register.
 164*/
 165#define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 166#define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 167#define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 168#define SMCM_BSY        ((unsigned char)0x04)
 169#define SMCM_TX         ((unsigned char)0x02)
 170#define SMCM_RX         ((unsigned char)0x01)
 171
 172/* Baud rate generators.
 173*/
 174#define CPM_BRG_RST             ((uint)0x00020000)
 175#define CPM_BRG_EN              ((uint)0x00010000)
 176#define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 177#define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 178#define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 179#define CPM_BRG_ATB             ((uint)0x00002000)
 180#define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 181#define CPM_BRG_DIV16           ((uint)0x00000001)
 182
 183/* SI Clock Route Register
 184*/
 185#define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 186#define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 187#define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 188#define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 189#define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 190#define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 191#define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 192#define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 193
 194/* SCCs.
 195*/
 196#define SCC_GSMRH_IRP           ((uint)0x00040000)
 197#define SCC_GSMRH_GDE           ((uint)0x00010000)
 198#define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 199#define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 200#define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 201#define SCC_GSMRH_REVD          ((uint)0x00002000)
 202#define SCC_GSMRH_TRX           ((uint)0x00001000)
 203#define SCC_GSMRH_TTX           ((uint)0x00000800)
 204#define SCC_GSMRH_CDP           ((uint)0x00000400)
 205#define SCC_GSMRH_CTSP          ((uint)0x00000200)
 206#define SCC_GSMRH_CDS           ((uint)0x00000100)
 207#define SCC_GSMRH_CTSS          ((uint)0x00000080)
 208#define SCC_GSMRH_TFL           ((uint)0x00000040)
 209#define SCC_GSMRH_RFW           ((uint)0x00000020)
 210#define SCC_GSMRH_TXSY          ((uint)0x00000010)
 211#define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 212#define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 213#define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 214#define SCC_GSMRH_RTSM          ((uint)0x00000002)
 215#define SCC_GSMRH_RSYN          ((uint)0x00000001)
 216
 217#define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 218#define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 219#define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 220#define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 221#define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 222#define SCC_GSMRL_TCI           ((uint)0x10000000)
 223#define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 224#define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 225#define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 226#define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 227#define SCC_GSMRL_RINV          ((uint)0x02000000)
 228#define SCC_GSMRL_TINV          ((uint)0x01000000)
 229#define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 230#define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 231#define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 232#define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 233#define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 234#define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 235#define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 236#define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 237#define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 238#define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 239#define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 240#define SCC_GSMRL_TEND          ((uint)0x00040000)
 241#define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 242#define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 243#define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 244#define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 245#define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 246#define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 247#define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 248#define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 249#define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 250#define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 251#define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 252#define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 253#define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 254#define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 255#define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 256#define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 257#define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 258#define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 259#define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 260#define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 261#define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 262#define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 263#define SCC_GSMRL_ENR           ((uint)0x00000020)
 264#define SCC_GSMRL_ENT           ((uint)0x00000010)
 265#define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 266#define SCC_GSMRL_MODE_QMC      ((uint)0x0000000a)
 267#define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 268#define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 269#define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 270#define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 271#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 272#define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 273#define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 274#define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 275#define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 276
 277#define SCC_TODR_TOD            ((ushort)0x8000)
 278
 279/* SCC Event and Mask register.
 280*/
 281#define SCCM_TXE        ((unsigned char)0x10)
 282#define SCCM_BSY        ((unsigned char)0x04)
 283#define SCCM_TX         ((unsigned char)0x02)
 284#define SCCM_RX         ((unsigned char)0x01)
 285
 286typedef struct scc_param {
 287        ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 288        ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 289        u_char  scc_rfcr;       /* Rx function code */
 290        u_char  scc_tfcr;       /* Tx function code */
 291        ushort  scc_mrblr;      /* Max receive buffer length */
 292        uint    scc_rstate;     /* Internal */
 293        uint    scc_idp;        /* Internal */
 294        ushort  scc_rbptr;      /* Internal */
 295        ushort  scc_ibc;        /* Internal */
 296        uint    scc_rxtmp;      /* Internal */
 297        uint    scc_tstate;     /* Internal */
 298        uint    scc_tdp;        /* Internal */
 299        ushort  scc_tbptr;      /* Internal */
 300        ushort  scc_tbc;        /* Internal */
 301        uint    scc_txtmp;      /* Internal */
 302        uint    scc_rcrc;       /* Internal */
 303        uint    scc_tcrc;       /* Internal */
 304} sccp_t;
 305
 306/* Function code bits.
 307*/
 308#define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 309
 310/* CPM Ethernet through SCCx.
 311 */
 312typedef struct scc_enet {
 313        sccp_t  sen_genscc;
 314        uint    sen_cpres;      /* Preset CRC */
 315        uint    sen_cmask;      /* Constant mask for CRC */
 316        uint    sen_crcec;      /* CRC Error counter */
 317        uint    sen_alec;       /* alignment error counter */
 318        uint    sen_disfc;      /* discard frame counter */
 319        ushort  sen_pads;       /* Tx short frame pad character */
 320        ushort  sen_retlim;     /* Retry limit threshold */
 321        ushort  sen_retcnt;     /* Retry limit counter */
 322        ushort  sen_maxflr;     /* maximum frame length register */
 323        ushort  sen_minflr;     /* minimum frame length register */
 324        ushort  sen_maxd1;      /* maximum DMA1 length */
 325        ushort  sen_maxd2;      /* maximum DMA2 length */
 326        ushort  sen_maxd;       /* Rx max DMA */
 327        ushort  sen_dmacnt;     /* Rx DMA counter */
 328        ushort  sen_maxb;       /* Max BD byte count */
 329        ushort  sen_gaddr1;     /* Group address filter */
 330        ushort  sen_gaddr2;
 331        ushort  sen_gaddr3;
 332        ushort  sen_gaddr4;
 333        uint    sen_tbuf0data0; /* Save area 0 - current frame */
 334        uint    sen_tbuf0data1; /* Save area 1 - current frame */
 335        uint    sen_tbuf0rba;   /* Internal */
 336        uint    sen_tbuf0crc;   /* Internal */
 337        ushort  sen_tbuf0bcnt;  /* Internal */
 338        ushort  sen_paddrh;     /* physical address (MSB) */
 339        ushort  sen_paddrm;
 340        ushort  sen_paddrl;     /* physical address (LSB) */
 341        ushort  sen_pper;       /* persistence */
 342        ushort  sen_rfbdptr;    /* Rx first BD pointer */
 343        ushort  sen_tfbdptr;    /* Tx first BD pointer */
 344        ushort  sen_tlbdptr;    /* Tx last BD pointer */
 345        uint    sen_tbuf1data0; /* Save area 0 - current frame */
 346        uint    sen_tbuf1data1; /* Save area 1 - current frame */
 347        uint    sen_tbuf1rba;   /* Internal */
 348        uint    sen_tbuf1crc;   /* Internal */
 349        ushort  sen_tbuf1bcnt;  /* Internal */
 350        ushort  sen_txlen;      /* Tx Frame length counter */
 351        ushort  sen_iaddr1;     /* Individual address filter */
 352        ushort  sen_iaddr2;
 353        ushort  sen_iaddr3;
 354        ushort  sen_iaddr4;
 355        ushort  sen_boffcnt;    /* Backoff counter */
 356
 357        /* NOTE: Some versions of the manual have the following items
 358         * incorrectly documented.  Below is the proper order.
 359         */
 360        ushort  sen_taddrh;     /* temp address (MSB) */
 361        ushort  sen_taddrm;
 362        ushort  sen_taddrl;     /* temp address (LSB) */
 363} scc_enet_t;
 364
 365/* SCC Event register as used by Ethernet.
 366*/
 367#define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 368#define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 369#define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 370#define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 371#define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 372#define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 373
 374/* SCC Mode Register (PMSR) as used by Ethernet.
 375*/
 376#define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 377#define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 378#define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 379#define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 380#define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 381#define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 382#define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 383#define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 384#define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 385#define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 386#define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 387#define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 388#define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 389
 390/* SCC as UART
 391*/
 392typedef struct scc_uart {
 393        sccp_t  scc_genscc;
 394        char    res1[8];        /* Reserved */
 395        ushort  scc_maxidl;     /* Maximum idle chars */
 396        ushort  scc_idlc;       /* temp idle counter */
 397        ushort  scc_brkcr;      /* Break count register */
 398        ushort  scc_parec;      /* receive parity error counter */
 399        ushort  scc_frmec;      /* receive framing error counter */
 400        ushort  scc_nosec;      /* receive noise counter */
 401        ushort  scc_brkec;      /* receive break condition counter */
 402        ushort  scc_brkln;      /* last received break length */
 403        ushort  scc_uaddr1;     /* UART address character 1 */
 404        ushort  scc_uaddr2;     /* UART address character 2 */
 405        ushort  scc_rtemp;      /* Temp storage */
 406        ushort  scc_toseq;      /* Transmit out of sequence char */
 407        ushort  scc_char1;      /* control character 1 */
 408        ushort  scc_char2;      /* control character 2 */
 409        ushort  scc_char3;      /* control character 3 */
 410        ushort  scc_char4;      /* control character 4 */
 411        ushort  scc_char5;      /* control character 5 */
 412        ushort  scc_char6;      /* control character 6 */
 413        ushort  scc_char7;      /* control character 7 */
 414        ushort  scc_char8;      /* control character 8 */
 415        ushort  scc_rccm;       /* receive control character mask */
 416        ushort  scc_rccr;       /* receive control character register */
 417        ushort  scc_rlbc;       /* receive last break character */
 418} scc_uart_t;
 419
 420/* SCC Event and Mask registers when it is used as a UART.
 421*/
 422#define UART_SCCM_GLR           ((ushort)0x1000)
 423#define UART_SCCM_GLT           ((ushort)0x0800)
 424#define UART_SCCM_AB            ((ushort)0x0200)
 425#define UART_SCCM_IDL           ((ushort)0x0100)
 426#define UART_SCCM_GRA           ((ushort)0x0080)
 427#define UART_SCCM_BRKE          ((ushort)0x0040)
 428#define UART_SCCM_BRKS          ((ushort)0x0020)
 429#define UART_SCCM_CCR           ((ushort)0x0008)
 430#define UART_SCCM_BSY           ((ushort)0x0004)
 431#define UART_SCCM_TX            ((ushort)0x0002)
 432#define UART_SCCM_RX            ((ushort)0x0001)
 433
 434/* The SCC PMSR when used as a UART.
 435*/
 436#define SCU_PSMR_FLC            ((ushort)0x8000)
 437#define SCU_PSMR_SL             ((ushort)0x4000)
 438#define SCU_PSMR_CL             ((ushort)0x3000)
 439#define SCU_PSMR_UM             ((ushort)0x0c00)
 440#define SCU_PSMR_FRZ            ((ushort)0x0200)
 441#define SCU_PSMR_RZS            ((ushort)0x0100)
 442#define SCU_PSMR_SYN            ((ushort)0x0080)
 443#define SCU_PSMR_DRT            ((ushort)0x0040)
 444#define SCU_PSMR_PEN            ((ushort)0x0010)
 445#define SCU_PSMR_RPM            ((ushort)0x000c)
 446#define SCU_PSMR_REVP           ((ushort)0x0008)
 447#define SCU_PSMR_TPM            ((ushort)0x0003)
 448#define SCU_PSMR_TEVP           ((ushort)0x0002)
 449
 450/* CPM Transparent mode SCC.
 451 */
 452typedef struct scc_trans {
 453        sccp_t  st_genscc;
 454        uint    st_cpres;       /* Preset CRC */
 455        uint    st_cmask;       /* Constant mask for CRC */
 456} scc_trans_t;
 457
 458/* IIC parameter RAM.
 459*/
 460typedef struct iic {
 461        ushort  iic_rbase;      /* Rx Buffer descriptor base address */
 462        ushort  iic_tbase;      /* Tx Buffer descriptor base address */
 463        u_char  iic_rfcr;       /* Rx function code */
 464        u_char  iic_tfcr;       /* Tx function code */
 465        ushort  iic_mrblr;      /* Max receive buffer length */
 466        uint    iic_rstate;     /* Internal */
 467        uint    iic_rdp;        /* Internal */
 468        ushort  iic_rbptr;      /* Internal */
 469        ushort  iic_rbc;        /* Internal */
 470        uint    iic_rxtmp;      /* Internal */
 471        uint    iic_tstate;     /* Internal */
 472        uint    iic_tdp;        /* Internal */
 473        ushort  iic_tbptr;      /* Internal */
 474        ushort  iic_tbc;        /* Internal */
 475        uint    iic_txtmp;      /* Internal */
 476        char    res1[4];        /* Reserved */
 477        ushort  iic_rpbase;     /* Relocation pointer */
 478        char    res2[2];        /* Reserved */
 479} iic_t;
 480
 481/* SPI parameter RAM.
 482*/
 483typedef struct spi {
 484        ushort  spi_rbase;      /* Rx Buffer descriptor base address */
 485        ushort  spi_tbase;      /* Tx Buffer descriptor base address */
 486        u_char  spi_rfcr;       /* Rx function code */
 487        u_char  spi_tfcr;       /* Tx function code */
 488        ushort  spi_mrblr;      /* Max receive buffer length */
 489        uint    spi_rstate;     /* Internal */
 490        uint    spi_rdp;        /* Internal */
 491        ushort  spi_rbptr;      /* Internal */
 492        ushort  spi_rbc;        /* Internal */
 493        uint    spi_rxtmp;      /* Internal */
 494        uint    spi_tstate;     /* Internal */
 495        uint    spi_tdp;        /* Internal */
 496        ushort  spi_tbptr;      /* Internal */
 497        ushort  spi_tbc;        /* Internal */
 498        uint    spi_txtmp;      /* Internal */
 499        uint    spi_res;
 500        ushort  spi_rpbase;     /* Relocation pointer */
 501        ushort  spi_res2;
 502} spi_t;
 503
 504/* SPI Mode register.
 505*/
 506#define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
 507#define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
 508#define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
 509#define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
 510#define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
 511#define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
 512#define SPMODE_EN       ((ushort)0x0100)        /* Enable */
 513#define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
 514#define SPMODE_LEN4     ((ushort)0x0030)        /*  4 bits per char */
 515#define SPMODE_LEN8     ((ushort)0x0070)        /*  8 bits per char */
 516#define SPMODE_LEN16    ((ushort)0x00f0)        /* 16 bits per char */
 517#define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
 518
 519/* SPIE fields */
 520#define SPIE_MME        0x20
 521#define SPIE_TXE        0x10
 522#define SPIE_BSY        0x04
 523#define SPIE_TXB        0x02
 524#define SPIE_RXB        0x01
 525
 526/*
 527 * RISC Controller Configuration Register definitons
 528 */
 529#define RCCR_TIME       0x8000                  /* RISC Timer Enable */
 530#define RCCR_TIMEP(t)   (((t) & 0x3F)<<8)       /* RISC Timer Period */
 531#define RCCR_TIME_MASK  0x00FF                  /* not RISC Timer related bits */
 532
 533/* RISC Timer Parameter RAM offset */
 534#define PROFF_RTMR      ((uint)0x01B0)
 535
 536typedef struct risc_timer_pram {
 537        unsigned short  tm_base;        /* RISC Timer Table Base Address */
 538        unsigned short  tm_ptr;         /* RISC Timer Table Pointer (internal) */
 539        unsigned short  r_tmr;          /* RISC Timer Mode Register */
 540        unsigned short  r_tmv;          /* RISC Timer Valid Register */
 541        unsigned long   tm_cmd;         /* RISC Timer Command Register */
 542        unsigned long   tm_cnt;         /* RISC Timer Internal Count */
 543} rt_pram_t;
 544
 545/* Bits in RISC Timer Command Register */
 546#define TM_CMD_VALID    0x80000000      /* Valid - Enables the timer */
 547#define TM_CMD_RESTART  0x40000000      /* Restart - for automatic restart */
 548#define TM_CMD_PWM      0x20000000      /* Run in Pulse Width Modulation Mode */
 549#define TM_CMD_NUM(n)   (((n)&0xF)<<16) /* Timer Number */
 550#define TM_CMD_PERIOD(p) ((p)&0xFFFF)   /* Timer Period */
 551
 552/* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 553 * channels or devices.  All of these are presented to the PPC core
 554 * as a single interrupt.  The CPM interrupt handler dispatches its
 555 * own handlers, in a similar fashion to the PPC core handler.  We
 556 * use the table as defined in the manuals (i.e. no special high
 557 * priority and SCC1 == SCCa, etc...).
 558 */
 559#define CPMVEC_NR               32
 560#define CPMVEC_PIO_PC15         ((ushort)0x1f)
 561#define CPMVEC_SCC1             ((ushort)0x1e)
 562#define CPMVEC_SCC2             ((ushort)0x1d)
 563#define CPMVEC_SCC3             ((ushort)0x1c)
 564#define CPMVEC_SCC4             ((ushort)0x1b)
 565#define CPMVEC_PIO_PC14         ((ushort)0x1a)
 566#define CPMVEC_TIMER1           ((ushort)0x19)
 567#define CPMVEC_PIO_PC13         ((ushort)0x18)
 568#define CPMVEC_PIO_PC12         ((ushort)0x17)
 569#define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
 570#define CPMVEC_IDMA1            ((ushort)0x15)
 571#define CPMVEC_IDMA2            ((ushort)0x14)
 572#define CPMVEC_TIMER2           ((ushort)0x12)
 573#define CPMVEC_RISCTIMER        ((ushort)0x11)
 574#define CPMVEC_I2C              ((ushort)0x10)
 575#define CPMVEC_PIO_PC11         ((ushort)0x0f)
 576#define CPMVEC_PIO_PC10         ((ushort)0x0e)
 577#define CPMVEC_TIMER3           ((ushort)0x0c)
 578#define CPMVEC_PIO_PC9          ((ushort)0x0b)
 579#define CPMVEC_PIO_PC8          ((ushort)0x0a)
 580#define CPMVEC_PIO_PC7          ((ushort)0x09)
 581#define CPMVEC_TIMER4           ((ushort)0x07)
 582#define CPMVEC_PIO_PC6          ((ushort)0x06)
 583#define CPMVEC_SPI              ((ushort)0x05)
 584#define CPMVEC_SMC1             ((ushort)0x04)
 585#define CPMVEC_SMC2             ((ushort)0x03)
 586#define CPMVEC_PIO_PC5          ((ushort)0x02)
 587#define CPMVEC_PIO_PC4          ((ushort)0x01)
 588#define CPMVEC_ERROR            ((ushort)0x00)
 589
 590/* CPM interrupt configuration vector.
 591*/
 592#define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
 593#define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 594#define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 595#define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
 596#define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
 597#define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
 598#define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
 599#define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
 600
 601#define IMAP_ADDR               (get_immrbase())
 602
 603#define CPM_PIN_INPUT     0
 604#define CPM_PIN_OUTPUT    1
 605#define CPM_PIN_PRIMARY   0
 606#define CPM_PIN_SECONDARY 2
 607#define CPM_PIN_GPIO      4
 608#define CPM_PIN_OPENDRAIN 8
 609
 610enum cpm_port {
 611        CPM_PORTA,
 612        CPM_PORTB,
 613        CPM_PORTC,
 614        CPM_PORTD,
 615        CPM_PORTE,
 616};
 617
 618void cpm1_set_pin(enum cpm_port port, int pin, int flags);
 619
 620enum cpm_clk_dir {
 621        CPM_CLK_RX,
 622        CPM_CLK_TX,
 623        CPM_CLK_RTX
 624};
 625
 626enum cpm_clk_target {
 627        CPM_CLK_SCC1,
 628        CPM_CLK_SCC2,
 629        CPM_CLK_SCC3,
 630        CPM_CLK_SCC4,
 631        CPM_CLK_SMC1,
 632        CPM_CLK_SMC2,
 633};
 634
 635enum cpm_clk {
 636        CPM_BRG1,       /* Baud Rate Generator  1 */
 637        CPM_BRG2,       /* Baud Rate Generator  2 */
 638        CPM_BRG3,       /* Baud Rate Generator  3 */
 639        CPM_BRG4,       /* Baud Rate Generator  4 */
 640        CPM_CLK1,       /* Clock  1 */
 641        CPM_CLK2,       /* Clock  2 */
 642        CPM_CLK3,       /* Clock  3 */
 643        CPM_CLK4,       /* Clock  4 */
 644        CPM_CLK5,       /* Clock  5 */
 645        CPM_CLK6,       /* Clock  6 */
 646        CPM_CLK7,       /* Clock  7 */
 647        CPM_CLK8,       /* Clock  8 */
 648};
 649
 650int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode);
 651
 652#endif /* __CPM1__ */
 653