linux/arch/cris/arch-v32/kernel/time.c
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   1/*
   2 *  linux/arch/cris/arch-v32/kernel/time.c
   3 *
   4 *  Copyright (C) 2003-2007 Axis Communications AB
   5 *
   6 */
   7
   8#include <linux/timex.h>
   9#include <linux/time.h>
  10#include <linux/jiffies.h>
  11#include <linux/interrupt.h>
  12#include <linux/swap.h>
  13#include <linux/sched.h>
  14#include <linux/init.h>
  15#include <linux/threads.h>
  16#include <linux/cpufreq.h>
  17#include <asm/types.h>
  18#include <asm/signal.h>
  19#include <asm/io.h>
  20#include <asm/delay.h>
  21#include <asm/rtc.h>
  22#include <asm/irq.h>
  23#include <asm/irq_regs.h>
  24
  25#include <hwregs/reg_map.h>
  26#include <hwregs/reg_rdwr.h>
  27#include <hwregs/timer_defs.h>
  28#include <hwregs/intr_vect_defs.h>
  29#ifdef CONFIG_CRIS_MACH_ARTPEC3
  30#include <hwregs/clkgen_defs.h>
  31#endif
  32
  33/* Watchdog defines */
  34#define ETRAX_WD_KEY_MASK       0x7F /* key is 7 bit */
  35#define ETRAX_WD_HZ             763 /* watchdog counts at 763 Hz */
  36/* Number of 763 counts before watchdog bites */
  37#define ETRAX_WD_CNT            ((2*ETRAX_WD_HZ)/HZ + 1)
  38
  39unsigned long timer_regs[NR_CPUS] =
  40{
  41        regi_timer0,
  42#ifdef CONFIG_SMP
  43        regi_timer2
  44#endif
  45};
  46
  47extern void update_xtime_from_cmos(void);
  48extern int set_rtc_mmss(unsigned long nowtime);
  49extern int setup_irq(int, struct irqaction *);
  50extern int have_rtc;
  51
  52#ifdef CONFIG_CPU_FREQ
  53static int
  54cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
  55                        void *data);
  56
  57static struct notifier_block cris_time_freq_notifier_block = {
  58        .notifier_call = cris_time_freq_notifier,
  59};
  60#endif
  61
  62unsigned long get_ns_in_jiffie(void)
  63{
  64        reg_timer_r_tmr0_data data;
  65        unsigned long ns;
  66
  67        data = REG_RD(timer, regi_timer0, r_tmr0_data);
  68        ns = (TIMER0_DIV - data) * 10;
  69        return ns;
  70}
  71
  72unsigned long do_slow_gettimeoffset(void)
  73{
  74        unsigned long count;
  75        unsigned long usec_count = 0;
  76
  77        /* For the first call after boot */
  78        static unsigned long count_p = TIMER0_DIV;
  79        static unsigned long jiffies_p = 0;
  80
  81        /* Cache volatile jiffies temporarily; we have IRQs turned off. */
  82        unsigned long jiffies_t;
  83
  84        /* The timer interrupt comes from Etrax timer 0. In order to get
  85         * better precision, we check the current value. It might have
  86         * underflowed already though. */
  87        count = REG_RD(timer, regi_timer0, r_tmr0_data);
  88        jiffies_t = jiffies;
  89
  90        /* Avoiding timer inconsistencies (they are rare, but they happen)
  91         * There is one problem that must be avoided here:
  92         *      1. the timer counter underflows
  93         */
  94        if( jiffies_t == jiffies_p ) {
  95                if( count > count_p ) {
  96                        /* Timer wrapped, use new count and prescale.
  97                         * Increase the time corresponding to one jiffy.
  98                         */
  99                        usec_count = 1000000/HZ;
 100                }
 101        } else
 102                jiffies_p = jiffies_t;
 103        count_p = count;
 104        /* Convert timer value to usec */
 105        /* 100 MHz timer, divide by 100 to get usec */
 106        usec_count +=  (TIMER0_DIV - count) / 100;
 107        return usec_count;
 108}
 109
 110/* From timer MDS describing the hardware watchdog:
 111 * 4.3.1 Watchdog Operation
 112 * The watchdog timer is an 8-bit timer with a configurable start value.
 113 * Once started the watchdog counts downwards with a frequency of 763 Hz
 114 * (100/131072 MHz). When the watchdog counts down to 1, it generates an
 115 * NMI (Non Maskable Interrupt), and when it counts down to 0, it resets the
 116 * chip.
 117 */
 118/* This gives us 1.3 ms to do something useful when the NMI comes */
 119
 120/* Right now, starting the watchdog is the same as resetting it */
 121#define start_watchdog reset_watchdog
 122
 123#if defined(CONFIG_ETRAX_WATCHDOG)
 124static short int watchdog_key = 42;  /* arbitrary 7 bit number */
 125#endif
 126
 127/* Number of pages to consider "out of memory". It is normal that the memory
 128 * is used though, so set this really low. */
 129#define WATCHDOG_MIN_FREE_PAGES 8
 130
 131void
 132reset_watchdog(void)
 133{
 134#if defined(CONFIG_ETRAX_WATCHDOG)
 135        reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 136
 137        /* Only keep watchdog happy as long as we have memory left! */
 138        if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 139                /* Reset the watchdog with the inverse of the old key */
 140                /* Invert key, which is 7 bits */
 141                watchdog_key ^= ETRAX_WD_KEY_MASK;
 142                wd_ctrl.cnt = ETRAX_WD_CNT;
 143                wd_ctrl.cmd = regk_timer_start;
 144                wd_ctrl.key = watchdog_key;
 145                REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 146        }
 147#endif
 148}
 149
 150/* stop the watchdog - we still need the correct key */
 151
 152void
 153stop_watchdog(void)
 154{
 155#if defined(CONFIG_ETRAX_WATCHDOG)
 156        reg_timer_rw_wd_ctrl wd_ctrl = { 0 };
 157        watchdog_key ^= ETRAX_WD_KEY_MASK; /* invert key, which is 7 bits */
 158        wd_ctrl.cnt = ETRAX_WD_CNT;
 159        wd_ctrl.cmd = regk_timer_stop;
 160        wd_ctrl.key = watchdog_key;
 161        REG_WR(timer, regi_timer0, rw_wd_ctrl, wd_ctrl);
 162#endif
 163}
 164
 165extern void show_registers(struct pt_regs *regs);
 166
 167void
 168handle_watchdog_bite(struct pt_regs* regs)
 169{
 170#if defined(CONFIG_ETRAX_WATCHDOG)
 171        extern int cause_of_death;
 172
 173        oops_in_progress = 1;
 174        printk(KERN_WARNING "Watchdog bite\n");
 175
 176        /* Check if forced restart or unexpected watchdog */
 177        if (cause_of_death == 0xbedead) {
 178#ifdef CONFIG_CRIS_MACH_ARTPEC3
 179                /* There is a bug in Artpec-3 (voodoo TR 78) that requires
 180                 * us to go to lower frequency for the reset to be reliable
 181                 */
 182                reg_clkgen_rw_clk_ctrl ctrl =
 183                        REG_RD(clkgen, regi_clkgen, rw_clk_ctrl);
 184                ctrl.pll = 0;
 185                REG_WR(clkgen, regi_clkgen, rw_clk_ctrl, ctrl);
 186#endif
 187                while(1);
 188        }
 189
 190        /* Unexpected watchdog, stop the watchdog and dump registers. */
 191        stop_watchdog();
 192        printk(KERN_WARNING "Oops: bitten by watchdog\n");
 193        show_registers(regs);
 194        oops_in_progress = 0;
 195#ifndef CONFIG_ETRAX_WATCHDOG_NICE_DOGGY
 196        reset_watchdog();
 197#endif
 198        while(1) /* nothing */;
 199#endif
 200}
 201
 202/* Last time the cmos clock got updated. */
 203static long last_rtc_update = 0;
 204
 205/*
 206 * timer_interrupt() needs to keep up the real-time clock,
 207 * as well as call the "do_timer()" routine every clocktick.
 208 */
 209extern void cris_do_profile(struct pt_regs *regs);
 210
 211static inline irqreturn_t
 212timer_interrupt(int irq, void *dev_id)
 213{
 214        struct pt_regs *regs = get_irq_regs();
 215        int cpu = smp_processor_id();
 216        reg_timer_r_masked_intr masked_intr;
 217        reg_timer_rw_ack_intr ack_intr = { 0 };
 218
 219        /* Check if the timer interrupt is for us (a tmr0 int) */
 220        masked_intr = REG_RD(timer, timer_regs[cpu], r_masked_intr);
 221        if (!masked_intr.tmr0)
 222                return IRQ_NONE;
 223
 224        /* Acknowledge the timer irq. */
 225        ack_intr.tmr0 = 1;
 226        REG_WR(timer, timer_regs[cpu], rw_ack_intr, ack_intr);
 227
 228        /* Reset watchdog otherwise it resets us! */
 229        reset_watchdog();
 230
 231        /* Update statistics. */
 232        update_process_times(user_mode(regs));
 233
 234        cris_do_profile(regs); /* Save profiling information */
 235
 236        /* The master CPU is responsible for the time keeping. */
 237        if (cpu != 0)
 238                return IRQ_HANDLED;
 239
 240        /* Call the real timer interrupt handler */
 241        do_timer(1);
 242
 243        /*
 244         * If we have an externally synchronized Linux clock, then update
 245         * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 246         * called as close as possible to 500 ms before the new second starts.
 247         *
 248         * The division here is not time critical since it will run once in
 249         * 11 minutes
 250         */
 251        if ((time_status & STA_UNSYNC) == 0 &&
 252            xtime.tv_sec > last_rtc_update + 660 &&
 253            (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
 254            (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
 255                if (set_rtc_mmss(xtime.tv_sec) == 0)
 256                        last_rtc_update = xtime.tv_sec;
 257                else
 258                        /* Do it again in 60 s */
 259                        last_rtc_update = xtime.tv_sec - 600;
 260        }
 261        return IRQ_HANDLED;
 262}
 263
 264/* Timer is IRQF_SHARED so drivers can add stuff to the timer irq chain.
 265 * It needs to be IRQF_DISABLED to make the jiffies update work properly.
 266 */
 267static struct irqaction irq_timer = {
 268        .handler = timer_interrupt,
 269        .flags = IRQF_SHARED | IRQF_DISABLED,
 270        .name = "timer"
 271};
 272
 273void __init
 274cris_timer_init(void)
 275{
 276        int cpu = smp_processor_id();
 277        reg_timer_rw_tmr0_ctrl tmr0_ctrl = { 0 };
 278        reg_timer_rw_tmr0_div tmr0_div = TIMER0_DIV;
 279        reg_timer_rw_intr_mask timer_intr_mask;
 280
 281        /* Setup the etrax timers.
 282         * Base frequency is 100MHz, divider 1000000 -> 100 HZ
 283         * We use timer0, so timer1 is free.
 284         * The trig timer is used by the fasttimer API if enabled.
 285         */
 286
 287        tmr0_ctrl.op = regk_timer_ld;
 288        tmr0_ctrl.freq = regk_timer_f100;
 289        REG_WR(timer, timer_regs[cpu], rw_tmr0_div, tmr0_div);
 290        REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Load */
 291        tmr0_ctrl.op = regk_timer_run;
 292        REG_WR(timer, timer_regs[cpu], rw_tmr0_ctrl, tmr0_ctrl); /* Start */
 293
 294        /* Enable the timer irq. */
 295        timer_intr_mask = REG_RD(timer, timer_regs[cpu], rw_intr_mask);
 296        timer_intr_mask.tmr0 = 1;
 297        REG_WR(timer, timer_regs[cpu], rw_intr_mask, timer_intr_mask);
 298}
 299
 300void __init
 301time_init(void)
 302{
 303        reg_intr_vect_rw_mask intr_mask;
 304
 305        /* Probe for the RTC and read it if it exists.
 306         * Before the RTC can be probed the loops_per_usec variable needs
 307         * to be initialized to make usleep work. A better value for
 308         * loops_per_usec is calculated by the kernel later once the
 309         * clock has started.
 310         */
 311        loops_per_usec = 50;
 312
 313        if(RTC_INIT() < 0) {
 314                /* No RTC, start at 1980 */
 315                xtime.tv_sec = 0;
 316                xtime.tv_nsec = 0;
 317                have_rtc = 0;
 318        } else {
 319                /* Get the current time */
 320                have_rtc = 1;
 321                update_xtime_from_cmos();
 322        }
 323
 324        /*
 325         * Initialize wall_to_monotonic such that adding it to
 326         * xtime will yield zero, the tv_nsec field must be normalized
 327         * (i.e., 0 <= nsec < NSEC_PER_SEC).
 328         */
 329        set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
 330
 331        /* Start CPU local timer. */
 332        cris_timer_init();
 333
 334        /* Enable the timer irq in global config. */
 335        intr_mask = REG_RD_VECT(intr_vect, regi_irq, rw_mask, 1);
 336        intr_mask.timer0 = 1;
 337        REG_WR_VECT(intr_vect, regi_irq, rw_mask, 1, intr_mask);
 338
 339        /* Now actually register the timer irq handler that calls
 340         * timer_interrupt(). */
 341        setup_irq(TIMER0_INTR_VECT, &irq_timer);
 342
 343        /* Enable watchdog if we should use one. */
 344
 345#if defined(CONFIG_ETRAX_WATCHDOG)
 346        printk(KERN_INFO "Enabling watchdog...\n");
 347        start_watchdog();
 348
 349        /* If we use the hardware watchdog, we want to trap it as an NMI
 350         * and dump registers before it resets us.  For this to happen, we
 351         * must set the "m" NMI enable flag (which once set, is unset only
 352         * when an NMI is taken). */
 353        {
 354                unsigned long flags;
 355                local_save_flags(flags);
 356                flags |= (1<<30); /* NMI M flag is at bit 30 */
 357                local_irq_restore(flags);
 358        }
 359#endif
 360
 361#ifdef CONFIG_CPU_FREQ
 362        cpufreq_register_notifier(&cris_time_freq_notifier_block,
 363                CPUFREQ_TRANSITION_NOTIFIER);
 364#endif
 365}
 366
 367#ifdef CONFIG_CPU_FREQ
 368static int
 369cris_time_freq_notifier(struct notifier_block *nb, unsigned long val,
 370                        void *data)
 371{
 372        struct cpufreq_freqs *freqs = data;
 373        if (val == CPUFREQ_POSTCHANGE) {
 374                reg_timer_r_tmr0_data data;
 375                reg_timer_rw_tmr0_div div = (freqs->new * 500) / HZ;
 376                do {
 377                        data = REG_RD(timer, timer_regs[freqs->cpu],
 378                                r_tmr0_data);
 379                } while (data > 20);
 380                REG_WR(timer, timer_regs[freqs->cpu], rw_tmr0_div, div);
 381        }
 382        return 0;
 383}
 384#endif
 385