1
2
3
4
5
6
7
8
9
10#undef DEBUG
11
12#include <linux/edac.h>
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/stop_machine.h>
17#include <linux/io.h>
18#include <asm/machdep.h>
19#include <asm/cell-regs.h>
20
21#include "edac_core.h"
22
23struct cell_edac_priv
24{
25 struct cbe_mic_tm_regs __iomem *regs;
26 int node;
27 int chanmask;
28#ifdef DEBUG
29 u64 prev_fir;
30#endif
31};
32
33static void cell_edac_count_ce(struct mem_ctl_info *mci, int chan, u64 ar)
34{
35 struct cell_edac_priv *priv = mci->pvt_info;
36 struct csrow_info *csrow = &mci->csrows[0];
37 unsigned long address, pfn, offset, syndrome;
38
39 dev_dbg(mci->dev, "ECC CE err on node %d, channel %d, ar = 0x%016llx\n",
40 priv->node, chan, ar);
41
42
43 address = (ar & 0xffffffffe0000000ul) >> 29;
44 if (priv->chanmask == 0x3)
45 address = (address << 1) | chan;
46 pfn = address >> PAGE_SHIFT;
47 offset = address & ~PAGE_MASK;
48 syndrome = (ar & 0x000000001fe00000ul) >> 21;
49
50
51 edac_mc_handle_ce(mci, csrow->first_page + pfn, offset,
52 syndrome, 0, chan, "");
53}
54
55static void cell_edac_count_ue(struct mem_ctl_info *mci, int chan, u64 ar)
56{
57 struct cell_edac_priv *priv = mci->pvt_info;
58 struct csrow_info *csrow = &mci->csrows[0];
59 unsigned long address, pfn, offset;
60
61 dev_dbg(mci->dev, "ECC UE err on node %d, channel %d, ar = 0x%016llx\n",
62 priv->node, chan, ar);
63
64
65 address = (ar & 0xffffffffe0000000ul) >> 29;
66 if (priv->chanmask == 0x3)
67 address = (address << 1) | chan;
68 pfn = address >> PAGE_SHIFT;
69 offset = address & ~PAGE_MASK;
70
71
72 edac_mc_handle_ue(mci, csrow->first_page + pfn, offset, 0, "");
73}
74
75static void cell_edac_check(struct mem_ctl_info *mci)
76{
77 struct cell_edac_priv *priv = mci->pvt_info;
78 u64 fir, addreg, clear = 0;
79
80 fir = in_be64(&priv->regs->mic_fir);
81#ifdef DEBUG
82 if (fir != priv->prev_fir) {
83 dev_dbg(mci->dev, "fir change : 0x%016lx\n", fir);
84 priv->prev_fir = fir;
85 }
86#endif
87 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_SINGLE_0_ERR)) {
88 addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
89 clear |= CBE_MIC_FIR_ECC_SINGLE_0_RESET;
90 cell_edac_count_ce(mci, 0, addreg);
91 }
92 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_SINGLE_1_ERR)) {
93 addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
94 clear |= CBE_MIC_FIR_ECC_SINGLE_1_RESET;
95 cell_edac_count_ce(mci, 1, addreg);
96 }
97 if ((priv->chanmask & 0x1) && (fir & CBE_MIC_FIR_ECC_MULTI_0_ERR)) {
98 addreg = in_be64(&priv->regs->mic_df_ecc_address_0);
99 clear |= CBE_MIC_FIR_ECC_MULTI_0_RESET;
100 cell_edac_count_ue(mci, 0, addreg);
101 }
102 if ((priv->chanmask & 0x2) && (fir & CBE_MIC_FIR_ECC_MULTI_1_ERR)) {
103 addreg = in_be64(&priv->regs->mic_df_ecc_address_1);
104 clear |= CBE_MIC_FIR_ECC_MULTI_1_RESET;
105 cell_edac_count_ue(mci, 1, addreg);
106 }
107
108
109 if (clear) {
110 fir &= ~(CBE_MIC_FIR_ECC_ERR_MASK | CBE_MIC_FIR_ECC_SET_MASK);
111 fir |= CBE_MIC_FIR_ECC_RESET_MASK;
112 fir &= ~clear;
113 out_be64(&priv->regs->mic_fir, fir);
114 (void)in_be64(&priv->regs->mic_fir);
115
116 mb();
117#ifdef DEBUG
118 fir = in_be64(&priv->regs->mic_fir);
119 dev_dbg(mci->dev, "fir clear : 0x%016lx\n", fir);
120#endif
121 }
122}
123
124static void __devinit cell_edac_init_csrows(struct mem_ctl_info *mci)
125{
126 struct csrow_info *csrow = &mci->csrows[0];
127 struct cell_edac_priv *priv = mci->pvt_info;
128 struct device_node *np;
129
130 for (np = NULL;
131 (np = of_find_node_by_name(np, "memory")) != NULL;) {
132 struct resource r;
133
134
135
136
137
138 if (of_address_to_resource(np, 0, &r))
139 continue;
140 if (of_node_to_nid(np) != priv->node)
141 continue;
142 csrow->first_page = r.start >> PAGE_SHIFT;
143 csrow->nr_pages = (r.end - r.start + 1) >> PAGE_SHIFT;
144 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
145 csrow->mtype = MEM_XDR;
146 csrow->edac_mode = EDAC_SECDED;
147 dev_dbg(mci->dev,
148 "Initialized on node %d, chanmask=0x%x,"
149 " first_page=0x%lx, nr_pages=0x%x\n",
150 priv->node, priv->chanmask,
151 csrow->first_page, csrow->nr_pages);
152 break;
153 }
154}
155
156static int __devinit cell_edac_probe(struct platform_device *pdev)
157{
158 struct cbe_mic_tm_regs __iomem *regs;
159 struct mem_ctl_info *mci;
160 struct cell_edac_priv *priv;
161 u64 reg;
162 int rc, chanmask;
163
164 regs = cbe_get_cpu_mic_tm_regs(cbe_node_to_cpu(pdev->id));
165 if (regs == NULL)
166 return -ENODEV;
167
168 edac_op_state = EDAC_OPSTATE_POLL;
169
170
171 reg = in_be64(®s->mic_mnt_cfg);
172 dev_dbg(&pdev->dev, "MIC_MNT_CFG = 0x%016llx\n", reg);
173 chanmask = 0;
174 if (reg & CBE_MIC_MNT_CFG_CHAN_0_POP)
175 chanmask |= 0x1;
176 if (reg & CBE_MIC_MNT_CFG_CHAN_1_POP)
177 chanmask |= 0x2;
178 if (chanmask == 0) {
179 dev_warn(&pdev->dev,
180 "Yuck ! No channel populated ? Aborting !\n");
181 return -ENODEV;
182 }
183 dev_dbg(&pdev->dev, "Initial FIR = 0x%016llx\n",
184 in_be64(®s->mic_fir));
185
186
187 mci = edac_mc_alloc(sizeof(struct cell_edac_priv), 1,
188 chanmask == 3 ? 2 : 1, pdev->id);
189 if (mci == NULL)
190 return -ENOMEM;
191 priv = mci->pvt_info;
192 priv->regs = regs;
193 priv->node = pdev->id;
194 priv->chanmask = chanmask;
195 mci->dev = &pdev->dev;
196 mci->mtype_cap = MEM_FLAG_XDR;
197 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
198 mci->edac_cap = EDAC_FLAG_EC | EDAC_FLAG_SECDED;
199 mci->mod_name = "cell_edac";
200 mci->ctl_name = "MIC";
201 mci->dev_name = dev_name(&pdev->dev);
202 mci->edac_check = cell_edac_check;
203 cell_edac_init_csrows(mci);
204
205
206 rc = edac_mc_add_mc(mci);
207 if (rc) {
208 dev_err(&pdev->dev, "failed to register with EDAC core\n");
209 edac_mc_free(mci);
210 return rc;
211 }
212
213 return 0;
214}
215
216static int __devexit cell_edac_remove(struct platform_device *pdev)
217{
218 struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
219 if (mci)
220 edac_mc_free(mci);
221 return 0;
222}
223
224static struct platform_driver cell_edac_driver = {
225 .driver = {
226 .name = "cbe-mic",
227 .owner = THIS_MODULE,
228 },
229 .probe = cell_edac_probe,
230 .remove = cell_edac_remove,
231};
232
233static int __init cell_edac_init(void)
234{
235
236 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
237 mic_df_ecc_address_0) != 0xf8);
238 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
239 mic_df_ecc_address_1) != 0x1b8);
240 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
241 mic_df_config) != 0x218);
242 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
243 mic_fir) != 0x230);
244 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
245 mic_mnt_cfg) != 0x210);
246 BUILD_BUG_ON(offsetof(struct cbe_mic_tm_regs,
247 mic_exc) != 0x208);
248
249 return platform_driver_register(&cell_edac_driver);
250}
251
252static void __exit cell_edac_exit(void)
253{
254 platform_driver_unregister(&cell_edac_driver);
255}
256
257module_init(cell_edac_init);
258module_exit(cell_edac_exit);
259
260MODULE_LICENSE("GPL");
261MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>");
262MODULE_DESCRIPTION("ECC counting for Cell MIC");
263
