1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include <linux/rculist.h>
27#include <linux/kernel.h>
28#include <linux/async_tx.h>
29
30#ifdef CONFIG_DMA_ENGINE
31static int __init async_tx_init(void)
32{
33 async_dmaengine_get();
34
35 printk(KERN_INFO "async_tx: api initialized (async)\n");
36
37 return 0;
38}
39
40static void __exit async_tx_exit(void)
41{
42 async_dmaengine_put();
43}
44
45
46
47
48
49
50
51struct dma_chan *
52__async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx,
53 enum dma_transaction_type tx_type)
54{
55
56 if (depend_tx &&
57 dma_has_cap(tx_type, depend_tx->chan->device->cap_mask))
58 return depend_tx->chan;
59 return async_dma_find_channel(tx_type);
60}
61EXPORT_SYMBOL_GPL(__async_tx_find_channel);
62#else
63static int __init async_tx_init(void)
64{
65 printk(KERN_INFO "async_tx: api initialized (sync-only)\n");
66 return 0;
67}
68
69static void __exit async_tx_exit(void)
70{
71 do { } while (0);
72}
73#endif
74
75
76
77
78
79
80
81
82static void
83async_tx_channel_switch(struct dma_async_tx_descriptor *depend_tx,
84 struct dma_async_tx_descriptor *tx)
85{
86 struct dma_chan *chan;
87 struct dma_device *device;
88 struct dma_async_tx_descriptor *intr_tx = (void *) ~0;
89
90
91 spin_lock_bh(&depend_tx->lock);
92 if (depend_tx->parent && depend_tx->chan == tx->chan) {
93 tx->parent = depend_tx;
94 depend_tx->next = tx;
95 intr_tx = NULL;
96 }
97 spin_unlock_bh(&depend_tx->lock);
98
99 if (!intr_tx)
100 return;
101
102 chan = depend_tx->chan;
103 device = chan->device;
104
105
106
107
108 if (dma_has_cap(DMA_INTERRUPT, device->cap_mask))
109 intr_tx = device->device_prep_dma_interrupt(chan, 0);
110 else
111 intr_tx = NULL;
112
113 if (intr_tx) {
114 intr_tx->callback = NULL;
115 intr_tx->callback_param = NULL;
116 tx->parent = intr_tx;
117
118
119
120 intr_tx->next = tx;
121
122
123 spin_lock_bh(&depend_tx->lock);
124 if (depend_tx->parent) {
125 intr_tx->parent = depend_tx;
126 depend_tx->next = intr_tx;
127 async_tx_ack(intr_tx);
128 intr_tx = NULL;
129 }
130 spin_unlock_bh(&depend_tx->lock);
131
132 if (intr_tx) {
133 intr_tx->parent = NULL;
134 intr_tx->tx_submit(intr_tx);
135 async_tx_ack(intr_tx);
136 }
137 } else {
138 if (dma_wait_for_async_tx(depend_tx) == DMA_ERROR)
139 panic("%s: DMA_ERROR waiting for depend_tx\n",
140 __func__);
141 tx->tx_submit(tx);
142 }
143}
144
145
146
147
148
149
150
151
152
153
154
155enum submit_disposition {
156 ASYNC_TX_SUBMITTED,
157 ASYNC_TX_CHANNEL_SWITCH,
158 ASYNC_TX_DIRECT_SUBMIT,
159};
160
161void
162async_tx_submit(struct dma_chan *chan, struct dma_async_tx_descriptor *tx,
163 enum async_tx_flags flags, struct dma_async_tx_descriptor *depend_tx,
164 dma_async_tx_callback cb_fn, void *cb_param)
165{
166 tx->callback = cb_fn;
167 tx->callback_param = cb_param;
168
169 if (depend_tx) {
170 enum submit_disposition s;
171
172
173
174
175
176
177
178 BUG_ON(async_tx_test_ack(depend_tx) || depend_tx->next ||
179 tx->parent);
180
181
182
183
184 spin_lock_bh(&depend_tx->lock);
185 if (depend_tx->parent) {
186
187
188
189
190 if (depend_tx->chan == chan) {
191 tx->parent = depend_tx;
192 depend_tx->next = tx;
193 s = ASYNC_TX_SUBMITTED;
194 } else
195 s = ASYNC_TX_CHANNEL_SWITCH;
196 } else {
197
198
199
200 if (depend_tx->chan == chan)
201 s = ASYNC_TX_DIRECT_SUBMIT;
202 else
203 s = ASYNC_TX_CHANNEL_SWITCH;
204 }
205 spin_unlock_bh(&depend_tx->lock);
206
207 switch (s) {
208 case ASYNC_TX_SUBMITTED:
209 break;
210 case ASYNC_TX_CHANNEL_SWITCH:
211 async_tx_channel_switch(depend_tx, tx);
212 break;
213 case ASYNC_TX_DIRECT_SUBMIT:
214 tx->parent = NULL;
215 tx->tx_submit(tx);
216 break;
217 }
218 } else {
219 tx->parent = NULL;
220 tx->tx_submit(tx);
221 }
222
223 if (flags & ASYNC_TX_ACK)
224 async_tx_ack(tx);
225
226 if (depend_tx && (flags & ASYNC_TX_DEP_ACK))
227 async_tx_ack(depend_tx);
228}
229EXPORT_SYMBOL_GPL(async_tx_submit);
230
231
232
233
234
235
236
237
238
239struct dma_async_tx_descriptor *
240async_trigger_callback(enum async_tx_flags flags,
241 struct dma_async_tx_descriptor *depend_tx,
242 dma_async_tx_callback cb_fn, void *cb_param)
243{
244 struct dma_chan *chan;
245 struct dma_device *device;
246 struct dma_async_tx_descriptor *tx;
247
248 if (depend_tx) {
249 chan = depend_tx->chan;
250 device = chan->device;
251
252
253
254
255 if (device && !dma_has_cap(DMA_INTERRUPT, device->cap_mask))
256 device = NULL;
257
258 tx = device ? device->device_prep_dma_interrupt(chan, 0) : NULL;
259 } else
260 tx = NULL;
261
262 if (tx) {
263 pr_debug("%s: (async)\n", __func__);
264
265 async_tx_submit(chan, tx, flags, depend_tx, cb_fn, cb_param);
266 } else {
267 pr_debug("%s: (sync)\n", __func__);
268
269
270 async_tx_quiesce(&depend_tx);
271
272 async_tx_sync_epilog(cb_fn, cb_param);
273 }
274
275 return tx;
276}
277EXPORT_SYMBOL_GPL(async_trigger_callback);
278
279
280
281
282
283void async_tx_quiesce(struct dma_async_tx_descriptor **tx)
284{
285 if (*tx) {
286
287
288
289 BUG_ON(async_tx_test_ack(*tx));
290 if (dma_wait_for_async_tx(*tx) == DMA_ERROR)
291 panic("DMA_ERROR waiting for transaction\n");
292 async_tx_ack(*tx);
293 *tx = NULL;
294 }
295}
296EXPORT_SYMBOL_GPL(async_tx_quiesce);
297
298module_init(async_tx_init);
299module_exit(async_tx_exit);
300
301MODULE_AUTHOR("Intel Corporation");
302MODULE_DESCRIPTION("Asynchronous Bulk Memory Transactions API");
303MODULE_LICENSE("GPL");
304