linux/arch/cris/arch-v10/kernel/time.c
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   1/*
   2 *  linux/arch/cris/arch-v10/kernel/time.c
   3 *
   4 *  Copyright (C) 1991, 1992, 1995  Linus Torvalds
   5 *  Copyright (C) 1999-2002 Axis Communications AB
   6 *
   7 */
   8
   9#include <linux/timex.h>
  10#include <linux/time.h>
  11#include <linux/jiffies.h>
  12#include <linux/interrupt.h>
  13#include <linux/swap.h>
  14#include <linux/sched.h>
  15#include <linux/init.h>
  16#include <linux/mm.h>
  17#include <arch/svinto.h>
  18#include <asm/types.h>
  19#include <asm/signal.h>
  20#include <asm/io.h>
  21#include <asm/delay.h>
  22#include <asm/rtc.h>
  23#include <asm/irq_regs.h>
  24
  25/* define this if you need to use print_timestamp */
  26/* it will make jiffies at 96 hz instead of 100 hz though */
  27#undef USE_CASCADE_TIMERS
  28
  29extern void update_xtime_from_cmos(void);
  30extern int set_rtc_mmss(unsigned long nowtime);
  31extern int setup_irq(int, struct irqaction *);
  32extern int have_rtc;
  33
  34unsigned long get_ns_in_jiffie(void)
  35{
  36        unsigned char timer_count, t1;
  37        unsigned short presc_count;
  38        unsigned long ns;
  39        unsigned long flags;
  40
  41        local_irq_save(flags);
  42        timer_count = *R_TIMER0_DATA;
  43        presc_count = *R_TIM_PRESC_STATUS;  
  44        /* presc_count might be wrapped */
  45        t1 = *R_TIMER0_DATA;
  46
  47        if (timer_count != t1){
  48                /* it wrapped, read prescaler again...  */
  49                presc_count = *R_TIM_PRESC_STATUS;
  50                timer_count = t1;
  51        }
  52        local_irq_restore(flags);
  53        if (presc_count >= PRESCALE_VALUE/2 ){
  54                presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
  55        } else {
  56                presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
  57        }
  58
  59        ns = ( (TIMER0_DIV - timer_count) * ((1000000000/HZ)/TIMER0_DIV )) + 
  60             ( (presc_count) * (1000000000/PRESCALE_FREQ));
  61        return ns;
  62}
  63
  64unsigned long do_slow_gettimeoffset(void)
  65{
  66        unsigned long count, t1;
  67        unsigned long usec_count = 0;
  68        unsigned short presc_count;
  69
  70        static unsigned long count_p = TIMER0_DIV;/* for the first call after boot */
  71        static unsigned long jiffies_p = 0;
  72
  73        /*
  74         * cache volatile jiffies temporarily; we have IRQs turned off. 
  75         */
  76        unsigned long jiffies_t;
  77
  78        /* The timer interrupt comes from Etrax timer 0. In order to get
  79         * better precision, we check the current value. It might have
  80         * underflowed already though.
  81         */
  82
  83#ifndef CONFIG_SVINTO_SIM
  84        /* Not available in the xsim simulator. */
  85        count = *R_TIMER0_DATA;
  86        presc_count = *R_TIM_PRESC_STATUS;  
  87        /* presc_count might be wrapped */
  88        t1 = *R_TIMER0_DATA;
  89        if (count != t1){
  90                /* it wrapped, read prescaler again...  */
  91                presc_count = *R_TIM_PRESC_STATUS;
  92                count = t1;
  93        }
  94#else
  95        count = 0;
  96        presc_count = 0;
  97#endif
  98
  99        jiffies_t = jiffies;
 100
 101        /*
 102         * avoiding timer inconsistencies (they are rare, but they happen)...
 103         * there are one problem that must be avoided here:
 104         *  1. the timer counter underflows
 105         */
 106        if( jiffies_t == jiffies_p ) {
 107                if( count > count_p ) {
 108                        /* Timer wrapped, use new count and prescale 
 109                         * increase the time corresponding to one jiffie
 110                         */
 111                        usec_count = 1000000/HZ;
 112                }
 113        } else
 114                jiffies_p = jiffies_t;
 115        count_p = count;
 116        if (presc_count >= PRESCALE_VALUE/2 ){
 117                presc_count =  PRESCALE_VALUE - presc_count + PRESCALE_VALUE/2;
 118        } else {
 119                presc_count =  PRESCALE_VALUE - presc_count - PRESCALE_VALUE/2;
 120        }
 121        /* Convert timer value to usec */
 122        usec_count += ( (TIMER0_DIV - count) * (1000000/HZ)/TIMER0_DIV ) +
 123                      (( (presc_count) * (1000000000/PRESCALE_FREQ))/1000);
 124
 125        return usec_count;
 126}
 127
 128/* Excerpt from the Etrax100 HSDD about the built-in watchdog:
 129 *
 130 * 3.10.4 Watchdog timer
 131
 132 * When the watchdog timer is started, it generates an NMI if the watchdog
 133 * isn't restarted or stopped within 0.1 s. If it still isn't restarted or
 134 * stopped after an additional 3.3 ms, the watchdog resets the chip.
 135 * The watchdog timer is stopped after reset. The watchdog timer is controlled
 136 * by the R_WATCHDOG register. The R_WATCHDOG register contains an enable bit
 137 * and a 3-bit key value. The effect of writing to the R_WATCHDOG register is
 138 * described in the table below:
 139 * 
 140 *   Watchdog    Value written:
 141 *   state:      To enable:  To key:      Operation:
 142 *   --------    ----------  -------      ----------
 143 *   stopped         0         X          No effect.
 144 *   stopped         1       key_val      Start watchdog with key = key_val.
 145 *   started         0       ~key         Stop watchdog
 146 *   started         1       ~key         Restart watchdog with key = ~key.
 147 *   started         X       new_key_val  Change key to new_key_val.
 148 * 
 149 * Note: '~' is the bitwise NOT operator.
 150 * 
 151 */
 152
 153/* right now, starting the watchdog is the same as resetting it */
 154#define start_watchdog reset_watchdog
 155
 156#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 157static int watchdog_key = 0;  /* arbitrary number */
 158#endif
 159
 160/* number of pages to consider "out of memory". it is normal that the memory
 161 * is used though, so put this really low.
 162 */
 163
 164#define WATCHDOG_MIN_FREE_PAGES 8
 165
 166void
 167reset_watchdog(void)
 168{
 169#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 170        /* only keep watchdog happy as long as we have memory left! */
 171        if(nr_free_pages() > WATCHDOG_MIN_FREE_PAGES) {
 172                /* reset the watchdog with the inverse of the old key */
 173                watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 174                *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 175                        IO_STATE(R_WATCHDOG, enable, start);
 176        }
 177#endif
 178}
 179
 180/* stop the watchdog - we still need the correct key */
 181
 182void 
 183stop_watchdog(void)
 184{
 185#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 186        watchdog_key ^= 0x7; /* invert key, which is 3 bits */
 187        *R_WATCHDOG = IO_FIELD(R_WATCHDOG, key, watchdog_key) |
 188                IO_STATE(R_WATCHDOG, enable, stop);
 189#endif  
 190}
 191
 192/* last time the cmos clock got updated */
 193static long last_rtc_update = 0;
 194
 195/*
 196 * timer_interrupt() needs to keep up the real-time clock,
 197 * as well as call the "do_timer()" routine every clocktick
 198 */
 199
 200//static unsigned short myjiff; /* used by our debug routine print_timestamp */
 201
 202extern void cris_do_profile(struct pt_regs *regs);
 203
 204static inline irqreturn_t
 205timer_interrupt(int irq, void *dev_id)
 206{
 207        struct pt_regs *regs = get_irq_regs();
 208        /* acknowledge the timer irq */
 209
 210#ifdef USE_CASCADE_TIMERS
 211        *R_TIMER_CTRL =
 212                IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 213                IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 214                IO_STATE( R_TIMER_CTRL, i1, clr) |
 215                IO_STATE( R_TIMER_CTRL, tm1, run) |
 216                IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 217                IO_STATE( R_TIMER_CTRL, i0, clr) |
 218                IO_STATE( R_TIMER_CTRL, tm0, run) |
 219                IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 220#else
 221        *R_TIMER_CTRL = r_timer_ctrl_shadow | 
 222                IO_STATE(R_TIMER_CTRL, i0, clr);
 223#endif
 224
 225        /* reset watchdog otherwise it resets us! */
 226        reset_watchdog();
 227        
 228        /* Update statistics. */
 229        update_process_times(user_mode(regs));
 230
 231        /* call the real timer interrupt handler */
 232
 233        do_timer(1);
 234        
 235        cris_do_profile(regs); /* Save profiling information */
 236
 237        /*
 238         * If we have an externally synchronized Linux clock, then update
 239         * CMOS clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
 240         * called as close as possible to 500 ms before the new second starts.
 241         *
 242         * The division here is not time critical since it will run once in 
 243         * 11 minutes
 244         */
 245        if (ntp_synced() &&
 246            xtime.tv_sec > last_rtc_update + 660 &&
 247            (xtime.tv_nsec / 1000) >= 500000 - (tick_nsec / 1000) / 2 &&
 248            (xtime.tv_nsec / 1000) <= 500000 + (tick_nsec / 1000) / 2) {
 249                if (set_rtc_mmss(xtime.tv_sec) == 0)
 250                        last_rtc_update = xtime.tv_sec;
 251                else
 252                        last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
 253        }
 254        return IRQ_HANDLED;
 255}
 256
 257/* timer is IRQF_SHARED so drivers can add stuff to the timer irq chain
 258 * it needs to be IRQF_DISABLED to make the jiffies update work properly
 259 */
 260
 261static struct irqaction irq2  = {
 262        .handler = timer_interrupt,
 263        .flags = IRQF_SHARED | IRQF_DISABLED,
 264        .name = "timer",
 265};
 266
 267void __init
 268time_init(void)
 269{       
 270        /* probe for the RTC and read it if it exists 
 271         * Before the RTC can be probed the loops_per_usec variable needs 
 272         * to be initialized to make usleep work. A better value for 
 273         * loops_per_usec is calculated by the kernel later once the 
 274         * clock has started.  
 275         */
 276        loops_per_usec = 50;
 277
 278        if(RTC_INIT() < 0) {
 279                /* no RTC, start at 1980 */
 280                xtime.tv_sec = 0;
 281                xtime.tv_nsec = 0;
 282                have_rtc = 0;
 283        } else {                
 284                /* get the current time */
 285                have_rtc = 1;
 286                update_xtime_from_cmos();
 287        }
 288
 289        /*
 290         * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
 291         * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
 292         */
 293        set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
 294
 295        /* Setup the etrax timers
 296         * Base frequency is 25000 hz, divider 250 -> 100 HZ
 297         * In normal mode, we use timer0, so timer1 is free. In cascade
 298         * mode (which we sometimes use for debugging) both timers are used.
 299         * Remember that linux/timex.h contains #defines that rely on the
 300         * timer settings below (hz and divide factor) !!!
 301         */
 302        
 303#ifdef USE_CASCADE_TIMERS
 304        *R_TIMER_CTRL =
 305                IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 306                IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 307                IO_STATE( R_TIMER_CTRL, i1, nop) |
 308                IO_STATE( R_TIMER_CTRL, tm1, stop_ld) |
 309                IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 310                IO_STATE( R_TIMER_CTRL, i0, nop) |
 311                IO_STATE( R_TIMER_CTRL, tm0, stop_ld) |
 312                IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 313        
 314        *R_TIMER_CTRL = r_timer_ctrl_shadow = 
 315                IO_FIELD( R_TIMER_CTRL, timerdiv1, 0) |
 316                IO_FIELD( R_TIMER_CTRL, timerdiv0, 0) |
 317                IO_STATE( R_TIMER_CTRL, i1, nop) |
 318                IO_STATE( R_TIMER_CTRL, tm1, run) |
 319                IO_STATE( R_TIMER_CTRL, clksel1, cascade0) |
 320                IO_STATE( R_TIMER_CTRL, i0, nop) |
 321                IO_STATE( R_TIMER_CTRL, tm0, run) |
 322                IO_STATE( R_TIMER_CTRL, clksel0, c6250kHz);
 323#else
 324        *R_TIMER_CTRL = 
 325                IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
 326                IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 327                IO_STATE(R_TIMER_CTRL, i1,        nop)      | 
 328                IO_STATE(R_TIMER_CTRL, tm1,       stop_ld)  |
 329                IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 330                IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 331                IO_STATE(R_TIMER_CTRL, tm0,       stop_ld)  |
 332                IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 333        
 334        *R_TIMER_CTRL = r_timer_ctrl_shadow =
 335                IO_FIELD(R_TIMER_CTRL, timerdiv1, 192)      | 
 336                IO_FIELD(R_TIMER_CTRL, timerdiv0, TIMER0_DIV)      |
 337                IO_STATE(R_TIMER_CTRL, i1,        nop)      |
 338                IO_STATE(R_TIMER_CTRL, tm1,       run)      |
 339                IO_STATE(R_TIMER_CTRL, clksel1,   c19k2Hz)  |
 340                IO_STATE(R_TIMER_CTRL, i0,        nop)      |
 341                IO_STATE(R_TIMER_CTRL, tm0,       run)      |
 342                IO_STATE(R_TIMER_CTRL, clksel0,   flexible);
 343
 344        *R_TIMER_PRESCALE = PRESCALE_VALUE;
 345#endif
 346
 347        *R_IRQ_MASK0_SET =
 348                IO_STATE(R_IRQ_MASK0_SET, timer0, set); /* unmask the timer irq */
 349        
 350        /* now actually register the timer irq handler that calls timer_interrupt() */
 351        
 352        setup_irq(2, &irq2); /* irq 2 is the timer0 irq in etrax */
 353
 354        /* enable watchdog if we should use one */
 355
 356#if defined(CONFIG_ETRAX_WATCHDOG) && !defined(CONFIG_SVINTO_SIM)
 357        printk("Enabling watchdog...\n");
 358        start_watchdog();
 359
 360        /* If we use the hardware watchdog, we want to trap it as an NMI
 361           and dump registers before it resets us.  For this to happen, we
 362           must set the "m" NMI enable flag (which once set, is unset only
 363           when an NMI is taken).
 364
 365           The same goes for the external NMI, but that doesn't have any
 366           driver or infrastructure support yet.  */
 367        asm ("setf m");
 368
 369        *R_IRQ_MASK0_SET =
 370                IO_STATE(R_IRQ_MASK0_SET, watchdog_nmi, set);
 371        *R_VECT_MASK_SET =
 372                IO_STATE(R_VECT_MASK_SET, nmi, set);
 373#endif
 374}
 375