1/* $Id: dma.h,v 1.2 1999/04/27 00:46:18 deller Exp $ 2 * linux/include/asm/dma.h: Defines for using and allocating dma channels. 3 * Written by Hennus Bergman, 1992. 4 * High DMA channel support & info by Hannu Savolainen 5 * and John Boyd, Nov. 1992. 6 * (c) Copyright 2000, Grant Grundler 7 */ 8 9#ifndef _ASM_DMA_H 10#define _ASM_DMA_H 11 12#include <asm/io.h> /* need byte IO */ 13#include <asm/system.h> 14 15#define dma_outb outb 16#define dma_inb inb 17 18/* 19** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up 20** (or rather not merge) DMAs into manageable chunks. 21** On parisc, this is more of the software/tuning constraint 22** rather than the HW. I/O MMU allocation algorithms can be 23** faster with smaller sizes (to some degree). 24*/ 25#define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE) 26 27/* The maximum address that we can perform a DMA transfer to on this platform 28** New dynamic DMA interfaces should obsolete this.... 29*/ 30#define MAX_DMA_ADDRESS (~0UL) 31 32/* 33** We don't have DMA channels... well V-class does but the 34** Dynamic DMA Mapping interface will support them... right? :^) 35** Note: this is not relevant right now for PA-RISC, but we cannot 36** leave this as undefined because some things (e.g. sound) 37** won't compile :-( 38*/ 39#define MAX_DMA_CHANNELS 8 40#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 41#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 42#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 43 44#define DMA_AUTOINIT 0x10 45 46/* 8237 DMA controllers */ 47#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 48#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 49 50/* DMA controller registers */ 51#define DMA1_CMD_REG 0x08 /* command register (w) */ 52#define DMA1_STAT_REG 0x08 /* status register (r) */ 53#define DMA1_REQ_REG 0x09 /* request register (w) */ 54#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 55#define DMA1_MODE_REG 0x0B /* mode register (w) */ 56#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 57#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 58#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 59#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 60#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 61#define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) 62 63#define DMA2_CMD_REG 0xD0 /* command register (w) */ 64#define DMA2_STAT_REG 0xD0 /* status register (r) */ 65#define DMA2_REQ_REG 0xD2 /* request register (w) */ 66#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 67#define DMA2_MODE_REG 0xD6 /* mode register (w) */ 68#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 69#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 70#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 71#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 72#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 73#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) 74 75static __inline__ unsigned long claim_dma_lock(void) 76{ 77 return 0; 78} 79 80static __inline__ void release_dma_lock(unsigned long flags) 81{ 82} 83 84 85/* Get DMA residue count. After a DMA transfer, this 86 * should return zero. Reading this while a DMA transfer is 87 * still in progress will return unpredictable results. 88 * If called before the channel has been used, it may return 1. 89 * Otherwise, it returns the number of _bytes_ left to transfer. 90 * 91 * Assumes DMA flip-flop is clear. 92 */ 93static __inline__ int get_dma_residue(unsigned int dmanr) 94{ 95 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 96 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 97 98 /* using short to get 16-bit wrap around */ 99 unsigned short count; 100 101 count = 1 + dma_inb(io_port); 102 count += dma_inb(io_port) << 8; 103 104 return (dmanr<=3)? count : (count<<1); 105} 106 107/* enable/disable a specific DMA channel */ 108static __inline__ void enable_dma(unsigned int dmanr) 109{ 110#ifdef CONFIG_SUPERIO 111 if (dmanr<=3) 112 dma_outb(dmanr, DMA1_MASK_REG); 113 else 114 dma_outb(dmanr & 3, DMA2_MASK_REG); 115#endif 116} 117 118static __inline__ void disable_dma(unsigned int dmanr) 119{ 120#ifdef CONFIG_SUPERIO 121 if (dmanr<=3) 122 dma_outb(dmanr | 4, DMA1_MASK_REG); 123 else 124 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 125#endif 126} 127 128/* reserve a DMA channel */ 129#define request_dma(dmanr, device_id) (0) 130 131/* Clear the 'DMA Pointer Flip Flop'. 132 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 133 * Use this once to initialize the FF to a known state. 134 * After that, keep track of it. :-) 135 * --- In order to do that, the DMA routines below should --- 136 * --- only be used while holding the DMA lock ! --- 137 */ 138static __inline__ void clear_dma_ff(unsigned int dmanr) 139{ 140} 141 142/* set mode (above) for a specific DMA channel */ 143static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 144{ 145} 146 147/* Set only the page register bits of the transfer address. 148 * This is used for successive transfers when we know the contents of 149 * the lower 16 bits of the DMA current address register, but a 64k boundary 150 * may have been crossed. 151 */ 152static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) 153{ 154} 155 156 157/* Set transfer address & page bits for specific DMA channel. 158 * Assumes dma flipflop is clear. 159 */ 160static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) 161{ 162} 163 164 165/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 166 * a specific DMA channel. 167 * You must ensure the parameters are valid. 168 * NOTE: from a manual: "the number of transfers is one more 169 * than the initial word count"! This is taken into account. 170 * Assumes dma flip-flop is clear. 171 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 172 */ 173static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 174{ 175} 176 177 178#define free_dma(dmanr) 179 180#ifdef CONFIG_PCI 181extern int isa_dma_bridge_buggy; 182#else 183#define isa_dma_bridge_buggy (0) 184#endif 185 186#endif /* _ASM_DMA_H */ 187