linux/sound/drivers/ml403-ac97cr.c
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   1/*
   2 * ALSA driver for Xilinx ML403 AC97 Controller Reference
   3 *   IP: opb_ac97_controller_ref_v1_00_a (EDK 8.1i)
   4 *   IP: opb_ac97_controller_ref_v1_00_a (EDK 9.1i)
   5 *
   6 *  Copyright (c) by 2007  Joachim Foerster <JOFT@gmx.de>
   7 *
   8 *   This program is free software; you can redistribute it and/or modify
   9 *   it under the terms of the GNU General Public License as published by
  10 *   the Free Software Foundation; either version 2 of the License, or
  11 *   (at your option) any later version.
  12 *
  13 *   This program is distributed in the hope that it will be useful,
  14 *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 *   GNU General Public License for more details.
  17 *
  18 *   You should have received a copy of the GNU General Public License
  19 *   along with this program; if not, write to the Free Software
  20 *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  21 *
  22 */
  23
  24/* Some notes / status of this driver:
  25 *
  26 * - Don't wonder about some strange implementations of things - especially the
  27 * (heavy) shadowing of codec registers, with which I tried to reduce read
  28 * accesses to a minimum, because after a variable amount of accesses, the AC97
  29 * controller doesn't raise the register access finished bit anymore ...
  30 *
  31 * - Playback support seems to be pretty stable - no issues here.
  32 * - Capture support "works" now, too. Overruns don't happen any longer so often.
  33 *   But there might still be some ...
  34 */
  35
  36#include <linux/init.h>
  37#include <linux/moduleparam.h>
  38
  39#include <linux/platform_device.h>
  40
  41#include <linux/ioport.h>
  42#include <linux/io.h>
  43#include <linux/interrupt.h>
  44
  45/* HZ */
  46#include <linux/param.h>
  47/* jiffies, time_*() */
  48#include <linux/jiffies.h>
  49/* schedule_timeout*() */
  50#include <linux/sched.h>
  51/* spin_lock*() */
  52#include <linux/spinlock.h>
  53/* struct mutex, mutex_init(), mutex_*lock() */
  54#include <linux/mutex.h>
  55
  56/* snd_printk(), snd_printd() */
  57#include <sound/core.h>
  58#include <sound/pcm.h>
  59#include <sound/pcm_params.h>
  60#include <sound/initval.h>
  61#include <sound/ac97_codec.h>
  62
  63#include "pcm-indirect2.h"
  64
  65
  66#define SND_ML403_AC97CR_DRIVER "ml403-ac97cr"
  67
  68MODULE_AUTHOR("Joachim Foerster <JOFT@gmx.de>");
  69MODULE_DESCRIPTION("Xilinx ML403 AC97 Controller Reference");
  70MODULE_LICENSE("GPL");
  71MODULE_SUPPORTED_DEVICE("{{Xilinx,ML403 AC97 Controller Reference}}");
  72
  73static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  74static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  75static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE;
  76
  77module_param_array(index, int, NULL, 0444);
  78MODULE_PARM_DESC(index, "Index value for ML403 AC97 Controller Reference.");
  79module_param_array(id, charp, NULL, 0444);
  80MODULE_PARM_DESC(id, "ID string for ML403 AC97 Controller Reference.");
  81module_param_array(enable, bool, NULL, 0444);
  82MODULE_PARM_DESC(enable, "Enable this ML403 AC97 Controller Reference.");
  83
  84/* Special feature options */
  85/*#define CODEC_WRITE_CHECK_RAF*/ /* don't return after a write to a codec
  86                                   * register, while RAF bit is not set
  87                                   */
  88/* Debug options for code which may be removed completely in a final version */
  89#ifdef CONFIG_SND_DEBUG
  90/*#define CODEC_STAT*/            /* turn on some minimal "statistics"
  91                                   * about codec register usage
  92                                   */
  93#define SND_PCM_INDIRECT2_STAT    /* turn on some "statistics" about the
  94                                   * process of copying bytes from the
  95                                   * intermediate buffer to the hardware
  96                                   * fifo and the other way round
  97                                   */
  98#endif
  99
 100/* Definition of a "level/facility dependent" printk(); may be removed
 101 * completely in a final version
 102 */
 103#undef PDEBUG
 104#ifdef CONFIG_SND_DEBUG
 105/* "facilities" for PDEBUG */
 106#define UNKNOWN       (1<<0)
 107#define CODEC_SUCCESS (1<<1)
 108#define CODEC_FAKE    (1<<2)
 109#define INIT_INFO     (1<<3)
 110#define INIT_FAILURE  (1<<4)
 111#define WORK_INFO     (1<<5)
 112#define WORK_FAILURE  (1<<6)
 113
 114#define PDEBUG_FACILITIES (UNKNOWN | INIT_FAILURE | WORK_FAILURE)
 115
 116#define PDEBUG(fac, fmt, args...) do { \
 117                if (fac & PDEBUG_FACILITIES) \
 118                        snd_printd(KERN_DEBUG SND_ML403_AC97CR_DRIVER ": " \
 119                                   fmt, ##args); \
 120        } while (0)
 121#else
 122#define PDEBUG(fac, fmt, args...) /* nothing */
 123#endif
 124
 125
 126
 127/* Defines for "waits"/timeouts (portions of HZ=250 on arch/ppc by default) */
 128#define CODEC_TIMEOUT_ON_INIT       5   /* timeout for checking for codec
 129                                         * readiness (after insmod)
 130                                         */
 131#ifndef CODEC_WRITE_CHECK_RAF
 132#define CODEC_WAIT_AFTER_WRITE    100   /* general, static wait after a write
 133                                         * access to a codec register, may be
 134                                         * 0 to completely remove wait
 135                                         */
 136#else
 137#define CODEC_TIMEOUT_AFTER_WRITE   5   /* timeout after a write access to a
 138                                         * codec register, if RAF bit is used
 139                                         */
 140#endif
 141#define CODEC_TIMEOUT_AFTER_READ    5   /* timeout after a read access to a
 142                                         * codec register (checking RAF bit)
 143                                         */
 144
 145/* Infrastructure for codec register shadowing */
 146#define LM4550_REG_OK        (1<<0)   /* register exists */
 147#define LM4550_REG_DONEREAD  (1<<1)   /* read register once, value should be
 148                                       * the same currently in the register
 149                                       */
 150#define LM4550_REG_NOSAVE    (1<<2)   /* values written to this register will
 151                                       * not be saved in the register
 152                                       */
 153#define LM4550_REG_NOSHADOW  (1<<3)   /* don't do register shadowing, use plain
 154                                       * hardware access
 155                                       */
 156#define LM4550_REG_READONLY  (1<<4)   /* register is read only */
 157#define LM4550_REG_FAKEPROBE (1<<5)   /* fake write _and_ read actions during
 158                                       * probe() correctly
 159                                       */
 160#define LM4550_REG_FAKEREAD  (1<<6)   /* fake read access, always return
 161                                       * default value
 162                                       */
 163#define LM4550_REG_ALLFAKE   (LM4550_REG_FAKEREAD | LM4550_REG_FAKEPROBE)
 164
 165struct lm4550_reg {
 166        u16 value;
 167        u16 flag;
 168        u16 wmask;
 169        u16 def;
 170};
 171
 172struct lm4550_reg lm4550_regfile[64] = {
 173        [AC97_RESET / 2]              = {.flag = LM4550_REG_OK \
 174                                                | LM4550_REG_NOSAVE \
 175                                                | LM4550_REG_FAKEREAD,
 176                                         .def = 0x0D50},
 177        [AC97_MASTER / 2]             = {.flag = LM4550_REG_OK
 178                                                | LM4550_REG_FAKEPROBE,
 179                                         .wmask = 0x9F1F,
 180                                         .def = 0x8000},
 181        [AC97_HEADPHONE / 2]          = {.flag = LM4550_REG_OK \
 182                                                | LM4550_REG_FAKEPROBE,
 183                                         .wmask = 0x9F1F,
 184                                         .def = 0x8000},
 185        [AC97_MASTER_MONO / 2]        = {.flag = LM4550_REG_OK \
 186                                                | LM4550_REG_FAKEPROBE,
 187                                         .wmask = 0x801F,
 188                                         .def = 0x8000},
 189        [AC97_PC_BEEP / 2]            = {.flag = LM4550_REG_OK \
 190                                                | LM4550_REG_FAKEPROBE,
 191                                         .wmask = 0x801E,
 192                                         .def = 0x0},
 193        [AC97_PHONE / 2]              = {.flag = LM4550_REG_OK \
 194                                                | LM4550_REG_FAKEPROBE,
 195                                         .wmask = 0x801F,
 196                                         .def = 0x8008},
 197        [AC97_MIC / 2]                = {.flag = LM4550_REG_OK \
 198                                                | LM4550_REG_FAKEPROBE,
 199                                         .wmask = 0x805F,
 200                                         .def = 0x8008},
 201        [AC97_LINE / 2]               = {.flag = LM4550_REG_OK \
 202                                                | LM4550_REG_FAKEPROBE,
 203                                         .wmask = 0x9F1F,
 204                                         .def = 0x8808},
 205        [AC97_CD / 2]                 = {.flag = LM4550_REG_OK \
 206                                                | LM4550_REG_FAKEPROBE,
 207                                         .wmask = 0x9F1F,
 208                                         .def = 0x8808},
 209        [AC97_VIDEO / 2]              = {.flag = LM4550_REG_OK \
 210                                                | LM4550_REG_FAKEPROBE,
 211                                         .wmask = 0x9F1F,
 212                                         .def = 0x8808},
 213        [AC97_AUX / 2]                = {.flag = LM4550_REG_OK \
 214                                                | LM4550_REG_FAKEPROBE,
 215                                         .wmask = 0x9F1F,
 216                                         .def = 0x8808},
 217        [AC97_PCM / 2]                = {.flag = LM4550_REG_OK \
 218                                                | LM4550_REG_FAKEPROBE,
 219                                         .wmask = 0x9F1F,
 220                                         .def = 0x8008},
 221        [AC97_REC_SEL / 2]            = {.flag = LM4550_REG_OK \
 222                                                | LM4550_REG_FAKEPROBE,
 223                                         .wmask = 0x707,
 224                                         .def = 0x0},
 225        [AC97_REC_GAIN / 2]           = {.flag = LM4550_REG_OK \
 226                                                | LM4550_REG_FAKEPROBE,
 227                                         .wmask = 0x8F0F,
 228                                         .def = 0x8000},
 229        [AC97_GENERAL_PURPOSE / 2]    = {.flag = LM4550_REG_OK \
 230                                                | LM4550_REG_FAKEPROBE,
 231                                         .def = 0x0,
 232                                         .wmask = 0xA380},
 233        [AC97_3D_CONTROL / 2]         = {.flag = LM4550_REG_OK \
 234                                                | LM4550_REG_FAKEREAD \
 235                                                | LM4550_REG_READONLY,
 236                                         .def = 0x0101},
 237        [AC97_POWERDOWN / 2]          = {.flag = LM4550_REG_OK \
 238                                                | LM4550_REG_NOSHADOW \
 239                                                | LM4550_REG_NOSAVE,
 240                                         .wmask = 0xFF00},
 241                                        /* may not write ones to
 242                                         * REF/ANL/DAC/ADC bits
 243                                         * FIXME: Is this ok?
 244                                         */
 245        [AC97_EXTENDED_ID / 2]        = {.flag = LM4550_REG_OK \
 246                                                | LM4550_REG_FAKEREAD \
 247                                                | LM4550_REG_READONLY,
 248                                         .def = 0x0201}, /* primary codec */
 249        [AC97_EXTENDED_STATUS / 2]    = {.flag = LM4550_REG_OK \
 250                                                | LM4550_REG_NOSHADOW \
 251                                                | LM4550_REG_NOSAVE,
 252                                         .wmask = 0x1},
 253        [AC97_PCM_FRONT_DAC_RATE / 2] = {.flag = LM4550_REG_OK \
 254                                                | LM4550_REG_FAKEPROBE,
 255                                         .def = 0xBB80,
 256                                         .wmask = 0xFFFF},
 257        [AC97_PCM_LR_ADC_RATE / 2]    = {.flag = LM4550_REG_OK \
 258                                                | LM4550_REG_FAKEPROBE,
 259                                         .def = 0xBB80,
 260                                         .wmask = 0xFFFF},
 261        [AC97_VENDOR_ID1 / 2]         = {.flag = LM4550_REG_OK \
 262                                                | LM4550_REG_READONLY \
 263                                                | LM4550_REG_FAKEREAD,
 264                                         .def = 0x4E53},
 265        [AC97_VENDOR_ID2 / 2]         = {.flag = LM4550_REG_OK \
 266                                                | LM4550_REG_READONLY \
 267                                                | LM4550_REG_FAKEREAD,
 268                                         .def = 0x4350}
 269};
 270
 271#define LM4550_RF_OK(reg)    (lm4550_regfile[reg / 2].flag & LM4550_REG_OK)
 272
 273static void lm4550_regfile_init(void)
 274{
 275        int i;
 276        for (i = 0; i < 64; i++)
 277                if (lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE)
 278                        lm4550_regfile[i].value = lm4550_regfile[i].def;
 279}
 280
 281static void lm4550_regfile_write_values_after_init(struct snd_ac97 *ac97)
 282{
 283        int i;
 284        for (i = 0; i < 64; i++)
 285                if ((lm4550_regfile[i].flag & LM4550_REG_FAKEPROBE) &&
 286                    (lm4550_regfile[i].value != lm4550_regfile[i].def)) {
 287                        PDEBUG(CODEC_FAKE, "lm4550_regfile_write_values_after_"
 288                               "init(): reg=0x%x value=0x%x / %d is different "
 289                               "from def=0x%x / %d\n",
 290                               i, lm4550_regfile[i].value,
 291                               lm4550_regfile[i].value, lm4550_regfile[i].def,
 292                               lm4550_regfile[i].def);
 293                        snd_ac97_write(ac97, i * 2, lm4550_regfile[i].value);
 294                        lm4550_regfile[i].flag |= LM4550_REG_DONEREAD;
 295                }
 296}
 297
 298
 299/* direct registers */
 300#define CR_REG(ml403_ac97cr, x) ((ml403_ac97cr)->port + CR_REG_##x)
 301
 302#define CR_REG_PLAYFIFO         0x00
 303#define   CR_PLAYDATA(a)        ((a) & 0xFFFF)
 304
 305#define CR_REG_RECFIFO          0x04
 306#define   CR_RECDATA(a)         ((a) & 0xFFFF)
 307
 308#define CR_REG_STATUS           0x08
 309#define   CR_RECOVER            (1<<7)
 310#define   CR_PLAYUNDER          (1<<6)
 311#define   CR_CODECREADY         (1<<5)
 312#define   CR_RAF                (1<<4)
 313#define   CR_RECEMPTY           (1<<3)
 314#define   CR_RECFULL            (1<<2)
 315#define   CR_PLAYHALF           (1<<1)
 316#define   CR_PLAYFULL           (1<<0)
 317
 318#define CR_REG_RESETFIFO        0x0C
 319#define   CR_RECRESET           (1<<1)
 320#define   CR_PLAYRESET          (1<<0)
 321
 322#define CR_REG_CODEC_ADDR       0x10
 323/* UG082 says:
 324 * #define   CR_CODEC_ADDR(a)  ((a) << 1)
 325 * #define   CR_CODEC_READ     (1<<0)
 326 * #define   CR_CODEC_WRITE    (0<<0)
 327 */
 328/* RefDesign example says: */
 329#define   CR_CODEC_ADDR(a)      ((a) << 0)
 330#define   CR_CODEC_READ         (1<<7)
 331#define   CR_CODEC_WRITE        (0<<7)
 332
 333#define CR_REG_CODEC_DATAREAD   0x14
 334#define   CR_CODEC_DATAREAD(v)  ((v) & 0xFFFF)
 335
 336#define CR_REG_CODEC_DATAWRITE  0x18
 337#define   CR_CODEC_DATAWRITE(v) ((v) & 0xFFFF)
 338
 339#define CR_FIFO_SIZE            32
 340
 341struct snd_ml403_ac97cr {
 342        /* lock for access to (controller) registers */
 343        spinlock_t reg_lock;
 344        /* mutex for the whole sequence of accesses to (controller) registers
 345         * which affect codec registers
 346         */
 347        struct mutex cdc_mutex;
 348
 349        int irq; /* for playback */
 350        int enable_irq; /* for playback */
 351
 352        int capture_irq;
 353        int enable_capture_irq;
 354
 355        struct resource *res_port;
 356        void *port;
 357
 358        struct snd_ac97 *ac97;
 359        int ac97_fake;
 360#ifdef CODEC_STAT
 361        int ac97_read;
 362        int ac97_write;
 363#endif
 364
 365        struct platform_device *pfdev;
 366        struct snd_card *card;
 367        struct snd_pcm *pcm;
 368        struct snd_pcm_substream *playback_substream;
 369        struct snd_pcm_substream *capture_substream;
 370
 371        struct snd_pcm_indirect2 ind_rec; /* for playback */
 372        struct snd_pcm_indirect2 capture_ind2_rec;
 373};
 374
 375static struct snd_pcm_hardware snd_ml403_ac97cr_playback = {
 376        .info =             (SNDRV_PCM_INFO_MMAP |
 377                             SNDRV_PCM_INFO_INTERLEAVED |
 378                             SNDRV_PCM_INFO_MMAP_VALID),
 379        .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 380        .rates =            (SNDRV_PCM_RATE_CONTINUOUS |
 381                             SNDRV_PCM_RATE_8000_48000),
 382        .rate_min =         4000,
 383        .rate_max =         48000,
 384        .channels_min =     2,
 385        .channels_max =     2,
 386        .buffer_bytes_max = (128*1024),
 387        .period_bytes_min = CR_FIFO_SIZE/2,
 388        .period_bytes_max = (64*1024),
 389        .periods_min =      2,
 390        .periods_max =      (128*1024)/(CR_FIFO_SIZE/2),
 391        .fifo_size =        0,
 392};
 393
 394static struct snd_pcm_hardware snd_ml403_ac97cr_capture = {
 395        .info =             (SNDRV_PCM_INFO_MMAP |
 396                             SNDRV_PCM_INFO_INTERLEAVED |
 397                             SNDRV_PCM_INFO_MMAP_VALID),
 398        .formats =          SNDRV_PCM_FMTBIT_S16_BE,
 399        .rates =            (SNDRV_PCM_RATE_CONTINUOUS |
 400                             SNDRV_PCM_RATE_8000_48000),
 401        .rate_min =         4000,
 402        .rate_max =         48000,
 403        .channels_min =     2,
 404        .channels_max =     2,
 405        .buffer_bytes_max = (128*1024),
 406        .period_bytes_min = CR_FIFO_SIZE/2,
 407        .period_bytes_max = (64*1024),
 408        .periods_min =      2,
 409        .periods_max =      (128*1024)/(CR_FIFO_SIZE/2),
 410        .fifo_size =        0,
 411};
 412
 413static size_t
 414snd_ml403_ac97cr_playback_ind2_zero(struct snd_pcm_substream *substream,
 415                                    struct snd_pcm_indirect2 *rec)
 416{
 417        struct snd_ml403_ac97cr *ml403_ac97cr;
 418        int copied_words = 0;
 419        u32 full = 0;
 420
 421        ml403_ac97cr = snd_pcm_substream_chip(substream);
 422
 423        spin_lock(&ml403_ac97cr->reg_lock);
 424        while ((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 425                        CR_PLAYFULL)) != CR_PLAYFULL) {
 426                out_be32(CR_REG(ml403_ac97cr, PLAYFIFO), 0);
 427                copied_words++;
 428        }
 429        rec->hw_ready = 0;
 430        spin_unlock(&ml403_ac97cr->reg_lock);
 431
 432        return (size_t) (copied_words * 2);
 433}
 434
 435static size_t
 436snd_ml403_ac97cr_playback_ind2_copy(struct snd_pcm_substream *substream,
 437                                    struct snd_pcm_indirect2 *rec,
 438                                    size_t bytes)
 439{
 440        struct snd_ml403_ac97cr *ml403_ac97cr;
 441        u16 *src;
 442        int copied_words = 0;
 443        u32 full = 0;
 444
 445        ml403_ac97cr = snd_pcm_substream_chip(substream);
 446        src = (u16 *)(substream->runtime->dma_area + rec->sw_data);
 447
 448        spin_lock(&ml403_ac97cr->reg_lock);
 449        while (((full = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 450                         CR_PLAYFULL)) != CR_PLAYFULL) && (bytes > 1)) {
 451                out_be32(CR_REG(ml403_ac97cr, PLAYFIFO),
 452                         CR_PLAYDATA(src[copied_words]));
 453                copied_words++;
 454                bytes = bytes - 2;
 455        }
 456        if (full != CR_PLAYFULL)
 457                rec->hw_ready = 1;
 458        else
 459                rec->hw_ready = 0;
 460        spin_unlock(&ml403_ac97cr->reg_lock);
 461
 462        return (size_t) (copied_words * 2);
 463}
 464
 465static size_t
 466snd_ml403_ac97cr_capture_ind2_null(struct snd_pcm_substream *substream,
 467                                   struct snd_pcm_indirect2 *rec)
 468{
 469        struct snd_ml403_ac97cr *ml403_ac97cr;
 470        int copied_words = 0;
 471        u32 empty = 0;
 472
 473        ml403_ac97cr = snd_pcm_substream_chip(substream);
 474
 475        spin_lock(&ml403_ac97cr->reg_lock);
 476        while ((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 477                         CR_RECEMPTY)) != CR_RECEMPTY) {
 478                volatile u32 trash;
 479
 480                trash = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr, RECFIFO)));
 481                /* Hmmmm, really necessary? Don't want call to in_be32()
 482                 * to be optimised away!
 483                 */
 484                trash++;
 485                copied_words++;
 486        }
 487        rec->hw_ready = 0;
 488        spin_unlock(&ml403_ac97cr->reg_lock);
 489
 490        return (size_t) (copied_words * 2);
 491}
 492
 493static size_t
 494snd_ml403_ac97cr_capture_ind2_copy(struct snd_pcm_substream *substream,
 495                                   struct snd_pcm_indirect2 *rec, size_t bytes)
 496{
 497        struct snd_ml403_ac97cr *ml403_ac97cr;
 498        u16 *dst;
 499        int copied_words = 0;
 500        u32 empty = 0;
 501
 502        ml403_ac97cr = snd_pcm_substream_chip(substream);
 503        dst = (u16 *)(substream->runtime->dma_area + rec->sw_data);
 504
 505        spin_lock(&ml403_ac97cr->reg_lock);
 506        while (((empty = (in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 507                          CR_RECEMPTY)) != CR_RECEMPTY) && (bytes > 1)) {
 508                dst[copied_words] = CR_RECDATA(in_be32(CR_REG(ml403_ac97cr,
 509                                                              RECFIFO)));
 510                copied_words++;
 511                bytes = bytes - 2;
 512        }
 513        if (empty != CR_RECEMPTY)
 514                rec->hw_ready = 1;
 515        else
 516                rec->hw_ready = 0;
 517        spin_unlock(&ml403_ac97cr->reg_lock);
 518
 519        return (size_t) (copied_words * 2);
 520}
 521
 522static snd_pcm_uframes_t
 523snd_ml403_ac97cr_pcm_pointer(struct snd_pcm_substream *substream)
 524{
 525        struct snd_ml403_ac97cr *ml403_ac97cr;
 526        struct snd_pcm_indirect2 *ind2_rec = NULL;
 527
 528        ml403_ac97cr = snd_pcm_substream_chip(substream);
 529
 530        if (substream == ml403_ac97cr->playback_substream)
 531                ind2_rec = &ml403_ac97cr->ind_rec;
 532        if (substream == ml403_ac97cr->capture_substream)
 533                ind2_rec = &ml403_ac97cr->capture_ind2_rec;
 534
 535        if (ind2_rec != NULL)
 536                return snd_pcm_indirect2_pointer(substream, ind2_rec);
 537        return (snd_pcm_uframes_t) 0;
 538}
 539
 540static int
 541snd_ml403_ac97cr_pcm_playback_trigger(struct snd_pcm_substream *substream,
 542                                      int cmd)
 543{
 544        struct snd_ml403_ac97cr *ml403_ac97cr;
 545        int err = 0;
 546
 547        ml403_ac97cr = snd_pcm_substream_chip(substream);
 548
 549        switch (cmd) {
 550        case SNDRV_PCM_TRIGGER_START:
 551                PDEBUG(WORK_INFO, "trigger(playback): START\n");
 552                ml403_ac97cr->ind_rec.hw_ready = 1;
 553
 554                /* clear play FIFO */
 555                out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_PLAYRESET);
 556
 557                /* enable play irq */
 558                ml403_ac97cr->enable_irq = 1;
 559                enable_irq(ml403_ac97cr->irq);
 560                break;
 561        case SNDRV_PCM_TRIGGER_STOP:
 562                PDEBUG(WORK_INFO, "trigger(playback): STOP\n");
 563                ml403_ac97cr->ind_rec.hw_ready = 0;
 564#ifdef SND_PCM_INDIRECT2_STAT
 565                snd_pcm_indirect2_stat(substream, &ml403_ac97cr->ind_rec);
 566#endif
 567                /* disable play irq */
 568                disable_irq_nosync(ml403_ac97cr->irq);
 569                ml403_ac97cr->enable_irq = 0;
 570                break;
 571        default:
 572                err = -EINVAL;
 573                break;
 574        }
 575        PDEBUG(WORK_INFO, "trigger(playback): (done)\n");
 576        return err;
 577}
 578
 579static int
 580snd_ml403_ac97cr_pcm_capture_trigger(struct snd_pcm_substream *substream,
 581                                      int cmd)
 582{
 583        struct snd_ml403_ac97cr *ml403_ac97cr;
 584        int err = 0;
 585
 586        ml403_ac97cr = snd_pcm_substream_chip(substream);
 587
 588        switch (cmd) {
 589        case SNDRV_PCM_TRIGGER_START:
 590                PDEBUG(WORK_INFO, "trigger(capture): START\n");
 591                ml403_ac97cr->capture_ind2_rec.hw_ready = 0;
 592
 593                /* clear record FIFO */
 594                out_be32(CR_REG(ml403_ac97cr, RESETFIFO), CR_RECRESET);
 595
 596                /* enable record irq */
 597                ml403_ac97cr->enable_capture_irq = 1;
 598                enable_irq(ml403_ac97cr->capture_irq);
 599                break;
 600        case SNDRV_PCM_TRIGGER_STOP:
 601                PDEBUG(WORK_INFO, "trigger(capture): STOP\n");
 602                ml403_ac97cr->capture_ind2_rec.hw_ready = 0;
 603#ifdef SND_PCM_INDIRECT2_STAT
 604                snd_pcm_indirect2_stat(substream,
 605                                       &ml403_ac97cr->capture_ind2_rec);
 606#endif
 607                /* disable capture irq */
 608                disable_irq_nosync(ml403_ac97cr->capture_irq);
 609                ml403_ac97cr->enable_capture_irq = 0;
 610                break;
 611        default:
 612                err = -EINVAL;
 613                break;
 614        }
 615        PDEBUG(WORK_INFO, "trigger(capture): (done)\n");
 616        return err;
 617}
 618
 619static int
 620snd_ml403_ac97cr_pcm_playback_prepare(struct snd_pcm_substream *substream)
 621{
 622        struct snd_ml403_ac97cr *ml403_ac97cr;
 623        struct snd_pcm_runtime *runtime;
 624
 625        ml403_ac97cr = snd_pcm_substream_chip(substream);
 626        runtime = substream->runtime;
 627
 628        PDEBUG(WORK_INFO,
 629               "prepare(): period_bytes=%d, minperiod_bytes=%d\n",
 630               snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2);
 631
 632        /* set sampling rate */
 633        snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_FRONT_DAC_RATE,
 634                          runtime->rate);
 635        PDEBUG(WORK_INFO, "prepare(): rate=%d\n", runtime->rate);
 636
 637        /* init struct for intermediate buffer */
 638        memset(&ml403_ac97cr->ind_rec, 0,
 639               sizeof(struct snd_pcm_indirect2));
 640        ml403_ac97cr->ind_rec.hw_buffer_size = CR_FIFO_SIZE;
 641        ml403_ac97cr->ind_rec.sw_buffer_size =
 642                snd_pcm_lib_buffer_bytes(substream);
 643        ml403_ac97cr->ind_rec.min_periods = -1;
 644        ml403_ac97cr->ind_rec.min_multiple =
 645                snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2);
 646        PDEBUG(WORK_INFO, "prepare(): hw_buffer_size=%d, "
 647               "sw_buffer_size=%d, min_multiple=%d\n",
 648               CR_FIFO_SIZE, ml403_ac97cr->ind_rec.sw_buffer_size,
 649               ml403_ac97cr->ind_rec.min_multiple);
 650        return 0;
 651}
 652
 653static int
 654snd_ml403_ac97cr_pcm_capture_prepare(struct snd_pcm_substream *substream)
 655{
 656        struct snd_ml403_ac97cr *ml403_ac97cr;
 657        struct snd_pcm_runtime *runtime;
 658
 659        ml403_ac97cr = snd_pcm_substream_chip(substream);
 660        runtime = substream->runtime;
 661
 662        PDEBUG(WORK_INFO,
 663               "prepare(capture): period_bytes=%d, minperiod_bytes=%d\n",
 664               snd_pcm_lib_period_bytes(substream), CR_FIFO_SIZE / 2);
 665
 666        /* set sampling rate */
 667        snd_ac97_set_rate(ml403_ac97cr->ac97, AC97_PCM_LR_ADC_RATE,
 668                          runtime->rate);
 669        PDEBUG(WORK_INFO, "prepare(capture): rate=%d\n", runtime->rate);
 670
 671        /* init struct for intermediate buffer */
 672        memset(&ml403_ac97cr->capture_ind2_rec, 0,
 673               sizeof(struct snd_pcm_indirect2));
 674        ml403_ac97cr->capture_ind2_rec.hw_buffer_size = CR_FIFO_SIZE;
 675        ml403_ac97cr->capture_ind2_rec.sw_buffer_size =
 676                snd_pcm_lib_buffer_bytes(substream);
 677        ml403_ac97cr->capture_ind2_rec.min_multiple =
 678                snd_pcm_lib_period_bytes(substream) / (CR_FIFO_SIZE / 2);
 679        PDEBUG(WORK_INFO, "prepare(capture): hw_buffer_size=%d, "
 680               "sw_buffer_size=%d, min_multiple=%d\n", CR_FIFO_SIZE,
 681               ml403_ac97cr->capture_ind2_rec.sw_buffer_size,
 682               ml403_ac97cr->capture_ind2_rec.min_multiple);
 683        return 0;
 684}
 685
 686static int snd_ml403_ac97cr_hw_free(struct snd_pcm_substream *substream)
 687{
 688        PDEBUG(WORK_INFO, "hw_free()\n");
 689        return snd_pcm_lib_free_pages(substream);
 690}
 691
 692static int
 693snd_ml403_ac97cr_hw_params(struct snd_pcm_substream *substream,
 694                           struct snd_pcm_hw_params *hw_params)
 695{
 696        PDEBUG(WORK_INFO, "hw_params(): desired buffer bytes=%d, desired "
 697               "period bytes=%d\n",
 698               params_buffer_bytes(hw_params), params_period_bytes(hw_params));
 699        return snd_pcm_lib_malloc_pages(substream,
 700                                        params_buffer_bytes(hw_params));
 701}
 702
 703static int snd_ml403_ac97cr_playback_open(struct snd_pcm_substream *substream)
 704{
 705        struct snd_ml403_ac97cr *ml403_ac97cr;
 706        struct snd_pcm_runtime *runtime;
 707
 708        ml403_ac97cr = snd_pcm_substream_chip(substream);
 709        runtime = substream->runtime;
 710
 711        PDEBUG(WORK_INFO, "open(playback)\n");
 712        ml403_ac97cr->playback_substream = substream;
 713        runtime->hw = snd_ml403_ac97cr_playback;
 714
 715        snd_pcm_hw_constraint_step(runtime, 0,
 716                                   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 717                                   CR_FIFO_SIZE / 2);
 718        return 0;
 719}
 720
 721static int snd_ml403_ac97cr_capture_open(struct snd_pcm_substream *substream)
 722{
 723        struct snd_ml403_ac97cr *ml403_ac97cr;
 724        struct snd_pcm_runtime *runtime;
 725
 726        ml403_ac97cr = snd_pcm_substream_chip(substream);
 727        runtime = substream->runtime;
 728
 729        PDEBUG(WORK_INFO, "open(capture)\n");
 730        ml403_ac97cr->capture_substream = substream;
 731        runtime->hw = snd_ml403_ac97cr_capture;
 732
 733        snd_pcm_hw_constraint_step(runtime, 0,
 734                                   SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
 735                                   CR_FIFO_SIZE / 2);
 736        return 0;
 737}
 738
 739static int snd_ml403_ac97cr_playback_close(struct snd_pcm_substream *substream)
 740{
 741        struct snd_ml403_ac97cr *ml403_ac97cr;
 742
 743        ml403_ac97cr = snd_pcm_substream_chip(substream);
 744
 745        PDEBUG(WORK_INFO, "close(playback)\n");
 746        ml403_ac97cr->playback_substream = NULL;
 747        return 0;
 748}
 749
 750static int snd_ml403_ac97cr_capture_close(struct snd_pcm_substream *substream)
 751{
 752        struct snd_ml403_ac97cr *ml403_ac97cr;
 753
 754        ml403_ac97cr = snd_pcm_substream_chip(substream);
 755
 756        PDEBUG(WORK_INFO, "close(capture)\n");
 757        ml403_ac97cr->capture_substream = NULL;
 758        return 0;
 759}
 760
 761static struct snd_pcm_ops snd_ml403_ac97cr_playback_ops = {
 762        .open = snd_ml403_ac97cr_playback_open,
 763        .close = snd_ml403_ac97cr_playback_close,
 764        .ioctl = snd_pcm_lib_ioctl,
 765        .hw_params = snd_ml403_ac97cr_hw_params,
 766        .hw_free = snd_ml403_ac97cr_hw_free,
 767        .prepare = snd_ml403_ac97cr_pcm_playback_prepare,
 768        .trigger = snd_ml403_ac97cr_pcm_playback_trigger,
 769        .pointer = snd_ml403_ac97cr_pcm_pointer,
 770};
 771
 772static struct snd_pcm_ops snd_ml403_ac97cr_capture_ops = {
 773        .open = snd_ml403_ac97cr_capture_open,
 774        .close = snd_ml403_ac97cr_capture_close,
 775        .ioctl = snd_pcm_lib_ioctl,
 776        .hw_params = snd_ml403_ac97cr_hw_params,
 777        .hw_free = snd_ml403_ac97cr_hw_free,
 778        .prepare = snd_ml403_ac97cr_pcm_capture_prepare,
 779        .trigger = snd_ml403_ac97cr_pcm_capture_trigger,
 780        .pointer = snd_ml403_ac97cr_pcm_pointer,
 781};
 782
 783static irqreturn_t snd_ml403_ac97cr_irq(int irq, void *dev_id)
 784{
 785        struct snd_ml403_ac97cr *ml403_ac97cr;
 786        struct platform_device *pfdev;
 787        int cmp_irq;
 788
 789        ml403_ac97cr = (struct snd_ml403_ac97cr *)dev_id;
 790        if (ml403_ac97cr == NULL)
 791                return IRQ_NONE;
 792
 793        pfdev = ml403_ac97cr->pfdev;
 794
 795        /* playback interrupt */
 796        cmp_irq = platform_get_irq(pfdev, 0);
 797        if (irq == cmp_irq) {
 798                if (ml403_ac97cr->enable_irq)
 799                        snd_pcm_indirect2_playback_interrupt(
 800                                ml403_ac97cr->playback_substream,
 801                                &ml403_ac97cr->ind_rec,
 802                                snd_ml403_ac97cr_playback_ind2_copy,
 803                                snd_ml403_ac97cr_playback_ind2_zero);
 804                else
 805                        goto __disable_irq;
 806        } else {
 807                /* record interrupt */
 808                cmp_irq = platform_get_irq(pfdev, 1);
 809                if (irq == cmp_irq) {
 810                        if (ml403_ac97cr->enable_capture_irq)
 811                                snd_pcm_indirect2_capture_interrupt(
 812                                        ml403_ac97cr->capture_substream,
 813                                        &ml403_ac97cr->capture_ind2_rec,
 814                                        snd_ml403_ac97cr_capture_ind2_copy,
 815                                        snd_ml403_ac97cr_capture_ind2_null);
 816                        else
 817                                goto __disable_irq;
 818                } else
 819                        return IRQ_NONE;
 820        }
 821        return IRQ_HANDLED;
 822
 823__disable_irq:
 824        PDEBUG(INIT_INFO, "irq(): irq %d is meant to be disabled! So, now try "
 825               "to disable it _really_!\n", irq);
 826        disable_irq_nosync(irq);
 827        return IRQ_HANDLED;
 828}
 829
 830static unsigned short
 831snd_ml403_ac97cr_codec_read(struct snd_ac97 *ac97, unsigned short reg)
 832{
 833        struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
 834#ifdef CODEC_STAT
 835        u32 stat;
 836        u32 rafaccess = 0;
 837#endif
 838        unsigned long end_time;
 839        u16 value = 0;
 840
 841        if (!LM4550_RF_OK(reg)) {
 842                snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 843                           "access to unknown/unused codec register 0x%x "
 844                           "ignored!\n", reg);
 845                return 0;
 846        }
 847        /* check if we can fake/answer this access from our shadow register */
 848        if ((lm4550_regfile[reg / 2].flag &
 849             (LM4550_REG_DONEREAD | LM4550_REG_ALLFAKE)) &&
 850            !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) {
 851                if (lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEREAD) {
 852                        PDEBUG(CODEC_FAKE, "codec_read(): faking read from "
 853                               "reg=0x%x, val=0x%x / %d\n",
 854                               reg, lm4550_regfile[reg / 2].def,
 855                               lm4550_regfile[reg / 2].def);
 856                        return lm4550_regfile[reg / 2].def;
 857                } else if ((lm4550_regfile[reg / 2].flag &
 858                            LM4550_REG_FAKEPROBE) &&
 859                           ml403_ac97cr->ac97_fake) {
 860                        PDEBUG(CODEC_FAKE, "codec_read(): faking read from "
 861                               "reg=0x%x, val=0x%x / %d (probe)\n",
 862                               reg, lm4550_regfile[reg / 2].value,
 863                               lm4550_regfile[reg / 2].value);
 864                        return lm4550_regfile[reg / 2].value;
 865                } else {
 866#ifdef CODEC_STAT
 867                        PDEBUG(CODEC_FAKE, "codec_read(): read access "
 868                               "answered by shadow register 0x%x (value=0x%x "
 869                               "/ %d) (cw=%d cr=%d)\n",
 870                               reg, lm4550_regfile[reg / 2].value,
 871                               lm4550_regfile[reg / 2].value,
 872                               ml403_ac97cr->ac97_write,
 873                               ml403_ac97cr->ac97_read);
 874#else
 875                        PDEBUG(CODEC_FAKE, "codec_read(): read access "
 876                               "answered by shadow register 0x%x (value=0x%x "
 877                               "/ %d)\n",
 878                               reg, lm4550_regfile[reg / 2].value,
 879                               lm4550_regfile[reg / 2].value);
 880#endif
 881                        return lm4550_regfile[reg / 2].value;
 882                }
 883        }
 884        /* if we are here, we _have_ to access the codec really, no faking */
 885        if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0)
 886                return 0;
 887#ifdef CODEC_STAT
 888        ml403_ac97cr->ac97_read++;
 889#endif
 890        spin_lock(&ml403_ac97cr->reg_lock);
 891        out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR),
 892                 CR_CODEC_ADDR(reg) | CR_CODEC_READ);
 893        spin_unlock(&ml403_ac97cr->reg_lock);
 894        end_time = jiffies + (HZ / CODEC_TIMEOUT_AFTER_READ);
 895        do {
 896                spin_lock(&ml403_ac97cr->reg_lock);
 897#ifdef CODEC_STAT
 898                rafaccess++;
 899                stat = in_be32(CR_REG(ml403_ac97cr, STATUS));
 900                if ((stat & CR_RAF) == CR_RAF) {
 901                        value = CR_CODEC_DATAREAD(
 902                                in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 903                        PDEBUG(CODEC_SUCCESS, "codec_read(): (done) reg=0x%x, "
 904                               "value=0x%x / %d (STATUS=0x%x)\n",
 905                               reg, value, value, stat);
 906#else
 907                if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) &
 908                     CR_RAF) == CR_RAF) {
 909                        value = CR_CODEC_DATAREAD(
 910                                in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 911                        PDEBUG(CODEC_SUCCESS, "codec_read(): (done) "
 912                               "reg=0x%x, value=0x%x / %d\n",
 913                               reg, value, value);
 914#endif
 915                        lm4550_regfile[reg / 2].value = value;
 916                        lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
 917                        spin_unlock(&ml403_ac97cr->reg_lock);
 918                        mutex_unlock(&ml403_ac97cr->cdc_mutex);
 919                        return value;
 920                }
 921                spin_unlock(&ml403_ac97cr->reg_lock);
 922                schedule_timeout_uninterruptible(1);
 923        } while (time_after(end_time, jiffies));
 924        /* read the DATAREAD register anyway, see comment below */
 925        spin_lock(&ml403_ac97cr->reg_lock);
 926        value =
 927            CR_CODEC_DATAREAD(in_be32(CR_REG(ml403_ac97cr, CODEC_DATAREAD)));
 928        spin_unlock(&ml403_ac97cr->reg_lock);
 929#ifdef CODEC_STAT
 930        snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 931                   "timeout while codec read! "
 932                   "(reg=0x%x, last STATUS=0x%x, DATAREAD=0x%x / %d, %d) "
 933                   "(cw=%d, cr=%d)\n",
 934                   reg, stat, value, value, rafaccess,
 935                   ml403_ac97cr->ac97_write, ml403_ac97cr->ac97_read);
 936#else
 937        snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 938                   "timeout while codec read! "
 939                   "(reg=0x%x, DATAREAD=0x%x / %d)\n",
 940                   reg, value, value);
 941#endif
 942        /* BUG: This is PURE speculation! But after _most_ read timeouts the
 943         * value in the register is ok!
 944         */
 945        lm4550_regfile[reg / 2].value = value;
 946        lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
 947        mutex_unlock(&ml403_ac97cr->cdc_mutex);
 948        return value;
 949}
 950
 951static void
 952snd_ml403_ac97cr_codec_write(struct snd_ac97 *ac97, unsigned short reg,
 953                             unsigned short val)
 954{
 955        struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
 956
 957#ifdef CODEC_STAT
 958        u32 stat;
 959        u32 rafaccess = 0;
 960#endif
 961#ifdef CODEC_WRITE_CHECK_RAF
 962        unsigned long end_time;
 963#endif
 964
 965        if (!LM4550_RF_OK(reg)) {
 966                snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 967                           "access to unknown/unused codec register 0x%x "
 968                           "ignored!\n", reg);
 969                return;
 970        }
 971        if (lm4550_regfile[reg / 2].flag & LM4550_REG_READONLY) {
 972                snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 973                           "write access to read only codec register 0x%x "
 974                           "ignored!\n", reg);
 975                return;
 976        }
 977        if ((val & lm4550_regfile[reg / 2].wmask) != val) {
 978                snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
 979                           "write access to codec register 0x%x "
 980                           "with bad value 0x%x / %d!\n",
 981                           reg, val, val);
 982                val = val & lm4550_regfile[reg / 2].wmask;
 983        }
 984        if (((lm4550_regfile[reg / 2].flag & LM4550_REG_FAKEPROBE) &&
 985             ml403_ac97cr->ac97_fake) &&
 986            !(lm4550_regfile[reg / 2].flag & LM4550_REG_NOSHADOW)) {
 987                PDEBUG(CODEC_FAKE, "codec_write(): faking write to reg=0x%x, "
 988                       "val=0x%x / %d\n", reg, val, val);
 989                lm4550_regfile[reg / 2].value = (val &
 990                                                lm4550_regfile[reg / 2].wmask);
 991                return;
 992        }
 993        if (mutex_lock_interruptible(&ml403_ac97cr->cdc_mutex) != 0)
 994                return;
 995#ifdef CODEC_STAT
 996        ml403_ac97cr->ac97_write++;
 997#endif
 998        spin_lock(&ml403_ac97cr->reg_lock);
 999        out_be32(CR_REG(ml403_ac97cr, CODEC_DATAWRITE),
1000                 CR_CODEC_DATAWRITE(val));
1001        out_be32(CR_REG(ml403_ac97cr, CODEC_ADDR),
1002                 CR_CODEC_ADDR(reg) | CR_CODEC_WRITE);
1003        spin_unlock(&ml403_ac97cr->reg_lock);
1004#ifdef CODEC_WRITE_CHECK_RAF
1005        /* check CR_CODEC_RAF bit to see if write access to register is done;
1006         * loop until bit is set or timeout happens
1007         */
1008        end_time = jiffies + HZ / CODEC_TIMEOUT_AFTER_WRITE;
1009        do {
1010                spin_lock(&ml403_ac97cr->reg_lock);
1011#ifdef CODEC_STAT
1012                rafaccess++;
1013                stat = in_be32(CR_REG(ml403_ac97cr, STATUS))
1014                if ((stat & CR_RAF) == CR_RAF) {
1015#else
1016                if ((in_be32(CR_REG(ml403_ac97cr, STATUS)) &
1017                     CR_RAF) == CR_RAF) {
1018#endif
1019                        PDEBUG(CODEC_SUCCESS, "codec_write(): (done) "
1020                               "reg=0x%x, value=%d / 0x%x\n",
1021                               reg, val, val);
1022                        if (!(lm4550_regfile[reg / 2].flag &
1023                              LM4550_REG_NOSHADOW) &&
1024                            !(lm4550_regfile[reg / 2].flag &
1025                              LM4550_REG_NOSAVE))
1026                                lm4550_regfile[reg / 2].value = val;
1027                        lm4550_regfile[reg / 2].flag |= LM4550_REG_DONEREAD;
1028                        spin_unlock(&ml403_ac97cr->reg_lock);
1029                        mutex_unlock(&ml403_ac97cr->cdc_mutex);
1030                        return;
1031                }
1032                spin_unlock(&ml403_ac97cr->reg_lock);
1033                schedule_timeout_uninterruptible(1);
1034        } while (time_after(end_time, jiffies));
1035#ifdef CODEC_STAT
1036        snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
1037                   "timeout while codec write "
1038                   "(reg=0x%x, val=0x%x / %d, last STATUS=0x%x, %d) "
1039                   "(cw=%d, cr=%d)\n",
1040                   reg, val, val, stat, rafaccess, ml403_ac97cr->ac97_write,
1041                   ml403_ac97cr->ac97_read);
1042#else
1043        snd_printk(KERN_WARNING SND_ML403_AC97CR_DRIVER ": "
1044                   "timeout while codec write (reg=0x%x, val=0x%x / %d)\n",
1045                   reg, val, val);
1046#endif
1047#else /* CODEC_WRITE_CHECK_RAF */
1048#if CODEC_WAIT_AFTER_WRITE > 0
1049        /* officially, in AC97 spec there is no possibility for a AC97
1050         * controller to determine, if write access is done or not - so: How
1051         * is Xilinx able to provide a RAF bit for write access?
1052         * => very strange, thus just don't check RAF bit (compare with
1053         * Xilinx's example app in EDK 8.1i) and wait
1054         */
1055        schedule_timeout_uninterruptible(HZ / CODEC_WAIT_AFTER_WRITE);
1056#endif
1057        PDEBUG(CODEC_SUCCESS, "codec_write(): (done) "
1058               "reg=0x%x, value=%d / 0x%x (no RAF check)\n",
1059               reg, val, val);
1060#endif
1061        mutex_unlock(&ml403_ac97cr->cdc_mutex);
1062        return;
1063}
1064
1065static int __devinit
1066snd_ml403_ac97cr_chip_init(struct snd_ml403_ac97cr *ml403_ac97cr)
1067{
1068        unsigned long end_time;
1069        PDEBUG(INIT_INFO, "chip_init():\n");
1070        end_time = jiffies + HZ / CODEC_TIMEOUT_ON_INIT;
1071        do {
1072                if (in_be32(CR_REG(ml403_ac97cr, STATUS)) & CR_CODECREADY) {
1073                        /* clear both hardware FIFOs */
1074                        out_be32(CR_REG(ml403_ac97cr, RESETFIFO),
1075                                 CR_RECRESET | CR_PLAYRESET);
1076                        PDEBUG(INIT_INFO, "chip_init(): (done)\n");
1077                        return 0;
1078                }
1079                schedule_timeout_uninterruptible(1);
1080        } while (time_after(end_time, jiffies));
1081        snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1082                   "timeout while waiting for codec, "
1083                   "not ready!\n");
1084        return -EBUSY;
1085}
1086
1087static int snd_ml403_ac97cr_free(struct snd_ml403_ac97cr *ml403_ac97cr)
1088{
1089        PDEBUG(INIT_INFO, "free():\n");
1090        /* irq release */
1091        if (ml403_ac97cr->irq >= 0)
1092                free_irq(ml403_ac97cr->irq, ml403_ac97cr);
1093        if (ml403_ac97cr->capture_irq >= 0)
1094                free_irq(ml403_ac97cr->capture_irq, ml403_ac97cr);
1095        /* give back "port" */
1096        if (ml403_ac97cr->port != NULL)
1097                iounmap(ml403_ac97cr->port);
1098        kfree(ml403_ac97cr);
1099        PDEBUG(INIT_INFO, "free(): (done)\n");
1100        return 0;
1101}
1102
1103static int snd_ml403_ac97cr_dev_free(struct snd_device *snddev)
1104{
1105        struct snd_ml403_ac97cr *ml403_ac97cr = snddev->device_data;
1106        PDEBUG(INIT_INFO, "dev_free():\n");
1107        return snd_ml403_ac97cr_free(ml403_ac97cr);
1108}
1109
1110static int __devinit
1111snd_ml403_ac97cr_create(struct snd_card *card, struct platform_device *pfdev,
1112                        struct snd_ml403_ac97cr **rml403_ac97cr)
1113{
1114        struct snd_ml403_ac97cr *ml403_ac97cr;
1115        int err;
1116        static struct snd_device_ops ops = {
1117                .dev_free = snd_ml403_ac97cr_dev_free,
1118        };
1119        struct resource *resource;
1120        int irq;
1121
1122        *rml403_ac97cr = NULL;
1123        ml403_ac97cr = kzalloc(sizeof(*ml403_ac97cr), GFP_KERNEL);
1124        if (ml403_ac97cr == NULL)
1125                return -ENOMEM;
1126        spin_lock_init(&ml403_ac97cr->reg_lock);
1127        mutex_init(&ml403_ac97cr->cdc_mutex);
1128        ml403_ac97cr->card = card;
1129        ml403_ac97cr->pfdev = pfdev;
1130        ml403_ac97cr->irq = -1;
1131        ml403_ac97cr->enable_irq = 0;
1132        ml403_ac97cr->capture_irq = -1;
1133        ml403_ac97cr->enable_capture_irq = 0;
1134        ml403_ac97cr->port = NULL;
1135        ml403_ac97cr->res_port = NULL;
1136
1137        PDEBUG(INIT_INFO, "Trying to reserve resources now ...\n");
1138        resource = platform_get_resource(pfdev, IORESOURCE_MEM, 0);
1139        /* get "port" */
1140        ml403_ac97cr->port = ioremap_nocache(resource->start,
1141                                             (resource->end) -
1142                                             (resource->start) + 1);
1143        if (ml403_ac97cr->port == NULL) {
1144                snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1145                           "unable to remap memory region (%x to %x)\n",
1146                           resource->start, resource->end);
1147                snd_ml403_ac97cr_free(ml403_ac97cr);
1148                return -EBUSY;
1149        }
1150        snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1151                   "remap controller memory region to "
1152                   "0x%x done\n", (unsigned int)ml403_ac97cr->port);
1153        /* get irq */
1154        irq = platform_get_irq(pfdev, 0);
1155        if (request_irq(irq, snd_ml403_ac97cr_irq, IRQF_DISABLED,
1156                        dev_name(&pfdev->dev), (void *)ml403_ac97cr)) {
1157                snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1158                           "unable to grab IRQ %d\n",
1159                           irq);
1160                snd_ml403_ac97cr_free(ml403_ac97cr);
1161                return -EBUSY;
1162        }
1163        ml403_ac97cr->irq = irq;
1164        snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1165                   "request (playback) irq %d done\n",
1166                   ml403_ac97cr->irq);
1167        irq = platform_get_irq(pfdev, 1);
1168        if (request_irq(irq, snd_ml403_ac97cr_irq, IRQF_DISABLED,
1169                        dev_name(&pfdev->dev), (void *)ml403_ac97cr)) {
1170                snd_printk(KERN_ERR SND_ML403_AC97CR_DRIVER ": "
1171                           "unable to grab IRQ %d\n",
1172                           irq);
1173                snd_ml403_ac97cr_free(ml403_ac97cr);
1174                return -EBUSY;
1175        }
1176        ml403_ac97cr->capture_irq = irq;
1177        snd_printk(KERN_INFO SND_ML403_AC97CR_DRIVER ": "
1178                   "request (capture) irq %d done\n",
1179                   ml403_ac97cr->capture_irq);
1180
1181        err = snd_ml403_ac97cr_chip_init(ml403_ac97cr);
1182        if (err < 0) {
1183                snd_ml403_ac97cr_free(ml403_ac97cr);
1184                return err;
1185        }
1186
1187        err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ml403_ac97cr, &ops);
1188        if (err < 0) {
1189                PDEBUG(INIT_FAILURE, "probe(): snd_device_new() failed!\n");
1190                snd_ml403_ac97cr_free(ml403_ac97cr);
1191                return err;
1192        }
1193
1194        *rml403_ac97cr = ml403_ac97cr;
1195        return 0;
1196}
1197
1198static void snd_ml403_ac97cr_mixer_free(struct snd_ac97 *ac97)
1199{
1200        struct snd_ml403_ac97cr *ml403_ac97cr = ac97->private_data;
1201        PDEBUG(INIT_INFO, "mixer_free():\n");
1202        ml403_ac97cr->ac97 = NULL;
1203        PDEBUG(INIT_INFO, "mixer_free(): (done)\n");
1204}
1205
1206static int __devinit
1207snd_ml403_ac97cr_mixer(struct snd_ml403_ac97cr *ml403_ac97cr)
1208{
1209        struct snd_ac97_bus *bus;
1210        struct snd_ac97_template ac97;
1211        int err;
1212        static struct snd_ac97_bus_ops ops = {
1213                .write = snd_ml403_ac97cr_codec_write,
1214                .read = snd_ml403_ac97cr_codec_read,
1215        };
1216        PDEBUG(INIT_INFO, "mixer():\n");
1217        err = snd_ac97_bus(ml403_ac97cr->card, 0, &ops, NULL, &bus);
1218        if (err < 0)
1219                return err;
1220
1221        memset(&ac97, 0, sizeof(ac97));
1222        ml403_ac97cr->ac97_fake = 1;
1223        lm4550_regfile_init();
1224#ifdef CODEC_STAT
1225        ml403_ac97cr->ac97_read = 0;
1226        ml403_ac97cr->ac97_write = 0;
1227#endif
1228        ac97.private_data = ml403_ac97cr;
1229        ac97.private_free = snd_ml403_ac97cr_mixer_free;
1230        ac97.scaps = AC97_SCAP_AUDIO | AC97_SCAP_SKIP_MODEM |
1231            AC97_SCAP_NO_SPDIF;
1232        err = snd_ac97_mixer(bus, &ac97, &ml403_ac97cr->ac97);
1233        ml403_ac97cr->ac97_fake = 0;
1234        lm4550_regfile_write_values_after_init(ml403_ac97cr->ac97);
1235        PDEBUG(INIT_INFO, "mixer(): (done) snd_ac97_mixer()=%d\n", err);
1236        return err;
1237}
1238
1239static int __devinit
1240snd_ml403_ac97cr_pcm(struct snd_ml403_ac97cr *ml403_ac97cr, int device,
1241                     struct snd_pcm **rpcm)
1242{
1243        struct snd_pcm *pcm;
1244        int err;
1245
1246        if (rpcm)
1247                *rpcm = NULL;
1248        err = snd_pcm_new(ml403_ac97cr->card, "ML403AC97CR/1", device, 1, 1,
1249                          &pcm);
1250        if (err < 0)
1251                return err;
1252        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
1253                        &snd_ml403_ac97cr_playback_ops);
1254        snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
1255                        &snd_ml403_ac97cr_capture_ops);
1256        pcm->private_data = ml403_ac97cr;
1257        pcm->info_flags = 0;
1258        strcpy(pcm->name, "ML403AC97CR DAC/ADC");
1259        ml403_ac97cr->pcm = pcm;
1260
1261        snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS,
1262                                          snd_dma_continuous_data(GFP_KERNEL),
1263                                          64 * 1024,
1264                                          128 * 1024);
1265        if (rpcm)
1266                *rpcm = pcm;
1267        return 0;
1268}
1269
1270static int __devinit snd_ml403_ac97cr_probe(struct platform_device *pfdev)
1271{
1272        struct snd_card *card;
1273        struct snd_ml403_ac97cr *ml403_ac97cr = NULL;
1274        int err;
1275        int dev = pfdev->id;
1276
1277        if (dev >= SNDRV_CARDS)
1278                return -ENODEV;
1279        if (!enable[dev])
1280                return -ENOENT;
1281
1282        card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1283        if (card == NULL)
1284                return -ENOMEM;
1285        err = snd_ml403_ac97cr_create(card, pfdev, &ml403_ac97cr);
1286        if (err < 0) {
1287                PDEBUG(INIT_FAILURE, "probe(): create failed!\n");
1288                snd_card_free(card);
1289                return err;
1290        }
1291        PDEBUG(INIT_INFO, "probe(): create done\n");
1292        card->private_data = ml403_ac97cr;
1293        err = snd_ml403_ac97cr_mixer(ml403_ac97cr);
1294        if (err < 0) {
1295                snd_card_free(card);
1296                return err;
1297        }
1298        PDEBUG(INIT_INFO, "probe(): mixer done\n");
1299        err = snd_ml403_ac97cr_pcm(ml403_ac97cr, 0, NULL);
1300        if (err < 0) {
1301                snd_card_free(card);
1302                return err;
1303        }
1304        PDEBUG(INIT_INFO, "probe(): PCM done\n");
1305        strcpy(card->driver, SND_ML403_AC97CR_DRIVER);
1306        strcpy(card->shortname, "ML403 AC97 Controller Reference");
1307        sprintf(card->longname, "%s %s at 0x%lx, irq %i & %i, device %i",
1308                card->shortname, card->driver,
1309                (unsigned long)ml403_ac97cr->port, ml403_ac97cr->irq,
1310                ml403_ac97cr->capture_irq, dev + 1);
1311
1312        snd_card_set_dev(card, &pfdev->dev);
1313
1314        err = snd_card_register(card);
1315        if (err < 0) {
1316                snd_card_free(card);
1317                return err;
1318        }
1319        platform_set_drvdata(pfdev, card);
1320        PDEBUG(INIT_INFO, "probe(): (done)\n");
1321        return 0;
1322}
1323
1324static int snd_ml403_ac97cr_remove(struct platform_device *pfdev)
1325{
1326        snd_card_free(platform_get_drvdata(pfdev));
1327        platform_set_drvdata(pfdev, NULL);
1328        return 0;
1329}
1330
1331/* work with hotplug and coldplug */
1332MODULE_ALIAS("platform:" SND_ML403_AC97CR_DRIVER);
1333
1334static struct platform_driver snd_ml403_ac97cr_driver = {
1335        .probe = snd_ml403_ac97cr_probe,
1336        .remove = snd_ml403_ac97cr_remove,
1337        .driver = {
1338                .name = SND_ML403_AC97CR_DRIVER,
1339                .owner = THIS_MODULE,
1340        },
1341};
1342
1343static int __init alsa_card_ml403_ac97cr_init(void)
1344{
1345        return platform_driver_register(&snd_ml403_ac97cr_driver);
1346}
1347
1348static void __exit alsa_card_ml403_ac97cr_exit(void)
1349{
1350        platform_driver_unregister(&snd_ml403_ac97cr_driver);
1351}
1352
1353module_init(alsa_card_ml403_ac97cr_init)
1354module_exit(alsa_card_ml403_ac97cr_exit)
1355