linux/Documentation/spi/pxa2xx
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   1PXA2xx SPI on SSP driver HOWTO
   2===================================================
   3This a mini howto on the pxa2xx_spi driver.  The driver turns a PXA2xx
   4synchronous serial port into a SPI master controller
   5(see Documentation/spi/spi_summary). The driver has the following features
   6
   7- Support for any PXA2xx SSP
   8- SSP PIO and SSP DMA data transfers.
   9- External and Internal (SSPFRM) chip selects.
  10- Per slave device (chip) configuration.
  11- Full suspend, freeze, resume support.
  12
  13The driver is built around a "spi_message" fifo serviced by workqueue and a
  14tasklet. The workqueue, "pump_messages", drives message fifo and the tasklet
  15(pump_transfer) is responsible for queuing SPI transactions and setting up and
  16launching the dma/interrupt driven transfers.
  17
  18Declaring PXA2xx Master Controllers
  19-----------------------------------
  20Typically a SPI master is defined in the arch/.../mach-*/board-*.c as a
  21"platform device".  The master configuration is passed to the driver via a table
  22found in arch/arm/mach-pxa/include/mach/pxa2xx_spi.h:
  23
  24struct pxa2xx_spi_master {
  25        enum pxa_ssp_type ssp_type;
  26        u32 clock_enable;
  27        u16 num_chipselect;
  28        u8 enable_dma;
  29};
  30
  31The "pxa2xx_spi_master.ssp_type" field must have a value between 1 and 3 and
  32informs the driver which features a particular SSP supports.
  33
  34The "pxa2xx_spi_master.clock_enable" field is used to enable/disable the
  35corresponding SSP peripheral block in the "Clock Enable Register (CKEN"). See
  36the "PXA2xx Developer Manual" section "Clocks and Power Management".
  37
  38The "pxa2xx_spi_master.num_chipselect" field is used to determine the number of
  39slave device (chips) attached to this SPI master.
  40
  41The "pxa2xx_spi_master.enable_dma" field informs the driver that SSP DMA should
  42be used.  This caused the driver to acquire two DMA channels: rx_channel and
  43tx_channel.  The rx_channel has a higher DMA service priority the tx_channel.
  44See the "PXA2xx Developer Manual" section "DMA Controller".
  45
  46NSSP MASTER SAMPLE
  47------------------
  48Below is a sample configuration using the PXA255 NSSP.
  49
  50static struct resource pxa_spi_nssp_resources[] = {
  51        [0] = {
  52                .start  = __PREG(SSCR0_P(2)), /* Start address of NSSP */
  53                .end    = __PREG(SSCR0_P(2)) + 0x2c, /* Range of registers */
  54                .flags  = IORESOURCE_MEM,
  55        },
  56        [1] = {
  57                .start  = IRQ_NSSP, /* NSSP IRQ */
  58                .end    = IRQ_NSSP,
  59                .flags  = IORESOURCE_IRQ,
  60        },
  61};
  62
  63static struct pxa2xx_spi_master pxa_nssp_master_info = {
  64        .ssp_type = PXA25x_NSSP, /* Type of SSP */
  65        .clock_enable = CKEN_NSSP, /* NSSP Peripheral clock */
  66        .num_chipselect = 1, /* Matches the number of chips attached to NSSP */
  67        .enable_dma = 1, /* Enables NSSP DMA */
  68};
  69
  70static struct platform_device pxa_spi_nssp = {
  71        .name = "pxa2xx-spi", /* MUST BE THIS VALUE, so device match driver */
  72        .id = 2, /* Bus number, MUST MATCH SSP number 1..n */
  73        .resource = pxa_spi_nssp_resources,
  74        .num_resources = ARRAY_SIZE(pxa_spi_nssp_resources),
  75        .dev = {
  76                .platform_data = &pxa_nssp_master_info, /* Passed to driver */
  77        },
  78};
  79
  80static struct platform_device *devices[] __initdata = {
  81        &pxa_spi_nssp,
  82};
  83
  84static void __init board_init(void)
  85{
  86        (void)platform_add_device(devices, ARRAY_SIZE(devices));
  87}
  88
  89Declaring Slave Devices
  90-----------------------
  91Typically each SPI slave (chip) is defined in the arch/.../mach-*/board-*.c
  92using the "spi_board_info" structure found in "linux/spi/spi.h". See
  93"Documentation/spi/spi_summary" for additional information.
  94
  95Each slave device attached to the PXA must provide slave specific configuration
  96information via the structure "pxa2xx_spi_chip" found in
  97"arch/arm/mach-pxa/include/mach/pxa2xx_spi.h".  The pxa2xx_spi master controller driver
  98will uses the configuration whenever the driver communicates with the slave
  99device. All fields are optional.
 100
 101struct pxa2xx_spi_chip {
 102        u8 tx_threshold;
 103        u8 rx_threshold;
 104        u8 dma_burst_size;
 105        u32 timeout;
 106        u8 enable_loopback;
 107        void (*cs_control)(u32 command);
 108};
 109
 110The "pxa2xx_spi_chip.tx_threshold" and "pxa2xx_spi_chip.rx_threshold" fields are
 111used to configure the SSP hardware fifo.  These fields are critical to the
 112performance of pxa2xx_spi driver and misconfiguration will result in rx
 113fifo overruns (especially in PIO mode transfers). Good default values are
 114
 115        .tx_threshold = 8,
 116        .rx_threshold = 8,
 117
 118The range is 1 to 16 where zero indicates "use default".
 119
 120The "pxa2xx_spi_chip.dma_burst_size" field is used to configure PXA2xx DMA
 121engine and is related the "spi_device.bits_per_word" field.  Read and understand
 122the PXA2xx "Developer Manual" sections on the DMA controller and SSP Controllers
 123to determine the correct value. An SSP configured for byte-wide transfers would
 124use a value of 8. The driver will determine a reasonable default if
 125dma_burst_size == 0.
 126
 127The "pxa2xx_spi_chip.timeout" fields is used to efficiently handle
 128trailing bytes in the SSP receiver fifo.  The correct value for this field is
 129dependent on the SPI bus speed ("spi_board_info.max_speed_hz") and the specific
 130slave device.  Please note that the PXA2xx SSP 1 does not support trailing byte
 131timeouts and must busy-wait any trailing bytes.
 132
 133The "pxa2xx_spi_chip.enable_loopback" field is used to place the SSP porting
 134into internal loopback mode.  In this mode the SSP controller internally
 135connects the SSPTX pin to the SSPRX pin.  This is useful for initial setup
 136testing.
 137
 138The "pxa2xx_spi_chip.cs_control" field is used to point to a board specific
 139function for asserting/deasserting a slave device chip select.  If the field is
 140NULL, the pxa2xx_spi master controller driver assumes that the SSP port is
 141configured to use SSPFRM instead.
 142
 143NOTE: the SPI driver cannot control the chip select if SSPFRM is used, so the
 144chipselect is dropped after each spi_transfer.  Most devices need chip select
 145asserted around the complete message.  Use SSPFRM as a GPIO (through cs_control)
 146to accomodate these chips.
 147
 148
 149NSSP SLAVE SAMPLE
 150-----------------
 151The pxa2xx_spi_chip structure is passed to the pxa2xx_spi driver in the
 152"spi_board_info.controller_data" field. Below is a sample configuration using
 153the PXA255 NSSP.
 154
 155/* Chip Select control for the CS8415A SPI slave device */
 156static void cs8415a_cs_control(u32 command)
 157{
 158        if (command & PXA2XX_CS_ASSERT)
 159                GPCR(2) = GPIO_bit(2);
 160        else
 161                GPSR(2) = GPIO_bit(2);
 162}
 163
 164/* Chip Select control for the CS8405A SPI slave device */
 165static void cs8405a_cs_control(u32 command)
 166{
 167        if (command & PXA2XX_CS_ASSERT)
 168                GPCR(3) = GPIO_bit(3);
 169        else
 170                GPSR(3) = GPIO_bit(3);
 171}
 172
 173static struct pxa2xx_spi_chip cs8415a_chip_info = {
 174        .tx_threshold = 8, /* SSP hardward FIFO threshold */
 175        .rx_threshold = 8, /* SSP hardward FIFO threshold */
 176        .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
 177        .timeout = 235, /* See Intel documentation */
 178        .cs_control = cs8415a_cs_control, /* Use external chip select */
 179};
 180
 181static struct pxa2xx_spi_chip cs8405a_chip_info = {
 182        .tx_threshold = 8, /* SSP hardward FIFO threshold */
 183        .rx_threshold = 8, /* SSP hardward FIFO threshold */
 184        .dma_burst_size = 8, /* Byte wide transfers used so 8 byte bursts */
 185        .timeout = 235, /* See Intel documentation */
 186        .cs_control = cs8405a_cs_control, /* Use external chip select */
 187};
 188
 189static struct spi_board_info streetracer_spi_board_info[] __initdata = {
 190        {
 191                .modalias = "cs8415a", /* Name of spi_driver for this device */
 192                .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
 193                .bus_num = 2, /* Framework bus number */
 194                .chip_select = 0, /* Framework chip select */
 195                .platform_data = NULL; /* No spi_driver specific config */
 196                .controller_data = &cs8415a_chip_info, /* Master chip config */
 197                .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
 198        },
 199        {
 200                .modalias = "cs8405a", /* Name of spi_driver for this device */
 201                .max_speed_hz = 3686400, /* Run SSP as fast a possbile */
 202                .bus_num = 2, /* Framework bus number */
 203                .chip_select = 1, /* Framework chip select */
 204                .controller_data = &cs8405a_chip_info, /* Master chip config */
 205                .irq = STREETRACER_APCI_IRQ, /* Slave device interrupt */
 206        },
 207};
 208
 209static void __init streetracer_init(void)
 210{
 211        spi_register_board_info(streetracer_spi_board_info,
 212                                ARRAY_SIZE(streetracer_spi_board_info));
 213}
 214
 215
 216DMA and PIO I/O Support
 217-----------------------
 218The pxa2xx_spi driver supports both DMA and interrupt driven PIO message
 219transfers.  The driver defaults to PIO mode and DMA transfers must be enabled
 220by setting the "enable_dma" flag in the "pxa2xx_spi_master" structure.  The DMA
 221mode supports both coherent and stream based DMA mappings.
 222
 223The following logic is used to determine the type of I/O to be used on
 224a per "spi_transfer" basis:
 225
 226if !enable_dma then
 227        always use PIO transfers
 228
 229if spi_message.len > 8191 then
 230        print "rate limited" warning
 231        use PIO transfers
 232
 233if spi_message.is_dma_mapped and rx_dma_buf != 0 and tx_dma_buf != 0 then
 234        use coherent DMA mode
 235
 236if rx_buf and tx_buf are aligned on 8 byte boundary then
 237        use streaming DMA mode
 238
 239otherwise
 240        use PIO transfer
 241
 242THANKS TO
 243---------
 244
 245David Brownell and others for mentoring the development of this driver.
 246
 247