linux/arch/x86/power/cpu_64.c
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   1/*
   2 * Suspend and hibernation support for x86-64
   3 *
   4 * Distribute under GPLv2
   5 *
   6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
   7 * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
   8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
   9 */
  10
  11#include <linux/smp.h>
  12#include <linux/suspend.h>
  13#include <asm/proto.h>
  14#include <asm/page.h>
  15#include <asm/pgtable.h>
  16#include <asm/mtrr.h>
  17#include <asm/xcr.h>
  18
  19static void fix_processor_context(void);
  20
  21struct saved_context saved_context;
  22
  23/**
  24 *      __save_processor_state - save CPU registers before creating a
  25 *              hibernation image and before restoring the memory state from it
  26 *      @ctxt - structure to store the registers contents in
  27 *
  28 *      NOTE: If there is a CPU register the modification of which by the
  29 *      boot kernel (ie. the kernel used for loading the hibernation image)
  30 *      might affect the operations of the restored target kernel (ie. the one
  31 *      saved in the hibernation image), then its contents must be saved by this
  32 *      function.  In other words, if kernel A is hibernated and different
  33 *      kernel B is used for loading the hibernation image into memory, the
  34 *      kernel A's __save_processor_state() function must save all registers
  35 *      needed by kernel A, so that it can operate correctly after the resume
  36 *      regardless of what kernel B does in the meantime.
  37 */
  38static void __save_processor_state(struct saved_context *ctxt)
  39{
  40        kernel_fpu_begin();
  41
  42        /*
  43         * descriptor tables
  44         */
  45        store_gdt((struct desc_ptr *)&ctxt->gdt_limit);
  46        store_idt((struct desc_ptr *)&ctxt->idt_limit);
  47        store_tr(ctxt->tr);
  48
  49        /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
  50        /*
  51         * segment registers
  52         */
  53        asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
  54        asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
  55        asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
  56        asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
  57        asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
  58
  59        rdmsrl(MSR_FS_BASE, ctxt->fs_base);
  60        rdmsrl(MSR_GS_BASE, ctxt->gs_base);
  61        rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
  62        mtrr_save_fixed_ranges(NULL);
  63
  64        /*
  65         * control registers
  66         */
  67        rdmsrl(MSR_EFER, ctxt->efer);
  68        ctxt->cr0 = read_cr0();
  69        ctxt->cr2 = read_cr2();
  70        ctxt->cr3 = read_cr3();
  71        ctxt->cr4 = read_cr4();
  72        ctxt->cr8 = read_cr8();
  73}
  74
  75void save_processor_state(void)
  76{
  77        __save_processor_state(&saved_context);
  78}
  79
  80static void do_fpu_end(void)
  81{
  82        /*
  83         * Restore FPU regs if necessary
  84         */
  85        kernel_fpu_end();
  86}
  87
  88/**
  89 *      __restore_processor_state - restore the contents of CPU registers saved
  90 *              by __save_processor_state()
  91 *      @ctxt - structure to load the registers contents from
  92 */
  93static void __restore_processor_state(struct saved_context *ctxt)
  94{
  95        /*
  96         * control registers
  97         */
  98        wrmsrl(MSR_EFER, ctxt->efer);
  99        write_cr8(ctxt->cr8);
 100        write_cr4(ctxt->cr4);
 101        write_cr3(ctxt->cr3);
 102        write_cr2(ctxt->cr2);
 103        write_cr0(ctxt->cr0);
 104
 105        /*
 106         * now restore the descriptor tables to their proper values
 107         * ltr is done i fix_processor_context().
 108         */
 109        load_gdt((const struct desc_ptr *)&ctxt->gdt_limit);
 110        load_idt((const struct desc_ptr *)&ctxt->idt_limit);
 111
 112
 113        /*
 114         * segment registers
 115         */
 116        asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
 117        asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
 118        asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
 119        load_gs_index(ctxt->gs);
 120        asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
 121
 122        wrmsrl(MSR_FS_BASE, ctxt->fs_base);
 123        wrmsrl(MSR_GS_BASE, ctxt->gs_base);
 124        wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
 125
 126        /*
 127         * restore XCR0 for xsave capable cpu's.
 128         */
 129        if (cpu_has_xsave)
 130                xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask);
 131
 132        fix_processor_context();
 133
 134        do_fpu_end();
 135        mtrr_ap_init();
 136}
 137
 138void restore_processor_state(void)
 139{
 140        __restore_processor_state(&saved_context);
 141}
 142
 143static void fix_processor_context(void)
 144{
 145        int cpu = smp_processor_id();
 146        struct tss_struct *t = &per_cpu(init_tss, cpu);
 147
 148        /*
 149         * This just modifies memory; should not be necessary. But... This
 150         * is necessary, because 386 hardware has concept of busy TSS or some
 151         * similar stupidity.
 152         */
 153        set_tss_desc(cpu, t);
 154
 155        get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9;
 156
 157        syscall_init();                         /* This sets MSR_*STAR and related */
 158        load_TR_desc();                         /* This does ltr */
 159        load_LDT(&current->active_mm->context); /* This does lldt */
 160
 161        /*
 162         * Now maybe reload the debug registers
 163         */
 164        if (current->thread.debugreg7){
 165                loaddebug(&current->thread, 0);
 166                loaddebug(&current->thread, 1);
 167                loaddebug(&current->thread, 2);
 168                loaddebug(&current->thread, 3);
 169                /* no 4 and 5 */
 170                loaddebug(&current->thread, 6);
 171                loaddebug(&current->thread, 7);
 172        }
 173}
 174