linux/drivers/ide/sgiioc4.c
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   1/*
   2 * Copyright (c) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
   3 * Copyright (C) 2008 MontaVista Software, Inc.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License
   7 * as published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it would be useful, but
  10 * WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  12 *
  13 * You should have received a copy of the GNU General Public
  14 * License along with this program; if not, write the Free Software
  15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  16 *
  17 * For further information regarding this notice, see:
  18 *
  19 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
  20 */
  21
  22#include <linux/module.h>
  23#include <linux/types.h>
  24#include <linux/pci.h>
  25#include <linux/delay.h>
  26#include <linux/init.h>
  27#include <linux/kernel.h>
  28#include <linux/ioport.h>
  29#include <linux/blkdev.h>
  30#include <linux/scatterlist.h>
  31#include <linux/ioc4.h>
  32#include <asm/io.h>
  33
  34#include <linux/ide.h>
  35
  36#define DRV_NAME "SGIIOC4"
  37
  38/* IOC4 Specific Definitions */
  39#define IOC4_CMD_OFFSET         0x100
  40#define IOC4_CTRL_OFFSET        0x120
  41#define IOC4_DMA_OFFSET         0x140
  42#define IOC4_INTR_OFFSET        0x0
  43
  44#define IOC4_TIMING             0x00
  45#define IOC4_DMA_PTR_L          0x01
  46#define IOC4_DMA_PTR_H          0x02
  47#define IOC4_DMA_ADDR_L         0x03
  48#define IOC4_DMA_ADDR_H         0x04
  49#define IOC4_BC_DEV             0x05
  50#define IOC4_BC_MEM             0x06
  51#define IOC4_DMA_CTRL           0x07
  52#define IOC4_DMA_END_ADDR       0x08
  53
  54/* Bits in the IOC4 Control/Status Register */
  55#define IOC4_S_DMA_START        0x01
  56#define IOC4_S_DMA_STOP         0x02
  57#define IOC4_S_DMA_DIR          0x04
  58#define IOC4_S_DMA_ACTIVE       0x08
  59#define IOC4_S_DMA_ERROR        0x10
  60#define IOC4_ATA_MEMERR         0x02
  61
  62/* Read/Write Directions */
  63#define IOC4_DMA_WRITE          0x04
  64#define IOC4_DMA_READ           0x00
  65
  66/* Interrupt Register Offsets */
  67#define IOC4_INTR_REG           0x03
  68#define IOC4_INTR_SET           0x05
  69#define IOC4_INTR_CLEAR         0x07
  70
  71#define IOC4_IDE_CACHELINE_SIZE 128
  72#define IOC4_CMD_CTL_BLK_SIZE   0x20
  73#define IOC4_SUPPORTED_FIRMWARE_REV 46
  74
  75typedef struct {
  76        u32 timing_reg0;
  77        u32 timing_reg1;
  78        u32 low_mem_ptr;
  79        u32 high_mem_ptr;
  80        u32 low_mem_addr;
  81        u32 high_mem_addr;
  82        u32 dev_byte_count;
  83        u32 mem_byte_count;
  84        u32 status;
  85} ioc4_dma_regs_t;
  86
  87/* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
  88/* IOC4 has only 1 IDE channel */
  89#define IOC4_PRD_BYTES       16
  90#define IOC4_PRD_ENTRIES     (PAGE_SIZE /(4*IOC4_PRD_BYTES))
  91
  92
  93static void
  94sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
  95                        unsigned long ctrl_port, unsigned long irq_port)
  96{
  97        unsigned long reg = data_port;
  98        int i;
  99
 100        /* Registers are word (32 bit) aligned */
 101        for (i = 0; i <= 7; i++)
 102                hw->io_ports_array[i] = reg + i * 4;
 103
 104        hw->io_ports.ctl_addr = ctrl_port;
 105        hw->io_ports.irq_addr = irq_port;
 106}
 107
 108static int
 109sgiioc4_checkirq(ide_hwif_t * hwif)
 110{
 111        unsigned long intr_addr =
 112                hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
 113
 114        if ((u8)readl((void __iomem *)intr_addr) & 0x03)
 115                return 1;
 116
 117        return 0;
 118}
 119
 120static u8 sgiioc4_read_status(ide_hwif_t *);
 121
 122static int
 123sgiioc4_clearirq(ide_drive_t * drive)
 124{
 125        u32 intr_reg;
 126        ide_hwif_t *hwif = HWIF(drive);
 127        struct ide_io_ports *io_ports = &hwif->io_ports;
 128        unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
 129
 130        /* Code to check for PCI error conditions */
 131        intr_reg = readl((void __iomem *)other_ir);
 132        if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
 133                /*
 134                 * Using sgiioc4_read_status to read the Status register has a
 135                 * side effect of clearing the interrupt.  The first read should
 136                 * clear it if it is set.  The second read should return
 137                 * a "clear" status if it got cleared.  If not, then spin
 138                 * for a bit trying to clear it.
 139                 */
 140                u8 stat = sgiioc4_read_status(hwif);
 141                int count = 0;
 142
 143                stat = sgiioc4_read_status(hwif);
 144                while ((stat & ATA_BUSY) && (count++ < 100)) {
 145                        udelay(1);
 146                        stat = sgiioc4_read_status(hwif);
 147                }
 148
 149                if (intr_reg & 0x02) {
 150                        struct pci_dev *dev = to_pci_dev(hwif->dev);
 151                        /* Error when transferring DMA data on PCI bus */
 152                        u32 pci_err_addr_low, pci_err_addr_high,
 153                            pci_stat_cmd_reg;
 154
 155                        pci_err_addr_low =
 156                                readl((void __iomem *)io_ports->irq_addr);
 157                        pci_err_addr_high =
 158                                readl((void __iomem *)(io_ports->irq_addr + 4));
 159                        pci_read_config_dword(dev, PCI_COMMAND,
 160                                              &pci_stat_cmd_reg);
 161                        printk(KERN_ERR
 162                               "%s(%s) : PCI Bus Error when doing DMA:"
 163                                   " status-cmd reg is 0x%x\n",
 164                               __func__, drive->name, pci_stat_cmd_reg);
 165                        printk(KERN_ERR
 166                               "%s(%s) : PCI Error Address is 0x%x%x\n",
 167                               __func__, drive->name,
 168                               pci_err_addr_high, pci_err_addr_low);
 169                        /* Clear the PCI Error indicator */
 170                        pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
 171                }
 172
 173                /* Clear the Interrupt, Error bits on the IOC4 */
 174                writel(0x03, (void __iomem *)other_ir);
 175
 176                intr_reg = readl((void __iomem *)other_ir);
 177        }
 178
 179        return intr_reg & 3;
 180}
 181
 182static void sgiioc4_dma_start(ide_drive_t *drive)
 183{
 184        ide_hwif_t *hwif = HWIF(drive);
 185        unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
 186        unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
 187        unsigned int temp_reg = reg | IOC4_S_DMA_START;
 188
 189        writel(temp_reg, (void __iomem *)ioc4_dma_addr);
 190}
 191
 192static u32
 193sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
 194{
 195        unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 196        u32     ioc4_dma;
 197        int     count;
 198
 199        count = 0;
 200        ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 201        while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
 202                udelay(1);
 203                ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 204        }
 205        return ioc4_dma;
 206}
 207
 208/* Stops the IOC4 DMA Engine */
 209static int sgiioc4_dma_end(ide_drive_t *drive)
 210{
 211        u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
 212        ide_hwif_t *hwif = HWIF(drive);
 213        unsigned long dma_base = hwif->dma_base;
 214        int dma_stat = 0;
 215        unsigned long *ending_dma = ide_get_hwifdata(hwif);
 216
 217        writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
 218
 219        ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 220
 221        if (ioc4_dma & IOC4_S_DMA_STOP) {
 222                printk(KERN_ERR
 223                       "%s(%s): IOC4 DMA STOP bit is still 1 :"
 224                       "ioc4_dma_reg 0x%x\n",
 225                       __func__, drive->name, ioc4_dma);
 226                dma_stat = 1;
 227        }
 228
 229        /*
 230         * The IOC4 will DMA 1's to the ending dma area to indicate that
 231         * previous data DMA is complete.  This is necessary because of relaxed
 232         * ordering between register reads and DMA writes on the Altix.
 233         */
 234        while ((cnt++ < 200) && (!valid)) {
 235                for (num = 0; num < 16; num++) {
 236                        if (ending_dma[num]) {
 237                                valid = 1;
 238                                break;
 239                        }
 240                }
 241                udelay(1);
 242        }
 243        if (!valid) {
 244                printk(KERN_ERR "%s(%s) : DMA incomplete\n", __func__,
 245                       drive->name);
 246                dma_stat = 1;
 247        }
 248
 249        bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
 250        bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
 251
 252        if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
 253                if (bc_dev > bc_mem + 8) {
 254                        printk(KERN_ERR
 255                               "%s(%s): WARNING!! byte_count_dev %d "
 256                               "!= byte_count_mem %d\n",
 257                               __func__, drive->name, bc_dev, bc_mem);
 258                }
 259        }
 260
 261        drive->waiting_for_dma = 0;
 262        ide_destroy_dmatable(drive);
 263
 264        return dma_stat;
 265}
 266
 267static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
 268{
 269}
 270
 271/* returns 1 if dma irq issued, 0 otherwise */
 272static int sgiioc4_dma_test_irq(ide_drive_t *drive)
 273{
 274        return sgiioc4_checkirq(HWIF(drive));
 275}
 276
 277static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
 278{
 279        if (!on)
 280                sgiioc4_clearirq(drive);
 281}
 282
 283static void
 284sgiioc4_resetproc(ide_drive_t * drive)
 285{
 286        sgiioc4_dma_end(drive);
 287        sgiioc4_clearirq(drive);
 288}
 289
 290static void
 291sgiioc4_dma_lost_irq(ide_drive_t * drive)
 292{
 293        sgiioc4_resetproc(drive);
 294
 295        ide_dma_lost_irq(drive);
 296}
 297
 298static u8 sgiioc4_read_status(ide_hwif_t *hwif)
 299{
 300        unsigned long port = hwif->io_ports.status_addr;
 301        u8 reg = (u8) readb((void __iomem *) port);
 302
 303        if (!(reg & ATA_BUSY)) {        /* Not busy... check for interrupt */
 304                unsigned long other_ir = port - 0x110;
 305                unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
 306
 307                /* Clear the Interrupt, Error bits on the IOC4 */
 308                if (intr_reg & 0x03) {
 309                        writel(0x03, (void __iomem *) other_ir);
 310                        intr_reg = (u32) readl((void __iomem *) other_ir);
 311                }
 312        }
 313
 314        return reg;
 315}
 316
 317/* Creates a dma map for the scatter-gather list entries */
 318static int __devinit
 319ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
 320{
 321        struct pci_dev *dev = to_pci_dev(hwif->dev);
 322        unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
 323        int num_ports = sizeof (ioc4_dma_regs_t);
 324        void *pad;
 325
 326        printk(KERN_INFO "    %s: MMIO-DMA\n", hwif->name);
 327
 328        if (request_mem_region(dma_base, num_ports, hwif->name) == NULL) {
 329                printk(KERN_ERR "%s(%s) -- ERROR: addresses 0x%08lx to 0x%08lx "
 330                       "already in use\n", __func__, hwif->name,
 331                       dma_base, dma_base + num_ports - 1);
 332                return -1;
 333        }
 334
 335        hwif->dma_base = (unsigned long)hwif->io_ports.irq_addr +
 336                         IOC4_DMA_OFFSET;
 337
 338        hwif->sg_max_nents = IOC4_PRD_ENTRIES;
 339
 340        hwif->prd_max_nents = IOC4_PRD_ENTRIES;
 341        hwif->prd_ent_size = IOC4_PRD_BYTES;
 342
 343        if (ide_allocate_dma_engine(hwif))
 344                goto dma_pci_alloc_failure;
 345
 346        pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
 347                                   (dma_addr_t *)&hwif->extra_base);
 348        if (pad) {
 349                ide_set_hwifdata(hwif, pad);
 350                return 0;
 351        }
 352
 353        ide_release_dma_engine(hwif);
 354
 355        printk(KERN_ERR "%s(%s) -- ERROR: Unable to allocate DMA maps\n",
 356               __func__, hwif->name);
 357        printk(KERN_INFO "%s: changing from DMA to PIO mode", hwif->name);
 358
 359dma_pci_alloc_failure:
 360        release_mem_region(dma_base, num_ports);
 361
 362        return -1;
 363}
 364
 365/* Initializes the IOC4 DMA Engine */
 366static void
 367sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
 368{
 369        u32 ioc4_dma;
 370        ide_hwif_t *hwif = HWIF(drive);
 371        unsigned long dma_base = hwif->dma_base;
 372        unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 373        u32 dma_addr, ending_dma_addr;
 374
 375        ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 376
 377        if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
 378                printk(KERN_WARNING
 379                        "%s(%s):Warning!! DMA from previous transfer was still active\n",
 380                       __func__, drive->name);
 381                writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 382                ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 383
 384                if (ioc4_dma & IOC4_S_DMA_STOP)
 385                        printk(KERN_ERR
 386                               "%s(%s) : IOC4 Dma STOP bit is still 1\n",
 387                               __func__, drive->name);
 388        }
 389
 390        ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 391        if (ioc4_dma & IOC4_S_DMA_ERROR) {
 392                printk(KERN_WARNING
 393                       "%s(%s) : Warning!! - DMA Error during Previous"
 394                       " transfer | status 0x%x\n",
 395                       __func__, drive->name, ioc4_dma);
 396                writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 397                ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 398
 399                if (ioc4_dma & IOC4_S_DMA_STOP)
 400                        printk(KERN_ERR
 401                               "%s(%s) : IOC4 DMA STOP bit is still 1\n",
 402                               __func__, drive->name);
 403        }
 404
 405        /* Address of the Scatter Gather List */
 406        dma_addr = cpu_to_le32(hwif->dmatable_dma);
 407        writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
 408
 409        /* Address of the Ending DMA */
 410        memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
 411        ending_dma_addr = cpu_to_le32(hwif->extra_base);
 412        writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
 413
 414        writel(dma_direction, (void __iomem *)ioc4_dma_addr);
 415        drive->waiting_for_dma = 1;
 416}
 417
 418/* IOC4 Scatter Gather list Format                                       */
 419/* 128 Bit entries to support 64 bit addresses in the future             */
 420/* The Scatter Gather list Entry should be in the BIG-ENDIAN Format      */
 421/* --------------------------------------------------------------------- */
 422/* | Upper 32 bits - Zero           |           Lower 32 bits- address | */
 423/* --------------------------------------------------------------------- */
 424/* | Upper 32 bits - Zero           |EOL| 15 unused     | 16 Bit Length| */
 425/* --------------------------------------------------------------------- */
 426/* Creates the scatter gather list, DMA Table */
 427static unsigned int
 428sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
 429{
 430        ide_hwif_t *hwif = HWIF(drive);
 431        unsigned int *table = hwif->dmatable_cpu;
 432        unsigned int count = 0, i = 1;
 433        struct scatterlist *sg;
 434
 435        hwif->sg_nents = i = ide_build_sglist(drive, rq);
 436
 437        if (!i)
 438                return 0;       /* sglist of length Zero */
 439
 440        sg = hwif->sg_table;
 441        while (i && sg_dma_len(sg)) {
 442                dma_addr_t cur_addr;
 443                int cur_len;
 444                cur_addr = sg_dma_address(sg);
 445                cur_len = sg_dma_len(sg);
 446
 447                while (cur_len) {
 448                        if (count++ >= IOC4_PRD_ENTRIES) {
 449                                printk(KERN_WARNING
 450                                       "%s: DMA table too small\n",
 451                                       drive->name);
 452                                goto use_pio_instead;
 453                        } else {
 454                                u32 bcount =
 455                                    0x10000 - (cur_addr & 0xffff);
 456
 457                                if (bcount > cur_len)
 458                                        bcount = cur_len;
 459
 460                                /* put the addr, length in
 461                                 * the IOC4 dma-table format */
 462                                *table = 0x0;
 463                                table++;
 464                                *table = cpu_to_be32(cur_addr);
 465                                table++;
 466                                *table = 0x0;
 467                                table++;
 468
 469                                *table = cpu_to_be32(bcount);
 470                                table++;
 471
 472                                cur_addr += bcount;
 473                                cur_len -= bcount;
 474                        }
 475                }
 476
 477                sg = sg_next(sg);
 478                i--;
 479        }
 480
 481        if (count) {
 482                table--;
 483                *table |= cpu_to_be32(0x80000000);
 484                return count;
 485        }
 486
 487use_pio_instead:
 488        ide_destroy_dmatable(drive);
 489
 490        return 0;               /* revert to PIO for this request */
 491}
 492
 493static int sgiioc4_dma_setup(ide_drive_t *drive)
 494{
 495        struct request *rq = HWGROUP(drive)->rq;
 496        unsigned int count = 0;
 497        int ddir;
 498
 499        if (rq_data_dir(rq))
 500                ddir = PCI_DMA_TODEVICE;
 501        else
 502                ddir = PCI_DMA_FROMDEVICE;
 503
 504        if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
 505                /* try PIO instead of DMA */
 506                ide_map_sg(drive, rq);
 507                return 1;
 508        }
 509
 510        if (rq_data_dir(rq))
 511                /* Writes TO the IOC4 FROM Main Memory */
 512                ddir = IOC4_DMA_READ;
 513        else
 514                /* Writes FROM the IOC4 TO Main Memory */
 515                ddir = IOC4_DMA_WRITE;
 516
 517        sgiioc4_configure_for_dma(ddir, drive);
 518
 519        return 0;
 520}
 521
 522static const struct ide_tp_ops sgiioc4_tp_ops = {
 523        .exec_command           = ide_exec_command,
 524        .read_status            = sgiioc4_read_status,
 525        .read_altstatus         = ide_read_altstatus,
 526        .read_sff_dma_status    = ide_read_sff_dma_status,
 527
 528        .set_irq                = ide_set_irq,
 529
 530        .tf_load                = ide_tf_load,
 531        .tf_read                = ide_tf_read,
 532
 533        .input_data             = ide_input_data,
 534        .output_data            = ide_output_data,
 535};
 536
 537static const struct ide_port_ops sgiioc4_port_ops = {
 538        .set_dma_mode           = sgiioc4_set_dma_mode,
 539        /* reset DMA engine, clear IRQs */
 540        .resetproc              = sgiioc4_resetproc,
 541};
 542
 543static const struct ide_dma_ops sgiioc4_dma_ops = {
 544        .dma_host_set           = sgiioc4_dma_host_set,
 545        .dma_setup              = sgiioc4_dma_setup,
 546        .dma_start              = sgiioc4_dma_start,
 547        .dma_end                = sgiioc4_dma_end,
 548        .dma_test_irq           = sgiioc4_dma_test_irq,
 549        .dma_lost_irq           = sgiioc4_dma_lost_irq,
 550        .dma_timeout            = ide_dma_timeout,
 551};
 552
 553static const struct ide_port_info sgiioc4_port_info __devinitconst = {
 554        .name                   = DRV_NAME,
 555        .chipset                = ide_pci,
 556        .init_dma               = ide_dma_sgiioc4,
 557        .tp_ops                 = &sgiioc4_tp_ops,
 558        .port_ops               = &sgiioc4_port_ops,
 559        .dma_ops                = &sgiioc4_dma_ops,
 560        .host_flags             = IDE_HFLAG_MMIO,
 561        .mwdma_mask             = ATA_MWDMA2_ONLY,
 562};
 563
 564static int __devinit
 565sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
 566{
 567        unsigned long cmd_base, irqport;
 568        unsigned long bar0, cmd_phys_base, ctl;
 569        void __iomem *virt_base;
 570        hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 571        int rc;
 572
 573        /*  Get the CmdBlk and CtrlBlk Base Registers */
 574        bar0 = pci_resource_start(dev, 0);
 575        virt_base = pci_ioremap_bar(dev, 0);
 576        if (virt_base == NULL) {
 577                printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
 578                                DRV_NAME, bar0);
 579                return -ENOMEM;
 580        }
 581        cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
 582        ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
 583        irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
 584
 585        cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
 586        if (request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
 587                               DRV_NAME) == NULL) {
 588                printk(KERN_ERR "%s %s -- ERROR: addresses 0x%08lx to 0x%08lx "
 589                       "already in use\n", DRV_NAME, pci_name(dev),
 590                       cmd_phys_base, cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
 591                rc = -EBUSY;
 592                goto req_mem_rgn_err;
 593        }
 594
 595        /* Initialize the IO registers */
 596        memset(&hw, 0, sizeof(hw));
 597        sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
 598        hw.irq = dev->irq;
 599        hw.chipset = ide_pci;
 600        hw.dev = &dev->dev;
 601
 602        /* Initializing chipset IRQ Registers */
 603        writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
 604
 605        rc = ide_host_add(&sgiioc4_port_info, hws, NULL);
 606        if (!rc)
 607                return 0;
 608
 609        release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE);
 610req_mem_rgn_err:
 611        iounmap(virt_base);
 612        return rc;
 613}
 614
 615static unsigned int __devinit
 616pci_init_sgiioc4(struct pci_dev *dev)
 617{
 618        int ret;
 619
 620        printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
 621                         DRV_NAME, pci_name(dev), dev->revision);
 622
 623        if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
 624                printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
 625                                "firmware is obsolete - please upgrade to "
 626                                "revision46 or higher\n",
 627                                DRV_NAME, pci_name(dev));
 628                ret = -EAGAIN;
 629                goto out;
 630        }
 631        ret = sgiioc4_ide_setup_pci_device(dev);
 632out:
 633        return ret;
 634}
 635
 636int __devinit
 637ioc4_ide_attach_one(struct ioc4_driver_data *idd)
 638{
 639        /* PCI-RT does not bring out IDE connection.
 640         * Do not attach to this particular IOC4.
 641         */
 642        if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
 643                return 0;
 644
 645        return pci_init_sgiioc4(idd->idd_pdev);
 646}
 647
 648static struct ioc4_submodule __devinitdata ioc4_ide_submodule = {
 649        .is_name = "IOC4_ide",
 650        .is_owner = THIS_MODULE,
 651        .is_probe = ioc4_ide_attach_one,
 652/*      .is_remove = ioc4_ide_remove_one,       */
 653};
 654
 655static int __init ioc4_ide_init(void)
 656{
 657        return ioc4_register_submodule(&ioc4_ide_submodule);
 658}
 659
 660late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
 661
 662MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
 663MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
 664MODULE_LICENSE("GPL");
 665