linux/drivers/spi/spi_mpc83xx.c
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   1/*
   2 * MPC83xx SPI controller driver.
   3 *
   4 * Maintainer: Kumar Gala
   5 *
   6 * Copyright (C) 2006 Polycom, Inc.
   7 *
   8 * This program is free software; you can redistribute  it and/or modify it
   9 * under  the terms of  the GNU General  Public License as published by the
  10 * Free Software Foundation;  either version 2 of the  License, or (at your
  11 * option) any later version.
  12 */
  13#include <linux/module.h>
  14#include <linux/init.h>
  15#include <linux/types.h>
  16#include <linux/kernel.h>
  17#include <linux/completion.h>
  18#include <linux/interrupt.h>
  19#include <linux/delay.h>
  20#include <linux/irq.h>
  21#include <linux/device.h>
  22#include <linux/spi/spi.h>
  23#include <linux/spi/spi_bitbang.h>
  24#include <linux/platform_device.h>
  25#include <linux/fsl_devices.h>
  26
  27#include <asm/irq.h>
  28#include <asm/io.h>
  29
  30/* SPI Controller registers */
  31struct mpc83xx_spi_reg {
  32        u8 res1[0x20];
  33        __be32 mode;
  34        __be32 event;
  35        __be32 mask;
  36        __be32 command;
  37        __be32 transmit;
  38        __be32 receive;
  39};
  40
  41/* SPI Controller mode register definitions */
  42#define SPMODE_LOOP             (1 << 30)
  43#define SPMODE_CI_INACTIVEHIGH  (1 << 29)
  44#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
  45#define SPMODE_DIV16            (1 << 27)
  46#define SPMODE_REV              (1 << 26)
  47#define SPMODE_MS               (1 << 25)
  48#define SPMODE_ENABLE           (1 << 24)
  49#define SPMODE_LEN(x)           ((x) << 20)
  50#define SPMODE_PM(x)            ((x) << 16)
  51#define SPMODE_OP               (1 << 14)
  52#define SPMODE_CG(x)            ((x) << 7)
  53
  54/*
  55 * Default for SPI Mode:
  56 *      SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
  57 */
  58#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
  59                         SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
  60
  61/* SPIE register values */
  62#define SPIE_NE         0x00000200      /* Not empty */
  63#define SPIE_NF         0x00000100      /* Not full */
  64
  65/* SPIM register values */
  66#define SPIM_NE         0x00000200      /* Not empty */
  67#define SPIM_NF         0x00000100      /* Not full */
  68
  69/* SPI Controller driver's private data. */
  70struct mpc83xx_spi {
  71        struct mpc83xx_spi_reg __iomem *base;
  72
  73        /* rx & tx bufs from the spi_transfer */
  74        const void *tx;
  75        void *rx;
  76
  77        /* functions to deal with different sized buffers */
  78        void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
  79        u32(*get_tx) (struct mpc83xx_spi *);
  80
  81        unsigned int count;
  82        int irq;
  83
  84        unsigned nsecs;         /* (clock cycle time)/2 */
  85
  86        u32 spibrg;             /* SPIBRG input clock */
  87        u32 rx_shift;           /* RX data reg shift when in qe mode */
  88        u32 tx_shift;           /* TX data reg shift when in qe mode */
  89
  90        bool qe_mode;
  91
  92        void (*activate_cs) (u8 cs, u8 polarity);
  93        void (*deactivate_cs) (u8 cs, u8 polarity);
  94
  95        u8 busy;
  96
  97        struct workqueue_struct *workqueue;
  98        struct work_struct work;
  99
 100        struct list_head queue;
 101        spinlock_t lock;
 102
 103        struct completion done;
 104};
 105
 106struct spi_mpc83xx_cs {
 107        /* functions to deal with different sized buffers */
 108        void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
 109        u32 (*get_tx) (struct mpc83xx_spi *);
 110        u32 rx_shift;           /* RX data reg shift when in qe mode */
 111        u32 tx_shift;           /* TX data reg shift when in qe mode */
 112        u32 hw_mode;            /* Holds HW mode register settings */
 113};
 114
 115static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
 116{
 117        out_be32(reg, val);
 118}
 119
 120static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
 121{
 122        return in_be32(reg);
 123}
 124
 125#define MPC83XX_SPI_RX_BUF(type)                                          \
 126void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
 127{                                                                         \
 128        type * rx = mpc83xx_spi->rx;                                      \
 129        *rx++ = (type)(data >> mpc83xx_spi->rx_shift);                    \
 130        mpc83xx_spi->rx = rx;                                             \
 131}
 132
 133#define MPC83XX_SPI_TX_BUF(type)                                \
 134u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)  \
 135{                                                               \
 136        u32 data;                                               \
 137        const type * tx = mpc83xx_spi->tx;                      \
 138        if (!tx)                                                \
 139                return 0;                                       \
 140        data = *tx++ << mpc83xx_spi->tx_shift;                  \
 141        mpc83xx_spi->tx = tx;                                   \
 142        return data;                                            \
 143}
 144
 145MPC83XX_SPI_RX_BUF(u8)
 146MPC83XX_SPI_RX_BUF(u16)
 147MPC83XX_SPI_RX_BUF(u32)
 148MPC83XX_SPI_TX_BUF(u8)
 149MPC83XX_SPI_TX_BUF(u16)
 150MPC83XX_SPI_TX_BUF(u32)
 151
 152static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
 153{
 154        struct mpc83xx_spi *mpc83xx_spi;
 155        u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 156        struct spi_mpc83xx_cs   *cs = spi->controller_state;
 157
 158        mpc83xx_spi = spi_master_get_devdata(spi->master);
 159
 160        if (value == BITBANG_CS_INACTIVE) {
 161                if (mpc83xx_spi->deactivate_cs)
 162                        mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
 163        }
 164
 165        if (value == BITBANG_CS_ACTIVE) {
 166                u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 167
 168                mpc83xx_spi->rx_shift = cs->rx_shift;
 169                mpc83xx_spi->tx_shift = cs->tx_shift;
 170                mpc83xx_spi->get_rx = cs->get_rx;
 171                mpc83xx_spi->get_tx = cs->get_tx;
 172
 173                if (cs->hw_mode != regval) {
 174                        unsigned long flags;
 175                        void *tmp_ptr = &mpc83xx_spi->base->mode;
 176
 177                        regval = cs->hw_mode;
 178                        /* Turn off IRQs locally to minimize time that
 179                         * SPI is disabled
 180                         */
 181                        local_irq_save(flags);
 182                        /* Turn off SPI unit prior changing mode */
 183                        mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
 184                        mpc83xx_spi_write_reg(tmp_ptr, regval);
 185                        local_irq_restore(flags);
 186                }
 187                if (mpc83xx_spi->activate_cs)
 188                        mpc83xx_spi->activate_cs(spi->chip_select, pol);
 189        }
 190}
 191
 192static
 193int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 194{
 195        struct mpc83xx_spi *mpc83xx_spi;
 196        u32 regval;
 197        u8 bits_per_word, pm;
 198        u32 hz;
 199        struct spi_mpc83xx_cs   *cs = spi->controller_state;
 200
 201        mpc83xx_spi = spi_master_get_devdata(spi->master);
 202
 203        if (t) {
 204                bits_per_word = t->bits_per_word;
 205                hz = t->speed_hz;
 206        } else {
 207                bits_per_word = 0;
 208                hz = 0;
 209        }
 210
 211        /* spi_transfer level calls that work per-word */
 212        if (!bits_per_word)
 213                bits_per_word = spi->bits_per_word;
 214
 215        /* Make sure its a bit width we support [4..16, 32] */
 216        if ((bits_per_word < 4)
 217            || ((bits_per_word > 16) && (bits_per_word != 32)))
 218                return -EINVAL;
 219
 220        if (!hz)
 221                hz = spi->max_speed_hz;
 222
 223        cs->rx_shift = 0;
 224        cs->tx_shift = 0;
 225        if (bits_per_word <= 8) {
 226                cs->get_rx = mpc83xx_spi_rx_buf_u8;
 227                cs->get_tx = mpc83xx_spi_tx_buf_u8;
 228                if (mpc83xx_spi->qe_mode) {
 229                        cs->rx_shift = 16;
 230                        cs->tx_shift = 24;
 231                }
 232        } else if (bits_per_word <= 16) {
 233                cs->get_rx = mpc83xx_spi_rx_buf_u16;
 234                cs->get_tx = mpc83xx_spi_tx_buf_u16;
 235                if (mpc83xx_spi->qe_mode) {
 236                        cs->rx_shift = 16;
 237                        cs->tx_shift = 16;
 238                }
 239        } else if (bits_per_word <= 32) {
 240                cs->get_rx = mpc83xx_spi_rx_buf_u32;
 241                cs->get_tx = mpc83xx_spi_tx_buf_u32;
 242        } else
 243                return -EINVAL;
 244
 245        if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
 246                cs->tx_shift = 0;
 247                if (bits_per_word <= 8)
 248                        cs->rx_shift = 8;
 249                else
 250                        cs->rx_shift = 0;
 251        }
 252
 253        mpc83xx_spi->rx_shift = cs->rx_shift;
 254        mpc83xx_spi->tx_shift = cs->tx_shift;
 255        mpc83xx_spi->get_rx = cs->get_rx;
 256        mpc83xx_spi->get_tx = cs->get_tx;
 257
 258        if (bits_per_word == 32)
 259                bits_per_word = 0;
 260        else
 261                bits_per_word = bits_per_word - 1;
 262
 263        /* mask out bits we are going to set */
 264        cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
 265                                  | SPMODE_PM(0xF));
 266
 267        cs->hw_mode |= SPMODE_LEN(bits_per_word);
 268
 269        if ((mpc83xx_spi->spibrg / hz) > 64) {
 270                cs->hw_mode |= SPMODE_DIV16;
 271                pm = mpc83xx_spi->spibrg / (hz * 64);
 272                if (pm > 16) {
 273                        dev_err(&spi->dev, "Requested speed is too "
 274                                "low: %d Hz. Will use %d Hz instead.\n",
 275                                hz, mpc83xx_spi->spibrg / 1024);
 276                        pm = 16;
 277                }
 278        } else
 279                pm = mpc83xx_spi->spibrg / (hz * 4);
 280        if (pm)
 281                pm--;
 282
 283        cs->hw_mode |= SPMODE_PM(pm);
 284        regval =  mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 285        if (cs->hw_mode != regval) {
 286                unsigned long flags;
 287                void *tmp_ptr = &mpc83xx_spi->base->mode;
 288
 289                regval = cs->hw_mode;
 290                /* Turn off IRQs locally to minimize time
 291                 * that SPI is disabled
 292                 */
 293                local_irq_save(flags);
 294                /* Turn off SPI unit prior changing mode */
 295                mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
 296                mpc83xx_spi_write_reg(tmp_ptr, regval);
 297                local_irq_restore(flags);
 298        }
 299        return 0;
 300}
 301
 302static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
 303{
 304        struct mpc83xx_spi *mpc83xx_spi;
 305        u32 word, len, bits_per_word;
 306
 307        mpc83xx_spi = spi_master_get_devdata(spi->master);
 308
 309        mpc83xx_spi->tx = t->tx_buf;
 310        mpc83xx_spi->rx = t->rx_buf;
 311        bits_per_word = spi->bits_per_word;
 312        if (t->bits_per_word)
 313                bits_per_word = t->bits_per_word;
 314        len = t->len;
 315        if (bits_per_word > 8) {
 316                /* invalid length? */
 317                if (len & 1)
 318                        return -EINVAL;
 319                len /= 2;
 320        }
 321        if (bits_per_word > 16) {
 322                /* invalid length? */
 323                if (len & 1)
 324                        return -EINVAL;
 325                len /= 2;
 326        }
 327        mpc83xx_spi->count = len;
 328
 329        INIT_COMPLETION(mpc83xx_spi->done);
 330
 331        /* enable rx ints */
 332        mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
 333
 334        /* transmit word */
 335        word = mpc83xx_spi->get_tx(mpc83xx_spi);
 336        mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 337
 338        wait_for_completion(&mpc83xx_spi->done);
 339
 340        /* disable rx ints */
 341        mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 342
 343        return mpc83xx_spi->count;
 344}
 345
 346static void mpc83xx_spi_work(struct work_struct *work)
 347{
 348        struct mpc83xx_spi *mpc83xx_spi =
 349                container_of(work, struct mpc83xx_spi, work);
 350
 351        spin_lock_irq(&mpc83xx_spi->lock);
 352        mpc83xx_spi->busy = 1;
 353        while (!list_empty(&mpc83xx_spi->queue)) {
 354                struct spi_message *m;
 355                struct spi_device *spi;
 356                struct spi_transfer *t = NULL;
 357                unsigned cs_change;
 358                int status, nsecs = 50;
 359
 360                m = container_of(mpc83xx_spi->queue.next,
 361                                struct spi_message, queue);
 362                list_del_init(&m->queue);
 363                spin_unlock_irq(&mpc83xx_spi->lock);
 364
 365                spi = m->spi;
 366                cs_change = 1;
 367                status = 0;
 368                list_for_each_entry(t, &m->transfers, transfer_list) {
 369                        if (t->bits_per_word || t->speed_hz) {
 370                                /* Don't allow changes if CS is active */
 371                                status = -EINVAL;
 372
 373                                if (cs_change)
 374                                        status = mpc83xx_spi_setup_transfer(spi, t);
 375                                if (status < 0)
 376                                        break;
 377                        }
 378
 379                        if (cs_change)
 380                                mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
 381                        cs_change = t->cs_change;
 382                        if (t->len)
 383                                status = mpc83xx_spi_bufs(spi, t);
 384                        if (status) {
 385                                status = -EMSGSIZE;
 386                                break;
 387                        }
 388                        m->actual_length += t->len;
 389
 390                        if (t->delay_usecs)
 391                                udelay(t->delay_usecs);
 392
 393                        if (cs_change) {
 394                                ndelay(nsecs);
 395                                mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 396                                ndelay(nsecs);
 397                        }
 398                }
 399
 400                m->status = status;
 401                m->complete(m->context);
 402
 403                if (status || !cs_change) {
 404                        ndelay(nsecs);
 405                        mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 406                }
 407
 408                mpc83xx_spi_setup_transfer(spi, NULL);
 409
 410                spin_lock_irq(&mpc83xx_spi->lock);
 411        }
 412        mpc83xx_spi->busy = 0;
 413        spin_unlock_irq(&mpc83xx_spi->lock);
 414}
 415
 416/* the spi->mode bits understood by this driver: */
 417#define MODEBITS        (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
 418                        | SPI_LSB_FIRST | SPI_LOOP)
 419
 420static int mpc83xx_spi_setup(struct spi_device *spi)
 421{
 422        struct mpc83xx_spi *mpc83xx_spi;
 423        int retval;
 424        u32 hw_mode;
 425        struct spi_mpc83xx_cs   *cs = spi->controller_state;
 426
 427        if (spi->mode & ~MODEBITS) {
 428                dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 429                        spi->mode & ~MODEBITS);
 430                return -EINVAL;
 431        }
 432
 433        if (!spi->max_speed_hz)
 434                return -EINVAL;
 435
 436        if (!cs) {
 437                cs = kzalloc(sizeof *cs, GFP_KERNEL);
 438                if (!cs)
 439                        return -ENOMEM;
 440                spi->controller_state = cs;
 441        }
 442        mpc83xx_spi = spi_master_get_devdata(spi->master);
 443
 444        if (!spi->bits_per_word)
 445                spi->bits_per_word = 8;
 446
 447        hw_mode = cs->hw_mode; /* Save orginal settings */
 448        cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
 449        /* mask out bits we are going to set */
 450        cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
 451                         | SPMODE_REV | SPMODE_LOOP);
 452
 453        if (spi->mode & SPI_CPHA)
 454                cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
 455        if (spi->mode & SPI_CPOL)
 456                cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
 457        if (!(spi->mode & SPI_LSB_FIRST))
 458                cs->hw_mode |= SPMODE_REV;
 459        if (spi->mode & SPI_LOOP)
 460                cs->hw_mode |= SPMODE_LOOP;
 461
 462        retval = mpc83xx_spi_setup_transfer(spi, NULL);
 463        if (retval < 0) {
 464                cs->hw_mode = hw_mode; /* Restore settings */
 465                return retval;
 466        }
 467
 468        dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
 469                __func__, spi->mode & (SPI_CPOL | SPI_CPHA),
 470                spi->bits_per_word, spi->max_speed_hz);
 471#if 0 /* Don't think this is needed */
 472        /* NOTE we _need_ to call chipselect() early, ideally with adapter
 473         * setup, unless the hardware defaults cooperate to avoid confusion
 474         * between normal (active low) and inverted chipselects.
 475         */
 476
 477        /* deselect chip (low or high) */
 478        spin_lock(&mpc83xx_spi->lock);
 479        if (!mpc83xx_spi->busy)
 480                mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
 481        spin_unlock(&mpc83xx_spi->lock);
 482#endif
 483        return 0;
 484}
 485
 486irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
 487{
 488        struct mpc83xx_spi *mpc83xx_spi = context_data;
 489        u32 event;
 490        irqreturn_t ret = IRQ_NONE;
 491
 492        /* Get interrupt events(tx/rx) */
 493        event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
 494
 495        /* We need handle RX first */
 496        if (event & SPIE_NE) {
 497                u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
 498
 499                if (mpc83xx_spi->rx)
 500                        mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
 501
 502                ret = IRQ_HANDLED;
 503        }
 504
 505        if ((event & SPIE_NF) == 0)
 506                /* spin until TX is done */
 507                while (((event =
 508                         mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
 509                                                SPIE_NF) == 0)
 510                         cpu_relax();
 511
 512        mpc83xx_spi->count -= 1;
 513        if (mpc83xx_spi->count) {
 514                u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
 515                mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
 516        } else {
 517                complete(&mpc83xx_spi->done);
 518        }
 519
 520        /* Clear the events */
 521        mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
 522
 523        return ret;
 524}
 525static int mpc83xx_spi_transfer(struct spi_device *spi,
 526                                struct spi_message *m)
 527{
 528        struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
 529        unsigned long flags;
 530
 531        m->actual_length = 0;
 532        m->status = -EINPROGRESS;
 533
 534        spin_lock_irqsave(&mpc83xx_spi->lock, flags);
 535        list_add_tail(&m->queue, &mpc83xx_spi->queue);
 536        queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
 537        spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
 538
 539        return 0;
 540}
 541
 542
 543static void mpc83xx_spi_cleanup(struct spi_device *spi)
 544{
 545        kfree(spi->controller_state);
 546}
 547
 548static int __init mpc83xx_spi_probe(struct platform_device *dev)
 549{
 550        struct spi_master *master;
 551        struct mpc83xx_spi *mpc83xx_spi;
 552        struct fsl_spi_platform_data *pdata;
 553        struct resource *r;
 554        u32 regval;
 555        int ret = 0;
 556
 557        /* Get resources(memory, IRQ) associated with the device */
 558        master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
 559
 560        if (master == NULL) {
 561                ret = -ENOMEM;
 562                goto err;
 563        }
 564
 565        platform_set_drvdata(dev, master);
 566        pdata = dev->dev.platform_data;
 567
 568        if (pdata == NULL) {
 569                ret = -ENODEV;
 570                goto free_master;
 571        }
 572
 573        r = platform_get_resource(dev, IORESOURCE_MEM, 0);
 574        if (r == NULL) {
 575                ret = -ENODEV;
 576                goto free_master;
 577        }
 578        master->setup = mpc83xx_spi_setup;
 579        master->transfer = mpc83xx_spi_transfer;
 580        master->cleanup = mpc83xx_spi_cleanup;
 581
 582        mpc83xx_spi = spi_master_get_devdata(master);
 583        mpc83xx_spi->activate_cs = pdata->activate_cs;
 584        mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
 585        mpc83xx_spi->qe_mode = pdata->qe_mode;
 586        mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
 587        mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
 588        mpc83xx_spi->spibrg = pdata->sysclk;
 589
 590        mpc83xx_spi->rx_shift = 0;
 591        mpc83xx_spi->tx_shift = 0;
 592        if (mpc83xx_spi->qe_mode) {
 593                mpc83xx_spi->rx_shift = 16;
 594                mpc83xx_spi->tx_shift = 24;
 595        }
 596
 597        init_completion(&mpc83xx_spi->done);
 598
 599        mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
 600        if (mpc83xx_spi->base == NULL) {
 601                ret = -ENOMEM;
 602                goto put_master;
 603        }
 604
 605        mpc83xx_spi->irq = platform_get_irq(dev, 0);
 606
 607        if (mpc83xx_spi->irq < 0) {
 608                ret = -ENXIO;
 609                goto unmap_io;
 610        }
 611
 612        /* Register for SPI Interrupt */
 613        ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
 614                          0, "mpc83xx_spi", mpc83xx_spi);
 615
 616        if (ret != 0)
 617                goto unmap_io;
 618
 619        master->bus_num = pdata->bus_num;
 620        master->num_chipselect = pdata->max_chipselect;
 621
 622        /* SPI controller initializations */
 623        mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
 624        mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
 625        mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
 626        mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
 627
 628        /* Enable SPI interface */
 629        regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 630        if (pdata->qe_mode)
 631                regval |= SPMODE_OP;
 632
 633        mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
 634        spin_lock_init(&mpc83xx_spi->lock);
 635        init_completion(&mpc83xx_spi->done);
 636        INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
 637        INIT_LIST_HEAD(&mpc83xx_spi->queue);
 638
 639        mpc83xx_spi->workqueue = create_singlethread_workqueue(
 640                master->dev.parent->bus_id);
 641        if (mpc83xx_spi->workqueue == NULL) {
 642                ret = -EBUSY;
 643                goto free_irq;
 644        }
 645
 646        ret = spi_register_master(master);
 647        if (ret < 0)
 648                goto unreg_master;
 649
 650        printk(KERN_INFO
 651               "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
 652               dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
 653
 654        return ret;
 655
 656unreg_master:
 657        destroy_workqueue(mpc83xx_spi->workqueue);
 658free_irq:
 659        free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 660unmap_io:
 661        iounmap(mpc83xx_spi->base);
 662put_master:
 663        spi_master_put(master);
 664free_master:
 665        kfree(master);
 666err:
 667        return ret;
 668}
 669
 670static int __exit mpc83xx_spi_remove(struct platform_device *dev)
 671{
 672        struct mpc83xx_spi *mpc83xx_spi;
 673        struct spi_master *master;
 674
 675        master = platform_get_drvdata(dev);
 676        mpc83xx_spi = spi_master_get_devdata(master);
 677
 678        flush_workqueue(mpc83xx_spi->workqueue);
 679        destroy_workqueue(mpc83xx_spi->workqueue);
 680        spi_unregister_master(master);
 681
 682        free_irq(mpc83xx_spi->irq, mpc83xx_spi);
 683        iounmap(mpc83xx_spi->base);
 684
 685        return 0;
 686}
 687
 688MODULE_ALIAS("platform:mpc83xx_spi");
 689static struct platform_driver mpc83xx_spi_driver = {
 690        .remove = __exit_p(mpc83xx_spi_remove),
 691        .driver = {
 692                .name = "mpc83xx_spi",
 693                .owner = THIS_MODULE,
 694        },
 695};
 696
 697static int __init mpc83xx_spi_init(void)
 698{
 699        return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
 700}
 701
 702static void __exit mpc83xx_spi_exit(void)
 703{
 704        platform_driver_unregister(&mpc83xx_spi_driver);
 705}
 706
 707module_init(mpc83xx_spi_init);
 708module_exit(mpc83xx_spi_exit);
 709
 710MODULE_AUTHOR("Kumar Gala");
 711MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
 712MODULE_LICENSE("GPL");
 713