linux/drivers/spi/mpc52xx_psc_spi.c
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   1/*
   2 * MPC52xx PSC in SPI mode driver.
   3 *
   4 * Maintainer: Dragos Carp
   5 *
   6 * Copyright (C) 2006 TOPTICA Photonics AG.
   7 *
   8 * This program is free software; you can redistribute  it and/or modify it
   9 * under  the terms of  the GNU General  Public License as published by the
  10 * Free Software Foundation;  either version 2 of the  License, or (at your
  11 * option) any later version.
  12 */
  13
  14#include <linux/module.h>
  15#include <linux/init.h>
  16#include <linux/errno.h>
  17#include <linux/interrupt.h>
  18#include <linux/of_platform.h>
  19#include <linux/workqueue.h>
  20#include <linux/completion.h>
  21#include <linux/io.h>
  22#include <linux/delay.h>
  23#include <linux/spi/spi.h>
  24#include <linux/fsl_devices.h>
  25
  26#include <asm/mpc52xx.h>
  27#include <asm/mpc52xx_psc.h>
  28
  29#define MCLK 20000000 /* PSC port MClk in hz */
  30
  31struct mpc52xx_psc_spi {
  32        /* fsl_spi_platform data */
  33        void (*activate_cs)(u8, u8);
  34        void (*deactivate_cs)(u8, u8);
  35        u32 sysclk;
  36
  37        /* driver internal data */
  38        struct mpc52xx_psc __iomem *psc;
  39        struct mpc52xx_psc_fifo __iomem *fifo;
  40        unsigned int irq;
  41        u8 bits_per_word;
  42        u8 busy;
  43
  44        struct workqueue_struct *workqueue;
  45        struct work_struct work;
  46
  47        struct list_head queue;
  48        spinlock_t lock;
  49
  50        struct completion done;
  51};
  52
  53/* controller state */
  54struct mpc52xx_psc_spi_cs {
  55        int bits_per_word;
  56        int speed_hz;
  57};
  58
  59/* set clock freq, clock ramp, bits per work
  60 * if t is NULL then reset the values to the default values
  61 */
  62static int mpc52xx_psc_spi_transfer_setup(struct spi_device *spi,
  63                struct spi_transfer *t)
  64{
  65        struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  66
  67        cs->speed_hz = (t && t->speed_hz)
  68                        ? t->speed_hz : spi->max_speed_hz;
  69        cs->bits_per_word = (t && t->bits_per_word)
  70                        ? t->bits_per_word : spi->bits_per_word;
  71        cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  72        return 0;
  73}
  74
  75static void mpc52xx_psc_spi_activate_cs(struct spi_device *spi)
  76{
  77        struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
  78        struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
  79        struct mpc52xx_psc __iomem *psc = mps->psc;
  80        u32 sicr;
  81        u16 ccr;
  82
  83        sicr = in_be32(&psc->sicr);
  84
  85        /* Set clock phase and polarity */
  86        if (spi->mode & SPI_CPHA)
  87                sicr |= 0x00001000;
  88        else
  89                sicr &= ~0x00001000;
  90        if (spi->mode & SPI_CPOL)
  91                sicr |= 0x00002000;
  92        else
  93                sicr &= ~0x00002000;
  94
  95        if (spi->mode & SPI_LSB_FIRST)
  96                sicr |= 0x10000000;
  97        else
  98                sicr &= ~0x10000000;
  99        out_be32(&psc->sicr, sicr);
 100
 101        /* Set clock frequency and bits per word
 102         * Because psc->ccr is defined as 16bit register instead of 32bit
 103         * just set the lower byte of BitClkDiv
 104         */
 105        ccr = in_be16((u16 __iomem *)&psc->ccr);
 106        ccr &= 0xFF00;
 107        if (cs->speed_hz)
 108                ccr |= (MCLK / cs->speed_hz - 1) & 0xFF;
 109        else /* by default SPI Clk 1MHz */
 110                ccr |= (MCLK / 1000000 - 1) & 0xFF;
 111        out_be16((u16 __iomem *)&psc->ccr, ccr);
 112        mps->bits_per_word = cs->bits_per_word;
 113
 114        if (mps->activate_cs)
 115                mps->activate_cs(spi->chip_select,
 116                                (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 117}
 118
 119static void mpc52xx_psc_spi_deactivate_cs(struct spi_device *spi)
 120{
 121        struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 122
 123        if (mps->deactivate_cs)
 124                mps->deactivate_cs(spi->chip_select,
 125                                (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 126}
 127
 128#define MPC52xx_PSC_BUFSIZE (MPC52xx_PSC_RFNUM_MASK + 1)
 129/* wake up when 80% fifo full */
 130#define MPC52xx_PSC_RFALARM (MPC52xx_PSC_BUFSIZE * 20 / 100)
 131
 132static int mpc52xx_psc_spi_transfer_rxtx(struct spi_device *spi,
 133                                                struct spi_transfer *t)
 134{
 135        struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 136        struct mpc52xx_psc __iomem *psc = mps->psc;
 137        struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 138        unsigned rb = 0;        /* number of bytes receieved */
 139        unsigned sb = 0;        /* number of bytes sent */
 140        unsigned char *rx_buf = (unsigned char *)t->rx_buf;
 141        unsigned char *tx_buf = (unsigned char *)t->tx_buf;
 142        unsigned rfalarm;
 143        unsigned send_at_once = MPC52xx_PSC_BUFSIZE;
 144        unsigned recv_at_once;
 145        int last_block = 0;
 146
 147        if (!t->tx_buf && !t->rx_buf && t->len)
 148                return -EINVAL;
 149
 150        /* enable transmiter/receiver */
 151        out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 152        while (rb < t->len) {
 153                if (t->len - rb > MPC52xx_PSC_BUFSIZE) {
 154                        rfalarm = MPC52xx_PSC_RFALARM;
 155                        last_block = 0;
 156                } else {
 157                        send_at_once = t->len - sb;
 158                        rfalarm = MPC52xx_PSC_BUFSIZE - (t->len - rb);
 159                        last_block = 1;
 160                }
 161
 162                dev_dbg(&spi->dev, "send %d bytes...\n", send_at_once);
 163                for (; send_at_once; sb++, send_at_once--) {
 164                        /* set EOF flag before the last word is sent */
 165                        if (send_at_once == 1 && last_block)
 166                                out_8(&psc->ircr2, 0x01);
 167
 168                        if (tx_buf)
 169                                out_8(&psc->mpc52xx_psc_buffer_8, tx_buf[sb]);
 170                        else
 171                                out_8(&psc->mpc52xx_psc_buffer_8, 0);
 172                }
 173
 174
 175                /* enable interrupts and wait for wake up
 176                 * if just one byte is expected the Rx FIFO genererates no
 177                 * FFULL interrupt, so activate the RxRDY interrupt
 178                 */
 179                out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 180                if (t->len - rb == 1) {
 181                        out_8(&psc->mode, 0);
 182                } else {
 183                        out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 184                        out_be16(&fifo->rfalarm, rfalarm);
 185                }
 186                out_be16(&psc->mpc52xx_psc_imr, MPC52xx_PSC_IMR_RXRDY);
 187                wait_for_completion(&mps->done);
 188                recv_at_once = in_be16(&fifo->rfnum);
 189                dev_dbg(&spi->dev, "%d bytes received\n", recv_at_once);
 190
 191                send_at_once = recv_at_once;
 192                if (rx_buf) {
 193                        for (; recv_at_once; rb++, recv_at_once--)
 194                                rx_buf[rb] = in_8(&psc->mpc52xx_psc_buffer_8);
 195                } else {
 196                        for (; recv_at_once; rb++, recv_at_once--)
 197                                in_8(&psc->mpc52xx_psc_buffer_8);
 198                }
 199        }
 200        /* disable transmiter/receiver */
 201        out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 202
 203        return 0;
 204}
 205
 206static void mpc52xx_psc_spi_work(struct work_struct *work)
 207{
 208        struct mpc52xx_psc_spi *mps =
 209                container_of(work, struct mpc52xx_psc_spi, work);
 210
 211        spin_lock_irq(&mps->lock);
 212        mps->busy = 1;
 213        while (!list_empty(&mps->queue)) {
 214                struct spi_message *m;
 215                struct spi_device *spi;
 216                struct spi_transfer *t = NULL;
 217                unsigned cs_change;
 218                int status;
 219
 220                m = container_of(mps->queue.next, struct spi_message, queue);
 221                list_del_init(&m->queue);
 222                spin_unlock_irq(&mps->lock);
 223
 224                spi = m->spi;
 225                cs_change = 1;
 226                status = 0;
 227                list_for_each_entry (t, &m->transfers, transfer_list) {
 228                        if (t->bits_per_word || t->speed_hz) {
 229                                status = mpc52xx_psc_spi_transfer_setup(spi, t);
 230                                if (status < 0)
 231                                        break;
 232                        }
 233
 234                        if (cs_change)
 235                                mpc52xx_psc_spi_activate_cs(spi);
 236                        cs_change = t->cs_change;
 237
 238                        status = mpc52xx_psc_spi_transfer_rxtx(spi, t);
 239                        if (status)
 240                                break;
 241                        m->actual_length += t->len;
 242
 243                        if (t->delay_usecs)
 244                                udelay(t->delay_usecs);
 245
 246                        if (cs_change)
 247                                mpc52xx_psc_spi_deactivate_cs(spi);
 248                }
 249
 250                m->status = status;
 251                m->complete(m->context);
 252
 253                if (status || !cs_change)
 254                        mpc52xx_psc_spi_deactivate_cs(spi);
 255
 256                mpc52xx_psc_spi_transfer_setup(spi, NULL);
 257
 258                spin_lock_irq(&mps->lock);
 259        }
 260        mps->busy = 0;
 261        spin_unlock_irq(&mps->lock);
 262}
 263
 264/* the spi->mode bits understood by this driver: */
 265#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
 266
 267static int mpc52xx_psc_spi_setup(struct spi_device *spi)
 268{
 269        struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 270        struct mpc52xx_psc_spi_cs *cs = spi->controller_state;
 271        unsigned long flags;
 272
 273        if (spi->bits_per_word%8)
 274                return -EINVAL;
 275
 276        if (spi->mode & ~MODEBITS) {
 277                dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 278                        spi->mode & ~MODEBITS);
 279                return -EINVAL;
 280        }
 281
 282        if (!cs) {
 283                cs = kzalloc(sizeof *cs, GFP_KERNEL);
 284                if (!cs)
 285                        return -ENOMEM;
 286                spi->controller_state = cs;
 287        }
 288
 289        cs->bits_per_word = spi->bits_per_word;
 290        cs->speed_hz = spi->max_speed_hz;
 291
 292        spin_lock_irqsave(&mps->lock, flags);
 293        if (!mps->busy)
 294                mpc52xx_psc_spi_deactivate_cs(spi);
 295        spin_unlock_irqrestore(&mps->lock, flags);
 296
 297        return 0;
 298}
 299
 300static int mpc52xx_psc_spi_transfer(struct spi_device *spi,
 301                struct spi_message *m)
 302{
 303        struct mpc52xx_psc_spi *mps = spi_master_get_devdata(spi->master);
 304        unsigned long flags;
 305
 306        m->actual_length = 0;
 307        m->status = -EINPROGRESS;
 308
 309        spin_lock_irqsave(&mps->lock, flags);
 310        list_add_tail(&m->queue, &mps->queue);
 311        queue_work(mps->workqueue, &mps->work);
 312        spin_unlock_irqrestore(&mps->lock, flags);
 313
 314        return 0;
 315}
 316
 317static void mpc52xx_psc_spi_cleanup(struct spi_device *spi)
 318{
 319        kfree(spi->controller_state);
 320}
 321
 322static int mpc52xx_psc_spi_port_config(int psc_id, struct mpc52xx_psc_spi *mps)
 323{
 324        struct mpc52xx_psc __iomem *psc = mps->psc;
 325        struct mpc52xx_psc_fifo __iomem *fifo = mps->fifo;
 326        u32 mclken_div;
 327        int ret = 0;
 328
 329        /* default sysclk is 512MHz */
 330        mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK;
 331        mpc52xx_set_psc_clkdiv(psc_id, mclken_div);
 332
 333        /* Reset the PSC into a known state */
 334        out_8(&psc->command, MPC52xx_PSC_RST_RX);
 335        out_8(&psc->command, MPC52xx_PSC_RST_TX);
 336        out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 337
 338        /* Disable interrupts, interrupts are based on alarm level */
 339        out_be16(&psc->mpc52xx_psc_imr, 0);
 340        out_8(&psc->command, MPC52xx_PSC_SEL_MODE_REG_1);
 341        out_8(&fifo->rfcntl, 0);
 342        out_8(&psc->mode, MPC52xx_PSC_MODE_FFULL);
 343
 344        /* Configure 8bit codec mode as a SPI master and use EOF flags */
 345        /* SICR_SIM_CODEC8|SICR_GENCLK|SICR_SPI|SICR_MSTR|SICR_USEEOF */
 346        out_be32(&psc->sicr, 0x0180C800);
 347        out_be16((u16 __iomem *)&psc->ccr, 0x070F); /* default SPI Clk 1MHz */
 348
 349        /* Set 2ms DTL delay */
 350        out_8(&psc->ctur, 0x00);
 351        out_8(&psc->ctlr, 0x84);
 352
 353        mps->bits_per_word = 8;
 354
 355        return ret;
 356}
 357
 358static irqreturn_t mpc52xx_psc_spi_isr(int irq, void *dev_id)
 359{
 360        struct mpc52xx_psc_spi *mps = (struct mpc52xx_psc_spi *)dev_id;
 361        struct mpc52xx_psc __iomem *psc = mps->psc;
 362
 363        /* disable interrupt and wake up the work queue */
 364        if (in_be16(&psc->mpc52xx_psc_isr) & MPC52xx_PSC_IMR_RXRDY) {
 365                out_be16(&psc->mpc52xx_psc_imr, 0);
 366                complete(&mps->done);
 367                return IRQ_HANDLED;
 368        }
 369        return IRQ_NONE;
 370}
 371
 372/* bus_num is used only for the case dev->platform_data == NULL */
 373static int __init mpc52xx_psc_spi_do_probe(struct device *dev, u32 regaddr,
 374                                u32 size, unsigned int irq, s16 bus_num)
 375{
 376        struct fsl_spi_platform_data *pdata = dev->platform_data;
 377        struct mpc52xx_psc_spi *mps;
 378        struct spi_master *master;
 379        int ret;
 380
 381        master = spi_alloc_master(dev, sizeof *mps);
 382        if (master == NULL)
 383                return -ENOMEM;
 384
 385        dev_set_drvdata(dev, master);
 386        mps = spi_master_get_devdata(master);
 387
 388        mps->irq = irq;
 389        if (pdata == NULL) {
 390                dev_warn(dev, "probe called without platform data, no "
 391                                "(de)activate_cs function will be called\n");
 392                mps->activate_cs = NULL;
 393                mps->deactivate_cs = NULL;
 394                mps->sysclk = 0;
 395                master->bus_num = bus_num;
 396                master->num_chipselect = 255;
 397        } else {
 398                mps->activate_cs = pdata->activate_cs;
 399                mps->deactivate_cs = pdata->deactivate_cs;
 400                mps->sysclk = pdata->sysclk;
 401                master->bus_num = pdata->bus_num;
 402                master->num_chipselect = pdata->max_chipselect;
 403        }
 404        master->setup = mpc52xx_psc_spi_setup;
 405        master->transfer = mpc52xx_psc_spi_transfer;
 406        master->cleanup = mpc52xx_psc_spi_cleanup;
 407
 408        mps->psc = ioremap(regaddr, size);
 409        if (!mps->psc) {
 410                dev_err(dev, "could not ioremap I/O port range\n");
 411                ret = -EFAULT;
 412                goto free_master;
 413        }
 414        /* On the 5200, fifo regs are immediately ajacent to the psc regs */
 415        mps->fifo = ((void __iomem *)mps->psc) + sizeof(struct mpc52xx_psc);
 416
 417        ret = request_irq(mps->irq, mpc52xx_psc_spi_isr, 0, "mpc52xx-psc-spi",
 418                                mps);
 419        if (ret)
 420                goto free_master;
 421
 422        ret = mpc52xx_psc_spi_port_config(master->bus_num, mps);
 423        if (ret < 0)
 424                goto free_irq;
 425
 426        spin_lock_init(&mps->lock);
 427        init_completion(&mps->done);
 428        INIT_WORK(&mps->work, mpc52xx_psc_spi_work);
 429        INIT_LIST_HEAD(&mps->queue);
 430
 431        mps->workqueue = create_singlethread_workqueue(
 432                master->dev.parent->bus_id);
 433        if (mps->workqueue == NULL) {
 434                ret = -EBUSY;
 435                goto free_irq;
 436        }
 437
 438        ret = spi_register_master(master);
 439        if (ret < 0)
 440                goto unreg_master;
 441
 442        return ret;
 443
 444unreg_master:
 445        destroy_workqueue(mps->workqueue);
 446free_irq:
 447        free_irq(mps->irq, mps);
 448free_master:
 449        if (mps->psc)
 450                iounmap(mps->psc);
 451        spi_master_put(master);
 452
 453        return ret;
 454}
 455
 456static int __exit mpc52xx_psc_spi_do_remove(struct device *dev)
 457{
 458        struct spi_master *master = dev_get_drvdata(dev);
 459        struct mpc52xx_psc_spi *mps = spi_master_get_devdata(master);
 460
 461        flush_workqueue(mps->workqueue);
 462        destroy_workqueue(mps->workqueue);
 463        spi_unregister_master(master);
 464        free_irq(mps->irq, mps);
 465        if (mps->psc)
 466                iounmap(mps->psc);
 467
 468        return 0;
 469}
 470
 471static int __init mpc52xx_psc_spi_of_probe(struct of_device *op,
 472        const struct of_device_id *match)
 473{
 474        const u32 *regaddr_p;
 475        u64 regaddr64, size64;
 476        s16 id = -1;
 477
 478        regaddr_p = of_get_address(op->node, 0, &size64, NULL);
 479        if (!regaddr_p) {
 480                printk(KERN_ERR "Invalid PSC address\n");
 481                return -EINVAL;
 482        }
 483        regaddr64 = of_translate_address(op->node, regaddr_p);
 484
 485        /* get PSC id (1..6, used by port_config) */
 486        if (op->dev.platform_data == NULL) {
 487                const u32 *psc_nump;
 488
 489                psc_nump = of_get_property(op->node, "cell-index", NULL);
 490                if (!psc_nump || *psc_nump > 5) {
 491                        printk(KERN_ERR "mpc52xx_psc_spi: Device node %s has invalid "
 492                                        "cell-index property\n", op->node->full_name);
 493                        return -EINVAL;
 494                }
 495                id = *psc_nump + 1;
 496        }
 497
 498        return mpc52xx_psc_spi_do_probe(&op->dev, (u32)regaddr64, (u32)size64,
 499                                        irq_of_parse_and_map(op->node, 0), id);
 500}
 501
 502static int __exit mpc52xx_psc_spi_of_remove(struct of_device *op)
 503{
 504        return mpc52xx_psc_spi_do_remove(&op->dev);
 505}
 506
 507static struct of_device_id mpc52xx_psc_spi_of_match[] = {
 508        { .compatible = "fsl,mpc5200-psc-spi", },
 509        { .compatible = "mpc5200-psc-spi", }, /* old */
 510        {}
 511};
 512
 513MODULE_DEVICE_TABLE(of, mpc52xx_psc_spi_of_match);
 514
 515static struct of_platform_driver mpc52xx_psc_spi_of_driver = {
 516        .owner = THIS_MODULE,
 517        .name = "mpc52xx-psc-spi",
 518        .match_table = mpc52xx_psc_spi_of_match,
 519        .probe = mpc52xx_psc_spi_of_probe,
 520        .remove = __exit_p(mpc52xx_psc_spi_of_remove),
 521        .driver = {
 522                .name = "mpc52xx-psc-spi",
 523                .owner = THIS_MODULE,
 524        },
 525};
 526
 527static int __init mpc52xx_psc_spi_init(void)
 528{
 529        return of_register_platform_driver(&mpc52xx_psc_spi_of_driver);
 530}
 531module_init(mpc52xx_psc_spi_init);
 532
 533static void __exit mpc52xx_psc_spi_exit(void)
 534{
 535        of_unregister_platform_driver(&mpc52xx_psc_spi_of_driver);
 536}
 537module_exit(mpc52xx_psc_spi_exit);
 538
 539MODULE_AUTHOR("Dragos Carp");
 540MODULE_DESCRIPTION("MPC52xx PSC SPI Driver");
 541MODULE_LICENSE("GPL");
 542