linux/include/asm-x86/mach-bigsmp/mach_apic.h
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   1#ifndef __ASM_MACH_APIC_H
   2#define __ASM_MACH_APIC_H
   3
   4#define xapic_phys_to_log_apicid(cpu) (per_cpu(x86_bios_cpu_apicid, cpu))
   5#define esr_disable (1)
   6
   7static inline int apic_id_registered(void)
   8{
   9        return (1);
  10}
  11
  12/* Round robin the irqs amoung the online cpus */
  13static inline cpumask_t target_cpus(void)
  14{ 
  15        static unsigned long cpu = NR_CPUS;
  16        do {
  17                if (cpu >= NR_CPUS)
  18                        cpu = first_cpu(cpu_online_map);
  19                else
  20                        cpu = next_cpu(cpu, cpu_online_map);
  21        } while (cpu >= NR_CPUS);
  22        return cpumask_of_cpu(cpu);
  23}
  24
  25#undef APIC_DEST_LOGICAL
  26#define APIC_DEST_LOGICAL       0
  27#define TARGET_CPUS             (target_cpus())
  28#define APIC_DFR_VALUE          (APIC_DFR_FLAT)
  29#define INT_DELIVERY_MODE       (dest_Fixed)
  30#define INT_DEST_MODE           (0)    /* phys delivery to target proc */
  31#define NO_BALANCE_IRQ          (0)
  32#define WAKE_SECONDARY_VIA_INIT
  33
  34
  35static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  36{
  37        return (0);
  38}
  39
  40static inline unsigned long check_apicid_present(int bit)
  41{
  42        return (1);
  43}
  44
  45static inline unsigned long calculate_ldr(int cpu)
  46{
  47        unsigned long val, id;
  48        val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  49        id = xapic_phys_to_log_apicid(cpu);
  50        val |= SET_APIC_LOGICAL_ID(id);
  51        return val;
  52}
  53
  54/*
  55 * Set up the logical destination ID.
  56 *
  57 * Intel recommends to set DFR, LDR and TPR before enabling
  58 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
  59 * document number 292116).  So here it goes...
  60 */
  61static inline void init_apic_ldr(void)
  62{
  63        unsigned long val;
  64        int cpu = smp_processor_id();
  65
  66        apic_write(APIC_DFR, APIC_DFR_VALUE);
  67        val = calculate_ldr(cpu);
  68        apic_write(APIC_LDR, val);
  69}
  70
  71static inline void setup_apic_routing(void)
  72{
  73        printk("Enabling APIC mode:  %s.  Using %d I/O APICs\n",
  74                "Physflat", nr_ioapics);
  75}
  76
  77static inline int multi_timer_check(int apic, int irq)
  78{
  79        return (0);
  80}
  81
  82static inline int apicid_to_node(int logical_apicid)
  83{
  84        return apicid_2_node[hard_smp_processor_id()];
  85}
  86
  87static inline int cpu_present_to_apicid(int mps_cpu)
  88{
  89        if (mps_cpu < NR_CPUS)
  90                return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
  91
  92        return BAD_APICID;
  93}
  94
  95static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
  96{
  97        return physid_mask_of_physid(phys_apicid);
  98}
  99
 100extern u8 cpu_2_logical_apicid[];
 101/* Mapping from cpu number to logical apicid */
 102static inline int cpu_to_logical_apicid(int cpu)
 103{
 104        if (cpu >= NR_CPUS)
 105                return BAD_APICID;
 106        return cpu_physical_id(cpu);
 107}
 108
 109static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
 110{
 111        /* For clustered we don't have a good way to do this yet - hack */
 112        return physids_promote(0xFFL);
 113}
 114
 115static inline void setup_portio_remap(void)
 116{
 117}
 118
 119static inline void enable_apic_mode(void)
 120{
 121}
 122
 123static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 124{
 125        return (1);
 126}
 127
 128/* As we are using single CPU as destination, pick only one CPU here */
 129static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
 130{
 131        int cpu;
 132        int apicid;     
 133
 134        cpu = first_cpu(cpumask);
 135        apicid = cpu_to_logical_apicid(cpu);
 136        return apicid;
 137}
 138
 139static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 140{
 141        return cpuid_apic >> index_msb;
 142}
 143
 144#endif /* __ASM_MACH_APIC_H */
 145