linux/arch/x86/kvm/svm.c
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   1/*
   2 * Kernel-based Virtual Machine driver for Linux
   3 *
   4 * AMD SVM support
   5 *
   6 * Copyright (C) 2006 Qumranet, Inc.
   7 *
   8 * Authors:
   9 *   Yaniv Kamay  <yaniv@qumranet.com>
  10 *   Avi Kivity   <avi@qumranet.com>
  11 *
  12 * This work is licensed under the terms of the GNU GPL, version 2.  See
  13 * the COPYING file in the top-level directory.
  14 *
  15 */
  16#include <linux/kvm_host.h>
  17
  18#include "kvm_svm.h"
  19#include "irq.h"
  20#include "mmu.h"
  21
  22#include <linux/module.h>
  23#include <linux/kernel.h>
  24#include <linux/vmalloc.h>
  25#include <linux/highmem.h>
  26#include <linux/sched.h>
  27
  28#include <asm/desc.h>
  29
  30#define __ex(x) __kvm_handle_fault_on_reboot(x)
  31
  32MODULE_AUTHOR("Qumranet");
  33MODULE_LICENSE("GPL");
  34
  35#define IOPM_ALLOC_ORDER 2
  36#define MSRPM_ALLOC_ORDER 1
  37
  38#define DB_VECTOR 1
  39#define UD_VECTOR 6
  40#define GP_VECTOR 13
  41
  42#define DR7_GD_MASK (1 << 13)
  43#define DR6_BD_MASK (1 << 13)
  44
  45#define SEG_TYPE_LDT 2
  46#define SEG_TYPE_BUSY_TSS16 3
  47
  48#define SVM_FEATURE_NPT  (1 << 0)
  49#define SVM_FEATURE_LBRV (1 << 1)
  50#define SVM_DEATURE_SVML (1 << 2)
  51
  52#define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  53
  54/* enable NPT for AMD64 and X86 with PAE */
  55#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  56static bool npt_enabled = true;
  57#else
  58static bool npt_enabled = false;
  59#endif
  60static int npt = 1;
  61
  62module_param(npt, int, S_IRUGO);
  63
  64static void kvm_reput_irq(struct vcpu_svm *svm);
  65static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  66
  67static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  68{
  69        return container_of(vcpu, struct vcpu_svm, vcpu);
  70}
  71
  72static unsigned long iopm_base;
  73
  74struct kvm_ldttss_desc {
  75        u16 limit0;
  76        u16 base0;
  77        unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  78        unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  79        u32 base3;
  80        u32 zero1;
  81} __attribute__((packed));
  82
  83struct svm_cpu_data {
  84        int cpu;
  85
  86        u64 asid_generation;
  87        u32 max_asid;
  88        u32 next_asid;
  89        struct kvm_ldttss_desc *tss_desc;
  90
  91        struct page *save_area;
  92};
  93
  94static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  95static uint32_t svm_features;
  96
  97struct svm_init_data {
  98        int cpu;
  99        int r;
 100};
 101
 102static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 103
 104#define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 105#define MSRS_RANGE_SIZE 2048
 106#define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 107
 108#define MAX_INST_SIZE 15
 109
 110static inline u32 svm_has(u32 feat)
 111{
 112        return svm_features & feat;
 113}
 114
 115static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 116{
 117        int word_index = __ffs(vcpu->arch.irq_summary);
 118        int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
 119        int irq = word_index * BITS_PER_LONG + bit_index;
 120
 121        clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
 122        if (!vcpu->arch.irq_pending[word_index])
 123                clear_bit(word_index, &vcpu->arch.irq_summary);
 124        return irq;
 125}
 126
 127static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 128{
 129        set_bit(irq, vcpu->arch.irq_pending);
 130        set_bit(irq / BITS_PER_LONG, &vcpu->arch.irq_summary);
 131}
 132
 133static inline void clgi(void)
 134{
 135        asm volatile (__ex(SVM_CLGI));
 136}
 137
 138static inline void stgi(void)
 139{
 140        asm volatile (__ex(SVM_STGI));
 141}
 142
 143static inline void invlpga(unsigned long addr, u32 asid)
 144{
 145        asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 146}
 147
 148static inline unsigned long kvm_read_cr2(void)
 149{
 150        unsigned long cr2;
 151
 152        asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 153        return cr2;
 154}
 155
 156static inline void kvm_write_cr2(unsigned long val)
 157{
 158        asm volatile ("mov %0, %%cr2" :: "r" (val));
 159}
 160
 161static inline unsigned long read_dr6(void)
 162{
 163        unsigned long dr6;
 164
 165        asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 166        return dr6;
 167}
 168
 169static inline void write_dr6(unsigned long val)
 170{
 171        asm volatile ("mov %0, %%dr6" :: "r" (val));
 172}
 173
 174static inline unsigned long read_dr7(void)
 175{
 176        unsigned long dr7;
 177
 178        asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 179        return dr7;
 180}
 181
 182static inline void write_dr7(unsigned long val)
 183{
 184        asm volatile ("mov %0, %%dr7" :: "r" (val));
 185}
 186
 187static inline void force_new_asid(struct kvm_vcpu *vcpu)
 188{
 189        to_svm(vcpu)->asid_generation--;
 190}
 191
 192static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 193{
 194        force_new_asid(vcpu);
 195}
 196
 197static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 198{
 199        if (!npt_enabled && !(efer & EFER_LMA))
 200                efer &= ~EFER_LME;
 201
 202        to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 203        vcpu->arch.shadow_efer = efer;
 204}
 205
 206static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 207                                bool has_error_code, u32 error_code)
 208{
 209        struct vcpu_svm *svm = to_svm(vcpu);
 210
 211        svm->vmcb->control.event_inj = nr
 212                | SVM_EVTINJ_VALID
 213                | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 214                | SVM_EVTINJ_TYPE_EXEPT;
 215        svm->vmcb->control.event_inj_err = error_code;
 216}
 217
 218static bool svm_exception_injected(struct kvm_vcpu *vcpu)
 219{
 220        struct vcpu_svm *svm = to_svm(vcpu);
 221
 222        return !(svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID);
 223}
 224
 225static int is_external_interrupt(u32 info)
 226{
 227        info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 228        return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 229}
 230
 231static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 232{
 233        struct vcpu_svm *svm = to_svm(vcpu);
 234
 235        if (!svm->next_rip) {
 236                printk(KERN_DEBUG "%s: NOP\n", __func__);
 237                return;
 238        }
 239        if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE)
 240                printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 241                       __func__,
 242                       svm->vmcb->save.rip,
 243                       svm->next_rip);
 244
 245        vcpu->arch.rip = svm->vmcb->save.rip = svm->next_rip;
 246        svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 247
 248        vcpu->arch.interrupt_window_open = 1;
 249}
 250
 251static int has_svm(void)
 252{
 253        uint32_t eax, ebx, ecx, edx;
 254
 255        if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 256                printk(KERN_INFO "has_svm: not amd\n");
 257                return 0;
 258        }
 259
 260        cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 261        if (eax < SVM_CPUID_FUNC) {
 262                printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 263                return 0;
 264        }
 265
 266        cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 267        if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 268                printk(KERN_DEBUG "has_svm: svm not available\n");
 269                return 0;
 270        }
 271        return 1;
 272}
 273
 274static void svm_hardware_disable(void *garbage)
 275{
 276        uint64_t efer;
 277
 278        wrmsrl(MSR_VM_HSAVE_PA, 0);
 279        rdmsrl(MSR_EFER, efer);
 280        wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 281}
 282
 283static void svm_hardware_enable(void *garbage)
 284{
 285
 286        struct svm_cpu_data *svm_data;
 287        uint64_t efer;
 288        struct desc_ptr gdt_descr;
 289        struct desc_struct *gdt;
 290        int me = raw_smp_processor_id();
 291
 292        if (!has_svm()) {
 293                printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 294                return;
 295        }
 296        svm_data = per_cpu(svm_data, me);
 297
 298        if (!svm_data) {
 299                printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 300                       me);
 301                return;
 302        }
 303
 304        svm_data->asid_generation = 1;
 305        svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 306        svm_data->next_asid = svm_data->max_asid + 1;
 307
 308        asm volatile ("sgdt %0" : "=m"(gdt_descr));
 309        gdt = (struct desc_struct *)gdt_descr.address;
 310        svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 311
 312        rdmsrl(MSR_EFER, efer);
 313        wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 314
 315        wrmsrl(MSR_VM_HSAVE_PA,
 316               page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 317}
 318
 319static void svm_cpu_uninit(int cpu)
 320{
 321        struct svm_cpu_data *svm_data
 322                = per_cpu(svm_data, raw_smp_processor_id());
 323
 324        if (!svm_data)
 325                return;
 326
 327        per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 328        __free_page(svm_data->save_area);
 329        kfree(svm_data);
 330}
 331
 332static int svm_cpu_init(int cpu)
 333{
 334        struct svm_cpu_data *svm_data;
 335        int r;
 336
 337        svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 338        if (!svm_data)
 339                return -ENOMEM;
 340        svm_data->cpu = cpu;
 341        svm_data->save_area = alloc_page(GFP_KERNEL);
 342        r = -ENOMEM;
 343        if (!svm_data->save_area)
 344                goto err_1;
 345
 346        per_cpu(svm_data, cpu) = svm_data;
 347
 348        return 0;
 349
 350err_1:
 351        kfree(svm_data);
 352        return r;
 353
 354}
 355
 356static void set_msr_interception(u32 *msrpm, unsigned msr,
 357                                 int read, int write)
 358{
 359        int i;
 360
 361        for (i = 0; i < NUM_MSR_MAPS; i++) {
 362                if (msr >= msrpm_ranges[i] &&
 363                    msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 364                        u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 365                                          msrpm_ranges[i]) * 2;
 366
 367                        u32 *base = msrpm + (msr_offset / 32);
 368                        u32 msr_shift = msr_offset % 32;
 369                        u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 370                        *base = (*base & ~(0x3 << msr_shift)) |
 371                                (mask << msr_shift);
 372                        return;
 373                }
 374        }
 375        BUG();
 376}
 377
 378static void svm_vcpu_init_msrpm(u32 *msrpm)
 379{
 380        memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 381
 382#ifdef CONFIG_X86_64
 383        set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 384        set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 385        set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 386        set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 387        set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 388        set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 389#endif
 390        set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 391        set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 392        set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 393        set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 394}
 395
 396static void svm_enable_lbrv(struct vcpu_svm *svm)
 397{
 398        u32 *msrpm = svm->msrpm;
 399
 400        svm->vmcb->control.lbr_ctl = 1;
 401        set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 402        set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 403        set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 404        set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 405}
 406
 407static void svm_disable_lbrv(struct vcpu_svm *svm)
 408{
 409        u32 *msrpm = svm->msrpm;
 410
 411        svm->vmcb->control.lbr_ctl = 0;
 412        set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 413        set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 414        set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 415        set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 416}
 417
 418static __init int svm_hardware_setup(void)
 419{
 420        int cpu;
 421        struct page *iopm_pages;
 422        void *iopm_va;
 423        int r;
 424
 425        iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 426
 427        if (!iopm_pages)
 428                return -ENOMEM;
 429
 430        iopm_va = page_address(iopm_pages);
 431        memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 432        iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 433
 434        if (boot_cpu_has(X86_FEATURE_NX))
 435                kvm_enable_efer_bits(EFER_NX);
 436
 437        for_each_online_cpu(cpu) {
 438                r = svm_cpu_init(cpu);
 439                if (r)
 440                        goto err;
 441        }
 442
 443        svm_features = cpuid_edx(SVM_CPUID_FUNC);
 444
 445        if (!svm_has(SVM_FEATURE_NPT))
 446                npt_enabled = false;
 447
 448        if (npt_enabled && !npt) {
 449                printk(KERN_INFO "kvm: Nested Paging disabled\n");
 450                npt_enabled = false;
 451        }
 452
 453        if (npt_enabled) {
 454                printk(KERN_INFO "kvm: Nested Paging enabled\n");
 455                kvm_enable_tdp();
 456        } else
 457                kvm_disable_tdp();
 458
 459        return 0;
 460
 461err:
 462        __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 463        iopm_base = 0;
 464        return r;
 465}
 466
 467static __exit void svm_hardware_unsetup(void)
 468{
 469        int cpu;
 470
 471        for_each_online_cpu(cpu)
 472                svm_cpu_uninit(cpu);
 473
 474        __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 475        iopm_base = 0;
 476}
 477
 478static void init_seg(struct vmcb_seg *seg)
 479{
 480        seg->selector = 0;
 481        seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 482                SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 483        seg->limit = 0xffff;
 484        seg->base = 0;
 485}
 486
 487static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 488{
 489        seg->selector = 0;
 490        seg->attrib = SVM_SELECTOR_P_MASK | type;
 491        seg->limit = 0xffff;
 492        seg->base = 0;
 493}
 494
 495static void init_vmcb(struct vcpu_svm *svm)
 496{
 497        struct vmcb_control_area *control = &svm->vmcb->control;
 498        struct vmcb_save_area *save = &svm->vmcb->save;
 499
 500        control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 501                                        INTERCEPT_CR3_MASK |
 502                                        INTERCEPT_CR4_MASK;
 503
 504        control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 505                                        INTERCEPT_CR3_MASK |
 506                                        INTERCEPT_CR4_MASK |
 507                                        INTERCEPT_CR8_MASK;
 508
 509        control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 510                                        INTERCEPT_DR1_MASK |
 511                                        INTERCEPT_DR2_MASK |
 512                                        INTERCEPT_DR3_MASK;
 513
 514        control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 515                                        INTERCEPT_DR1_MASK |
 516                                        INTERCEPT_DR2_MASK |
 517                                        INTERCEPT_DR3_MASK |
 518                                        INTERCEPT_DR5_MASK |
 519                                        INTERCEPT_DR7_MASK;
 520
 521        control->intercept_exceptions = (1 << PF_VECTOR) |
 522                                        (1 << UD_VECTOR) |
 523                                        (1 << MC_VECTOR);
 524
 525
 526        control->intercept =    (1ULL << INTERCEPT_INTR) |
 527                                (1ULL << INTERCEPT_NMI) |
 528                                (1ULL << INTERCEPT_SMI) |
 529                                (1ULL << INTERCEPT_CPUID) |
 530                                (1ULL << INTERCEPT_INVD) |
 531                                (1ULL << INTERCEPT_HLT) |
 532                                (1ULL << INTERCEPT_INVLPGA) |
 533                                (1ULL << INTERCEPT_IOIO_PROT) |
 534                                (1ULL << INTERCEPT_MSR_PROT) |
 535                                (1ULL << INTERCEPT_TASK_SWITCH) |
 536                                (1ULL << INTERCEPT_SHUTDOWN) |
 537                                (1ULL << INTERCEPT_VMRUN) |
 538                                (1ULL << INTERCEPT_VMMCALL) |
 539                                (1ULL << INTERCEPT_VMLOAD) |
 540                                (1ULL << INTERCEPT_VMSAVE) |
 541                                (1ULL << INTERCEPT_STGI) |
 542                                (1ULL << INTERCEPT_CLGI) |
 543                                (1ULL << INTERCEPT_SKINIT) |
 544                                (1ULL << INTERCEPT_WBINVD) |
 545                                (1ULL << INTERCEPT_MONITOR) |
 546                                (1ULL << INTERCEPT_MWAIT);
 547
 548        control->iopm_base_pa = iopm_base;
 549        control->msrpm_base_pa = __pa(svm->msrpm);
 550        control->tsc_offset = 0;
 551        control->int_ctl = V_INTR_MASKING_MASK;
 552
 553        init_seg(&save->es);
 554        init_seg(&save->ss);
 555        init_seg(&save->ds);
 556        init_seg(&save->fs);
 557        init_seg(&save->gs);
 558
 559        save->cs.selector = 0xf000;
 560        /* Executable/Readable Code Segment */
 561        save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 562                SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 563        save->cs.limit = 0xffff;
 564        /*
 565         * cs.base should really be 0xffff0000, but vmx can't handle that, so
 566         * be consistent with it.
 567         *
 568         * Replace when we have real mode working for vmx.
 569         */
 570        save->cs.base = 0xf0000;
 571
 572        save->gdtr.limit = 0xffff;
 573        save->idtr.limit = 0xffff;
 574
 575        init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 576        init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 577
 578        save->efer = MSR_EFER_SVME_MASK;
 579        save->dr6 = 0xffff0ff0;
 580        save->dr7 = 0x400;
 581        save->rflags = 2;
 582        save->rip = 0x0000fff0;
 583
 584        /*
 585         * cr0 val on cpu init should be 0x60000010, we enable cpu
 586         * cache by default. the orderly way is to enable cache in bios.
 587         */
 588        save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 589        save->cr4 = X86_CR4_PAE;
 590        /* rdx = ?? */
 591
 592        if (npt_enabled) {
 593                /* Setup VMCB for Nested Paging */
 594                control->nested_ctl = 1;
 595                control->intercept &= ~(1ULL << INTERCEPT_TASK_SWITCH);
 596                control->intercept_exceptions &= ~(1 << PF_VECTOR);
 597                control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 598                                                INTERCEPT_CR3_MASK);
 599                control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 600                                                 INTERCEPT_CR3_MASK);
 601                save->g_pat = 0x0007040600070406ULL;
 602                /* enable caching because the QEMU Bios doesn't enable it */
 603                save->cr0 = X86_CR0_ET;
 604                save->cr3 = 0;
 605                save->cr4 = 0;
 606        }
 607        force_new_asid(&svm->vcpu);
 608}
 609
 610static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 611{
 612        struct vcpu_svm *svm = to_svm(vcpu);
 613
 614        init_vmcb(svm);
 615
 616        if (vcpu->vcpu_id != 0) {
 617                svm->vmcb->save.rip = 0;
 618                svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 619                svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 620        }
 621
 622        return 0;
 623}
 624
 625static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 626{
 627        struct vcpu_svm *svm;
 628        struct page *page;
 629        struct page *msrpm_pages;
 630        int err;
 631
 632        svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 633        if (!svm) {
 634                err = -ENOMEM;
 635                goto out;
 636        }
 637
 638        err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 639        if (err)
 640                goto free_svm;
 641
 642        page = alloc_page(GFP_KERNEL);
 643        if (!page) {
 644                err = -ENOMEM;
 645                goto uninit;
 646        }
 647
 648        err = -ENOMEM;
 649        msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 650        if (!msrpm_pages)
 651                goto uninit;
 652        svm->msrpm = page_address(msrpm_pages);
 653        svm_vcpu_init_msrpm(svm->msrpm);
 654
 655        svm->vmcb = page_address(page);
 656        clear_page(svm->vmcb);
 657        svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 658        svm->asid_generation = 0;
 659        memset(svm->db_regs, 0, sizeof(svm->db_regs));
 660        init_vmcb(svm);
 661
 662        fx_init(&svm->vcpu);
 663        svm->vcpu.fpu_active = 1;
 664        svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 665        if (svm->vcpu.vcpu_id == 0)
 666                svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 667
 668        return &svm->vcpu;
 669
 670uninit:
 671        kvm_vcpu_uninit(&svm->vcpu);
 672free_svm:
 673        kmem_cache_free(kvm_vcpu_cache, svm);
 674out:
 675        return ERR_PTR(err);
 676}
 677
 678static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 679{
 680        struct vcpu_svm *svm = to_svm(vcpu);
 681
 682        __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 683        __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 684        kvm_vcpu_uninit(vcpu);
 685        kmem_cache_free(kvm_vcpu_cache, svm);
 686}
 687
 688static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 689{
 690        struct vcpu_svm *svm = to_svm(vcpu);
 691        int i;
 692
 693        if (unlikely(cpu != vcpu->cpu)) {
 694                u64 tsc_this, delta;
 695
 696                /*
 697                 * Make sure that the guest sees a monotonically
 698                 * increasing TSC.
 699                 */
 700                rdtscll(tsc_this);
 701                delta = vcpu->arch.host_tsc - tsc_this;
 702                svm->vmcb->control.tsc_offset += delta;
 703                vcpu->cpu = cpu;
 704                kvm_migrate_timers(vcpu);
 705        }
 706
 707        for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 708                rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 709}
 710
 711static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 712{
 713        struct vcpu_svm *svm = to_svm(vcpu);
 714        int i;
 715
 716        ++vcpu->stat.host_state_reload;
 717        for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 718                wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 719
 720        rdtscll(vcpu->arch.host_tsc);
 721}
 722
 723static void svm_cache_regs(struct kvm_vcpu *vcpu)
 724{
 725        struct vcpu_svm *svm = to_svm(vcpu);
 726
 727        vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 728        vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 729        vcpu->arch.rip = svm->vmcb->save.rip;
 730}
 731
 732static void svm_decache_regs(struct kvm_vcpu *vcpu)
 733{
 734        struct vcpu_svm *svm = to_svm(vcpu);
 735        svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
 736        svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
 737        svm->vmcb->save.rip = vcpu->arch.rip;
 738}
 739
 740static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 741{
 742        return to_svm(vcpu)->vmcb->save.rflags;
 743}
 744
 745static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 746{
 747        to_svm(vcpu)->vmcb->save.rflags = rflags;
 748}
 749
 750static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 751{
 752        struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 753
 754        switch (seg) {
 755        case VCPU_SREG_CS: return &save->cs;
 756        case VCPU_SREG_DS: return &save->ds;
 757        case VCPU_SREG_ES: return &save->es;
 758        case VCPU_SREG_FS: return &save->fs;
 759        case VCPU_SREG_GS: return &save->gs;
 760        case VCPU_SREG_SS: return &save->ss;
 761        case VCPU_SREG_TR: return &save->tr;
 762        case VCPU_SREG_LDTR: return &save->ldtr;
 763        }
 764        BUG();
 765        return NULL;
 766}
 767
 768static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 769{
 770        struct vmcb_seg *s = svm_seg(vcpu, seg);
 771
 772        return s->base;
 773}
 774
 775static void svm_get_segment(struct kvm_vcpu *vcpu,
 776                            struct kvm_segment *var, int seg)
 777{
 778        struct vmcb_seg *s = svm_seg(vcpu, seg);
 779
 780        var->base = s->base;
 781        var->limit = s->limit;
 782        var->selector = s->selector;
 783        var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 784        var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 785        var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 786        var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 787        var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 788        var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 789        var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 790        var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 791        var->unusable = !var->present;
 792}
 793
 794static int svm_get_cpl(struct kvm_vcpu *vcpu)
 795{
 796        struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 797
 798        return save->cpl;
 799}
 800
 801static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 802{
 803        struct vcpu_svm *svm = to_svm(vcpu);
 804
 805        dt->limit = svm->vmcb->save.idtr.limit;
 806        dt->base = svm->vmcb->save.idtr.base;
 807}
 808
 809static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 810{
 811        struct vcpu_svm *svm = to_svm(vcpu);
 812
 813        svm->vmcb->save.idtr.limit = dt->limit;
 814        svm->vmcb->save.idtr.base = dt->base ;
 815}
 816
 817static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 818{
 819        struct vcpu_svm *svm = to_svm(vcpu);
 820
 821        dt->limit = svm->vmcb->save.gdtr.limit;
 822        dt->base = svm->vmcb->save.gdtr.base;
 823}
 824
 825static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 826{
 827        struct vcpu_svm *svm = to_svm(vcpu);
 828
 829        svm->vmcb->save.gdtr.limit = dt->limit;
 830        svm->vmcb->save.gdtr.base = dt->base ;
 831}
 832
 833static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 834{
 835}
 836
 837static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 838{
 839        struct vcpu_svm *svm = to_svm(vcpu);
 840
 841#ifdef CONFIG_X86_64
 842        if (vcpu->arch.shadow_efer & EFER_LME) {
 843                if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 844                        vcpu->arch.shadow_efer |= EFER_LMA;
 845                        svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 846                }
 847
 848                if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 849                        vcpu->arch.shadow_efer &= ~EFER_LMA;
 850                        svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 851                }
 852        }
 853#endif
 854        if (npt_enabled)
 855                goto set;
 856
 857        if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 858                svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 859                vcpu->fpu_active = 1;
 860        }
 861
 862        vcpu->arch.cr0 = cr0;
 863        cr0 |= X86_CR0_PG | X86_CR0_WP;
 864        if (!vcpu->fpu_active) {
 865                svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 866                cr0 |= X86_CR0_TS;
 867        }
 868set:
 869        /*
 870         * re-enable caching here because the QEMU bios
 871         * does not do it - this results in some delay at
 872         * reboot
 873         */
 874        cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 875        svm->vmcb->save.cr0 = cr0;
 876}
 877
 878static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 879{
 880        unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 881        unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 882
 883        if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 884                force_new_asid(vcpu);
 885
 886        vcpu->arch.cr4 = cr4;
 887        if (!npt_enabled)
 888                cr4 |= X86_CR4_PAE;
 889        cr4 |= host_cr4_mce;
 890        to_svm(vcpu)->vmcb->save.cr4 = cr4;
 891}
 892
 893static void svm_set_segment(struct kvm_vcpu *vcpu,
 894                            struct kvm_segment *var, int seg)
 895{
 896        struct vcpu_svm *svm = to_svm(vcpu);
 897        struct vmcb_seg *s = svm_seg(vcpu, seg);
 898
 899        s->base = var->base;
 900        s->limit = var->limit;
 901        s->selector = var->selector;
 902        if (var->unusable)
 903                s->attrib = 0;
 904        else {
 905                s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 906                s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 907                s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 908                s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 909                s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 910                s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 911                s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 912                s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 913        }
 914        if (seg == VCPU_SREG_CS)
 915                svm->vmcb->save.cpl
 916                        = (svm->vmcb->save.cs.attrib
 917                           >> SVM_SELECTOR_DPL_SHIFT) & 3;
 918
 919}
 920
 921static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 922{
 923        return -EOPNOTSUPP;
 924}
 925
 926static int svm_get_irq(struct kvm_vcpu *vcpu)
 927{
 928        struct vcpu_svm *svm = to_svm(vcpu);
 929        u32 exit_int_info = svm->vmcb->control.exit_int_info;
 930
 931        if (is_external_interrupt(exit_int_info))
 932                return exit_int_info & SVM_EVTINJ_VEC_MASK;
 933        return -1;
 934}
 935
 936static void load_host_msrs(struct kvm_vcpu *vcpu)
 937{
 938#ifdef CONFIG_X86_64
 939        wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 940#endif
 941}
 942
 943static void save_host_msrs(struct kvm_vcpu *vcpu)
 944{
 945#ifdef CONFIG_X86_64
 946        rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 947#endif
 948}
 949
 950static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 951{
 952        if (svm_data->next_asid > svm_data->max_asid) {
 953                ++svm_data->asid_generation;
 954                svm_data->next_asid = 1;
 955                svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 956        }
 957
 958        svm->vcpu.cpu = svm_data->cpu;
 959        svm->asid_generation = svm_data->asid_generation;
 960        svm->vmcb->control.asid = svm_data->next_asid++;
 961}
 962
 963static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 964{
 965        unsigned long val = to_svm(vcpu)->db_regs[dr];
 966        KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
 967        return val;
 968}
 969
 970static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 971                       int *exception)
 972{
 973        struct vcpu_svm *svm = to_svm(vcpu);
 974
 975        *exception = 0;
 976
 977        if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 978                svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 979                svm->vmcb->save.dr6 |= DR6_BD_MASK;
 980                *exception = DB_VECTOR;
 981                return;
 982        }
 983
 984        switch (dr) {
 985        case 0 ... 3:
 986                svm->db_regs[dr] = value;
 987                return;
 988        case 4 ... 5:
 989                if (vcpu->arch.cr4 & X86_CR4_DE) {
 990                        *exception = UD_VECTOR;
 991                        return;
 992                }
 993        case 7: {
 994                if (value & ~((1ULL << 32) - 1)) {
 995                        *exception = GP_VECTOR;
 996                        return;
 997                }
 998                svm->vmcb->save.dr7 = value;
 999                return;
1000        }
1001        default:
1002                printk(KERN_DEBUG "%s: unexpected dr %u\n",
1003                       __func__, dr);
1004                *exception = UD_VECTOR;
1005                return;
1006        }
1007}
1008
1009static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1010{
1011        u32 exit_int_info = svm->vmcb->control.exit_int_info;
1012        struct kvm *kvm = svm->vcpu.kvm;
1013        u64 fault_address;
1014        u32 error_code;
1015        bool event_injection = false;
1016
1017        if (!irqchip_in_kernel(kvm) &&
1018            is_external_interrupt(exit_int_info)) {
1019                event_injection = true;
1020                push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
1021        }
1022
1023        fault_address  = svm->vmcb->control.exit_info_2;
1024        error_code = svm->vmcb->control.exit_info_1;
1025
1026        if (!npt_enabled)
1027                KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1028                            (u32)fault_address, (u32)(fault_address >> 32),
1029                            handler);
1030        else
1031                KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1032                            (u32)fault_address, (u32)(fault_address >> 32),
1033                            handler);
1034        /*
1035         * FIXME: Tis shouldn't be necessary here, but there is a flush
1036         * missing in the MMU code. Until we find this bug, flush the
1037         * complete TLB here on an NPF
1038         */
1039        if (npt_enabled)
1040                svm_flush_tlb(&svm->vcpu);
1041
1042        if (event_injection)
1043                kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1044        return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1045}
1046
1047static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1048{
1049        int er;
1050
1051        er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1052        if (er != EMULATE_DONE)
1053                kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1054        return 1;
1055}
1056
1057static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058{
1059        svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1060        if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1061                svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1062        svm->vcpu.fpu_active = 1;
1063
1064        return 1;
1065}
1066
1067static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1068{
1069        /*
1070         * On an #MC intercept the MCE handler is not called automatically in
1071         * the host. So do it by hand here.
1072         */
1073        asm volatile (
1074                "int $0x12\n");
1075        /* not sure if we ever come back to this point */
1076
1077        return 1;
1078}
1079
1080static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1081{
1082        /*
1083         * VMCB is undefined after a SHUTDOWN intercept
1084         * so reinitialize it.
1085         */
1086        clear_page(svm->vmcb);
1087        init_vmcb(svm);
1088
1089        kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1090        return 0;
1091}
1092
1093static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1094{
1095        u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1096        int size, down, in, string, rep;
1097        unsigned port;
1098
1099        ++svm->vcpu.stat.io_exits;
1100
1101        svm->next_rip = svm->vmcb->control.exit_info_2;
1102
1103        string = (io_info & SVM_IOIO_STR_MASK) != 0;
1104
1105        if (string) {
1106                if (emulate_instruction(&svm->vcpu,
1107                                        kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1108                        return 0;
1109                return 1;
1110        }
1111
1112        in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1113        port = io_info >> 16;
1114        size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1115        rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1116        down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1117
1118        return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1119}
1120
1121static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1122{
1123        KVMTRACE_0D(NMI, &svm->vcpu, handler);
1124        return 1;
1125}
1126
1127static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1128{
1129        ++svm->vcpu.stat.irq_exits;
1130        KVMTRACE_0D(INTR, &svm->vcpu, handler);
1131        return 1;
1132}
1133
1134static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1135{
1136        return 1;
1137}
1138
1139static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1140{
1141        svm->next_rip = svm->vmcb->save.rip + 1;
1142        skip_emulated_instruction(&svm->vcpu);
1143        return kvm_emulate_halt(&svm->vcpu);
1144}
1145
1146static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1147{
1148        svm->next_rip = svm->vmcb->save.rip + 3;
1149        skip_emulated_instruction(&svm->vcpu);
1150        kvm_emulate_hypercall(&svm->vcpu);
1151        return 1;
1152}
1153
1154static int invalid_op_interception(struct vcpu_svm *svm,
1155                                   struct kvm_run *kvm_run)
1156{
1157        kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1158        return 1;
1159}
1160
1161static int task_switch_interception(struct vcpu_svm *svm,
1162                                    struct kvm_run *kvm_run)
1163{
1164        u16 tss_selector;
1165
1166        tss_selector = (u16)svm->vmcb->control.exit_info_1;
1167        if (svm->vmcb->control.exit_info_2 &
1168            (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1169                return kvm_task_switch(&svm->vcpu, tss_selector,
1170                                       TASK_SWITCH_IRET);
1171        if (svm->vmcb->control.exit_info_2 &
1172            (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1173                return kvm_task_switch(&svm->vcpu, tss_selector,
1174                                       TASK_SWITCH_JMP);
1175        return kvm_task_switch(&svm->vcpu, tss_selector, TASK_SWITCH_CALL);
1176}
1177
1178static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1179{
1180        svm->next_rip = svm->vmcb->save.rip + 2;
1181        kvm_emulate_cpuid(&svm->vcpu);
1182        return 1;
1183}
1184
1185static int emulate_on_interception(struct vcpu_svm *svm,
1186                                   struct kvm_run *kvm_run)
1187{
1188        if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1189                pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1190        return 1;
1191}
1192
1193static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1194{
1195        emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1196        if (irqchip_in_kernel(svm->vcpu.kvm))
1197                return 1;
1198        kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1199        return 0;
1200}
1201
1202static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1203{
1204        struct vcpu_svm *svm = to_svm(vcpu);
1205
1206        switch (ecx) {
1207        case MSR_IA32_TIME_STAMP_COUNTER: {
1208                u64 tsc;
1209
1210                rdtscll(tsc);
1211                *data = svm->vmcb->control.tsc_offset + tsc;
1212                break;
1213        }
1214        case MSR_K6_STAR:
1215                *data = svm->vmcb->save.star;
1216                break;
1217#ifdef CONFIG_X86_64
1218        case MSR_LSTAR:
1219                *data = svm->vmcb->save.lstar;
1220                break;
1221        case MSR_CSTAR:
1222                *data = svm->vmcb->save.cstar;
1223                break;
1224        case MSR_KERNEL_GS_BASE:
1225                *data = svm->vmcb->save.kernel_gs_base;
1226                break;
1227        case MSR_SYSCALL_MASK:
1228                *data = svm->vmcb->save.sfmask;
1229                break;
1230#endif
1231        case MSR_IA32_SYSENTER_CS:
1232                *data = svm->vmcb->save.sysenter_cs;
1233                break;
1234        case MSR_IA32_SYSENTER_EIP:
1235                *data = svm->vmcb->save.sysenter_eip;
1236                break;
1237        case MSR_IA32_SYSENTER_ESP:
1238                *data = svm->vmcb->save.sysenter_esp;
1239                break;
1240        /* Nobody will change the following 5 values in the VMCB so
1241           we can safely return them on rdmsr. They will always be 0
1242           until LBRV is implemented. */
1243        case MSR_IA32_DEBUGCTLMSR:
1244                *data = svm->vmcb->save.dbgctl;
1245                break;
1246        case MSR_IA32_LASTBRANCHFROMIP:
1247                *data = svm->vmcb->save.br_from;
1248                break;
1249        case MSR_IA32_LASTBRANCHTOIP:
1250                *data = svm->vmcb->save.br_to;
1251                break;
1252        case MSR_IA32_LASTINTFROMIP:
1253                *data = svm->vmcb->save.last_excp_from;
1254                break;
1255        case MSR_IA32_LASTINTTOIP:
1256                *data = svm->vmcb->save.last_excp_to;
1257                break;
1258        default:
1259                return kvm_get_msr_common(vcpu, ecx, data);
1260        }
1261        return 0;
1262}
1263
1264static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1265{
1266        u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1267        u64 data;
1268
1269        if (svm_get_msr(&svm->vcpu, ecx, &data))
1270                kvm_inject_gp(&svm->vcpu, 0);
1271        else {
1272                KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
1273                            (u32)(data >> 32), handler);
1274
1275                svm->vmcb->save.rax = data & 0xffffffff;
1276                svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
1277                svm->next_rip = svm->vmcb->save.rip + 2;
1278                skip_emulated_instruction(&svm->vcpu);
1279        }
1280        return 1;
1281}
1282
1283static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1284{
1285        struct vcpu_svm *svm = to_svm(vcpu);
1286
1287        switch (ecx) {
1288        case MSR_IA32_TIME_STAMP_COUNTER: {
1289                u64 tsc;
1290
1291                rdtscll(tsc);
1292                svm->vmcb->control.tsc_offset = data - tsc;
1293                break;
1294        }
1295        case MSR_K6_STAR:
1296                svm->vmcb->save.star = data;
1297                break;
1298#ifdef CONFIG_X86_64
1299        case MSR_LSTAR:
1300                svm->vmcb->save.lstar = data;
1301                break;
1302        case MSR_CSTAR:
1303                svm->vmcb->save.cstar = data;
1304                break;
1305        case MSR_KERNEL_GS_BASE:
1306                svm->vmcb->save.kernel_gs_base = data;
1307                break;
1308        case MSR_SYSCALL_MASK:
1309                svm->vmcb->save.sfmask = data;
1310                break;
1311#endif
1312        case MSR_IA32_SYSENTER_CS:
1313                svm->vmcb->save.sysenter_cs = data;
1314                break;
1315        case MSR_IA32_SYSENTER_EIP:
1316                svm->vmcb->save.sysenter_eip = data;
1317                break;
1318        case MSR_IA32_SYSENTER_ESP:
1319                svm->vmcb->save.sysenter_esp = data;
1320                break;
1321        case MSR_IA32_DEBUGCTLMSR:
1322                if (!svm_has(SVM_FEATURE_LBRV)) {
1323                        pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
1324                                        __func__, data);
1325                        break;
1326                }
1327                if (data & DEBUGCTL_RESERVED_BITS)
1328                        return 1;
1329
1330                svm->vmcb->save.dbgctl = data;
1331                if (data & (1ULL<<0))
1332                        svm_enable_lbrv(svm);
1333                else
1334                        svm_disable_lbrv(svm);
1335                break;
1336        case MSR_K7_EVNTSEL0:
1337        case MSR_K7_EVNTSEL1:
1338        case MSR_K7_EVNTSEL2:
1339        case MSR_K7_EVNTSEL3:
1340        case MSR_K7_PERFCTR0:
1341        case MSR_K7_PERFCTR1:
1342        case MSR_K7_PERFCTR2:
1343        case MSR_K7_PERFCTR3:
1344                /*
1345                 * Just discard all writes to the performance counters; this
1346                 * should keep both older linux and windows 64-bit guests
1347                 * happy
1348                 */
1349                pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
1350
1351                break;
1352        default:
1353                return kvm_set_msr_common(vcpu, ecx, data);
1354        }
1355        return 0;
1356}
1357
1358static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1359{
1360        u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1361        u64 data = (svm->vmcb->save.rax & -1u)
1362                | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
1363
1364        KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
1365                    handler);
1366
1367        svm->next_rip = svm->vmcb->save.rip + 2;
1368        if (svm_set_msr(&svm->vcpu, ecx, data))
1369                kvm_inject_gp(&svm->vcpu, 0);
1370        else
1371                skip_emulated_instruction(&svm->vcpu);
1372        return 1;
1373}
1374
1375static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1376{
1377        if (svm->vmcb->control.exit_info_1)
1378                return wrmsr_interception(svm, kvm_run);
1379        else
1380                return rdmsr_interception(svm, kvm_run);
1381}
1382
1383static int interrupt_window_interception(struct vcpu_svm *svm,
1384                                   struct kvm_run *kvm_run)
1385{
1386        KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
1387
1388        svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1389        svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1390        /*
1391         * If the user space waits to inject interrupts, exit as soon as
1392         * possible
1393         */
1394        if (kvm_run->request_interrupt_window &&
1395            !svm->vcpu.arch.irq_summary) {
1396                ++svm->vcpu.stat.irq_window_exits;
1397                kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1398                return 0;
1399        }
1400
1401        return 1;
1402}
1403
1404static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1405                                      struct kvm_run *kvm_run) = {
1406        [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1407        [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1408        [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1409        [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
1410        /* for now: */
1411        [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1412        [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1413        [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1414        [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
1415        [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1416        [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1417        [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1418        [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1419        [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1420        [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1421        [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1422        [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1423        [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1424        [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1425        [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1426        [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1427        [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1428        [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
1429        [SVM_EXIT_INTR]                         = intr_interception,
1430        [SVM_EXIT_NMI]                          = nmi_interception,
1431        [SVM_EXIT_SMI]                          = nop_on_interception,
1432        [SVM_EXIT_INIT]                         = nop_on_interception,
1433        [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1434        /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1435        [SVM_EXIT_CPUID]                        = cpuid_interception,
1436        [SVM_EXIT_INVD]                         = emulate_on_interception,
1437        [SVM_EXIT_HLT]                          = halt_interception,
1438        [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1439        [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1440        [SVM_EXIT_IOIO]                         = io_interception,
1441        [SVM_EXIT_MSR]                          = msr_interception,
1442        [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1443        [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1444        [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1445        [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1446        [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1447        [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1448        [SVM_EXIT_STGI]                         = invalid_op_interception,
1449        [SVM_EXIT_CLGI]                         = invalid_op_interception,
1450        [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1451        [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1452        [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1453        [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1454        [SVM_EXIT_NPF]                          = pf_interception,
1455};
1456
1457static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1458{
1459        struct vcpu_svm *svm = to_svm(vcpu);
1460        u32 exit_code = svm->vmcb->control.exit_code;
1461
1462        KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
1463                    (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
1464
1465        if (npt_enabled) {
1466                int mmu_reload = 0;
1467                if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
1468                        svm_set_cr0(vcpu, svm->vmcb->save.cr0);
1469                        mmu_reload = 1;
1470                }
1471                vcpu->arch.cr0 = svm->vmcb->save.cr0;
1472                vcpu->arch.cr3 = svm->vmcb->save.cr3;
1473                if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1474                        if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1475                                kvm_inject_gp(vcpu, 0);
1476                                return 1;
1477                        }
1478                }
1479                if (mmu_reload) {
1480                        kvm_mmu_reset_context(vcpu);
1481                        kvm_mmu_load(vcpu);
1482                }
1483        }
1484
1485        kvm_reput_irq(svm);
1486
1487        if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1488                kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1489                kvm_run->fail_entry.hardware_entry_failure_reason
1490                        = svm->vmcb->control.exit_code;
1491                return 0;
1492        }
1493
1494        if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1495            exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
1496            exit_code != SVM_EXIT_NPF)
1497                printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1498                       "exit_code 0x%x\n",
1499                       __func__, svm->vmcb->control.exit_int_info,
1500                       exit_code);
1501
1502        if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1503            || !svm_exit_handlers[exit_code]) {
1504                kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1505                kvm_run->hw.hardware_exit_reason = exit_code;
1506                return 0;
1507        }
1508
1509        return svm_exit_handlers[exit_code](svm, kvm_run);
1510}
1511
1512static void reload_tss(struct kvm_vcpu *vcpu)
1513{
1514        int cpu = raw_smp_processor_id();
1515
1516        struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1517        svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
1518        load_TR_desc();
1519}
1520
1521static void pre_svm_run(struct vcpu_svm *svm)
1522{
1523        int cpu = raw_smp_processor_id();
1524
1525        struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1526
1527        svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1528        if (svm->vcpu.cpu != cpu ||
1529            svm->asid_generation != svm_data->asid_generation)
1530                new_asid(svm, svm_data);
1531}
1532
1533
1534static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1535{
1536        struct vmcb_control_area *control;
1537
1538        KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
1539
1540        control = &svm->vmcb->control;
1541        control->int_vector = irq;
1542        control->int_ctl &= ~V_INTR_PRIO_MASK;
1543        control->int_ctl |= V_IRQ_MASK |
1544                ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1545}
1546
1547static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1548{
1549        struct vcpu_svm *svm = to_svm(vcpu);
1550
1551        svm_inject_irq(svm, irq);
1552}
1553
1554static void update_cr8_intercept(struct kvm_vcpu *vcpu)
1555{
1556        struct vcpu_svm *svm = to_svm(vcpu);
1557        struct vmcb *vmcb = svm->vmcb;
1558        int max_irr, tpr;
1559
1560        if (!irqchip_in_kernel(vcpu->kvm) || vcpu->arch.apic->vapic_addr)
1561                return;
1562
1563        vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1564
1565        max_irr = kvm_lapic_find_highest_irr(vcpu);
1566        if (max_irr == -1)
1567                return;
1568
1569        tpr = kvm_lapic_get_cr8(vcpu) << 4;
1570
1571        if (tpr >= (max_irr & 0xf0))
1572                vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
1573}
1574
1575static void svm_intr_assist(struct kvm_vcpu *vcpu)
1576{
1577        struct vcpu_svm *svm = to_svm(vcpu);
1578        struct vmcb *vmcb = svm->vmcb;
1579        int intr_vector = -1;
1580
1581        if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1582            ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1583                intr_vector = vmcb->control.exit_int_info &
1584                              SVM_EVTINJ_VEC_MASK;
1585                vmcb->control.exit_int_info = 0;
1586                svm_inject_irq(svm, intr_vector);
1587                goto out;
1588        }
1589
1590        if (vmcb->control.int_ctl & V_IRQ_MASK)
1591                goto out;
1592
1593        if (!kvm_cpu_has_interrupt(vcpu))
1594                goto out;
1595
1596        if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1597            (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1598            (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1599                /* unable to deliver irq, set pending irq */
1600                vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1601                svm_inject_irq(svm, 0x0);
1602                goto out;
1603        }
1604        /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1605        intr_vector = kvm_cpu_get_interrupt(vcpu);
1606        svm_inject_irq(svm, intr_vector);
1607        kvm_timer_intr_post(vcpu, intr_vector);
1608out:
1609        update_cr8_intercept(vcpu);
1610}
1611
1612static void kvm_reput_irq(struct vcpu_svm *svm)
1613{
1614        struct vmcb_control_area *control = &svm->vmcb->control;
1615
1616        if ((control->int_ctl & V_IRQ_MASK)
1617            && !irqchip_in_kernel(svm->vcpu.kvm)) {
1618                control->int_ctl &= ~V_IRQ_MASK;
1619                push_irq(&svm->vcpu, control->int_vector);
1620        }
1621
1622        svm->vcpu.arch.interrupt_window_open =
1623                !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1624}
1625
1626static void svm_do_inject_vector(struct vcpu_svm *svm)
1627{
1628        struct kvm_vcpu *vcpu = &svm->vcpu;
1629        int word_index = __ffs(vcpu->arch.irq_summary);
1630        int bit_index = __ffs(vcpu->arch.irq_pending[word_index]);
1631        int irq = word_index * BITS_PER_LONG + bit_index;
1632
1633        clear_bit(bit_index, &vcpu->arch.irq_pending[word_index]);
1634        if (!vcpu->arch.irq_pending[word_index])
1635                clear_bit(word_index, &vcpu->arch.irq_summary);
1636        svm_inject_irq(svm, irq);
1637}
1638
1639static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1640                                       struct kvm_run *kvm_run)
1641{
1642        struct vcpu_svm *svm = to_svm(vcpu);
1643        struct vmcb_control_area *control = &svm->vmcb->control;
1644
1645        svm->vcpu.arch.interrupt_window_open =
1646                (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1647                 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1648
1649        if (svm->vcpu.arch.interrupt_window_open && svm->vcpu.arch.irq_summary)
1650                /*
1651                 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1652                 */
1653                svm_do_inject_vector(svm);
1654
1655        /*
1656         * Interrupts blocked.  Wait for unblock.
1657         */
1658        if (!svm->vcpu.arch.interrupt_window_open &&
1659            (svm->vcpu.arch.irq_summary || kvm_run->request_interrupt_window))
1660                control->intercept |= 1ULL << INTERCEPT_VINTR;
1661         else
1662                control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1663}
1664
1665static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
1666{
1667        return 0;
1668}
1669
1670static void save_db_regs(unsigned long *db_regs)
1671{
1672        asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1673        asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1674        asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1675        asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1676}
1677
1678static void load_db_regs(unsigned long *db_regs)
1679{
1680        asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1681        asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1682        asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1683        asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1684}
1685
1686static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1687{
1688        force_new_asid(vcpu);
1689}
1690
1691static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1692{
1693}
1694
1695static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
1696{
1697        struct vcpu_svm *svm = to_svm(vcpu);
1698
1699        if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
1700                int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
1701                kvm_lapic_set_tpr(vcpu, cr8);
1702        }
1703}
1704
1705static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
1706{
1707        struct vcpu_svm *svm = to_svm(vcpu);
1708        u64 cr8;
1709
1710        if (!irqchip_in_kernel(vcpu->kvm))
1711                return;
1712
1713        cr8 = kvm_get_cr8(vcpu);
1714        svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
1715        svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
1716}
1717
1718static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1719{
1720        struct vcpu_svm *svm = to_svm(vcpu);
1721        u16 fs_selector;
1722        u16 gs_selector;
1723        u16 ldt_selector;
1724
1725        pre_svm_run(svm);
1726
1727        sync_lapic_to_cr8(vcpu);
1728
1729        save_host_msrs(vcpu);
1730        fs_selector = kvm_read_fs();
1731        gs_selector = kvm_read_gs();
1732        ldt_selector = kvm_read_ldt();
1733        svm->host_cr2 = kvm_read_cr2();
1734        svm->host_dr6 = read_dr6();
1735        svm->host_dr7 = read_dr7();
1736        svm->vmcb->save.cr2 = vcpu->arch.cr2;
1737        /* required for live migration with NPT */
1738        if (npt_enabled)
1739                svm->vmcb->save.cr3 = vcpu->arch.cr3;
1740
1741        if (svm->vmcb->save.dr7 & 0xff) {
1742                write_dr7(0);
1743                save_db_regs(svm->host_db_regs);
1744                load_db_regs(svm->db_regs);
1745        }
1746
1747        clgi();
1748
1749        local_irq_enable();
1750
1751        asm volatile (
1752#ifdef CONFIG_X86_64
1753                "push %%rbp; \n\t"
1754#else
1755                "push %%ebp; \n\t"
1756#endif
1757
1758#ifdef CONFIG_X86_64
1759                "mov %c[rbx](%[svm]), %%rbx \n\t"
1760                "mov %c[rcx](%[svm]), %%rcx \n\t"
1761                "mov %c[rdx](%[svm]), %%rdx \n\t"
1762                "mov %c[rsi](%[svm]), %%rsi \n\t"
1763                "mov %c[rdi](%[svm]), %%rdi \n\t"
1764                "mov %c[rbp](%[svm]), %%rbp \n\t"
1765                "mov %c[r8](%[svm]),  %%r8  \n\t"
1766                "mov %c[r9](%[svm]),  %%r9  \n\t"
1767                "mov %c[r10](%[svm]), %%r10 \n\t"
1768                "mov %c[r11](%[svm]), %%r11 \n\t"
1769                "mov %c[r12](%[svm]), %%r12 \n\t"
1770                "mov %c[r13](%[svm]), %%r13 \n\t"
1771                "mov %c[r14](%[svm]), %%r14 \n\t"
1772                "mov %c[r15](%[svm]), %%r15 \n\t"
1773#else
1774                "mov %c[rbx](%[svm]), %%ebx \n\t"
1775                "mov %c[rcx](%[svm]), %%ecx \n\t"
1776                "mov %c[rdx](%[svm]), %%edx \n\t"
1777                "mov %c[rsi](%[svm]), %%esi \n\t"
1778                "mov %c[rdi](%[svm]), %%edi \n\t"
1779                "mov %c[rbp](%[svm]), %%ebp \n\t"
1780#endif
1781
1782#ifdef CONFIG_X86_64
1783                /* Enter guest mode */
1784                "push %%rax \n\t"
1785                "mov %c[vmcb](%[svm]), %%rax \n\t"
1786                __ex(SVM_VMLOAD) "\n\t"
1787                __ex(SVM_VMRUN) "\n\t"
1788                __ex(SVM_VMSAVE) "\n\t"
1789                "pop %%rax \n\t"
1790#else
1791                /* Enter guest mode */
1792                "push %%eax \n\t"
1793                "mov %c[vmcb](%[svm]), %%eax \n\t"
1794                __ex(SVM_VMLOAD) "\n\t"
1795                __ex(SVM_VMRUN) "\n\t"
1796                __ex(SVM_VMSAVE) "\n\t"
1797                "pop %%eax \n\t"
1798#endif
1799
1800                /* Save guest registers, load host registers */
1801#ifdef CONFIG_X86_64
1802                "mov %%rbx, %c[rbx](%[svm]) \n\t"
1803                "mov %%rcx, %c[rcx](%[svm]) \n\t"
1804                "mov %%rdx, %c[rdx](%[svm]) \n\t"
1805                "mov %%rsi, %c[rsi](%[svm]) \n\t"
1806                "mov %%rdi, %c[rdi](%[svm]) \n\t"
1807                "mov %%rbp, %c[rbp](%[svm]) \n\t"
1808                "mov %%r8,  %c[r8](%[svm]) \n\t"
1809                "mov %%r9,  %c[r9](%[svm]) \n\t"
1810                "mov %%r10, %c[r10](%[svm]) \n\t"
1811                "mov %%r11, %c[r11](%[svm]) \n\t"
1812                "mov %%r12, %c[r12](%[svm]) \n\t"
1813                "mov %%r13, %c[r13](%[svm]) \n\t"
1814                "mov %%r14, %c[r14](%[svm]) \n\t"
1815                "mov %%r15, %c[r15](%[svm]) \n\t"
1816
1817                "pop  %%rbp; \n\t"
1818#else
1819                "mov %%ebx, %c[rbx](%[svm]) \n\t"
1820                "mov %%ecx, %c[rcx](%[svm]) \n\t"
1821                "mov %%edx, %c[rdx](%[svm]) \n\t"
1822                "mov %%esi, %c[rsi](%[svm]) \n\t"
1823                "mov %%edi, %c[rdi](%[svm]) \n\t"
1824                "mov %%ebp, %c[rbp](%[svm]) \n\t"
1825
1826                "pop  %%ebp; \n\t"
1827#endif
1828                :
1829                : [svm]"a"(svm),
1830                  [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1831                  [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
1832                  [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
1833                  [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
1834                  [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
1835                  [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
1836                  [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
1837#ifdef CONFIG_X86_64
1838                  , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
1839                  [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
1840                  [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
1841                  [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
1842                  [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
1843                  [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
1844                  [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
1845                  [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
1846#endif
1847                : "cc", "memory"
1848#ifdef CONFIG_X86_64
1849                , "rbx", "rcx", "rdx", "rsi", "rdi"
1850                , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
1851#else
1852                , "ebx", "ecx", "edx" , "esi", "edi"
1853#endif
1854                );
1855
1856        if ((svm->vmcb->save.dr7 & 0xff))
1857                load_db_regs(svm->host_db_regs);
1858
1859        vcpu->arch.cr2 = svm->vmcb->save.cr2;
1860
1861        write_dr6(svm->host_dr6);
1862        write_dr7(svm->host_dr7);
1863        kvm_write_cr2(svm->host_cr2);
1864
1865        kvm_load_fs(fs_selector);
1866        kvm_load_gs(gs_selector);
1867        kvm_load_ldt(ldt_selector);
1868        load_host_msrs(vcpu);
1869
1870        reload_tss(vcpu);
1871
1872        local_irq_disable();
1873
1874        stgi();
1875
1876        sync_cr8_to_lapic(vcpu);
1877
1878        svm->next_rip = 0;
1879}
1880
1881static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1882{
1883        struct vcpu_svm *svm = to_svm(vcpu);
1884
1885        if (npt_enabled) {
1886                svm->vmcb->control.nested_cr3 = root;
1887                force_new_asid(vcpu);
1888                return;
1889        }
1890
1891        svm->vmcb->save.cr3 = root;
1892        force_new_asid(vcpu);
1893
1894        if (vcpu->fpu_active) {
1895                svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1896                svm->vmcb->save.cr0 |= X86_CR0_TS;
1897                vcpu->fpu_active = 0;
1898        }
1899}
1900
1901static int is_disabled(void)
1902{
1903        u64 vm_cr;
1904
1905        rdmsrl(MSR_VM_CR, vm_cr);
1906        if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1907                return 1;
1908
1909        return 0;
1910}
1911
1912static void
1913svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1914{
1915        /*
1916         * Patch in the VMMCALL instruction:
1917         */
1918        hypercall[0] = 0x0f;
1919        hypercall[1] = 0x01;
1920        hypercall[2] = 0xd9;
1921}
1922
1923static void svm_check_processor_compat(void *rtn)
1924{
1925        *(int *)rtn = 0;
1926}
1927
1928static bool svm_cpu_has_accelerated_tpr(void)
1929{
1930        return false;
1931}
1932
1933static int get_npt_level(void)
1934{
1935#ifdef CONFIG_X86_64
1936        return PT64_ROOT_LEVEL;
1937#else
1938        return PT32E_ROOT_LEVEL;
1939#endif
1940}
1941
1942static struct kvm_x86_ops svm_x86_ops = {
1943        .cpu_has_kvm_support = has_svm,
1944        .disabled_by_bios = is_disabled,
1945        .hardware_setup = svm_hardware_setup,
1946        .hardware_unsetup = svm_hardware_unsetup,
1947        .check_processor_compatibility = svm_check_processor_compat,
1948        .hardware_enable = svm_hardware_enable,
1949        .hardware_disable = svm_hardware_disable,
1950        .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
1951
1952        .vcpu_create = svm_create_vcpu,
1953        .vcpu_free = svm_free_vcpu,
1954        .vcpu_reset = svm_vcpu_reset,
1955
1956        .prepare_guest_switch = svm_prepare_guest_switch,
1957        .vcpu_load = svm_vcpu_load,
1958        .vcpu_put = svm_vcpu_put,
1959
1960        .set_guest_debug = svm_guest_debug,
1961        .get_msr = svm_get_msr,
1962        .set_msr = svm_set_msr,
1963        .get_segment_base = svm_get_segment_base,
1964        .get_segment = svm_get_segment,
1965        .set_segment = svm_set_segment,
1966        .get_cpl = svm_get_cpl,
1967        .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1968        .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1969        .set_cr0 = svm_set_cr0,
1970        .set_cr3 = svm_set_cr3,
1971        .set_cr4 = svm_set_cr4,
1972        .set_efer = svm_set_efer,
1973        .get_idt = svm_get_idt,
1974        .set_idt = svm_set_idt,
1975        .get_gdt = svm_get_gdt,
1976        .set_gdt = svm_set_gdt,
1977        .get_dr = svm_get_dr,
1978        .set_dr = svm_set_dr,
1979        .cache_regs = svm_cache_regs,
1980        .decache_regs = svm_decache_regs,
1981        .get_rflags = svm_get_rflags,
1982        .set_rflags = svm_set_rflags,
1983
1984        .tlb_flush = svm_flush_tlb,
1985
1986        .run = svm_vcpu_run,
1987        .handle_exit = handle_exit,
1988        .skip_emulated_instruction = skip_emulated_instruction,
1989        .patch_hypercall = svm_patch_hypercall,
1990        .get_irq = svm_get_irq,
1991        .set_irq = svm_set_irq,
1992        .queue_exception = svm_queue_exception,
1993        .exception_injected = svm_exception_injected,
1994        .inject_pending_irq = svm_intr_assist,
1995        .inject_pending_vectors = do_interrupt_requests,
1996
1997        .set_tss_addr = svm_set_tss_addr,
1998        .get_tdp_level = get_npt_level,
1999};
2000
2001static int __init svm_init(void)
2002{
2003        return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2004                              THIS_MODULE);
2005}
2006
2007static void __exit svm_exit(void)
2008{
2009        kvm_exit();
2010}
2011
2012module_init(svm_init)
2013module_exit(svm_exit)
2014