linux/arch/ia64/mm/tlb.c
<<
>>
Prefs
   1/*
   2 * TLB support routines.
   3 *
   4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
   5 *      David Mosberger-Tang <davidm@hpl.hp.com>
   6 *
   7 * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
   8 *              Modified RID allocation for SMP
   9 *          Goutham Rao <goutham.rao@intel.com>
  10 *              IPI based ptc implementation and A-step IPI implementation.
  11 * Rohit Seth <rohit.seth@intel.com>
  12 * Ken Chen <kenneth.w.chen@intel.com>
  13 * Christophe de Dinechin <ddd@hp.com>: Avoid ptc.e on memory allocation
  14 * Copyright (C) 2007 Intel Corp
  15 *      Fenghua Yu <fenghua.yu@intel.com>
  16 *      Add multiple ptc.g/ptc.ga instruction support in global tlb purge.
  17 */
  18#include <linux/module.h>
  19#include <linux/init.h>
  20#include <linux/kernel.h>
  21#include <linux/sched.h>
  22#include <linux/smp.h>
  23#include <linux/mm.h>
  24#include <linux/bootmem.h>
  25
  26#include <asm/delay.h>
  27#include <asm/mmu_context.h>
  28#include <asm/pgalloc.h>
  29#include <asm/pal.h>
  30#include <asm/tlbflush.h>
  31#include <asm/dma.h>
  32#include <asm/processor.h>
  33#include <asm/sal.h>
  34#include <asm/tlb.h>
  35
  36static struct {
  37        unsigned long mask;     /* mask of supported purge page-sizes */
  38        unsigned long max_bits; /* log2 of largest supported purge page-size */
  39} purge;
  40
  41struct ia64_ctx ia64_ctx = {
  42        .lock = __SPIN_LOCK_UNLOCKED(ia64_ctx.lock),
  43        .next = 1,
  44        .max_ctx = ~0U
  45};
  46
  47DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
  48DEFINE_PER_CPU(u8, ia64_tr_num);  /*Number of TR slots in current processor*/
  49DEFINE_PER_CPU(u8, ia64_tr_used); /*Max Slot number used by kernel*/
  50
  51struct ia64_tr_entry __per_cpu_idtrs[NR_CPUS][2][IA64_TR_ALLOC_MAX];
  52
  53/*
  54 * Initializes the ia64_ctx.bitmap array based on max_ctx+1.
  55 * Called after cpu_init() has setup ia64_ctx.max_ctx based on
  56 * maximum RID that is supported by boot CPU.
  57 */
  58void __init
  59mmu_context_init (void)
  60{
  61        ia64_ctx.bitmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
  62        ia64_ctx.flushmap = alloc_bootmem((ia64_ctx.max_ctx+1)>>3);
  63}
  64
  65/*
  66 * Acquire the ia64_ctx.lock before calling this function!
  67 */
  68void
  69wrap_mmu_context (struct mm_struct *mm)
  70{
  71        int i, cpu;
  72        unsigned long flush_bit;
  73
  74        for (i=0; i <= ia64_ctx.max_ctx / BITS_PER_LONG; i++) {
  75                flush_bit = xchg(&ia64_ctx.flushmap[i], 0);
  76                ia64_ctx.bitmap[i] ^= flush_bit;
  77        }
  78 
  79        /* use offset at 300 to skip daemons */
  80        ia64_ctx.next = find_next_zero_bit(ia64_ctx.bitmap,
  81                                ia64_ctx.max_ctx, 300);
  82        ia64_ctx.limit = find_next_bit(ia64_ctx.bitmap,
  83                                ia64_ctx.max_ctx, ia64_ctx.next);
  84
  85        /*
  86         * can't call flush_tlb_all() here because of race condition
  87         * with O(1) scheduler [EF]
  88         */
  89        cpu = get_cpu(); /* prevent preemption/migration */
  90        for_each_online_cpu(i)
  91                if (i != cpu)
  92                        per_cpu(ia64_need_tlb_flush, i) = 1;
  93        put_cpu();
  94        local_flush_tlb_all();
  95}
  96
  97/*
  98 * Implement "spinaphores" ... like counting semaphores, but they
  99 * spin instead of sleeping.  If there are ever any other users for
 100 * this primitive it can be moved up to a spinaphore.h header.
 101 */
 102struct spinaphore {
 103        atomic_t        cur;
 104};
 105
 106static inline void spinaphore_init(struct spinaphore *ss, int val)
 107{
 108        atomic_set(&ss->cur, val);
 109}
 110
 111static inline void down_spin(struct spinaphore *ss)
 112{
 113        while (unlikely(!atomic_add_unless(&ss->cur, -1, 0)))
 114                while (atomic_read(&ss->cur) == 0)
 115                        cpu_relax();
 116}
 117
 118static inline void up_spin(struct spinaphore *ss)
 119{
 120        atomic_add(1, &ss->cur);
 121}
 122
 123static struct spinaphore ptcg_sem;
 124static u16 nptcg = 1;
 125static int need_ptcg_sem = 1;
 126static int toolatetochangeptcgsem = 0;
 127
 128/*
 129 * Kernel parameter "nptcg=" overrides max number of concurrent global TLB
 130 * purges which is reported from either PAL or SAL PALO.
 131 *
 132 * We don't have sanity checking for nptcg value. It's the user's responsibility
 133 * for valid nptcg value on the platform. Otherwise, kernel may hang in some
 134 * cases.
 135 */
 136static int __init
 137set_nptcg(char *str)
 138{
 139        int value = 0;
 140
 141        get_option(&str, &value);
 142        setup_ptcg_sem(value, NPTCG_FROM_KERNEL_PARAMETER);
 143
 144        return 1;
 145}
 146
 147__setup("nptcg=", set_nptcg);
 148
 149/*
 150 * Maximum number of simultaneous ptc.g purges in the system can
 151 * be defined by PAL_VM_SUMMARY (in which case we should take
 152 * the smallest value for any cpu in the system) or by the PAL
 153 * override table (in which case we should ignore the value from
 154 * PAL_VM_SUMMARY).
 155 *
 156 * Kernel parameter "nptcg=" overrides maximum number of simultanesous ptc.g
 157 * purges defined in either PAL_VM_SUMMARY or PAL override table. In this case,
 158 * we should ignore the value from either PAL_VM_SUMMARY or PAL override table.
 159 *
 160 * Complicating the logic here is the fact that num_possible_cpus()
 161 * isn't fully setup until we start bringing cpus online.
 162 */
 163void
 164setup_ptcg_sem(int max_purges, int nptcg_from)
 165{
 166        static int kp_override;
 167        static int palo_override;
 168        static int firstcpu = 1;
 169
 170        if (toolatetochangeptcgsem) {
 171                if (nptcg_from == NPTCG_FROM_PAL && max_purges == 0)
 172                        BUG_ON(1 < nptcg);
 173                else
 174                        BUG_ON(max_purges < nptcg);
 175                return;
 176        }
 177
 178        if (nptcg_from == NPTCG_FROM_KERNEL_PARAMETER) {
 179                kp_override = 1;
 180                nptcg = max_purges;
 181                goto resetsema;
 182        }
 183        if (kp_override) {
 184                need_ptcg_sem = num_possible_cpus() > nptcg;
 185                return;
 186        }
 187
 188        if (nptcg_from == NPTCG_FROM_PALO) {
 189                palo_override = 1;
 190
 191                /* In PALO max_purges == 0 really means it! */
 192                if (max_purges == 0)
 193                        panic("Whoa! Platform does not support global TLB purges.\n");
 194                nptcg = max_purges;
 195                if (nptcg == PALO_MAX_TLB_PURGES) {
 196                        need_ptcg_sem = 0;
 197                        return;
 198                }
 199                goto resetsema;
 200        }
 201        if (palo_override) {
 202                if (nptcg != PALO_MAX_TLB_PURGES)
 203                        need_ptcg_sem = (num_possible_cpus() > nptcg);
 204                return;
 205        }
 206
 207        /* In PAL_VM_SUMMARY max_purges == 0 actually means 1 */
 208        if (max_purges == 0) max_purges = 1;
 209
 210        if (firstcpu) {
 211                nptcg = max_purges;
 212                firstcpu = 0;
 213        }
 214        if (max_purges < nptcg)
 215                nptcg = max_purges;
 216        if (nptcg == PAL_MAX_PURGES) {
 217                need_ptcg_sem = 0;
 218                return;
 219        } else
 220                need_ptcg_sem = (num_possible_cpus() > nptcg);
 221
 222resetsema:
 223        spinaphore_init(&ptcg_sem, max_purges);
 224}
 225
 226void
 227ia64_global_tlb_purge (struct mm_struct *mm, unsigned long start,
 228                       unsigned long end, unsigned long nbits)
 229{
 230        struct mm_struct *active_mm = current->active_mm;
 231
 232        toolatetochangeptcgsem = 1;
 233
 234        if (mm != active_mm) {
 235                /* Restore region IDs for mm */
 236                if (mm && active_mm) {
 237                        activate_context(mm);
 238                } else {
 239                        flush_tlb_all();
 240                        return;
 241                }
 242        }
 243
 244        if (need_ptcg_sem)
 245                down_spin(&ptcg_sem);
 246
 247        do {
 248                /*
 249                 * Flush ALAT entries also.
 250                 */
 251                ia64_ptcga(start, (nbits << 2));
 252                ia64_srlz_i();
 253                start += (1UL << nbits);
 254        } while (start < end);
 255
 256        if (need_ptcg_sem)
 257                up_spin(&ptcg_sem);
 258
 259        if (mm != active_mm) {
 260                activate_context(active_mm);
 261        }
 262}
 263
 264void
 265local_flush_tlb_all (void)
 266{
 267        unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
 268
 269        addr    = local_cpu_data->ptce_base;
 270        count0  = local_cpu_data->ptce_count[0];
 271        count1  = local_cpu_data->ptce_count[1];
 272        stride0 = local_cpu_data->ptce_stride[0];
 273        stride1 = local_cpu_data->ptce_stride[1];
 274
 275        local_irq_save(flags);
 276        for (i = 0; i < count0; ++i) {
 277                for (j = 0; j < count1; ++j) {
 278                        ia64_ptce(addr);
 279                        addr += stride1;
 280                }
 281                addr += stride0;
 282        }
 283        local_irq_restore(flags);
 284        ia64_srlz_i();                  /* srlz.i implies srlz.d */
 285}
 286
 287void
 288flush_tlb_range (struct vm_area_struct *vma, unsigned long start,
 289                 unsigned long end)
 290{
 291        struct mm_struct *mm = vma->vm_mm;
 292        unsigned long size = end - start;
 293        unsigned long nbits;
 294
 295#ifndef CONFIG_SMP
 296        if (mm != current->active_mm) {
 297                mm->context = 0;
 298                return;
 299        }
 300#endif
 301
 302        nbits = ia64_fls(size + 0xfff);
 303        while (unlikely (((1UL << nbits) & purge.mask) == 0) &&
 304                        (nbits < purge.max_bits))
 305                ++nbits;
 306        if (nbits > purge.max_bits)
 307                nbits = purge.max_bits;
 308        start &= ~((1UL << nbits) - 1);
 309
 310        preempt_disable();
 311#ifdef CONFIG_SMP
 312        if (mm != current->active_mm || cpus_weight(mm->cpu_vm_mask) != 1) {
 313                platform_global_tlb_purge(mm, start, end, nbits);
 314                preempt_enable();
 315                return;
 316        }
 317#endif
 318        do {
 319                ia64_ptcl(start, (nbits<<2));
 320                start += (1UL << nbits);
 321        } while (start < end);
 322        preempt_enable();
 323        ia64_srlz_i();                  /* srlz.i implies srlz.d */
 324}
 325EXPORT_SYMBOL(flush_tlb_range);
 326
 327void __devinit
 328ia64_tlb_init (void)
 329{
 330        ia64_ptce_info_t uninitialized_var(ptce_info); /* GCC be quiet */
 331        unsigned long tr_pgbits;
 332        long status;
 333        pal_vm_info_1_u_t vm_info_1;
 334        pal_vm_info_2_u_t vm_info_2;
 335        int cpu = smp_processor_id();
 336
 337        if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
 338                printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld; "
 339                       "defaulting to architected purge page-sizes.\n", status);
 340                purge.mask = 0x115557000UL;
 341        }
 342        purge.max_bits = ia64_fls(purge.mask);
 343
 344        ia64_get_ptce(&ptce_info);
 345        local_cpu_data->ptce_base = ptce_info.base;
 346        local_cpu_data->ptce_count[0] = ptce_info.count[0];
 347        local_cpu_data->ptce_count[1] = ptce_info.count[1];
 348        local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
 349        local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
 350
 351        local_flush_tlb_all();  /* nuke left overs from bootstrapping... */
 352        status = ia64_pal_vm_summary(&vm_info_1, &vm_info_2);
 353
 354        if (status) {
 355                printk(KERN_ERR "ia64_pal_vm_summary=%ld\n", status);
 356                per_cpu(ia64_tr_num, cpu) = 8;
 357                return;
 358        }
 359        per_cpu(ia64_tr_num, cpu) = vm_info_1.pal_vm_info_1_s.max_itr_entry+1;
 360        if (per_cpu(ia64_tr_num, cpu) >
 361                                (vm_info_1.pal_vm_info_1_s.max_dtr_entry+1))
 362                per_cpu(ia64_tr_num, cpu) =
 363                                vm_info_1.pal_vm_info_1_s.max_dtr_entry+1;
 364        if (per_cpu(ia64_tr_num, cpu) > IA64_TR_ALLOC_MAX) {
 365                per_cpu(ia64_tr_num, cpu) = IA64_TR_ALLOC_MAX;
 366                printk(KERN_DEBUG "TR register number exceeds IA64_TR_ALLOC_MAX!"
 367                        "IA64_TR_ALLOC_MAX should be extended\n");
 368        }
 369}
 370
 371/*
 372 * is_tr_overlap
 373 *
 374 * Check overlap with inserted TRs.
 375 */
 376static int is_tr_overlap(struct ia64_tr_entry *p, u64 va, u64 log_size)
 377{
 378        u64 tr_log_size;
 379        u64 tr_end;
 380        u64 va_rr = ia64_get_rr(va);
 381        u64 va_rid = RR_TO_RID(va_rr);
 382        u64 va_end = va + (1<<log_size) - 1;
 383
 384        if (va_rid != RR_TO_RID(p->rr))
 385                return 0;
 386        tr_log_size = (p->itir & 0xff) >> 2;
 387        tr_end = p->ifa + (1<<tr_log_size) - 1;
 388
 389        if (va > tr_end || p->ifa > va_end)
 390                return 0;
 391        return 1;
 392
 393}
 394
 395/*
 396 * ia64_insert_tr in virtual mode. Allocate a TR slot
 397 *
 398 * target_mask : 0x1 : itr, 0x2 : dtr, 0x3 : idtr
 399 *
 400 * va   : virtual address.
 401 * pte  : pte entries inserted.
 402 * log_size: range to be covered.
 403 *
 404 * Return value:  <0 :  error No.
 405 *
 406 *                >=0 : slot number allocated for TR.
 407 * Must be called with preemption disabled.
 408 */
 409int ia64_itr_entry(u64 target_mask, u64 va, u64 pte, u64 log_size)
 410{
 411        int i, r;
 412        unsigned long psr;
 413        struct ia64_tr_entry *p;
 414        int cpu = smp_processor_id();
 415
 416        r = -EINVAL;
 417        /*Check overlap with existing TR entries*/
 418        if (target_mask & 0x1) {
 419                p = &__per_cpu_idtrs[cpu][0][0];
 420                for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
 421                                                                i++, p++) {
 422                        if (p->pte & 0x1)
 423                                if (is_tr_overlap(p, va, log_size)) {
 424                                        printk(KERN_DEBUG "Overlapped Entry"
 425                                                "Inserted for TR Reigster!!\n");
 426                                        goto out;
 427                        }
 428                }
 429        }
 430        if (target_mask & 0x2) {
 431                p = &__per_cpu_idtrs[cpu][1][0];
 432                for (i = IA64_TR_ALLOC_BASE; i <= per_cpu(ia64_tr_used, cpu);
 433                                                                i++, p++) {
 434                        if (p->pte & 0x1)
 435                                if (is_tr_overlap(p, va, log_size)) {
 436                                        printk(KERN_DEBUG "Overlapped Entry"
 437                                                "Inserted for TR Reigster!!\n");
 438                                        goto out;
 439                                }
 440                }
 441        }
 442
 443        for (i = IA64_TR_ALLOC_BASE; i < per_cpu(ia64_tr_num, cpu); i++) {
 444                switch (target_mask & 0x3) {
 445                case 1:
 446                        if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1))
 447                                goto found;
 448                        continue;
 449                case 2:
 450                        if (!(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
 451                                goto found;
 452                        continue;
 453                case 3:
 454                        if (!(__per_cpu_idtrs[cpu][0][i].pte & 0x1) &&
 455                                !(__per_cpu_idtrs[cpu][1][i].pte & 0x1))
 456                                goto found;
 457                        continue;
 458                default:
 459                        r = -EINVAL;
 460                        goto out;
 461                }
 462        }
 463found:
 464        if (i >= per_cpu(ia64_tr_num, cpu))
 465                return -EBUSY;
 466
 467        /*Record tr info for mca hander use!*/
 468        if (i > per_cpu(ia64_tr_used, cpu))
 469                per_cpu(ia64_tr_used, cpu) = i;
 470
 471        psr = ia64_clear_ic();
 472        if (target_mask & 0x1) {
 473                ia64_itr(0x1, i, va, pte, log_size);
 474                ia64_srlz_i();
 475                p = &__per_cpu_idtrs[cpu][0][i];
 476                p->ifa = va;
 477                p->pte = pte;
 478                p->itir = log_size << 2;
 479                p->rr = ia64_get_rr(va);
 480        }
 481        if (target_mask & 0x2) {
 482                ia64_itr(0x2, i, va, pte, log_size);
 483                ia64_srlz_i();
 484                p = &__per_cpu_idtrs[cpu][1][i];
 485                p->ifa = va;
 486                p->pte = pte;
 487                p->itir = log_size << 2;
 488                p->rr = ia64_get_rr(va);
 489        }
 490        ia64_set_psr(psr);
 491        r = i;
 492out:
 493        return r;
 494}
 495EXPORT_SYMBOL_GPL(ia64_itr_entry);
 496
 497/*
 498 * ia64_purge_tr
 499 *
 500 * target_mask: 0x1: purge itr, 0x2 : purge dtr, 0x3 purge idtr.
 501 * slot: slot number to be freed.
 502 *
 503 * Must be called with preemption disabled.
 504 */
 505void ia64_ptr_entry(u64 target_mask, int slot)
 506{
 507        int cpu = smp_processor_id();
 508        int i;
 509        struct ia64_tr_entry *p;
 510
 511        if (slot < IA64_TR_ALLOC_BASE || slot >= per_cpu(ia64_tr_num, cpu))
 512                return;
 513
 514        if (target_mask & 0x1) {
 515                p = &__per_cpu_idtrs[cpu][0][slot];
 516                if ((p->pte&0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
 517                        p->pte = 0;
 518                        ia64_ptr(0x1, p->ifa, p->itir>>2);
 519                        ia64_srlz_i();
 520                }
 521        }
 522
 523        if (target_mask & 0x2) {
 524                p = &__per_cpu_idtrs[cpu][1][slot];
 525                if ((p->pte & 0x1) && is_tr_overlap(p, p->ifa, p->itir>>2)) {
 526                        p->pte = 0;
 527                        ia64_ptr(0x2, p->ifa, p->itir>>2);
 528                        ia64_srlz_i();
 529                }
 530        }
 531
 532        for (i = per_cpu(ia64_tr_used, cpu); i >= IA64_TR_ALLOC_BASE; i--) {
 533                if ((__per_cpu_idtrs[cpu][0][i].pte & 0x1) ||
 534                                (__per_cpu_idtrs[cpu][1][i].pte & 0x1))
 535                        break;
 536        }
 537        per_cpu(ia64_tr_used, cpu) = i;
 538}
 539EXPORT_SYMBOL_GPL(ia64_ptr_entry);
 540