linux/arch/blackfin/mach-common/cpufreq.c
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   1/*
   2 * File:         arch/blackfin/mach-common/cpufreq.c
   3 * Based on:
   4 * Author:
   5 *
   6 * Created:
   7 * Description:  Blackfin core clock scaling
   8 *
   9 * Modified:
  10 *               Copyright 2004-2008 Analog Devices Inc.
  11 *
  12 * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  13 *
  14 * This program is free software; you can redistribute it and/or modify
  15 * it under the terms of the GNU General Public License as published by
  16 * the Free Software Foundation; either version 2 of the License, or
  17 * (at your option) any later version.
  18 *
  19 * This program is distributed in the hope that it will be useful,
  20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22 * GNU General Public License for more details.
  23 *
  24 * You should have received a copy of the GNU General Public License
  25 * along with this program; if not, see the file COPYING, or write
  26 * to the Free Software Foundation, Inc.,
  27 * 51 Franklin St, Fifth Floor, Boston, MA      02110-1301      USA
  28 */
  29
  30#include <linux/kernel.h>
  31#include <linux/types.h>
  32#include <linux/init.h>
  33#include <linux/cpufreq.h>
  34#include <linux/fs.h>
  35#include <asm/blackfin.h>
  36#include <asm/time.h>
  37
  38
  39/* this is the table of CCLK frequencies, in Hz */
  40/* .index is the entry in the auxillary dpm_state_table[] */
  41static struct cpufreq_frequency_table bfin_freq_table[] = {
  42        {
  43                .frequency = CPUFREQ_TABLE_END,
  44                .index = 0,
  45        },
  46        {
  47                .frequency = CPUFREQ_TABLE_END,
  48                .index = 1,
  49        },
  50        {
  51                .frequency = CPUFREQ_TABLE_END,
  52                .index = 2,
  53        },
  54        {
  55                .frequency = CPUFREQ_TABLE_END,
  56                .index = 0,
  57        },
  58};
  59
  60static struct bfin_dpm_state {
  61        unsigned int csel; /* system clock divider */
  62        unsigned int tscale; /* change the divider on the core timer interrupt */
  63} dpm_state_table[3];
  64
  65/*
  66   normalized to maximum frequncy offset for CYCLES,
  67   used in time-ts cycles clock source, but could be used
  68   somewhere also.
  69 */
  70unsigned long long __bfin_cycles_off;
  71unsigned int __bfin_cycles_mod;
  72
  73/**************************************************************************/
  74
  75static unsigned int bfin_getfreq(unsigned int cpu)
  76{
  77        /* The driver only support single cpu */
  78        if (cpu != 0)
  79                return -1;
  80
  81        return get_cclk();
  82}
  83
  84
  85static int bfin_target(struct cpufreq_policy *policy,
  86                        unsigned int target_freq, unsigned int relation)
  87{
  88        unsigned int index, plldiv, tscale;
  89        unsigned long flags, cclk_hz;
  90        struct cpufreq_freqs freqs;
  91        cycles_t cycles;
  92
  93        if (cpufreq_frequency_table_target(policy, bfin_freq_table,
  94                 target_freq, relation, &index))
  95                return -EINVAL;
  96
  97        cclk_hz = bfin_freq_table[index].frequency;
  98
  99        freqs.old = bfin_getfreq(0);
 100        freqs.new = cclk_hz;
 101        freqs.cpu = 0;
 102
 103        pr_debug("cpufreq: changing cclk to %lu; target = %u, oldfreq = %u\n",
 104                 cclk_hz, target_freq, freqs.old);
 105
 106        cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 107        local_irq_save(flags);
 108                plldiv = (bfin_read_PLL_DIV() & SSEL) | dpm_state_table[index].csel;
 109                tscale = dpm_state_table[index].tscale;
 110                bfin_write_PLL_DIV(plldiv);
 111                /* we have to adjust the core timer, because it is using cclk */
 112                bfin_write_TSCALE(tscale);
 113                cycles = get_cycles();
 114                SSYNC();
 115        cycles += 10; /* ~10 cycles we loose after get_cycles() */
 116        __bfin_cycles_off += (cycles << __bfin_cycles_mod) - (cycles << index);
 117        __bfin_cycles_mod = index;
 118        local_irq_restore(flags);
 119        /* TODO: just test case for cycles clock source, remove later */
 120        pr_debug("cpufreq: done\n");
 121        cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 122
 123        return 0;
 124}
 125
 126static int bfin_verify_speed(struct cpufreq_policy *policy)
 127{
 128        return cpufreq_frequency_table_verify(policy, bfin_freq_table);
 129}
 130
 131static int __init __bfin_cpu_init(struct cpufreq_policy *policy)
 132{
 133
 134        unsigned long cclk, sclk, csel, min_cclk;
 135        int index;
 136
 137        if (policy->cpu != 0)
 138                return -EINVAL;
 139
 140        cclk = get_cclk();
 141        sclk = get_sclk();
 142
 143#if ANOMALY_05000273 || (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_DCACHE))
 144        min_cclk = sclk * 2;
 145#else
 146        min_cclk = sclk;
 147#endif
 148        csel = ((bfin_read_PLL_DIV() & CSEL) >> 4);
 149
 150        for (index = 0;  (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) {
 151                bfin_freq_table[index].frequency = cclk >> index;
 152                dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
 153                dpm_state_table[index].tscale =  (TIME_SCALE / (1 << csel)) - 1;
 154
 155                pr_debug("cpufreq: freq:%d csel:%d tscale:%d\n",
 156                                                 bfin_freq_table[index].frequency,
 157                                                 dpm_state_table[index].csel,
 158                                                 dpm_state_table[index].tscale);
 159        }
 160
 161        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
 162
 163        policy->cpuinfo.transition_latency = (bfin_read_PLL_LOCKCNT() / (sclk / 1000000)) * 1000;
 164        /*Now ,only support one cpu */
 165        policy->cur = cclk;
 166        cpufreq_frequency_table_get_attr(bfin_freq_table, policy->cpu);
 167        return cpufreq_frequency_table_cpuinfo(policy, bfin_freq_table);
 168}
 169
 170static struct freq_attr *bfin_freq_attr[] = {
 171        &cpufreq_freq_attr_scaling_available_freqs,
 172        NULL,
 173};
 174
 175static struct cpufreq_driver bfin_driver = {
 176        .verify = bfin_verify_speed,
 177        .target = bfin_target,
 178        .get = bfin_getfreq,
 179        .init = __bfin_cpu_init,
 180        .name = "bfin cpufreq",
 181        .owner = THIS_MODULE,
 182        .attr = bfin_freq_attr,
 183};
 184
 185static int __init bfin_cpu_init(void)
 186{
 187        return cpufreq_register_driver(&bfin_driver);
 188}
 189
 190static void __exit bfin_cpu_exit(void)
 191{
 192        cpufreq_unregister_driver(&bfin_driver);
 193}
 194
 195MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
 196MODULE_DESCRIPTION("cpufreq driver for Blackfin");
 197MODULE_LICENSE("GPL");
 198
 199module_init(bfin_cpu_init);
 200module_exit(bfin_cpu_exit);
 201