linux/arch/avr32/mach-at32ap/at32ap700x.c
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   1/*
   2 * Copyright (C) 2005-2006 Atmel Corporation
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 as
   6 * published by the Free Software Foundation.
   7 */
   8#include <linux/clk.h>
   9#include <linux/delay.h>
  10#include <linux/dw_dmac.h>
  11#include <linux/fb.h>
  12#include <linux/init.h>
  13#include <linux/platform_device.h>
  14#include <linux/dma-mapping.h>
  15#include <linux/gpio.h>
  16#include <linux/spi/spi.h>
  17#include <linux/usb/atmel_usba_udc.h>
  18
  19#include <asm/atmel-mci.h>
  20#include <asm/io.h>
  21#include <asm/irq.h>
  22
  23#include <mach/at32ap700x.h>
  24#include <mach/board.h>
  25#include <mach/hmatrix.h>
  26#include <mach/portmux.h>
  27#include <mach/sram.h>
  28
  29#include <video/atmel_lcdc.h>
  30
  31#include "clock.h"
  32#include "pio.h"
  33#include "pm.h"
  34
  35
  36#define PBMEM(base)                                     \
  37        {                                               \
  38                .start          = base,                 \
  39                .end            = base + 0x3ff,         \
  40                .flags          = IORESOURCE_MEM,       \
  41        }
  42#define IRQ(num)                                        \
  43        {                                               \
  44                .start          = num,                  \
  45                .end            = num,                  \
  46                .flags          = IORESOURCE_IRQ,       \
  47        }
  48#define NAMED_IRQ(num, _name)                           \
  49        {                                               \
  50                .start          = num,                  \
  51                .end            = num,                  \
  52                .name           = _name,                \
  53                .flags          = IORESOURCE_IRQ,       \
  54        }
  55
  56/* REVISIT these assume *every* device supports DMA, but several
  57 * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
  58 */
  59#define DEFINE_DEV(_name, _id)                                  \
  60static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  61static struct platform_device _name##_id##_device = {           \
  62        .name           = #_name,                               \
  63        .id             = _id,                                  \
  64        .dev            = {                                     \
  65                .dma_mask = &_name##_id##_dma_mask,             \
  66                .coherent_dma_mask = DMA_32BIT_MASK,            \
  67        },                                                      \
  68        .resource       = _name##_id##_resource,                \
  69        .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  70}
  71#define DEFINE_DEV_DATA(_name, _id)                             \
  72static u64 _name##_id##_dma_mask = DMA_32BIT_MASK;              \
  73static struct platform_device _name##_id##_device = {           \
  74        .name           = #_name,                               \
  75        .id             = _id,                                  \
  76        .dev            = {                                     \
  77                .dma_mask = &_name##_id##_dma_mask,             \
  78                .platform_data  = &_name##_id##_data,           \
  79                .coherent_dma_mask = DMA_32BIT_MASK,            \
  80        },                                                      \
  81        .resource       = _name##_id##_resource,                \
  82        .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  83}
  84
  85#define select_peripheral(pin, periph, flags)                   \
  86        at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  87
  88#define DEV_CLK(_name, devname, bus, _index)                    \
  89static struct clk devname##_##_name = {                         \
  90        .name           = #_name,                               \
  91        .dev            = &devname##_device.dev,                \
  92        .parent         = &bus##_clk,                           \
  93        .mode           = bus##_clk_mode,                       \
  94        .get_rate       = bus##_clk_get_rate,                   \
  95        .index          = _index,                               \
  96}
  97
  98static DEFINE_SPINLOCK(pm_lock);
  99
 100static struct clk osc0;
 101static struct clk osc1;
 102
 103static unsigned long osc_get_rate(struct clk *clk)
 104{
 105        return at32_board_osc_rates[clk->index];
 106}
 107
 108static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
 109{
 110        unsigned long div, mul, rate;
 111
 112        div = PM_BFEXT(PLLDIV, control) + 1;
 113        mul = PM_BFEXT(PLLMUL, control) + 1;
 114
 115        rate = clk->parent->get_rate(clk->parent);
 116        rate = (rate + div / 2) / div;
 117        rate *= mul;
 118
 119        return rate;
 120}
 121
 122static long pll_set_rate(struct clk *clk, unsigned long rate,
 123                         u32 *pll_ctrl)
 124{
 125        unsigned long mul;
 126        unsigned long mul_best_fit = 0;
 127        unsigned long div;
 128        unsigned long div_min;
 129        unsigned long div_max;
 130        unsigned long div_best_fit = 0;
 131        unsigned long base;
 132        unsigned long pll_in;
 133        unsigned long actual = 0;
 134        unsigned long rate_error;
 135        unsigned long rate_error_prev = ~0UL;
 136        u32 ctrl;
 137
 138        /* Rate must be between 80 MHz and 200 Mhz. */
 139        if (rate < 80000000UL || rate > 200000000UL)
 140                return -EINVAL;
 141
 142        ctrl = PM_BF(PLLOPT, 4);
 143        base = clk->parent->get_rate(clk->parent);
 144
 145        /* PLL input frequency must be between 6 MHz and 32 MHz. */
 146        div_min = DIV_ROUND_UP(base, 32000000UL);
 147        div_max = base / 6000000UL;
 148
 149        if (div_max < div_min)
 150                return -EINVAL;
 151
 152        for (div = div_min; div <= div_max; div++) {
 153                pll_in = (base + div / 2) / div;
 154                mul = (rate + pll_in / 2) / pll_in;
 155
 156                if (mul == 0)
 157                        continue;
 158
 159                actual = pll_in * mul;
 160                rate_error = abs(actual - rate);
 161
 162                if (rate_error < rate_error_prev) {
 163                        mul_best_fit = mul;
 164                        div_best_fit = div;
 165                        rate_error_prev = rate_error;
 166                }
 167
 168                if (rate_error == 0)
 169                        break;
 170        }
 171
 172        if (div_best_fit == 0)
 173                return -EINVAL;
 174
 175        ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
 176        ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
 177        ctrl |= PM_BF(PLLCOUNT, 16);
 178
 179        if (clk->parent == &osc1)
 180                ctrl |= PM_BIT(PLLOSC);
 181
 182        *pll_ctrl = ctrl;
 183
 184        return actual;
 185}
 186
 187static unsigned long pll0_get_rate(struct clk *clk)
 188{
 189        u32 control;
 190
 191        control = pm_readl(PLL0);
 192
 193        return pll_get_rate(clk, control);
 194}
 195
 196static void pll1_mode(struct clk *clk, int enabled)
 197{
 198        unsigned long timeout;
 199        u32 status;
 200        u32 ctrl;
 201
 202        ctrl = pm_readl(PLL1);
 203
 204        if (enabled) {
 205                if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
 206                        pr_debug("clk %s: failed to enable, rate not set\n",
 207                                        clk->name);
 208                        return;
 209                }
 210
 211                ctrl |= PM_BIT(PLLEN);
 212                pm_writel(PLL1, ctrl);
 213
 214                /* Wait for PLL lock. */
 215                for (timeout = 10000; timeout; timeout--) {
 216                        status = pm_readl(ISR);
 217                        if (status & PM_BIT(LOCK1))
 218                                break;
 219                        udelay(10);
 220                }
 221
 222                if (!(status & PM_BIT(LOCK1)))
 223                        printk(KERN_ERR "clk %s: timeout waiting for lock\n",
 224                                        clk->name);
 225        } else {
 226                ctrl &= ~PM_BIT(PLLEN);
 227                pm_writel(PLL1, ctrl);
 228        }
 229}
 230
 231static unsigned long pll1_get_rate(struct clk *clk)
 232{
 233        u32 control;
 234
 235        control = pm_readl(PLL1);
 236
 237        return pll_get_rate(clk, control);
 238}
 239
 240static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
 241{
 242        u32 ctrl = 0;
 243        unsigned long actual_rate;
 244
 245        actual_rate = pll_set_rate(clk, rate, &ctrl);
 246
 247        if (apply) {
 248                if (actual_rate != rate)
 249                        return -EINVAL;
 250                if (clk->users > 0)
 251                        return -EBUSY;
 252                pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
 253                                clk->name, rate, actual_rate);
 254                pm_writel(PLL1, ctrl);
 255        }
 256
 257        return actual_rate;
 258}
 259
 260static int pll1_set_parent(struct clk *clk, struct clk *parent)
 261{
 262        u32 ctrl;
 263
 264        if (clk->users > 0)
 265                return -EBUSY;
 266
 267        ctrl = pm_readl(PLL1);
 268        WARN_ON(ctrl & PM_BIT(PLLEN));
 269
 270        if (parent == &osc0)
 271                ctrl &= ~PM_BIT(PLLOSC);
 272        else if (parent == &osc1)
 273                ctrl |= PM_BIT(PLLOSC);
 274        else
 275                return -EINVAL;
 276
 277        pm_writel(PLL1, ctrl);
 278        clk->parent = parent;
 279
 280        return 0;
 281}
 282
 283/*
 284 * The AT32AP7000 has five primary clock sources: One 32kHz
 285 * oscillator, two crystal oscillators and two PLLs.
 286 */
 287static struct clk osc32k = {
 288        .name           = "osc32k",
 289        .get_rate       = osc_get_rate,
 290        .users          = 1,
 291        .index          = 0,
 292};
 293static struct clk osc0 = {
 294        .name           = "osc0",
 295        .get_rate       = osc_get_rate,
 296        .users          = 1,
 297        .index          = 1,
 298};
 299static struct clk osc1 = {
 300        .name           = "osc1",
 301        .get_rate       = osc_get_rate,
 302        .index          = 2,
 303};
 304static struct clk pll0 = {
 305        .name           = "pll0",
 306        .get_rate       = pll0_get_rate,
 307        .parent         = &osc0,
 308};
 309static struct clk pll1 = {
 310        .name           = "pll1",
 311        .mode           = pll1_mode,
 312        .get_rate       = pll1_get_rate,
 313        .set_rate       = pll1_set_rate,
 314        .set_parent     = pll1_set_parent,
 315        .parent         = &osc0,
 316};
 317
 318/*
 319 * The main clock can be either osc0 or pll0.  The boot loader may
 320 * have chosen one for us, so we don't really know which one until we
 321 * have a look at the SM.
 322 */
 323static struct clk *main_clock;
 324
 325/*
 326 * Synchronous clocks are generated from the main clock. The clocks
 327 * must satisfy the constraint
 328 *   fCPU >= fHSB >= fPB
 329 * i.e. each clock must not be faster than its parent.
 330 */
 331static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 332{
 333        return main_clock->get_rate(main_clock) >> shift;
 334};
 335
 336static void cpu_clk_mode(struct clk *clk, int enabled)
 337{
 338        unsigned long flags;
 339        u32 mask;
 340
 341        spin_lock_irqsave(&pm_lock, flags);
 342        mask = pm_readl(CPU_MASK);
 343        if (enabled)
 344                mask |= 1 << clk->index;
 345        else
 346                mask &= ~(1 << clk->index);
 347        pm_writel(CPU_MASK, mask);
 348        spin_unlock_irqrestore(&pm_lock, flags);
 349}
 350
 351static unsigned long cpu_clk_get_rate(struct clk *clk)
 352{
 353        unsigned long cksel, shift = 0;
 354
 355        cksel = pm_readl(CKSEL);
 356        if (cksel & PM_BIT(CPUDIV))
 357                shift = PM_BFEXT(CPUSEL, cksel) + 1;
 358
 359        return bus_clk_get_rate(clk, shift);
 360}
 361
 362static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
 363{
 364        u32 control;
 365        unsigned long parent_rate, child_div, actual_rate, div;
 366
 367        parent_rate = clk->parent->get_rate(clk->parent);
 368        control = pm_readl(CKSEL);
 369
 370        if (control & PM_BIT(HSBDIV))
 371                child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
 372        else
 373                child_div = 1;
 374
 375        if (rate > 3 * (parent_rate / 4) || child_div == 1) {
 376                actual_rate = parent_rate;
 377                control &= ~PM_BIT(CPUDIV);
 378        } else {
 379                unsigned int cpusel;
 380                div = (parent_rate + rate / 2) / rate;
 381                if (div > child_div)
 382                        div = child_div;
 383                cpusel = (div > 1) ? (fls(div) - 2) : 0;
 384                control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
 385                actual_rate = parent_rate / (1 << (cpusel + 1));
 386        }
 387
 388        pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
 389                        clk->name, rate, actual_rate);
 390
 391        if (apply)
 392                pm_writel(CKSEL, control);
 393
 394        return actual_rate;
 395}
 396
 397static void hsb_clk_mode(struct clk *clk, int enabled)
 398{
 399        unsigned long flags;
 400        u32 mask;
 401
 402        spin_lock_irqsave(&pm_lock, flags);
 403        mask = pm_readl(HSB_MASK);
 404        if (enabled)
 405                mask |= 1 << clk->index;
 406        else
 407                mask &= ~(1 << clk->index);
 408        pm_writel(HSB_MASK, mask);
 409        spin_unlock_irqrestore(&pm_lock, flags);
 410}
 411
 412static unsigned long hsb_clk_get_rate(struct clk *clk)
 413{
 414        unsigned long cksel, shift = 0;
 415
 416        cksel = pm_readl(CKSEL);
 417        if (cksel & PM_BIT(HSBDIV))
 418                shift = PM_BFEXT(HSBSEL, cksel) + 1;
 419
 420        return bus_clk_get_rate(clk, shift);
 421}
 422
 423static void pba_clk_mode(struct clk *clk, int enabled)
 424{
 425        unsigned long flags;
 426        u32 mask;
 427
 428        spin_lock_irqsave(&pm_lock, flags);
 429        mask = pm_readl(PBA_MASK);
 430        if (enabled)
 431                mask |= 1 << clk->index;
 432        else
 433                mask &= ~(1 << clk->index);
 434        pm_writel(PBA_MASK, mask);
 435        spin_unlock_irqrestore(&pm_lock, flags);
 436}
 437
 438static unsigned long pba_clk_get_rate(struct clk *clk)
 439{
 440        unsigned long cksel, shift = 0;
 441
 442        cksel = pm_readl(CKSEL);
 443        if (cksel & PM_BIT(PBADIV))
 444                shift = PM_BFEXT(PBASEL, cksel) + 1;
 445
 446        return bus_clk_get_rate(clk, shift);
 447}
 448
 449static void pbb_clk_mode(struct clk *clk, int enabled)
 450{
 451        unsigned long flags;
 452        u32 mask;
 453
 454        spin_lock_irqsave(&pm_lock, flags);
 455        mask = pm_readl(PBB_MASK);
 456        if (enabled)
 457                mask |= 1 << clk->index;
 458        else
 459                mask &= ~(1 << clk->index);
 460        pm_writel(PBB_MASK, mask);
 461        spin_unlock_irqrestore(&pm_lock, flags);
 462}
 463
 464static unsigned long pbb_clk_get_rate(struct clk *clk)
 465{
 466        unsigned long cksel, shift = 0;
 467
 468        cksel = pm_readl(CKSEL);
 469        if (cksel & PM_BIT(PBBDIV))
 470                shift = PM_BFEXT(PBBSEL, cksel) + 1;
 471
 472        return bus_clk_get_rate(clk, shift);
 473}
 474
 475static struct clk cpu_clk = {
 476        .name           = "cpu",
 477        .get_rate       = cpu_clk_get_rate,
 478        .set_rate       = cpu_clk_set_rate,
 479        .users          = 1,
 480};
 481static struct clk hsb_clk = {
 482        .name           = "hsb",
 483        .parent         = &cpu_clk,
 484        .get_rate       = hsb_clk_get_rate,
 485};
 486static struct clk pba_clk = {
 487        .name           = "pba",
 488        .parent         = &hsb_clk,
 489        .mode           = hsb_clk_mode,
 490        .get_rate       = pba_clk_get_rate,
 491        .index          = 1,
 492};
 493static struct clk pbb_clk = {
 494        .name           = "pbb",
 495        .parent         = &hsb_clk,
 496        .mode           = hsb_clk_mode,
 497        .get_rate       = pbb_clk_get_rate,
 498        .users          = 1,
 499        .index          = 2,
 500};
 501
 502/* --------------------------------------------------------------------
 503 *  Generic Clock operations
 504 * -------------------------------------------------------------------- */
 505
 506static void genclk_mode(struct clk *clk, int enabled)
 507{
 508        u32 control;
 509
 510        control = pm_readl(GCCTRL(clk->index));
 511        if (enabled)
 512                control |= PM_BIT(CEN);
 513        else
 514                control &= ~PM_BIT(CEN);
 515        pm_writel(GCCTRL(clk->index), control);
 516}
 517
 518static unsigned long genclk_get_rate(struct clk *clk)
 519{
 520        u32 control;
 521        unsigned long div = 1;
 522
 523        control = pm_readl(GCCTRL(clk->index));
 524        if (control & PM_BIT(DIVEN))
 525                div = 2 * (PM_BFEXT(DIV, control) + 1);
 526
 527        return clk->parent->get_rate(clk->parent) / div;
 528}
 529
 530static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 531{
 532        u32 control;
 533        unsigned long parent_rate, actual_rate, div;
 534
 535        parent_rate = clk->parent->get_rate(clk->parent);
 536        control = pm_readl(GCCTRL(clk->index));
 537
 538        if (rate > 3 * parent_rate / 4) {
 539                actual_rate = parent_rate;
 540                control &= ~PM_BIT(DIVEN);
 541        } else {
 542                div = (parent_rate + rate) / (2 * rate) - 1;
 543                control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
 544                actual_rate = parent_rate / (2 * (div + 1));
 545        }
 546
 547        dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
 548                clk->name, rate, actual_rate);
 549
 550        if (apply)
 551                pm_writel(GCCTRL(clk->index), control);
 552
 553        return actual_rate;
 554}
 555
 556int genclk_set_parent(struct clk *clk, struct clk *parent)
 557{
 558        u32 control;
 559
 560        dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
 561                clk->name, parent->name, clk->parent->name);
 562
 563        control = pm_readl(GCCTRL(clk->index));
 564
 565        if (parent == &osc1 || parent == &pll1)
 566                control |= PM_BIT(OSCSEL);
 567        else if (parent == &osc0 || parent == &pll0)
 568                control &= ~PM_BIT(OSCSEL);
 569        else
 570                return -EINVAL;
 571
 572        if (parent == &pll0 || parent == &pll1)
 573                control |= PM_BIT(PLLSEL);
 574        else
 575                control &= ~PM_BIT(PLLSEL);
 576
 577        pm_writel(GCCTRL(clk->index), control);
 578        clk->parent = parent;
 579
 580        return 0;
 581}
 582
 583static void __init genclk_init_parent(struct clk *clk)
 584{
 585        u32 control;
 586        struct clk *parent;
 587
 588        BUG_ON(clk->index > 7);
 589
 590        control = pm_readl(GCCTRL(clk->index));
 591        if (control & PM_BIT(OSCSEL))
 592                parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
 593        else
 594                parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
 595
 596        clk->parent = parent;
 597}
 598
 599static struct dw_dma_platform_data dw_dmac0_data = {
 600        .nr_channels    = 3,
 601};
 602
 603static struct resource dw_dmac0_resource[] = {
 604        PBMEM(0xff200000),
 605        IRQ(2),
 606};
 607DEFINE_DEV_DATA(dw_dmac, 0);
 608DEV_CLK(hclk, dw_dmac0, hsb, 10);
 609
 610/* --------------------------------------------------------------------
 611 *  System peripherals
 612 * -------------------------------------------------------------------- */
 613static struct resource at32_pm0_resource[] = {
 614        {
 615                .start  = 0xfff00000,
 616                .end    = 0xfff0007f,
 617                .flags  = IORESOURCE_MEM,
 618        },
 619        IRQ(20),
 620};
 621
 622static struct resource at32ap700x_rtc0_resource[] = {
 623        {
 624                .start  = 0xfff00080,
 625                .end    = 0xfff000af,
 626                .flags  = IORESOURCE_MEM,
 627        },
 628        IRQ(21),
 629};
 630
 631static struct resource at32_wdt0_resource[] = {
 632        {
 633                .start  = 0xfff000b0,
 634                .end    = 0xfff000cf,
 635                .flags  = IORESOURCE_MEM,
 636        },
 637};
 638
 639static struct resource at32_eic0_resource[] = {
 640        {
 641                .start  = 0xfff00100,
 642                .end    = 0xfff0013f,
 643                .flags  = IORESOURCE_MEM,
 644        },
 645        IRQ(19),
 646};
 647
 648DEFINE_DEV(at32_pm, 0);
 649DEFINE_DEV(at32ap700x_rtc, 0);
 650DEFINE_DEV(at32_wdt, 0);
 651DEFINE_DEV(at32_eic, 0);
 652
 653/*
 654 * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
 655 * is always running.
 656 */
 657static struct clk at32_pm_pclk = {
 658        .name           = "pclk",
 659        .dev            = &at32_pm0_device.dev,
 660        .parent         = &pbb_clk,
 661        .mode           = pbb_clk_mode,
 662        .get_rate       = pbb_clk_get_rate,
 663        .users          = 1,
 664        .index          = 0,
 665};
 666
 667static struct resource intc0_resource[] = {
 668        PBMEM(0xfff00400),
 669};
 670struct platform_device at32_intc0_device = {
 671        .name           = "intc",
 672        .id             = 0,
 673        .resource       = intc0_resource,
 674        .num_resources  = ARRAY_SIZE(intc0_resource),
 675};
 676DEV_CLK(pclk, at32_intc0, pbb, 1);
 677
 678static struct clk ebi_clk = {
 679        .name           = "ebi",
 680        .parent         = &hsb_clk,
 681        .mode           = hsb_clk_mode,
 682        .get_rate       = hsb_clk_get_rate,
 683        .users          = 1,
 684};
 685static struct clk hramc_clk = {
 686        .name           = "hramc",
 687        .parent         = &hsb_clk,
 688        .mode           = hsb_clk_mode,
 689        .get_rate       = hsb_clk_get_rate,
 690        .users          = 1,
 691        .index          = 3,
 692};
 693static struct clk sdramc_clk = {
 694        .name           = "sdramc_clk",
 695        .parent         = &pbb_clk,
 696        .mode           = pbb_clk_mode,
 697        .get_rate       = pbb_clk_get_rate,
 698        .users          = 1,
 699        .index          = 14,
 700};
 701
 702static struct resource smc0_resource[] = {
 703        PBMEM(0xfff03400),
 704};
 705DEFINE_DEV(smc, 0);
 706DEV_CLK(pclk, smc0, pbb, 13);
 707DEV_CLK(mck, smc0, hsb, 0);
 708
 709static struct platform_device pdc_device = {
 710        .name           = "pdc",
 711        .id             = 0,
 712};
 713DEV_CLK(hclk, pdc, hsb, 4);
 714DEV_CLK(pclk, pdc, pba, 16);
 715
 716static struct clk pico_clk = {
 717        .name           = "pico",
 718        .parent         = &cpu_clk,
 719        .mode           = cpu_clk_mode,
 720        .get_rate       = cpu_clk_get_rate,
 721        .users          = 1,
 722};
 723
 724/* --------------------------------------------------------------------
 725 * HMATRIX
 726 * -------------------------------------------------------------------- */
 727
 728struct clk at32_hmatrix_clk = {
 729        .name           = "hmatrix_clk",
 730        .parent         = &pbb_clk,
 731        .mode           = pbb_clk_mode,
 732        .get_rate       = pbb_clk_get_rate,
 733        .index          = 2,
 734        .users          = 1,
 735};
 736
 737/*
 738 * Set bits in the HMATRIX Special Function Register (SFR) used by the
 739 * External Bus Interface (EBI). This can be used to enable special
 740 * features like CompactFlash support, NAND Flash support, etc. on
 741 * certain chipselects.
 742 */
 743static inline void set_ebi_sfr_bits(u32 mask)
 744{
 745        hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
 746}
 747
 748/* --------------------------------------------------------------------
 749 *  Timer/Counter (TC)
 750 * -------------------------------------------------------------------- */
 751
 752static struct resource at32_tcb0_resource[] = {
 753        PBMEM(0xfff00c00),
 754        IRQ(22),
 755};
 756static struct platform_device at32_tcb0_device = {
 757        .name           = "atmel_tcb",
 758        .id             = 0,
 759        .resource       = at32_tcb0_resource,
 760        .num_resources  = ARRAY_SIZE(at32_tcb0_resource),
 761};
 762DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
 763
 764static struct resource at32_tcb1_resource[] = {
 765        PBMEM(0xfff01000),
 766        IRQ(23),
 767};
 768static struct platform_device at32_tcb1_device = {
 769        .name           = "atmel_tcb",
 770        .id             = 1,
 771        .resource       = at32_tcb1_resource,
 772        .num_resources  = ARRAY_SIZE(at32_tcb1_resource),
 773};
 774DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
 775
 776/* --------------------------------------------------------------------
 777 *  PIO
 778 * -------------------------------------------------------------------- */
 779
 780static struct resource pio0_resource[] = {
 781        PBMEM(0xffe02800),
 782        IRQ(13),
 783};
 784DEFINE_DEV(pio, 0);
 785DEV_CLK(mck, pio0, pba, 10);
 786
 787static struct resource pio1_resource[] = {
 788        PBMEM(0xffe02c00),
 789        IRQ(14),
 790};
 791DEFINE_DEV(pio, 1);
 792DEV_CLK(mck, pio1, pba, 11);
 793
 794static struct resource pio2_resource[] = {
 795        PBMEM(0xffe03000),
 796        IRQ(15),
 797};
 798DEFINE_DEV(pio, 2);
 799DEV_CLK(mck, pio2, pba, 12);
 800
 801static struct resource pio3_resource[] = {
 802        PBMEM(0xffe03400),
 803        IRQ(16),
 804};
 805DEFINE_DEV(pio, 3);
 806DEV_CLK(mck, pio3, pba, 13);
 807
 808static struct resource pio4_resource[] = {
 809        PBMEM(0xffe03800),
 810        IRQ(17),
 811};
 812DEFINE_DEV(pio, 4);
 813DEV_CLK(mck, pio4, pba, 14);
 814
 815void __init at32_add_system_devices(void)
 816{
 817        platform_device_register(&at32_pm0_device);
 818        platform_device_register(&at32_intc0_device);
 819        platform_device_register(&at32ap700x_rtc0_device);
 820        platform_device_register(&at32_wdt0_device);
 821        platform_device_register(&at32_eic0_device);
 822        platform_device_register(&smc0_device);
 823        platform_device_register(&pdc_device);
 824        platform_device_register(&dw_dmac0_device);
 825
 826        platform_device_register(&at32_tcb0_device);
 827        platform_device_register(&at32_tcb1_device);
 828
 829        platform_device_register(&pio0_device);
 830        platform_device_register(&pio1_device);
 831        platform_device_register(&pio2_device);
 832        platform_device_register(&pio3_device);
 833        platform_device_register(&pio4_device);
 834}
 835
 836/* --------------------------------------------------------------------
 837 *  PSIF
 838 * -------------------------------------------------------------------- */
 839static struct resource atmel_psif0_resource[] __initdata = {
 840        {
 841                .start  = 0xffe03c00,
 842                .end    = 0xffe03cff,
 843                .flags  = IORESOURCE_MEM,
 844        },
 845        IRQ(18),
 846};
 847static struct clk atmel_psif0_pclk = {
 848        .name           = "pclk",
 849        .parent         = &pba_clk,
 850        .mode           = pba_clk_mode,
 851        .get_rate       = pba_clk_get_rate,
 852        .index          = 15,
 853};
 854
 855static struct resource atmel_psif1_resource[] __initdata = {
 856        {
 857                .start  = 0xffe03d00,
 858                .end    = 0xffe03dff,
 859                .flags  = IORESOURCE_MEM,
 860        },
 861        IRQ(18),
 862};
 863static struct clk atmel_psif1_pclk = {
 864        .name           = "pclk",
 865        .parent         = &pba_clk,
 866        .mode           = pba_clk_mode,
 867        .get_rate       = pba_clk_get_rate,
 868        .index          = 15,
 869};
 870
 871struct platform_device *__init at32_add_device_psif(unsigned int id)
 872{
 873        struct platform_device *pdev;
 874
 875        if (!(id == 0 || id == 1))
 876                return NULL;
 877
 878        pdev = platform_device_alloc("atmel_psif", id);
 879        if (!pdev)
 880                return NULL;
 881
 882        switch (id) {
 883        case 0:
 884                if (platform_device_add_resources(pdev, atmel_psif0_resource,
 885                                        ARRAY_SIZE(atmel_psif0_resource)))
 886                        goto err_add_resources;
 887                atmel_psif0_pclk.dev = &pdev->dev;
 888                select_peripheral(PA(8), PERIPH_A, 0); /* CLOCK */
 889                select_peripheral(PA(9), PERIPH_A, 0); /* DATA  */
 890                break;
 891        case 1:
 892                if (platform_device_add_resources(pdev, atmel_psif1_resource,
 893                                        ARRAY_SIZE(atmel_psif1_resource)))
 894                        goto err_add_resources;
 895                atmel_psif1_pclk.dev = &pdev->dev;
 896                select_peripheral(PB(11), PERIPH_A, 0); /* CLOCK */
 897                select_peripheral(PB(12), PERIPH_A, 0); /* DATA  */
 898                break;
 899        default:
 900                return NULL;
 901        }
 902
 903        platform_device_add(pdev);
 904        return pdev;
 905
 906err_add_resources:
 907        platform_device_put(pdev);
 908        return NULL;
 909}
 910
 911/* --------------------------------------------------------------------
 912 *  USART
 913 * -------------------------------------------------------------------- */
 914
 915static struct atmel_uart_data atmel_usart0_data = {
 916        .use_dma_tx     = 1,
 917        .use_dma_rx     = 1,
 918};
 919static struct resource atmel_usart0_resource[] = {
 920        PBMEM(0xffe00c00),
 921        IRQ(6),
 922};
 923DEFINE_DEV_DATA(atmel_usart, 0);
 924DEV_CLK(usart, atmel_usart0, pba, 3);
 925
 926static struct atmel_uart_data atmel_usart1_data = {
 927        .use_dma_tx     = 1,
 928        .use_dma_rx     = 1,
 929};
 930static struct resource atmel_usart1_resource[] = {
 931        PBMEM(0xffe01000),
 932        IRQ(7),
 933};
 934DEFINE_DEV_DATA(atmel_usart, 1);
 935DEV_CLK(usart, atmel_usart1, pba, 4);
 936
 937static struct atmel_uart_data atmel_usart2_data = {
 938        .use_dma_tx     = 1,
 939        .use_dma_rx     = 1,
 940};
 941static struct resource atmel_usart2_resource[] = {
 942        PBMEM(0xffe01400),
 943        IRQ(8),
 944};
 945DEFINE_DEV_DATA(atmel_usart, 2);
 946DEV_CLK(usart, atmel_usart2, pba, 5);
 947
 948static struct atmel_uart_data atmel_usart3_data = {
 949        .use_dma_tx     = 1,
 950        .use_dma_rx     = 1,
 951};
 952static struct resource atmel_usart3_resource[] = {
 953        PBMEM(0xffe01800),
 954        IRQ(9),
 955};
 956DEFINE_DEV_DATA(atmel_usart, 3);
 957DEV_CLK(usart, atmel_usart3, pba, 6);
 958
 959static inline void configure_usart0_pins(void)
 960{
 961        select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 962        select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 963}
 964
 965static inline void configure_usart1_pins(void)
 966{
 967        select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 968        select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 969}
 970
 971static inline void configure_usart2_pins(void)
 972{
 973        select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 974        select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 975}
 976
 977static inline void configure_usart3_pins(void)
 978{
 979        select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 980        select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 981}
 982
 983static struct platform_device *__initdata at32_usarts[4];
 984
 985void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 986{
 987        struct platform_device *pdev;
 988
 989        switch (hw_id) {
 990        case 0:
 991                pdev = &atmel_usart0_device;
 992                configure_usart0_pins();
 993                break;
 994        case 1:
 995                pdev = &atmel_usart1_device;
 996                configure_usart1_pins();
 997                break;
 998        case 2:
 999                pdev = &atmel_usart2_device;
1000                configure_usart2_pins();
1001                break;
1002        case 3:
1003                pdev = &atmel_usart3_device;
1004                configure_usart3_pins();
1005                break;
1006        default:
1007                return;
1008        }
1009
1010        if (PXSEG(pdev->resource[0].start) == P4SEG) {
1011                /* Addresses in the P4 segment are permanently mapped 1:1 */
1012                struct atmel_uart_data *data = pdev->dev.platform_data;
1013                data->regs = (void __iomem *)pdev->resource[0].start;
1014        }
1015
1016        pdev->id = line;
1017        at32_usarts[line] = pdev;
1018}
1019
1020struct platform_device *__init at32_add_device_usart(unsigned int id)
1021{
1022        platform_device_register(at32_usarts[id]);
1023        return at32_usarts[id];
1024}
1025
1026struct platform_device *atmel_default_console_device;
1027
1028void __init at32_setup_serial_console(unsigned int usart_id)
1029{
1030        atmel_default_console_device = at32_usarts[usart_id];
1031}
1032
1033/* --------------------------------------------------------------------
1034 *  Ethernet
1035 * -------------------------------------------------------------------- */
1036
1037#ifdef CONFIG_CPU_AT32AP7000
1038static struct eth_platform_data macb0_data;
1039static struct resource macb0_resource[] = {
1040        PBMEM(0xfff01800),
1041        IRQ(25),
1042};
1043DEFINE_DEV_DATA(macb, 0);
1044DEV_CLK(hclk, macb0, hsb, 8);
1045DEV_CLK(pclk, macb0, pbb, 6);
1046
1047static struct eth_platform_data macb1_data;
1048static struct resource macb1_resource[] = {
1049        PBMEM(0xfff01c00),
1050        IRQ(26),
1051};
1052DEFINE_DEV_DATA(macb, 1);
1053DEV_CLK(hclk, macb1, hsb, 9);
1054DEV_CLK(pclk, macb1, pbb, 7);
1055
1056struct platform_device *__init
1057at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
1058{
1059        struct platform_device *pdev;
1060
1061        switch (id) {
1062        case 0:
1063                pdev = &macb0_device;
1064
1065                select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
1066                select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
1067                select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
1068                select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
1069                select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
1070                select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
1071                select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
1072                select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
1073                select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
1074                select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
1075
1076                if (!data->is_rmii) {
1077                        select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
1078                        select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
1079                        select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
1080                        select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
1081                        select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
1082                        select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
1083                        select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
1084                        select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
1085                        select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
1086                }
1087                break;
1088
1089        case 1:
1090                pdev = &macb1_device;
1091
1092                select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
1093                select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
1094                select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
1095                select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
1096                select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
1097                select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
1098                select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
1099                select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
1100                select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
1101                select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
1102
1103                if (!data->is_rmii) {
1104                        select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
1105                        select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
1106                        select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
1107                        select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
1108                        select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
1109                        select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
1110                        select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
1111                        select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
1112                        select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
1113                }
1114                break;
1115
1116        default:
1117                return NULL;
1118        }
1119
1120        memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
1121        platform_device_register(pdev);
1122
1123        return pdev;
1124}
1125#endif
1126
1127/* --------------------------------------------------------------------
1128 *  SPI
1129 * -------------------------------------------------------------------- */
1130static struct resource atmel_spi0_resource[] = {
1131        PBMEM(0xffe00000),
1132        IRQ(3),
1133};
1134DEFINE_DEV(atmel_spi, 0);
1135DEV_CLK(spi_clk, atmel_spi0, pba, 0);
1136
1137static struct resource atmel_spi1_resource[] = {
1138        PBMEM(0xffe00400),
1139        IRQ(4),
1140};
1141DEFINE_DEV(atmel_spi, 1);
1142DEV_CLK(spi_clk, atmel_spi1, pba, 1);
1143
1144static void __init
1145at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
1146                      unsigned int n, const u8 *pins)
1147{
1148        unsigned int pin, mode;
1149
1150        for (; n; n--, b++) {
1151                b->bus_num = bus_num;
1152                if (b->chip_select >= 4)
1153                        continue;
1154                pin = (unsigned)b->controller_data;
1155                if (!pin) {
1156                        pin = pins[b->chip_select];
1157                        b->controller_data = (void *)pin;
1158                }
1159                mode = AT32_GPIOF_OUTPUT;
1160                if (!(b->mode & SPI_CS_HIGH))
1161                        mode |= AT32_GPIOF_HIGH;
1162                at32_select_gpio(pin, mode);
1163        }
1164}
1165
1166struct platform_device *__init
1167at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
1168{
1169        /*
1170         * Manage the chipselects as GPIOs, normally using the same pins
1171         * the SPI controller expects; but boards can use other pins.
1172         */
1173        static u8 __initdata spi0_pins[] =
1174                { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
1175                  GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
1176        static u8 __initdata spi1_pins[] =
1177                { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
1178                  GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
1179        struct platform_device *pdev;
1180
1181        switch (id) {
1182        case 0:
1183                pdev = &atmel_spi0_device;
1184                /* pullup MISO so a level is always defined */
1185                select_peripheral(PA(0),  PERIPH_A, AT32_GPIOF_PULLUP);
1186                select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
1187                select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
1188                at32_spi_setup_slaves(0, b, n, spi0_pins);
1189                break;
1190
1191        case 1:
1192                pdev = &atmel_spi1_device;
1193                /* pullup MISO so a level is always defined */
1194                select_peripheral(PB(0),  PERIPH_B, AT32_GPIOF_PULLUP);
1195                select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
1196                select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
1197                at32_spi_setup_slaves(1, b, n, spi1_pins);
1198                break;
1199
1200        default:
1201                return NULL;
1202        }
1203
1204        spi_register_board_info(b, n);
1205        platform_device_register(pdev);
1206        return pdev;
1207}
1208
1209/* --------------------------------------------------------------------
1210 *  TWI
1211 * -------------------------------------------------------------------- */
1212static struct resource atmel_twi0_resource[] __initdata = {
1213        PBMEM(0xffe00800),
1214        IRQ(5),
1215};
1216static struct clk atmel_twi0_pclk = {
1217        .name           = "twi_pclk",
1218        .parent         = &pba_clk,
1219        .mode           = pba_clk_mode,
1220        .get_rate       = pba_clk_get_rate,
1221        .index          = 2,
1222};
1223
1224struct platform_device *__init at32_add_device_twi(unsigned int id,
1225                                                    struct i2c_board_info *b,
1226                                                    unsigned int n)
1227{
1228        struct platform_device *pdev;
1229
1230        if (id != 0)
1231                return NULL;
1232
1233        pdev = platform_device_alloc("atmel_twi", id);
1234        if (!pdev)
1235                return NULL;
1236
1237        if (platform_device_add_resources(pdev, atmel_twi0_resource,
1238                                ARRAY_SIZE(atmel_twi0_resource)))
1239                goto err_add_resources;
1240
1241        select_peripheral(PA(6),  PERIPH_A, 0); /* SDA  */
1242        select_peripheral(PA(7),  PERIPH_A, 0); /* SDL  */
1243
1244        atmel_twi0_pclk.dev = &pdev->dev;
1245
1246        if (b)
1247                i2c_register_board_info(id, b, n);
1248
1249        platform_device_add(pdev);
1250        return pdev;
1251
1252err_add_resources:
1253        platform_device_put(pdev);
1254        return NULL;
1255}
1256
1257/* --------------------------------------------------------------------
1258 * MMC
1259 * -------------------------------------------------------------------- */
1260static struct resource atmel_mci0_resource[] __initdata = {
1261        PBMEM(0xfff02400),
1262        IRQ(28),
1263};
1264static struct clk atmel_mci0_pclk = {
1265        .name           = "mci_clk",
1266        .parent         = &pbb_clk,
1267        .mode           = pbb_clk_mode,
1268        .get_rate       = pbb_clk_get_rate,
1269        .index          = 9,
1270};
1271
1272struct platform_device *__init
1273at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
1274{
1275        struct mci_platform_data        _data;
1276        struct platform_device          *pdev;
1277
1278        if (id != 0)
1279                return NULL;
1280
1281        pdev = platform_device_alloc("atmel_mci", id);
1282        if (!pdev)
1283                goto fail;
1284
1285        if (platform_device_add_resources(pdev, atmel_mci0_resource,
1286                                ARRAY_SIZE(atmel_mci0_resource)))
1287                goto fail;
1288
1289        if (!data) {
1290                data = &_data;
1291                memset(data, -1, sizeof(struct mci_platform_data));
1292                data->detect_pin = GPIO_PIN_NONE;
1293                data->wp_pin = GPIO_PIN_NONE;
1294        }
1295
1296        if (platform_device_add_data(pdev, data,
1297                                sizeof(struct mci_platform_data)))
1298                goto fail;
1299
1300        select_peripheral(PA(10), PERIPH_A, 0); /* CLK   */
1301        select_peripheral(PA(11), PERIPH_A, 0); /* CMD   */
1302        select_peripheral(PA(12), PERIPH_A, 0); /* DATA0 */
1303        select_peripheral(PA(13), PERIPH_A, 0); /* DATA1 */
1304        select_peripheral(PA(14), PERIPH_A, 0); /* DATA2 */
1305        select_peripheral(PA(15), PERIPH_A, 0); /* DATA3 */
1306
1307        if (gpio_is_valid(data->detect_pin))
1308                at32_select_gpio(data->detect_pin, 0);
1309        if (gpio_is_valid(data->wp_pin))
1310                at32_select_gpio(data->wp_pin, 0);
1311
1312        atmel_mci0_pclk.dev = &pdev->dev;
1313
1314        platform_device_add(pdev);
1315        return pdev;
1316
1317fail:
1318        platform_device_put(pdev);
1319        return NULL;
1320}
1321
1322/* --------------------------------------------------------------------
1323 *  LCDC
1324 * -------------------------------------------------------------------- */
1325#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
1326static struct atmel_lcdfb_info atmel_lcdfb0_data;
1327static struct resource atmel_lcdfb0_resource[] = {
1328        {
1329                .start          = 0xff000000,
1330                .end            = 0xff000fff,
1331                .flags          = IORESOURCE_MEM,
1332        },
1333        IRQ(1),
1334        {
1335                /* Placeholder for pre-allocated fb memory */
1336                .start          = 0x00000000,
1337                .end            = 0x00000000,
1338                .flags          = 0,
1339        },
1340};
1341DEFINE_DEV_DATA(atmel_lcdfb, 0);
1342DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
1343static struct clk atmel_lcdfb0_pixclk = {
1344        .name           = "lcdc_clk",
1345        .dev            = &atmel_lcdfb0_device.dev,
1346        .mode           = genclk_mode,
1347        .get_rate       = genclk_get_rate,
1348        .set_rate       = genclk_set_rate,
1349        .set_parent     = genclk_set_parent,
1350        .index          = 7,
1351};
1352
1353struct platform_device *__init
1354at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
1355                     unsigned long fbmem_start, unsigned long fbmem_len,
1356                     unsigned int pin_config)
1357{
1358        struct platform_device *pdev;
1359        struct atmel_lcdfb_info *info;
1360        struct fb_monspecs *monspecs;
1361        struct fb_videomode *modedb;
1362        unsigned int modedb_size;
1363
1364        /*
1365         * Do a deep copy of the fb data, monspecs and modedb. Make
1366         * sure all allocations are done before setting up the
1367         * portmux.
1368         */
1369        monspecs = kmemdup(data->default_monspecs,
1370                           sizeof(struct fb_monspecs), GFP_KERNEL);
1371        if (!monspecs)
1372                return NULL;
1373
1374        modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
1375        modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
1376        if (!modedb)
1377                goto err_dup_modedb;
1378        monspecs->modedb = modedb;
1379
1380        switch (id) {
1381        case 0:
1382                pdev = &atmel_lcdfb0_device;
1383
1384                switch (pin_config) {
1385                case 0:
1386                        select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
1387                        select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1388                        select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1389                        select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1390                        select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
1391                        select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
1392                        select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1393                        select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
1394                        select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
1395                        select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
1396                        select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
1397                        select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
1398                        select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1399                        select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1400                        select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1401                        select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
1402                        select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
1403                        select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
1404                        select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
1405                        select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
1406                        select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1407                        select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1408                        select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1409                        select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
1410                        select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
1411                        select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
1412                        select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
1413                        select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
1414                        select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
1415                        select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1416                        select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1417                        break;
1418                case 1:
1419                        select_peripheral(PE(0),  PERIPH_B, 0); /* CC     */
1420                        select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
1421                        select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
1422                        select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
1423                        select_peripheral(PE(1),  PERIPH_B, 0); /* DVAL   */
1424                        select_peripheral(PE(2),  PERIPH_B, 0); /* MODE   */
1425                        select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
1426                        select_peripheral(PE(3),  PERIPH_B, 0); /* DATA0  */
1427                        select_peripheral(PE(4),  PERIPH_B, 0); /* DATA1  */
1428                        select_peripheral(PE(5),  PERIPH_B, 0); /* DATA2  */
1429                        select_peripheral(PE(6),  PERIPH_B, 0); /* DATA3  */
1430                        select_peripheral(PE(7),  PERIPH_B, 0); /* DATA4  */
1431                        select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
1432                        select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
1433                        select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
1434                        select_peripheral(PE(8),  PERIPH_B, 0); /* DATA8  */
1435                        select_peripheral(PE(9),  PERIPH_B, 0); /* DATA9  */
1436                        select_peripheral(PE(10), PERIPH_B, 0); /* DATA10 */
1437                        select_peripheral(PE(11), PERIPH_B, 0); /* DATA11 */
1438                        select_peripheral(PE(12), PERIPH_B, 0); /* DATA12 */
1439                        select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
1440                        select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
1441                        select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
1442                        select_peripheral(PE(13), PERIPH_B, 0); /* DATA16 */
1443                        select_peripheral(PE(14), PERIPH_B, 0); /* DATA17 */
1444                        select_peripheral(PE(15), PERIPH_B, 0); /* DATA18 */
1445                        select_peripheral(PE(16), PERIPH_B, 0); /* DATA19 */
1446                        select_peripheral(PE(17), PERIPH_B, 0); /* DATA20 */
1447                        select_peripheral(PE(18), PERIPH_B, 0); /* DATA21 */
1448                        select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
1449                        select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
1450                        break;
1451                default:
1452                        goto err_invalid_id;
1453                }
1454
1455                clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
1456                clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
1457                break;
1458
1459        default:
1460                goto err_invalid_id;
1461        }
1462
1463        if (fbmem_len) {
1464                pdev->resource[2].start = fbmem_start;
1465                pdev->resource[2].end = fbmem_start + fbmem_len - 1;
1466                pdev->resource[2].flags = IORESOURCE_MEM;
1467        }
1468
1469        info = pdev->dev.platform_data;
1470        memcpy(info, data, sizeof(struct atmel_lcdfb_info));
1471        info->default_monspecs = monspecs;
1472
1473        platform_device_register(pdev);
1474        return pdev;
1475
1476err_invalid_id:
1477        kfree(modedb);
1478err_dup_modedb:
1479        kfree(monspecs);
1480        return NULL;
1481}
1482#endif
1483
1484/* --------------------------------------------------------------------
1485 *  PWM
1486 * -------------------------------------------------------------------- */
1487static struct resource atmel_pwm0_resource[] __initdata = {
1488        PBMEM(0xfff01400),
1489        IRQ(24),
1490};
1491static struct clk atmel_pwm0_mck = {
1492        .name           = "pwm_clk",
1493        .parent         = &pbb_clk,
1494        .mode           = pbb_clk_mode,
1495        .get_rate       = pbb_clk_get_rate,
1496        .index          = 5,
1497};
1498
1499struct platform_device *__init at32_add_device_pwm(u32 mask)
1500{
1501        struct platform_device *pdev;
1502
1503        if (!mask)
1504                return NULL;
1505
1506        pdev = platform_device_alloc("atmel_pwm", 0);
1507        if (!pdev)
1508                return NULL;
1509
1510        if (platform_device_add_resources(pdev, atmel_pwm0_resource,
1511                                ARRAY_SIZE(atmel_pwm0_resource)))
1512                goto out_free_pdev;
1513
1514        if (platform_device_add_data(pdev, &mask, sizeof(mask)))
1515                goto out_free_pdev;
1516
1517        if (mask & (1 << 0))
1518                select_peripheral(PA(28), PERIPH_A, 0);
1519        if (mask & (1 << 1))
1520                select_peripheral(PA(29), PERIPH_A, 0);
1521        if (mask & (1 << 2))
1522                select_peripheral(PA(21), PERIPH_B, 0);
1523        if (mask & (1 << 3))
1524                select_peripheral(PA(22), PERIPH_B, 0);
1525
1526        atmel_pwm0_mck.dev = &pdev->dev;
1527
1528        platform_device_add(pdev);
1529
1530        return pdev;
1531
1532out_free_pdev:
1533        platform_device_put(pdev);
1534        return NULL;
1535}
1536
1537/* --------------------------------------------------------------------
1538 *  SSC
1539 * -------------------------------------------------------------------- */
1540static struct resource ssc0_resource[] = {
1541        PBMEM(0xffe01c00),
1542        IRQ(10),
1543};
1544DEFINE_DEV(ssc, 0);
1545DEV_CLK(pclk, ssc0, pba, 7);
1546
1547static struct resource ssc1_resource[] = {
1548        PBMEM(0xffe02000),
1549        IRQ(11),
1550};
1551DEFINE_DEV(ssc, 1);
1552DEV_CLK(pclk, ssc1, pba, 8);
1553
1554static struct resource ssc2_resource[] = {
1555        PBMEM(0xffe02400),
1556        IRQ(12),
1557};
1558DEFINE_DEV(ssc, 2);
1559DEV_CLK(pclk, ssc2, pba, 9);
1560
1561struct platform_device *__init
1562at32_add_device_ssc(unsigned int id, unsigned int flags)
1563{
1564        struct platform_device *pdev;
1565
1566        switch (id) {
1567        case 0:
1568                pdev = &ssc0_device;
1569                if (flags & ATMEL_SSC_RF)
1570                        select_peripheral(PA(21), PERIPH_A, 0); /* RF */
1571                if (flags & ATMEL_SSC_RK)
1572                        select_peripheral(PA(22), PERIPH_A, 0); /* RK */
1573                if (flags & ATMEL_SSC_TK)
1574                        select_peripheral(PA(23), PERIPH_A, 0); /* TK */
1575                if (flags & ATMEL_SSC_TF)
1576                        select_peripheral(PA(24), PERIPH_A, 0); /* TF */
1577                if (flags & ATMEL_SSC_TD)
1578                        select_peripheral(PA(25), PERIPH_A, 0); /* TD */
1579                if (flags & ATMEL_SSC_RD)
1580                        select_peripheral(PA(26), PERIPH_A, 0); /* RD */
1581                break;
1582        case 1:
1583                pdev = &ssc1_device;
1584                if (flags & ATMEL_SSC_RF)
1585                        select_peripheral(PA(0), PERIPH_B, 0);  /* RF */
1586                if (flags & ATMEL_SSC_RK)
1587                        select_peripheral(PA(1), PERIPH_B, 0);  /* RK */
1588                if (flags & ATMEL_SSC_TK)
1589                        select_peripheral(PA(2), PERIPH_B, 0);  /* TK */
1590                if (flags & ATMEL_SSC_TF)
1591                        select_peripheral(PA(3), PERIPH_B, 0);  /* TF */
1592                if (flags & ATMEL_SSC_TD)
1593                        select_peripheral(PA(4), PERIPH_B, 0);  /* TD */
1594                if (flags & ATMEL_SSC_RD)
1595                        select_peripheral(PA(5), PERIPH_B, 0);  /* RD */
1596                break;
1597        case 2:
1598                pdev = &ssc2_device;
1599                if (flags & ATMEL_SSC_TD)
1600                        select_peripheral(PB(13), PERIPH_A, 0); /* TD */
1601                if (flags & ATMEL_SSC_RD)
1602                        select_peripheral(PB(14), PERIPH_A, 0); /* RD */
1603                if (flags & ATMEL_SSC_TK)
1604                        select_peripheral(PB(15), PERIPH_A, 0); /* TK */
1605                if (flags & ATMEL_SSC_TF)
1606                        select_peripheral(PB(16), PERIPH_A, 0); /* TF */
1607                if (flags & ATMEL_SSC_RF)
1608                        select_peripheral(PB(17), PERIPH_A, 0); /* RF */
1609                if (flags & ATMEL_SSC_RK)
1610                        select_peripheral(PB(18), PERIPH_A, 0); /* RK */
1611                break;
1612        default:
1613                return NULL;
1614        }
1615
1616        platform_device_register(pdev);
1617        return pdev;
1618}
1619
1620/* --------------------------------------------------------------------
1621 *  USB Device Controller
1622 * -------------------------------------------------------------------- */
1623static struct resource usba0_resource[] __initdata = {
1624        {
1625                .start          = 0xff300000,
1626                .end            = 0xff3fffff,
1627                .flags          = IORESOURCE_MEM,
1628        }, {
1629                .start          = 0xfff03000,
1630                .end            = 0xfff033ff,
1631                .flags          = IORESOURCE_MEM,
1632        },
1633        IRQ(31),
1634};
1635static struct clk usba0_pclk = {
1636        .name           = "pclk",
1637        .parent         = &pbb_clk,
1638        .mode           = pbb_clk_mode,
1639        .get_rate       = pbb_clk_get_rate,
1640        .index          = 12,
1641};
1642static struct clk usba0_hclk = {
1643        .name           = "hclk",
1644        .parent         = &hsb_clk,
1645        .mode           = hsb_clk_mode,
1646        .get_rate       = hsb_clk_get_rate,
1647        .index          = 6,
1648};
1649
1650#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
1651        [idx] = {                                               \
1652                .name           = nam,                          \
1653                .index          = idx,                          \
1654                .fifo_size      = maxpkt,                       \
1655                .nr_banks       = maxbk,                        \
1656                .can_dma        = dma,                          \
1657                .can_isoc       = isoc,                         \
1658        }
1659
1660static struct usba_ep_data at32_usba_ep[] __initdata = {
1661        EP("ep0",     0,   64, 1, 0, 0),
1662        EP("ep1",     1,  512, 2, 1, 1),
1663        EP("ep2",     2,  512, 2, 1, 1),
1664        EP("ep3-int", 3,   64, 3, 1, 0),
1665        EP("ep4-int", 4,   64, 3, 1, 0),
1666        EP("ep5",     5, 1024, 3, 1, 1),
1667        EP("ep6",     6, 1024, 3, 1, 1),
1668};
1669
1670#undef EP
1671
1672struct platform_device *__init
1673at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
1674{
1675        /*
1676         * pdata doesn't have room for any endpoints, so we need to
1677         * append room for the ones we need right after it.
1678         */
1679        struct {
1680                struct usba_platform_data pdata;
1681                struct usba_ep_data ep[7];
1682        } usba_data;
1683        struct platform_device *pdev;
1684
1685        if (id != 0)
1686                return NULL;
1687
1688        pdev = platform_device_alloc("atmel_usba_udc", 0);
1689        if (!pdev)
1690                return NULL;
1691
1692        if (platform_device_add_resources(pdev, usba0_resource,
1693                                          ARRAY_SIZE(usba0_resource)))
1694                goto out_free_pdev;
1695
1696        if (data)
1697                usba_data.pdata.vbus_pin = data->vbus_pin;
1698        else
1699                usba_data.pdata.vbus_pin = -EINVAL;
1700
1701        data = &usba_data.pdata;
1702        data->num_ep = ARRAY_SIZE(at32_usba_ep);
1703        memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
1704
1705        if (platform_device_add_data(pdev, data, sizeof(usba_data)))
1706                goto out_free_pdev;
1707
1708        if (data->vbus_pin >= 0)
1709                at32_select_gpio(data->vbus_pin, 0);
1710
1711        usba0_pclk.dev = &pdev->dev;
1712        usba0_hclk.dev = &pdev->dev;
1713
1714        platform_device_add(pdev);
1715
1716        return pdev;
1717
1718out_free_pdev:
1719        platform_device_put(pdev);
1720        return NULL;
1721}
1722
1723/* --------------------------------------------------------------------
1724 * IDE / CompactFlash
1725 * -------------------------------------------------------------------- */
1726#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
1727static struct resource at32_smc_cs4_resource[] __initdata = {
1728        {
1729                .start  = 0x04000000,
1730                .end    = 0x07ffffff,
1731                .flags  = IORESOURCE_MEM,
1732        },
1733        IRQ(~0UL), /* Magic IRQ will be overridden */
1734};
1735static struct resource at32_smc_cs5_resource[] __initdata = {
1736        {
1737                .start  = 0x20000000,
1738                .end    = 0x23ffffff,
1739                .flags  = IORESOURCE_MEM,
1740        },
1741        IRQ(~0UL), /* Magic IRQ will be overridden */
1742};
1743
1744static int __init at32_init_ide_or_cf(struct platform_device *pdev,
1745                unsigned int cs, unsigned int extint)
1746{
1747        static unsigned int extint_pin_map[4] __initdata = {
1748                GPIO_PIN_PB(25),
1749                GPIO_PIN_PB(26),
1750                GPIO_PIN_PB(27),
1751                GPIO_PIN_PB(28),
1752        };
1753        static bool common_pins_initialized __initdata = false;
1754        unsigned int extint_pin;
1755        int ret;
1756
1757        if (extint >= ARRAY_SIZE(extint_pin_map))
1758                return -EINVAL;
1759        extint_pin = extint_pin_map[extint];
1760
1761        switch (cs) {
1762        case 4:
1763                ret = platform_device_add_resources(pdev,
1764                                at32_smc_cs4_resource,
1765                                ARRAY_SIZE(at32_smc_cs4_resource));
1766                if (ret)
1767                        return ret;
1768
1769                select_peripheral(PE(21), PERIPH_A, 0); /* NCS4   -> OE_N  */
1770                hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
1771                break;
1772        case 5:
1773                ret = platform_device_add_resources(pdev,
1774                                at32_smc_cs5_resource,
1775                                ARRAY_SIZE(at32_smc_cs5_resource));
1776                if (ret)
1777                        return ret;
1778
1779                select_peripheral(PE(22), PERIPH_A, 0); /* NCS5   -> OE_N  */
1780                hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
1781                break;
1782        default:
1783                return -EINVAL;
1784        }
1785
1786        if (!common_pins_initialized) {
1787                select_peripheral(PE(19), PERIPH_A, 0); /* CFCE1  -> CS0_N */
1788                select_peripheral(PE(20), PERIPH_A, 0); /* CFCE2  -> CS1_N */
1789                select_peripheral(PE(23), PERIPH_A, 0); /* CFRNW  -> DIR   */
1790                select_peripheral(PE(24), PERIPH_A, 0); /* NWAIT  <- IORDY */
1791                common_pins_initialized = true;
1792        }
1793
1794        at32_select_periph(extint_pin, GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
1795
1796        pdev->resource[1].start = EIM_IRQ_BASE + extint;
1797        pdev->resource[1].end = pdev->resource[1].start;
1798
1799        return 0;
1800}
1801
1802struct platform_device *__init
1803at32_add_device_ide(unsigned int id, unsigned int extint,
1804                    struct ide_platform_data *data)
1805{
1806        struct platform_device *pdev;
1807
1808        pdev = platform_device_alloc("at32_ide", id);
1809        if (!pdev)
1810                goto fail;
1811
1812        if (platform_device_add_data(pdev, data,
1813                                sizeof(struct ide_platform_data)))
1814                goto fail;
1815
1816        if (at32_init_ide_or_cf(pdev, data->cs, extint))
1817                goto fail;
1818
1819        platform_device_add(pdev);
1820        return pdev;
1821
1822fail:
1823        platform_device_put(pdev);
1824        return NULL;
1825}
1826
1827struct platform_device *__init
1828at32_add_device_cf(unsigned int id, unsigned int extint,
1829                    struct cf_platform_data *data)
1830{
1831        struct platform_device *pdev;
1832
1833        pdev = platform_device_alloc("at32_cf", id);
1834        if (!pdev)
1835                goto fail;
1836
1837        if (platform_device_add_data(pdev, data,
1838                                sizeof(struct cf_platform_data)))
1839                goto fail;
1840
1841        if (at32_init_ide_or_cf(pdev, data->cs, extint))
1842                goto fail;
1843
1844        if (gpio_is_valid(data->detect_pin))
1845                at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
1846        if (gpio_is_valid(data->reset_pin))
1847                at32_select_gpio(data->reset_pin, 0);
1848        if (gpio_is_valid(data->vcc_pin))
1849                at32_select_gpio(data->vcc_pin, 0);
1850        /* READY is used as extint, so we can't select it as gpio */
1851
1852        platform_device_add(pdev);
1853        return pdev;
1854
1855fail:
1856        platform_device_put(pdev);
1857        return NULL;
1858}
1859#endif
1860
1861/* --------------------------------------------------------------------
1862 * NAND Flash / SmartMedia
1863 * -------------------------------------------------------------------- */
1864static struct resource smc_cs3_resource[] __initdata = {
1865        {
1866                .start  = 0x0c000000,
1867                .end    = 0x0fffffff,
1868                .flags  = IORESOURCE_MEM,
1869        }, {
1870                .start  = 0xfff03c00,
1871                .end    = 0xfff03fff,
1872                .flags  = IORESOURCE_MEM,
1873        },
1874};
1875
1876struct platform_device *__init
1877at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
1878{
1879        struct platform_device *pdev;
1880
1881        if (id != 0 || !data)
1882                return NULL;
1883
1884        pdev = platform_device_alloc("atmel_nand", id);
1885        if (!pdev)
1886                goto fail;
1887
1888        if (platform_device_add_resources(pdev, smc_cs3_resource,
1889                                ARRAY_SIZE(smc_cs3_resource)))
1890                goto fail;
1891
1892        if (platform_device_add_data(pdev, data,
1893                                sizeof(struct atmel_nand_data)))
1894                goto fail;
1895
1896        hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
1897        if (data->enable_pin)
1898                at32_select_gpio(data->enable_pin,
1899                                AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
1900        if (data->rdy_pin)
1901                at32_select_gpio(data->rdy_pin, 0);
1902        if (data->det_pin)
1903                at32_select_gpio(data->det_pin, 0);
1904
1905        platform_device_add(pdev);
1906        return pdev;
1907
1908fail:
1909        platform_device_put(pdev);
1910        return NULL;
1911}
1912
1913/* --------------------------------------------------------------------
1914 * AC97C
1915 * -------------------------------------------------------------------- */
1916static struct resource atmel_ac97c0_resource[] __initdata = {
1917        PBMEM(0xfff02800),
1918        IRQ(29),
1919};
1920static struct clk atmel_ac97c0_pclk = {
1921        .name           = "pclk",
1922        .parent         = &pbb_clk,
1923        .mode           = pbb_clk_mode,
1924        .get_rate       = pbb_clk_get_rate,
1925        .index          = 10,
1926};
1927
1928struct platform_device *__init
1929at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data)
1930{
1931        struct platform_device *pdev;
1932        struct ac97c_platform_data _data;
1933
1934        if (id != 0)
1935                return NULL;
1936
1937        pdev = platform_device_alloc("atmel_ac97c", id);
1938        if (!pdev)
1939                return NULL;
1940
1941        if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
1942                                ARRAY_SIZE(atmel_ac97c0_resource)))
1943                goto fail;
1944
1945        if (!data) {
1946                data = &_data;
1947                memset(data, 0, sizeof(struct ac97c_platform_data));
1948                data->reset_pin = GPIO_PIN_NONE;
1949        }
1950
1951        data->dma_rx_periph_id = 3;
1952        data->dma_tx_periph_id = 4;
1953        data->dma_controller_id = 0;
1954
1955        if (platform_device_add_data(pdev, data,
1956                                sizeof(struct ac97c_platform_data)))
1957                goto fail;
1958
1959        select_peripheral(PB(20), PERIPH_B, 0); /* SDO  */
1960        select_peripheral(PB(21), PERIPH_B, 0); /* SYNC */
1961        select_peripheral(PB(22), PERIPH_B, 0); /* SCLK */
1962        select_peripheral(PB(23), PERIPH_B, 0); /* SDI  */
1963
1964        /* TODO: gpio_is_valid(data->reset_pin) with kernel 2.6.26. */
1965        if (data->reset_pin != GPIO_PIN_NONE)
1966                at32_select_gpio(data->reset_pin, 0);
1967
1968        atmel_ac97c0_pclk.dev = &pdev->dev;
1969
1970        platform_device_add(pdev);
1971        return pdev;
1972
1973fail:
1974        platform_device_put(pdev);
1975        return NULL;
1976}
1977
1978/* --------------------------------------------------------------------
1979 * ABDAC
1980 * -------------------------------------------------------------------- */
1981static struct resource abdac0_resource[] __initdata = {
1982        PBMEM(0xfff02000),
1983        IRQ(27),
1984};
1985static struct clk abdac0_pclk = {
1986        .name           = "pclk",
1987        .parent         = &pbb_clk,
1988        .mode           = pbb_clk_mode,
1989        .get_rate       = pbb_clk_get_rate,
1990        .index          = 8,
1991};
1992static struct clk abdac0_sample_clk = {
1993        .name           = "sample_clk",
1994        .mode           = genclk_mode,
1995        .get_rate       = genclk_get_rate,
1996        .set_rate       = genclk_set_rate,
1997        .set_parent     = genclk_set_parent,
1998        .index          = 6,
1999};
2000
2001struct platform_device *__init at32_add_device_abdac(unsigned int id)
2002{
2003        struct platform_device *pdev;
2004
2005        if (id != 0)
2006                return NULL;
2007
2008        pdev = platform_device_alloc("abdac", id);
2009        if (!pdev)
2010                return NULL;
2011
2012        if (platform_device_add_resources(pdev, abdac0_resource,
2013                                ARRAY_SIZE(abdac0_resource)))
2014                goto err_add_resources;
2015
2016        select_peripheral(PB(20), PERIPH_A, 0); /* DATA1        */
2017        select_peripheral(PB(21), PERIPH_A, 0); /* DATA0        */
2018        select_peripheral(PB(22), PERIPH_A, 0); /* DATAN1       */
2019        select_peripheral(PB(23), PERIPH_A, 0); /* DATAN0       */
2020
2021        abdac0_pclk.dev = &pdev->dev;
2022        abdac0_sample_clk.dev = &pdev->dev;
2023
2024        platform_device_add(pdev);
2025        return pdev;
2026
2027err_add_resources:
2028        platform_device_put(pdev);
2029        return NULL;
2030}
2031
2032/* --------------------------------------------------------------------
2033 *  GCLK
2034 * -------------------------------------------------------------------- */
2035static struct clk gclk0 = {
2036        .name           = "gclk0",
2037        .mode           = genclk_mode,
2038        .get_rate       = genclk_get_rate,
2039        .set_rate       = genclk_set_rate,
2040        .set_parent     = genclk_set_parent,
2041        .index          = 0,
2042};
2043static struct clk gclk1 = {
2044        .name           = "gclk1",
2045        .mode           = genclk_mode,
2046        .get_rate       = genclk_get_rate,
2047        .set_rate       = genclk_set_rate,
2048        .set_parent     = genclk_set_parent,
2049        .index          = 1,
2050};
2051static struct clk gclk2 = {
2052        .name           = "gclk2",
2053        .mode           = genclk_mode,
2054        .get_rate       = genclk_get_rate,
2055        .set_rate       = genclk_set_rate,
2056        .set_parent     = genclk_set_parent,
2057        .index          = 2,
2058};
2059static struct clk gclk3 = {
2060        .name           = "gclk3",
2061        .mode           = genclk_mode,
2062        .get_rate       = genclk_get_rate,
2063        .set_rate       = genclk_set_rate,
2064        .set_parent     = genclk_set_parent,
2065        .index          = 3,
2066};
2067static struct clk gclk4 = {
2068        .name           = "gclk4",
2069        .mode           = genclk_mode,
2070        .get_rate       = genclk_get_rate,
2071        .set_rate       = genclk_set_rate,
2072        .set_parent     = genclk_set_parent,
2073        .index          = 4,
2074};
2075
2076struct clk *at32_clock_list[] = {
2077        &osc32k,
2078        &osc0,
2079        &osc1,
2080        &pll0,
2081        &pll1,
2082        &cpu_clk,
2083        &hsb_clk,
2084        &pba_clk,
2085        &pbb_clk,
2086        &at32_pm_pclk,
2087        &at32_intc0_pclk,
2088        &at32_hmatrix_clk,
2089        &ebi_clk,
2090        &hramc_clk,
2091        &sdramc_clk,
2092        &smc0_pclk,
2093        &smc0_mck,
2094        &pdc_hclk,
2095        &pdc_pclk,
2096        &dw_dmac0_hclk,
2097        &pico_clk,
2098        &pio0_mck,
2099        &pio1_mck,
2100        &pio2_mck,
2101        &pio3_mck,
2102        &pio4_mck,
2103        &at32_tcb0_t0_clk,
2104        &at32_tcb1_t0_clk,
2105        &atmel_psif0_pclk,
2106        &atmel_psif1_pclk,
2107        &atmel_usart0_usart,
2108        &atmel_usart1_usart,
2109        &atmel_usart2_usart,
2110        &atmel_usart3_usart,
2111        &atmel_pwm0_mck,
2112#if defined(CONFIG_CPU_AT32AP7000)
2113        &macb0_hclk,
2114        &macb0_pclk,
2115        &macb1_hclk,
2116        &macb1_pclk,
2117#endif
2118        &atmel_spi0_spi_clk,
2119        &atmel_spi1_spi_clk,
2120        &atmel_twi0_pclk,
2121        &atmel_mci0_pclk,
2122#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2123        &atmel_lcdfb0_hck1,
2124        &atmel_lcdfb0_pixclk,
2125#endif
2126        &ssc0_pclk,
2127        &ssc1_pclk,
2128        &ssc2_pclk,
2129        &usba0_hclk,
2130        &usba0_pclk,
2131        &atmel_ac97c0_pclk,
2132        &abdac0_pclk,
2133        &abdac0_sample_clk,
2134        &gclk0,
2135        &gclk1,
2136        &gclk2,
2137        &gclk3,
2138        &gclk4,
2139};
2140unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
2141
2142void __init setup_platform(void)
2143{
2144        u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
2145        int i;
2146
2147        if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
2148                main_clock = &pll0;
2149                cpu_clk.parent = &pll0;
2150        } else {
2151                main_clock = &osc0;
2152                cpu_clk.parent = &osc0;
2153        }
2154
2155        if (pm_readl(PLL0) & PM_BIT(PLLOSC))
2156                pll0.parent = &osc1;
2157        if (pm_readl(PLL1) & PM_BIT(PLLOSC))
2158                pll1.parent = &osc1;
2159
2160        genclk_init_parent(&gclk0);
2161        genclk_init_parent(&gclk1);
2162        genclk_init_parent(&gclk2);
2163        genclk_init_parent(&gclk3);
2164        genclk_init_parent(&gclk4);
2165#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
2166        genclk_init_parent(&atmel_lcdfb0_pixclk);
2167#endif
2168        genclk_init_parent(&abdac0_sample_clk);
2169
2170        /*
2171         * Turn on all clocks that have at least one user already, and
2172         * turn off everything else. We only do this for module
2173         * clocks, and even though it isn't particularly pretty to
2174         * check the address of the mode function, it should do the
2175         * trick...
2176         */
2177        for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
2178                struct clk *clk = at32_clock_list[i];
2179
2180                if (clk->users == 0)
2181                        continue;
2182
2183                if (clk->mode == &cpu_clk_mode)
2184                        cpu_mask |= 1 << clk->index;
2185                else if (clk->mode == &hsb_clk_mode)
2186                        hsb_mask |= 1 << clk->index;
2187                else if (clk->mode == &pba_clk_mode)
2188                        pba_mask |= 1 << clk->index;
2189                else if (clk->mode == &pbb_clk_mode)
2190                        pbb_mask |= 1 << clk->index;
2191        }
2192
2193        pm_writel(CPU_MASK, cpu_mask);
2194        pm_writel(HSB_MASK, hsb_mask);
2195        pm_writel(PBA_MASK, pba_mask);
2196        pm_writel(PBB_MASK, pbb_mask);
2197
2198        /* Initialize the port muxes */
2199        at32_init_pio(&pio0_device);
2200        at32_init_pio(&pio1_device);
2201        at32_init_pio(&pio2_device);
2202        at32_init_pio(&pio3_device);
2203        at32_init_pio(&pio4_device);
2204}
2205
2206struct gen_pool *sram_pool;
2207
2208static int __init sram_init(void)
2209{
2210        struct gen_pool *pool;
2211
2212        /* 1KiB granularity */
2213        pool = gen_pool_create(10, -1);
2214        if (!pool)
2215                goto fail;
2216
2217        if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
2218                goto err_pool_add;
2219
2220        sram_pool = pool;
2221        return 0;
2222
2223err_pool_add:
2224        gen_pool_destroy(pool);
2225fail:
2226        pr_err("Failed to create SRAM pool\n");
2227        return -ENOMEM;
2228}
2229core_initcall(sram_init);
2230