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13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/sysdev.h>
20#include <linux/delay.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/i2c.h>
24
25#include <video/ili9320.h>
26
27#include <linux/spi/spi.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/irq.h>
32
33#include <asm/plat-s3c/regs-serial.h>
34#include <asm/plat-s3c/nand.h>
35#include <asm/plat-s3c/iic.h>
36
37#include <mach/regs-power.h>
38#include <mach/regs-gpio.h>
39#include <mach/regs-mem.h>
40#include <mach/regs-lcd.h>
41#include <mach/spi-gpio.h>
42#include <mach/fb.h>
43
44#include <asm/mach-types.h>
45
46#include <linux/mtd/mtd.h>
47#include <linux/mtd/nand.h>
48#include <linux/mtd/nand_ecc.h>
49#include <linux/mtd/partitions.h>
50
51#include <asm/plat-s3c24xx/clock.h>
52#include <asm/plat-s3c24xx/devs.h>
53#include <asm/plat-s3c24xx/cpu.h>
54#include <asm/plat-s3c24xx/pm.h>
55#include <asm/plat-s3c24xx/udc.h>
56
57static struct map_desc jive_iodesc[] __initdata = {
58};
59
60#define UCON S3C2410_UCON_DEFAULT
61#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
62#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
63
64static struct s3c2410_uartcfg jive_uartcfgs[] = {
65 [0] = {
66 .hwport = 0,
67 .flags = 0,
68 .ucon = UCON,
69 .ulcon = ULCON,
70 .ufcon = UFCON,
71 },
72 [1] = {
73 .hwport = 1,
74 .flags = 0,
75 .ucon = UCON,
76 .ulcon = ULCON,
77 .ufcon = UFCON,
78 },
79 [2] = {
80 .hwport = 2,
81 .flags = 0,
82 .ucon = UCON,
83 .ulcon = ULCON,
84 .ufcon = UFCON,
85 }
86};
87
88
89
90
91
92
93
94
95
96
97
98
99static struct mtd_partition jive_imageA_nand_part[] = {
100
101#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
102
103 {
104 .name = "uboot",
105 .offset = 0,
106 .size = (160 * SZ_1K),
107 .mask_flags = MTD_WRITEABLE,
108 },
109
110
111 {
112 .name = "spare",
113 .offset = (176 * SZ_1K),
114 .size = (16 * SZ_1K),
115 },
116#endif
117
118
119 {
120 .name = "kernel (ro)",
121 .offset = (192 * SZ_1K),
122 .size = (SZ_2M) - (192 * SZ_1K),
123 .mask_flags = MTD_WRITEABLE,
124 }, {
125 .name = "root (ro)",
126 .offset = (SZ_2M),
127 .size = (20 * SZ_1M),
128 .mask_flags = MTD_WRITEABLE,
129 },
130
131
132 {
133 .name = "yaffs",
134 .offset = (44 * SZ_1M),
135 .size = (20 * SZ_1M),
136 },
137
138
139 {
140 .name = "env",
141 .offset = (160 * SZ_1K),
142 .size = (16 * SZ_1K),
143 },
144
145
146 {
147 .name = "zimage",
148 .offset = (22 * SZ_1M),
149 .size = (2 * SZ_1M) - (192 * SZ_1K),
150 }, {
151 .name = "cramfs",
152 .offset = (24 * SZ_1M) - (192*SZ_1K),
153 .size = (20 * SZ_1M),
154 },
155};
156
157static struct mtd_partition jive_imageB_nand_part[] = {
158
159#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
160
161 {
162 .name = "uboot",
163 .offset = 0,
164 .size = (160 * SZ_1K),
165 .mask_flags = MTD_WRITEABLE,
166 },
167
168
169 {
170 .name = "spare",
171 .offset = (176 * SZ_1K),
172 .size = (16 * SZ_1K),
173 },
174#endif
175
176
177 {
178 .name = "kernel (ro)",
179 .offset = (22 * SZ_1M),
180 .size = (2 * SZ_1M) - (192 * SZ_1K),
181 .mask_flags = MTD_WRITEABLE,
182 },
183 {
184 .name = "root (ro)",
185 .offset = (24 * SZ_1M) - (192 * SZ_1K),
186 .size = (20 * SZ_1M),
187 .mask_flags = MTD_WRITEABLE,
188 },
189
190
191 {
192 .name = "yaffs",
193 .offset = (44 * SZ_1M),
194 .size = (20 * SZ_1M),
195 },
196
197
198 {
199 .name = "env",
200 .offset = (160 * SZ_1K),
201 .size = (16 * SZ_1K),
202 },
203
204
205 {
206 .name = "zimage",
207 .offset = (192 * SZ_1K),
208 .size = (2 * SZ_1M) - (192 * SZ_1K),
209 }, {
210 .name = "cramfs",
211 .offset = (2 * SZ_1M),
212 .size = (20 * SZ_1M),
213 },
214};
215
216static struct s3c2410_nand_set jive_nand_sets[] = {
217 [0] = {
218 .name = "flash",
219 .nr_chips = 1,
220 .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
221 .partitions = jive_imageA_nand_part,
222 },
223};
224
225static struct s3c2410_platform_nand jive_nand_info = {
226
227 .tacls = 30,
228 .twrph0 = 55,
229 .twrph1 = 40,
230 .sets = jive_nand_sets,
231 .nr_sets = ARRAY_SIZE(jive_nand_sets),
232};
233
234static int __init jive_mtdset(char *options)
235{
236 struct s3c2410_nand_set *nand = &jive_nand_sets[0];
237 unsigned long set;
238
239 if (options == NULL || options[0] == '\0')
240 return 0;
241
242 if (strict_strtoul(options, 10, &set)) {
243 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
244 return 0;
245 }
246
247 switch (set) {
248 case 1:
249 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
250 nand->partitions = jive_imageB_nand_part;
251 case 0:
252
253 break;
254 default:
255 printk(KERN_ERR "Unknown mtd set %ld specified,"
256 "using default.", set);
257 }
258
259 return 0;
260}
261
262
263__setup("mtdset=", jive_mtdset);
264
265
266
267#define LCD_XRES (240)
268#define LCD_YRES (320)
269#define LCD_LEFT_MARGIN (12)
270#define LCD_RIGHT_MARGIN (12)
271#define LCD_LOWER_MARGIN (12)
272#define LCD_UPPER_MARGIN (12)
273#define LCD_VSYNC (2)
274#define LCD_HSYNC (2)
275
276#define LCD_REFRESH (60)
277
278#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
279#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
280
281struct s3c2410fb_display jive_vgg2432a4_display[] = {
282 [0] = {
283 .width = LCD_XRES,
284 .height = LCD_YRES,
285 .xres = LCD_XRES,
286 .yres = LCD_YRES,
287 .left_margin = LCD_LEFT_MARGIN,
288 .right_margin = LCD_RIGHT_MARGIN,
289 .upper_margin = LCD_UPPER_MARGIN,
290 .lower_margin = LCD_LOWER_MARGIN,
291 .hsync_len = LCD_HSYNC,
292 .vsync_len = LCD_VSYNC,
293
294 .pixclock = (1000000000000LL /
295 (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
296
297 .bpp = 16,
298 .type = (S3C2410_LCDCON1_TFT16BPP |
299 S3C2410_LCDCON1_TFT),
300
301 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
302 S3C2410_LCDCON5_INVVLINE |
303 S3C2410_LCDCON5_INVVFRAME |
304 S3C2410_LCDCON5_INVVDEN |
305 S3C2410_LCDCON5_PWREN),
306 },
307};
308
309
310
311#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
312#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
313
314struct s3c2410fb_mach_info jive_lcd_config = {
315 .displays = jive_vgg2432a4_display,
316 .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
317 .default_display = 0,
318
319
320
321
322
323 .gpcup = (0xf << 1) | (0x3f << 10),
324
325 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
326 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
327 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
328 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
329 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
330
331 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
332 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
333 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
334 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
335 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
336
337 .gpdup = (0x3f << 2) | (0x3f << 10),
338
339 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
340 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
341 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
342 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
343 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
344 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
345
346 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
347 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
348 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
349 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
350 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
351 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
352};
353
354
355
356static void jive_lcm_reset(unsigned int set)
357{
358 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
359
360 s3c2410_gpio_setpin(S3C2410_GPG13, set);
361 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
362}
363
364#undef LCD_UPPER_MARGIN
365#define LCD_UPPER_MARGIN 2
366
367static struct ili9320_platdata jive_lcm_config = {
368 .hsize = LCD_XRES,
369 .vsize = LCD_YRES,
370
371 .reset = jive_lcm_reset,
372 .suspend = ILI9320_SUSPEND_DEEP,
373
374 .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
375 .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
376 ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
377 .display3 = 0x0,
378 .display4 = 0x0,
379 .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
380 ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
381 .rgb_if2 = ILI9320_RGBIF2_DPL,
382 .interface2 = 0x0,
383 .interface3 = 0x3,
384 .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
385 ILI9320_INTERFACE4_DIVE(1)),
386 .interface5 = 0x0,
387 .interface6 = 0x0,
388};
389
390
391
392static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
393{
394 s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
395}
396
397static struct s3c2410_spigpio_info jive_lcd_spi = {
398 .bus_num = 1,
399 .pin_clk = S3C2410_GPG8,
400 .pin_mosi = S3C2410_GPB8,
401 .chip_select = jive_lcd_spi_chipselect,
402};
403
404static struct platform_device jive_device_lcdspi = {
405 .name = "s3c24xx-spi-gpio",
406 .id = 1,
407 .num_resources = 0,
408 .dev.platform_data = &jive_lcd_spi,
409};
410
411
412
413static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
414{
415 s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
416}
417
418static struct s3c2410_spigpio_info jive_wm8750_spi = {
419 .bus_num = 2,
420 .pin_clk = S3C2410_GPB4,
421 .pin_mosi = S3C2410_GPB9,
422 .chip_select = jive_wm8750_chipselect,
423};
424
425static struct platform_device jive_device_wm8750 = {
426 .name = "s3c24xx-spi-gpio",
427 .id = 2,
428 .num_resources = 0,
429 .dev.platform_data = &jive_wm8750_spi,
430};
431
432
433
434static struct spi_board_info __initdata jive_spi_devs[] = {
435 [0] = {
436 .modalias = "VGG2432A4",
437 .bus_num = 1,
438 .chip_select = 0,
439 .mode = SPI_MODE_3,
440 .max_speed_hz = 100000,
441 .platform_data = &jive_lcm_config,
442 }, {
443 .modalias = "WM8750",
444 .bus_num = 2,
445 .chip_select = 0,
446 .mode = SPI_MODE_0,
447 .max_speed_hz = 100000,
448 },
449};
450
451
452
453static struct s3c2410_platform_i2c jive_i2c_cfg = {
454 .max_freq = 80 * 1000,
455 .bus_freq = 50 * 1000,
456 .flags = S3C_IICFLG_FILTER,
457 .sda_delay = 2,
458};
459
460static struct i2c_board_info jive_i2c_devs[] = {
461 [0] = {
462 I2C_BOARD_INFO("lis302dl", 0x1c),
463 .irq = IRQ_EINT14,
464 },
465};
466
467
468
469static struct platform_device *jive_devices[] __initdata = {
470 &s3c_device_usb,
471 &s3c_device_rtc,
472 &s3c_device_wdt,
473 &s3c_device_i2c,
474 &s3c_device_lcd,
475 &jive_device_lcdspi,
476 &jive_device_wm8750,
477 &s3c_device_nand,
478 &s3c_device_usbgadget,
479};
480
481static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
482 .vbus_pin = S3C2410_GPG1,
483};
484
485
486
487#ifdef CONFIG_PM
488static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
489{
490
491
492
493
494 __raw_writel(0x2BED, S3C2412_INFORM0);
495 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
496
497 return 0;
498}
499
500static int jive_pm_resume(struct sys_device *sd)
501{
502 __raw_writel(0x0, S3C2412_INFORM0);
503 return 0;
504}
505
506#else
507#define jive_pm_suspend NULL
508#define jive_pm_resume NULL
509#endif
510
511static struct sysdev_class jive_pm_sysclass = {
512 .name = "jive-pm",
513 .suspend = jive_pm_suspend,
514 .resume = jive_pm_resume,
515};
516
517static struct sys_device jive_pm_sysdev = {
518 .cls = &jive_pm_sysclass,
519};
520
521static void __init jive_map_io(void)
522{
523 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
524 s3c24xx_init_clocks(12000000);
525 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
526}
527
528static void jive_power_off(void)
529{
530 printk(KERN_INFO "powering system down...\n");
531
532 s3c2410_gpio_setpin(S3C2410_GPC5, 1);
533 s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
534}
535
536static void __init jive_machine_init(void)
537{
538
539
540 sysdev_class_register(&jive_pm_sysclass);
541 sysdev_register(&jive_pm_sysdev);
542
543
544
545
546
547
548
549 __raw_writel(S3C2412_SLPCON_IN(0) |
550 S3C2412_SLPCON_PULL(1) |
551 S3C2412_SLPCON_HIGH(2) |
552 S3C2412_SLPCON_PULL(3) |
553 S3C2412_SLPCON_PULL(4) |
554 S3C2412_SLPCON_PULL(5) |
555 S3C2412_SLPCON_PULL(6) |
556 S3C2412_SLPCON_HIGH(7) |
557 S3C2412_SLPCON_PULL(8) |
558 S3C2412_SLPCON_PULL(9) |
559 S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
560
561
562
563 __raw_writel(S3C2412_SLPCON_PULL(0) |
564 S3C2412_SLPCON_PULL(1) |
565 S3C2412_SLPCON_PULL(2) |
566 S3C2412_SLPCON_PULL(3) |
567 S3C2412_SLPCON_PULL(4) |
568 S3C2412_SLPCON_PULL(5) |
569 S3C2412_SLPCON_LOW(6) |
570 S3C2412_SLPCON_PULL(6) |
571 S3C2412_SLPCON_PULL(7) |
572 S3C2412_SLPCON_PULL(8) |
573 S3C2412_SLPCON_PULL(9) |
574 S3C2412_SLPCON_PULL(10) |
575 S3C2412_SLPCON_PULL(11) |
576 S3C2412_SLPCON_PULL(12) |
577 S3C2412_SLPCON_PULL(13) |
578 S3C2412_SLPCON_PULL(14) |
579 S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
580
581
582
583 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
584
585
586
587 __raw_writel(S3C2412_SLPCON_LOW(0) |
588 S3C2412_SLPCON_LOW(1) |
589 S3C2412_SLPCON_LOW(2) |
590 S3C2412_SLPCON_EINT(3) |
591 S3C2412_SLPCON_EINT(4) |
592 S3C2412_SLPCON_EINT(5) |
593 S3C2412_SLPCON_EINT(6) |
594 S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
595
596
597
598 __raw_writel(S3C2412_SLPCON_IN(0) |
599 S3C2412_SLPCON_IN(1) |
600 S3C2412_SLPCON_IN(2) |
601 S3C2412_SLPCON_IN(3) |
602 S3C2412_SLPCON_IN(4) |
603 S3C2412_SLPCON_IN(5) |
604 S3C2412_SLPCON_IN(6) |
605 S3C2412_SLPCON_IN(7) |
606 S3C2412_SLPCON_PULL(8) |
607 S3C2412_SLPCON_PULL(9) |
608 S3C2412_SLPCON_IN(10) |
609 S3C2412_SLPCON_PULL(11) |
610 S3C2412_SLPCON_PULL(12) |
611 S3C2412_SLPCON_PULL(13) |
612 S3C2412_SLPCON_IN(14) |
613 S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
614
615
616
617 __raw_writel(S3C2412_SLPCON_PULL(0) |
618 S3C2412_SLPCON_PULL(1) |
619 S3C2412_SLPCON_PULL(2) |
620 S3C2412_SLPCON_PULL(3) |
621 S3C2412_SLPCON_PULL(4) |
622 S3C2412_SLPCON_PULL(5) |
623 S3C2412_SLPCON_PULL(6) |
624 S3C2412_SLPCON_IN(7) |
625 S3C2412_SLPCON_IN(8) |
626 S3C2412_SLPCON_PULL(9) |
627 S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
628
629
630
631 s3c2410_pm_init();
632
633 s3c_device_nand.dev.platform_data = &jive_nand_info;
634
635
636
637 s3c2410_gpio_setpin(S3C2410_GPG13, 0);
638 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
639
640 s3c2410_gpio_setpin(S3C2410_GPB7, 1);
641 s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
642
643 s3c2410_gpio_setpin(S3C2410_GPB6, 0);
644 s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
645
646 s3c2410_gpio_setpin(S3C2410_GPG8, 1);
647 s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
648
649
650
651 s3c2410_gpio_setpin(S3C2410_GPH10, 1);
652 s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
653
654
655
656
657 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
658 S3C2410_MISCCR_USBSUSPND0 |
659 S3C2410_MISCCR_USBSUSPND1, 0x0);
660
661 s3c24xx_udc_set_platdata(&jive_udc_cfg);
662 s3c24xx_fb_set_platdata(&jive_lcd_config);
663
664 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
665
666 s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
667 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
668
669 pm_power_off = jive_power_off;
670
671 platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
672}
673
674MACHINE_START(JIVE, "JIVE")
675
676 .phys_io = S3C2410_PA_UART,
677 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
678 .boot_params = S3C2410_SDRAM_PA + 0x100,
679
680 .init_irq = s3c24xx_init_irq,
681 .map_io = jive_map_io,
682 .init_machine = jive_machine_init,
683 .timer = &s3c24xx_timer,
684MACHINE_END
685
