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12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/ioport.h>
17#include <linux/spinlock.h>
18
19#include <asm/io.h>
20#include <asm/mach-types.h>
21#include <mach/gpmc.h>
22
23#undef DEBUG
24
25#ifdef CONFIG_ARCH_OMAP2420
26#define GPMC_BASE 0x6800a000
27#endif
28
29#ifdef CONFIG_ARCH_OMAP2430
30#define GPMC_BASE 0x6E000000
31#endif
32
33#define GPMC_REVISION 0x00
34#define GPMC_SYSCONFIG 0x10
35#define GPMC_SYSSTATUS 0x14
36#define GPMC_IRQSTATUS 0x18
37#define GPMC_IRQENABLE 0x1c
38#define GPMC_TIMEOUT_CONTROL 0x40
39#define GPMC_ERR_ADDRESS 0x44
40#define GPMC_ERR_TYPE 0x48
41#define GPMC_CONFIG 0x50
42#define GPMC_STATUS 0x54
43#define GPMC_PREFETCH_CONFIG1 0x1e0
44#define GPMC_PREFETCH_CONFIG2 0x1e4
45#define GPMC_PREFETCH_CONTROL 0x1ec
46#define GPMC_PREFETCH_STATUS 0x1f0
47#define GPMC_ECC_CONFIG 0x1f4
48#define GPMC_ECC_CONTROL 0x1f8
49#define GPMC_ECC_SIZE_CONFIG 0x1fc
50
51#define GPMC_CS0 0x60
52#define GPMC_CS_SIZE 0x30
53
54#define GPMC_CS_NUM 8
55#define GPMC_MEM_START 0x00000000
56#define GPMC_MEM_END 0x3FFFFFFF
57#define BOOT_ROM_SPACE 0x100000
58
59#define GPMC_CHUNK_SHIFT 24
60#define GPMC_SECTION_SHIFT 28
61
62static struct resource gpmc_mem_root;
63static struct resource gpmc_cs_mem[GPMC_CS_NUM];
64static DEFINE_SPINLOCK(gpmc_mem_lock);
65static unsigned gpmc_cs_map;
66
67static void __iomem *gpmc_base =
68 (void __iomem *) IO_ADDRESS(GPMC_BASE);
69static void __iomem *gpmc_cs_base =
70 (void __iomem *) IO_ADDRESS(GPMC_BASE) + GPMC_CS0;
71
72static struct clk *gpmc_fck;
73
74static void gpmc_write_reg(int idx, u32 val)
75{
76 __raw_writel(val, gpmc_base + idx);
77}
78
79static u32 gpmc_read_reg(int idx)
80{
81 return __raw_readl(gpmc_base + idx);
82}
83
84void gpmc_cs_write_reg(int cs, int idx, u32 val)
85{
86 void __iomem *reg_addr;
87
88 reg_addr = gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx;
89 __raw_writel(val, reg_addr);
90}
91
92u32 gpmc_cs_read_reg(int cs, int idx)
93{
94 return __raw_readl(gpmc_cs_base + (cs * GPMC_CS_SIZE) + idx);
95}
96
97unsigned long gpmc_get_fclk_period(void)
98{
99
100 return 1000000000 / ((clk_get_rate(gpmc_fck)) / 1000);
101}
102
103unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
104{
105 unsigned long tick_ps;
106
107
108 tick_ps = gpmc_get_fclk_period();
109
110 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
111}
112
113unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns)
114{
115 unsigned long ticks = gpmc_ns_to_ticks(time_ns);
116
117 return ticks * gpmc_get_fclk_period() / 1000;
118}
119
120#ifdef DEBUG
121static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
122 int time, const char *name)
123#else
124static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
125 int time)
126#endif
127{
128 u32 l;
129 int ticks, mask, nr_bits;
130
131 if (time == 0)
132 ticks = 0;
133 else
134 ticks = gpmc_ns_to_ticks(time);
135 nr_bits = end_bit - st_bit + 1;
136 if (ticks >= 1 << nr_bits) {
137#ifdef DEBUG
138 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n",
139 cs, name, time, ticks, 1 << nr_bits);
140#endif
141 return -1;
142 }
143
144 mask = (1 << nr_bits) - 1;
145 l = gpmc_cs_read_reg(cs, reg);
146#ifdef DEBUG
147 printk(KERN_INFO
148 "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
149 cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
150 (l >> st_bit) & mask, time);
151#endif
152 l &= ~(mask << st_bit);
153 l |= ticks << st_bit;
154 gpmc_cs_write_reg(cs, reg, l);
155
156 return 0;
157}
158
159#ifdef DEBUG
160#define GPMC_SET_ONE(reg, st, end, field) \
161 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
162 t->field, #field) < 0) \
163 return -1
164#else
165#define GPMC_SET_ONE(reg, st, end, field) \
166 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
167 return -1
168#endif
169
170int gpmc_cs_calc_divider(int cs, unsigned int sync_clk)
171{
172 int div;
173 u32 l;
174
175 l = sync_clk * 1000 + (gpmc_get_fclk_period() - 1);
176 div = l / gpmc_get_fclk_period();
177 if (div > 4)
178 return -1;
179 if (div <= 0)
180 div = 1;
181
182 return div;
183}
184
185int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
186{
187 int div;
188 u32 l;
189
190 div = gpmc_cs_calc_divider(cs, t->sync_clk);
191 if (div < 0)
192 return -1;
193
194 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
195 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
196 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
197
198 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
199 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
200 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
201
202 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
203 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
204 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
205 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
206
207 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
208 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
209 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
210
211 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
212
213
214
215
216 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
217 if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
218#ifdef DEBUG
219 printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
220 cs, (div * gpmc_get_fclk_period()) / 1000, div);
221#endif
222 l &= ~0x03;
223 l |= (div - 1);
224 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
225 }
226
227 return 0;
228}
229
230static void gpmc_cs_enable_mem(int cs, u32 base, u32 size)
231{
232 u32 l;
233 u32 mask;
234
235 mask = (1 << GPMC_SECTION_SHIFT) - size;
236 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
237 l &= ~0x3f;
238 l = (base >> GPMC_CHUNK_SHIFT) & 0x3f;
239 l &= ~(0x0f << 8);
240 l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8;
241 l |= 1 << 6;
242 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
243}
244
245static void gpmc_cs_disable_mem(int cs)
246{
247 u32 l;
248
249 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
250 l &= ~(1 << 6);
251 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
252}
253
254static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
255{
256 u32 l;
257 u32 mask;
258
259 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
260 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
261 mask = (l >> 8) & 0x0f;
262 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
263}
264
265static int gpmc_cs_mem_enabled(int cs)
266{
267 u32 l;
268
269 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
270 return l & (1 << 6);
271}
272
273int gpmc_cs_set_reserved(int cs, int reserved)
274{
275 if (cs > GPMC_CS_NUM)
276 return -ENODEV;
277
278 gpmc_cs_map &= ~(1 << cs);
279 gpmc_cs_map |= (reserved ? 1 : 0) << cs;
280
281 return 0;
282}
283
284int gpmc_cs_reserved(int cs)
285{
286 if (cs > GPMC_CS_NUM)
287 return -ENODEV;
288
289 return gpmc_cs_map & (1 << cs);
290}
291
292static unsigned long gpmc_mem_align(unsigned long size)
293{
294 int order;
295
296 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
297 order = GPMC_CHUNK_SHIFT - 1;
298 do {
299 size >>= 1;
300 order++;
301 } while (size);
302 size = 1 << order;
303 return size;
304}
305
306static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
307{
308 struct resource *res = &gpmc_cs_mem[cs];
309 int r;
310
311 size = gpmc_mem_align(size);
312 spin_lock(&gpmc_mem_lock);
313 res->start = base;
314 res->end = base + size - 1;
315 r = request_resource(&gpmc_mem_root, res);
316 spin_unlock(&gpmc_mem_lock);
317
318 return r;
319}
320
321int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
322{
323 struct resource *res = &gpmc_cs_mem[cs];
324 int r = -1;
325
326 if (cs > GPMC_CS_NUM)
327 return -ENODEV;
328
329 size = gpmc_mem_align(size);
330 if (size > (1 << GPMC_SECTION_SHIFT))
331 return -ENOMEM;
332
333 spin_lock(&gpmc_mem_lock);
334 if (gpmc_cs_reserved(cs)) {
335 r = -EBUSY;
336 goto out;
337 }
338 if (gpmc_cs_mem_enabled(cs))
339 r = adjust_resource(res, res->start & ~(size - 1), size);
340 if (r < 0)
341 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
342 size, NULL, NULL);
343 if (r < 0)
344 goto out;
345
346 gpmc_cs_enable_mem(cs, res->start, res->end - res->start + 1);
347 *base = res->start;
348 gpmc_cs_set_reserved(cs, 1);
349out:
350 spin_unlock(&gpmc_mem_lock);
351 return r;
352}
353
354void gpmc_cs_free(int cs)
355{
356 spin_lock(&gpmc_mem_lock);
357 if (cs >= GPMC_CS_NUM || !gpmc_cs_reserved(cs)) {
358 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
359 BUG();
360 spin_unlock(&gpmc_mem_lock);
361 return;
362 }
363 gpmc_cs_disable_mem(cs);
364 release_resource(&gpmc_cs_mem[cs]);
365 gpmc_cs_set_reserved(cs, 0);
366 spin_unlock(&gpmc_mem_lock);
367}
368
369void __init gpmc_mem_init(void)
370{
371 int cs;
372 unsigned long boot_rom_space = 0;
373
374
375
376
377 boot_rom_space = BOOT_ROM_SPACE;
378
379 if (machine_is_omap_apollon())
380 boot_rom_space = 0;
381 gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space;
382 gpmc_mem_root.end = GPMC_MEM_END;
383
384
385 for (cs = 0; cs < GPMC_CS_NUM; cs++) {
386 u32 base, size;
387
388 if (!gpmc_cs_mem_enabled(cs))
389 continue;
390 gpmc_cs_get_memconf(cs, &base, &size);
391 if (gpmc_cs_insert_mem(cs, base, size) < 0)
392 BUG();
393 }
394}
395
396void __init gpmc_init(void)
397{
398 u32 l;
399
400 gpmc_fck = clk_get(NULL, "gpmc_fck");
401 if (IS_ERR(gpmc_fck))
402 WARN_ON(1);
403 else
404 clk_enable(gpmc_fck);
405
406 l = gpmc_read_reg(GPMC_REVISION);
407 printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
408
409 l = gpmc_read_reg(GPMC_SYSCONFIG);
410 l &= 0x03 << 3;
411 l |= (0x02 << 3) | (1 << 0);
412 gpmc_write_reg(GPMC_SYSCONFIG, l);
413
414 gpmc_mem_init();
415}
416
