1#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H 2#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_24XX_H 3 4/* 5 * OMAP24XX Clock Management register bits 6 * 7 * Copyright (C) 2007 Texas Instruments, Inc. 8 * Copyright (C) 2007 Nokia Corporation 9 * 10 * Written by Paul Walmsley 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License version 2 as 14 * published by the Free Software Foundation. 15 */ 16 17#include "cm.h" 18 19/* Bits shared between registers */ 20 21/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ 22#define OMAP24XX_EN_CAM_SHIFT 31 23#define OMAP24XX_EN_CAM (1 << 31) 24#define OMAP24XX_EN_WDT4_SHIFT 29 25#define OMAP24XX_EN_WDT4 (1 << 29) 26#define OMAP2420_EN_WDT3_SHIFT 28 27#define OMAP2420_EN_WDT3 (1 << 28) 28#define OMAP24XX_EN_MSPRO_SHIFT 27 29#define OMAP24XX_EN_MSPRO (1 << 27) 30#define OMAP24XX_EN_FAC_SHIFT 25 31#define OMAP24XX_EN_FAC (1 << 25) 32#define OMAP2420_EN_EAC_SHIFT 24 33#define OMAP2420_EN_EAC (1 << 24) 34#define OMAP24XX_EN_HDQ_SHIFT 23 35#define OMAP24XX_EN_HDQ (1 << 23) 36#define OMAP2420_EN_I2C2_SHIFT 20 37#define OMAP2420_EN_I2C2 (1 << 20) 38#define OMAP2420_EN_I2C1_SHIFT 19 39#define OMAP2420_EN_I2C1 (1 << 19) 40 41/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */ 42#define OMAP2430_EN_MCBSP5_SHIFT 5 43#define OMAP2430_EN_MCBSP5 (1 << 5) 44#define OMAP2430_EN_MCBSP4_SHIFT 4 45#define OMAP2430_EN_MCBSP4 (1 << 4) 46#define OMAP2430_EN_MCBSP3_SHIFT 3 47#define OMAP2430_EN_MCBSP3 (1 << 3) 48#define OMAP24XX_EN_SSI_SHIFT 1 49#define OMAP24XX_EN_SSI (1 << 1) 50 51/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */ 52#define OMAP24XX_EN_MPU_WDT_SHIFT 3 53#define OMAP24XX_EN_MPU_WDT (1 << 3) 54 55/* Bits specific to each register */ 56 57/* CM_IDLEST_MPU */ 58/* 2430 only */ 59#define OMAP2430_ST_MPU (1 << 0) 60 61/* CM_CLKSEL_MPU */ 62#define OMAP24XX_CLKSEL_MPU_SHIFT 0 63#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0) 64 65/* CM_CLKSTCTRL_MPU */ 66#define OMAP24XX_AUTOSTATE_MPU (1 << 0) 67 68/* CM_FCLKEN1_CORE specific bits*/ 69#define OMAP24XX_EN_TV_SHIFT 2 70#define OMAP24XX_EN_TV (1 << 2) 71#define OMAP24XX_EN_DSS2_SHIFT 1 72#define OMAP24XX_EN_DSS2 (1 << 1) 73#define OMAP24XX_EN_DSS1_SHIFT 0 74#define OMAP24XX_EN_DSS1 (1 << 0) 75 76/* CM_FCLKEN2_CORE specific bits */ 77#define OMAP2430_EN_I2CHS2_SHIFT 20 78#define OMAP2430_EN_I2CHS2 (1 << 20) 79#define OMAP2430_EN_I2CHS1_SHIFT 19 80#define OMAP2430_EN_I2CHS1 (1 << 19) 81#define OMAP2430_EN_MMCHSDB2_SHIFT 17 82#define OMAP2430_EN_MMCHSDB2 (1 << 17) 83#define OMAP2430_EN_MMCHSDB1_SHIFT 16 84#define OMAP2430_EN_MMCHSDB1 (1 << 16) 85 86/* CM_ICLKEN1_CORE specific bits */ 87#define OMAP24XX_EN_MAILBOXES_SHIFT 30 88#define OMAP24XX_EN_MAILBOXES (1 << 30) 89#define OMAP24XX_EN_DSS_SHIFT 0 90#define OMAP24XX_EN_DSS (1 << 0) 91 92/* CM_ICLKEN2_CORE specific bits */ 93 94/* CM_ICLKEN3_CORE */ 95/* 2430 only */ 96#define OMAP2430_EN_SDRC_SHIFT 2 97#define OMAP2430_EN_SDRC (1 << 2) 98 99/* CM_ICLKEN4_CORE */ 100#define OMAP24XX_EN_PKA_SHIFT 4 101#define OMAP24XX_EN_PKA (1 << 4) 102#define OMAP24XX_EN_AES_SHIFT 3 103#define OMAP24XX_EN_AES (1 << 3) 104#define OMAP24XX_EN_RNG_SHIFT 2 105#define OMAP24XX_EN_RNG (1 << 2) 106#define OMAP24XX_EN_SHA_SHIFT 1 107#define OMAP24XX_EN_SHA (1 << 1) 108#define OMAP24XX_EN_DES_SHIFT 0 109#define OMAP24XX_EN_DES (1 << 0) 110 111/* CM_IDLEST1_CORE specific bits */ 112#define OMAP24XX_ST_MAILBOXES (1 << 30) 113#define OMAP24XX_ST_WDT4 (1 << 29) 114#define OMAP2420_ST_WDT3 (1 << 28) 115#define OMAP24XX_ST_MSPRO (1 << 27) 116#define OMAP24XX_ST_FAC (1 << 25) 117#define OMAP2420_ST_EAC (1 << 24) 118#define OMAP24XX_ST_HDQ (1 << 23) 119#define OMAP24XX_ST_I2C2 (1 << 20) 120#define OMAP24XX_ST_I2C1 (1 << 19) 121#define OMAP24XX_ST_MCBSP2 (1 << 16) 122#define OMAP24XX_ST_MCBSP1 (1 << 15) 123#define OMAP24XX_ST_DSS (1 << 0) 124 125/* CM_IDLEST2_CORE */ 126#define OMAP2430_ST_MCBSP5 (1 << 5) 127#define OMAP2430_ST_MCBSP4 (1 << 4) 128#define OMAP2430_ST_MCBSP3 (1 << 3) 129#define OMAP24XX_ST_SSI (1 << 1) 130 131/* CM_IDLEST3_CORE */ 132/* 2430 only */ 133#define OMAP2430_ST_SDRC (1 << 2) 134 135/* CM_IDLEST4_CORE */ 136#define OMAP24XX_ST_PKA (1 << 4) 137#define OMAP24XX_ST_AES (1 << 3) 138#define OMAP24XX_ST_RNG (1 << 2) 139#define OMAP24XX_ST_SHA (1 << 1) 140#define OMAP24XX_ST_DES (1 << 0) 141 142/* CM_AUTOIDLE1_CORE */ 143#define OMAP24XX_AUTO_CAM (1 << 31) 144#define OMAP24XX_AUTO_MAILBOXES (1 << 30) 145#define OMAP24XX_AUTO_WDT4 (1 << 29) 146#define OMAP2420_AUTO_WDT3 (1 << 28) 147#define OMAP24XX_AUTO_MSPRO (1 << 27) 148#define OMAP2420_AUTO_MMC (1 << 26) 149#define OMAP24XX_AUTO_FAC (1 << 25) 150#define OMAP2420_AUTO_EAC (1 << 24) 151#define OMAP24XX_AUTO_HDQ (1 << 23) 152#define OMAP24XX_AUTO_UART2 (1 << 22) 153#define OMAP24XX_AUTO_UART1 (1 << 21) 154#define OMAP24XX_AUTO_I2C2 (1 << 20) 155#define OMAP24XX_AUTO_I2C1 (1 << 19) 156#define OMAP24XX_AUTO_MCSPI2 (1 << 18) 157#define OMAP24XX_AUTO_MCSPI1 (1 << 17) 158#define OMAP24XX_AUTO_MCBSP2 (1 << 16) 159#define OMAP24XX_AUTO_MCBSP1 (1 << 15) 160#define OMAP24XX_AUTO_GPT12 (1 << 14) 161#define OMAP24XX_AUTO_GPT11 (1 << 13) 162#define OMAP24XX_AUTO_GPT10 (1 << 12) 163#define OMAP24XX_AUTO_GPT9 (1 << 11) 164#define OMAP24XX_AUTO_GPT8 (1 << 10) 165#define OMAP24XX_AUTO_GPT7 (1 << 9) 166#define OMAP24XX_AUTO_GPT6 (1 << 8) 167#define OMAP24XX_AUTO_GPT5 (1 << 7) 168#define OMAP24XX_AUTO_GPT4 (1 << 6) 169#define OMAP24XX_AUTO_GPT3 (1 << 5) 170#define OMAP24XX_AUTO_GPT2 (1 << 4) 171#define OMAP2420_AUTO_VLYNQ (1 << 3) 172#define OMAP24XX_AUTO_DSS (1 << 0) 173 174/* CM_AUTOIDLE2_CORE */ 175#define OMAP2430_AUTO_MDM_INTC (1 << 11) 176#define OMAP2430_AUTO_GPIO5 (1 << 10) 177#define OMAP2430_AUTO_MCSPI3 (1 << 9) 178#define OMAP2430_AUTO_MMCHS2 (1 << 8) 179#define OMAP2430_AUTO_MMCHS1 (1 << 7) 180#define OMAP2430_AUTO_USBHS (1 << 6) 181#define OMAP2430_AUTO_MCBSP5 (1 << 5) 182#define OMAP2430_AUTO_MCBSP4 (1 << 4) 183#define OMAP2430_AUTO_MCBSP3 (1 << 3) 184#define OMAP24XX_AUTO_UART3 (1 << 2) 185#define OMAP24XX_AUTO_SSI (1 << 1) 186#define OMAP24XX_AUTO_USB (1 << 0) 187 188/* CM_AUTOIDLE3_CORE */ 189#define OMAP24XX_AUTO_SDRC (1 << 2) 190#define OMAP24XX_AUTO_GPMC (1 << 1) 191#define OMAP24XX_AUTO_SDMA (1 << 0) 192 193/* CM_AUTOIDLE4_CORE */ 194#define OMAP24XX_AUTO_PKA (1 << 4) 195#define OMAP24XX_AUTO_AES (1 << 3) 196#define OMAP24XX_AUTO_RNG (1 << 2) 197#define OMAP24XX_AUTO_SHA (1 << 1) 198#define OMAP24XX_AUTO_DES (1 << 0) 199 200/* CM_CLKSEL1_CORE */ 201#define OMAP24XX_CLKSEL_USB_SHIFT 25 202#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) 203#define OMAP24XX_CLKSEL_SSI_SHIFT 20 204#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) 205#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15 206#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) 207#define OMAP24XX_CLKSEL_DSS2_SHIFT 13 208#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) 209#define OMAP24XX_CLKSEL_DSS1_SHIFT 8 210#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) 211#define OMAP24XX_CLKSEL_L4_SHIFT 5 212#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5) 213#define OMAP24XX_CLKSEL_L3_SHIFT 0 214#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0) 215 216/* CM_CLKSEL2_CORE */ 217#define OMAP24XX_CLKSEL_GPT12_SHIFT 22 218#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) 219#define OMAP24XX_CLKSEL_GPT11_SHIFT 20 220#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) 221#define OMAP24XX_CLKSEL_GPT10_SHIFT 18 222#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) 223#define OMAP24XX_CLKSEL_GPT9_SHIFT 16 224#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) 225#define OMAP24XX_CLKSEL_GPT8_SHIFT 14 226#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) 227#define OMAP24XX_CLKSEL_GPT7_SHIFT 12 228#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) 229#define OMAP24XX_CLKSEL_GPT6_SHIFT 10 230#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) 231#define OMAP24XX_CLKSEL_GPT5_SHIFT 8 232#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) 233#define OMAP24XX_CLKSEL_GPT4_SHIFT 6 234#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) 235#define OMAP24XX_CLKSEL_GPT3_SHIFT 4 236#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) 237#define OMAP24XX_CLKSEL_GPT2_SHIFT 2 238#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) 239 240/* CM_CLKSTCTRL_CORE */ 241#define OMAP24XX_AUTOSTATE_DSS (1 << 2) 242#define OMAP24XX_AUTOSTATE_L4 (1 << 1) 243#define OMAP24XX_AUTOSTATE_L3 (1 << 0) 244 245/* CM_FCLKEN_GFX */ 246#define OMAP24XX_EN_3D_SHIFT 2 247#define OMAP24XX_EN_3D (1 << 2) 248#define OMAP24XX_EN_2D_SHIFT 1 249#define OMAP24XX_EN_2D (1 << 1) 250 251/* CM_ICLKEN_GFX specific bits */ 252 253/* CM_IDLEST_GFX specific bits */ 254 255/* CM_CLKSEL_GFX specific bits */ 256 257/* CM_CLKSTCTRL_GFX */ 258#define OMAP24XX_AUTOSTATE_GFX (1 << 0) 259 260/* CM_FCLKEN_WKUP specific bits */ 261 262/* CM_ICLKEN_WKUP specific bits */ 263#define OMAP2430_EN_ICR_SHIFT 6 264#define OMAP2430_EN_ICR (1 << 6) 265#define OMAP24XX_EN_OMAPCTRL_SHIFT 5 266#define OMAP24XX_EN_OMAPCTRL (1 << 5) 267#define OMAP24XX_EN_WDT1_SHIFT 4 268#define OMAP24XX_EN_WDT1 (1 << 4) 269#define OMAP24XX_EN_32KSYNC_SHIFT 1 270#define OMAP24XX_EN_32KSYNC (1 << 1) 271 272/* CM_IDLEST_WKUP specific bits */ 273#define OMAP2430_ST_ICR (1 << 6) 274#define OMAP24XX_ST_OMAPCTRL (1 << 5) 275#define OMAP24XX_ST_WDT1 (1 << 4) 276#define OMAP24XX_ST_MPU_WDT (1 << 3) 277#define OMAP24XX_ST_32KSYNC (1 << 1) 278 279/* CM_AUTOIDLE_WKUP */ 280#define OMAP24XX_AUTO_OMAPCTRL (1 << 5) 281#define OMAP24XX_AUTO_WDT1 (1 << 4) 282#define OMAP24XX_AUTO_MPU_WDT (1 << 3) 283#define OMAP24XX_AUTO_GPIOS (1 << 2) 284#define OMAP24XX_AUTO_32KSYNC (1 << 1) 285#define OMAP24XX_AUTO_GPT1 (1 << 0) 286 287/* CM_CLKSEL_WKUP */ 288#define OMAP24XX_CLKSEL_GPT1_SHIFT 0 289#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) 290 291/* CM_CLKEN_PLL */ 292#define OMAP24XX_EN_54M_PLL_SHIFT 6 293#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6) 294#define OMAP24XX_EN_96M_PLL_SHIFT 2 295#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2) 296#define OMAP24XX_EN_DPLL_SHIFT 0 297#define OMAP24XX_EN_DPLL_MASK (0x3 << 0) 298 299/* CM_IDLEST_CKGEN */ 300#define OMAP24XX_ST_54M_APLL (1 << 9) 301#define OMAP24XX_ST_96M_APLL (1 << 8) 302#define OMAP24XX_ST_54M_CLK (1 << 6) 303#define OMAP24XX_ST_12M_CLK (1 << 5) 304#define OMAP24XX_ST_48M_CLK (1 << 4) 305#define OMAP24XX_ST_96M_CLK (1 << 2) 306#define OMAP24XX_ST_CORE_CLK_SHIFT 0 307#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0) 308 309/* CM_AUTOIDLE_PLL */ 310#define OMAP24XX_AUTO_54M_SHIFT 6 311#define OMAP24XX_AUTO_54M_MASK (0x3 << 6) 312#define OMAP24XX_AUTO_96M_SHIFT 2 313#define OMAP24XX_AUTO_96M_MASK (0x3 << 2) 314#define OMAP24XX_AUTO_DPLL_SHIFT 0 315#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) 316 317/* CM_CLKSEL1_PLL */ 318#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28 319#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28) 320#define OMAP24XX_APLLS_CLKIN_SHIFT 23 321#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) 322#define OMAP24XX_DPLL_MULT_SHIFT 12 323#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) 324#define OMAP24XX_DPLL_DIV_SHIFT 8 325#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) 326#define OMAP24XX_54M_SOURCE_SHIFT 5 327#define OMAP24XX_54M_SOURCE (1 << 5) 328#define OMAP2430_96M_SOURCE_SHIFT 4 329#define OMAP2430_96M_SOURCE (1 << 4) 330#define OMAP24XX_48M_SOURCE_SHIFT 3 331#define OMAP24XX_48M_SOURCE (1 << 3) 332#define OMAP2430_ALTCLK_SOURCE_SHIFT 0 333#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0) 334 335/* CM_CLKSEL2_PLL */ 336#define OMAP24XX_CORE_CLK_SRC_SHIFT 0 337#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) 338 339/* CM_FCLKEN_DSP */ 340#define OMAP2420_EN_IVA_COP_SHIFT 10 341#define OMAP2420_EN_IVA_COP (1 << 10) 342#define OMAP2420_EN_IVA_MPU_SHIFT 8 343#define OMAP2420_EN_IVA_MPU (1 << 8) 344#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 345#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP (1 << 0) 346 347/* CM_ICLKEN_DSP */ 348#define OMAP2420_EN_DSP_IPI_SHIFT 1 349#define OMAP2420_EN_DSP_IPI (1 << 1) 350 351/* CM_IDLEST_DSP */ 352#define OMAP2420_ST_IVA (1 << 8) 353#define OMAP2420_ST_IPI (1 << 1) 354#define OMAP24XX_ST_DSP (1 << 0) 355 356/* CM_AUTOIDLE_DSP */ 357#define OMAP2420_AUTO_DSP_IPI (1 << 1) 358 359/* CM_CLKSEL_DSP */ 360#define OMAP2420_SYNC_IVA (1 << 13) 361#define OMAP2420_CLKSEL_IVA_SHIFT 8 362#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) 363#define OMAP24XX_SYNC_DSP (1 << 7) 364#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5 365#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) 366#define OMAP24XX_CLKSEL_DSP_SHIFT 0 367#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) 368 369/* CM_CLKSTCTRL_DSP */ 370#define OMAP2420_AUTOSTATE_IVA (1 << 8) 371#define OMAP24XX_AUTOSTATE_DSP (1 << 0) 372 373/* CM_FCLKEN_MDM */ 374/* 2430 only */ 375#define OMAP2430_EN_OSC_SHIFT 1 376#define OMAP2430_EN_OSC (1 << 1) 377 378/* CM_ICLKEN_MDM */ 379/* 2430 only */ 380#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 381#define OMAP2430_CM_ICLKEN_MDM_EN_MDM (1 << 0) 382 383/* CM_IDLEST_MDM specific bits */ 384/* 2430 only */ 385 386/* CM_AUTOIDLE_MDM */ 387/* 2430 only */ 388#define OMAP2430_AUTO_OSC (1 << 1) 389#define OMAP2430_AUTO_MDM (1 << 0) 390 391/* CM_CLKSEL_MDM */ 392/* 2430 only */ 393#define OMAP2430_SYNC_MDM (1 << 4) 394#define OMAP2430_CLKSEL_MDM_SHIFT 0 395#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) 396 397/* CM_CLKSTCTRL_MDM */ 398/* 2430 only */ 399#define OMAP2430_AUTOSTATE_MDM (1 << 0) 400 401#endif 402