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28#include <linux/clk.h>
29#include <linux/device.h>
30#include <linux/io.h>
31#include <linux/module.h>
32#include <linux/of.h>
33#include <linux/platform_device.h>
34#include <linux/pm_runtime.h>
35#include <linux/regmap.h>
36#include <linux/slab.h>
37#include <sound/core.h>
38#include <sound/pcm.h>
39#include <sound/pcm_params.h>
40#include <sound/soc.h>
41
42#include "tegra30_ahub.h"
43#include "tegra30_i2s.h"
44
45#define DRV_NAME "tegra30-i2s"
46
47static int tegra30_i2s_runtime_suspend(struct device *dev)
48{
49 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
50
51 regcache_cache_only(i2s->regmap, true);
52
53 clk_disable_unprepare(i2s->clk_i2s);
54
55 return 0;
56}
57
58static int tegra30_i2s_runtime_resume(struct device *dev)
59{
60 struct tegra30_i2s *i2s = dev_get_drvdata(dev);
61 int ret;
62
63 ret = clk_prepare_enable(i2s->clk_i2s);
64 if (ret) {
65 dev_err(dev, "clk_enable failed: %d\n", ret);
66 return ret;
67 }
68
69 regcache_cache_only(i2s->regmap, false);
70
71 return 0;
72}
73
74static int tegra30_i2s_startup(struct snd_pcm_substream *substream,
75 struct snd_soc_dai *dai)
76{
77 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
78 int ret;
79
80 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
81 ret = tegra30_ahub_allocate_tx_fifo(&i2s->playback_fifo_cif,
82 &i2s->playback_dma_data.addr,
83 &i2s->playback_dma_data.req_sel);
84 i2s->playback_dma_data.wrap = 4;
85 i2s->playback_dma_data.width = 32;
86 tegra30_ahub_set_rx_cif_source(i2s->playback_i2s_cif,
87 i2s->playback_fifo_cif);
88 } else {
89 ret = tegra30_ahub_allocate_rx_fifo(&i2s->capture_fifo_cif,
90 &i2s->capture_dma_data.addr,
91 &i2s->capture_dma_data.req_sel);
92 i2s->capture_dma_data.wrap = 4;
93 i2s->capture_dma_data.width = 32;
94 tegra30_ahub_set_rx_cif_source(i2s->capture_fifo_cif,
95 i2s->capture_i2s_cif);
96 }
97
98 return ret;
99}
100
101static void tegra30_i2s_shutdown(struct snd_pcm_substream *substream,
102 struct snd_soc_dai *dai)
103{
104 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
105
106 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
107 tegra30_ahub_unset_rx_cif_source(i2s->playback_i2s_cif);
108 tegra30_ahub_free_tx_fifo(i2s->playback_fifo_cif);
109 } else {
110 tegra30_ahub_unset_rx_cif_source(i2s->capture_fifo_cif);
111 tegra30_ahub_free_rx_fifo(i2s->capture_fifo_cif);
112 }
113}
114
115static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
116 unsigned int fmt)
117{
118 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
119 unsigned int mask, val;
120
121 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
122 case SND_SOC_DAIFMT_NB_NF:
123 break;
124 default:
125 return -EINVAL;
126 }
127
128 mask = TEGRA30_I2S_CTRL_MASTER_ENABLE;
129 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
130 case SND_SOC_DAIFMT_CBS_CFS:
131 val = TEGRA30_I2S_CTRL_MASTER_ENABLE;
132 break;
133 case SND_SOC_DAIFMT_CBM_CFM:
134 break;
135 default:
136 return -EINVAL;
137 }
138
139 mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
140 TEGRA30_I2S_CTRL_LRCK_MASK;
141 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
142 case SND_SOC_DAIFMT_DSP_A:
143 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
144 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
145 break;
146 case SND_SOC_DAIFMT_DSP_B:
147 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
148 val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
149 break;
150 case SND_SOC_DAIFMT_I2S:
151 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
152 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
153 break;
154 case SND_SOC_DAIFMT_RIGHT_J:
155 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
156 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
157 break;
158 case SND_SOC_DAIFMT_LEFT_J:
159 val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_LRCK;
160 val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
161 break;
162 default:
163 return -EINVAL;
164 }
165
166 pm_runtime_get_sync(dai->dev);
167 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
168 pm_runtime_put(dai->dev);
169
170 return 0;
171}
172
173static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
174 struct snd_pcm_hw_params *params,
175 struct snd_soc_dai *dai)
176{
177 struct device *dev = dai->dev;
178 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
179 unsigned int mask, val, reg;
180 int ret, sample_size, srate, i2sclock, bitcnt;
181
182 if (params_channels(params) != 2)
183 return -EINVAL;
184
185 mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
186 switch (params_format(params)) {
187 case SNDRV_PCM_FORMAT_S16_LE:
188 val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
189 sample_size = 16;
190 break;
191 default:
192 return -EINVAL;
193 }
194
195 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
196
197 srate = params_rate(params);
198
199
200 i2sclock = srate * params_channels(params) * sample_size * 2;
201
202 bitcnt = (i2sclock / (2 * srate)) - 1;
203 if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
204 return -EINVAL;
205
206 ret = clk_set_rate(i2s->clk_i2s, i2sclock);
207 if (ret) {
208 dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
209 return ret;
210 }
211
212 val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
213
214 if (i2sclock % (2 * srate))
215 val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
216
217 regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
218
219 val = (0 << TEGRA30_AUDIOCIF_CTRL_FIFO_THRESHOLD_SHIFT) |
220 (1 << TEGRA30_AUDIOCIF_CTRL_AUDIO_CHANNELS_SHIFT) |
221 (1 << TEGRA30_AUDIOCIF_CTRL_CLIENT_CHANNELS_SHIFT) |
222 TEGRA30_AUDIOCIF_CTRL_AUDIO_BITS_16 |
223 TEGRA30_AUDIOCIF_CTRL_CLIENT_BITS_16;
224
225 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
226 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_RX;
227 reg = TEGRA30_I2S_CIF_RX_CTRL;
228 } else {
229 val |= TEGRA30_AUDIOCIF_CTRL_DIRECTION_TX;
230 reg = TEGRA30_I2S_CIF_RX_CTRL;
231 }
232
233 regmap_write(i2s->regmap, reg, val);
234
235 val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
236 (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
237 regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
238
239 return 0;
240}
241
242static void tegra30_i2s_start_playback(struct tegra30_i2s *i2s)
243{
244 tegra30_ahub_enable_tx_fifo(i2s->playback_fifo_cif);
245 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
246 TEGRA30_I2S_CTRL_XFER_EN_TX,
247 TEGRA30_I2S_CTRL_XFER_EN_TX);
248}
249
250static void tegra30_i2s_stop_playback(struct tegra30_i2s *i2s)
251{
252 tegra30_ahub_disable_tx_fifo(i2s->playback_fifo_cif);
253 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
254 TEGRA30_I2S_CTRL_XFER_EN_TX, 0);
255}
256
257static void tegra30_i2s_start_capture(struct tegra30_i2s *i2s)
258{
259 tegra30_ahub_enable_rx_fifo(i2s->capture_fifo_cif);
260 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
261 TEGRA30_I2S_CTRL_XFER_EN_RX,
262 TEGRA30_I2S_CTRL_XFER_EN_RX);
263}
264
265static void tegra30_i2s_stop_capture(struct tegra30_i2s *i2s)
266{
267 tegra30_ahub_disable_rx_fifo(i2s->capture_fifo_cif);
268 regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL,
269 TEGRA30_I2S_CTRL_XFER_EN_RX, 0);
270}
271
272static int tegra30_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
273 struct snd_soc_dai *dai)
274{
275 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
276
277 switch (cmd) {
278 case SNDRV_PCM_TRIGGER_START:
279 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
280 case SNDRV_PCM_TRIGGER_RESUME:
281 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
282 tegra30_i2s_start_playback(i2s);
283 else
284 tegra30_i2s_start_capture(i2s);
285 break;
286 case SNDRV_PCM_TRIGGER_STOP:
287 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
288 case SNDRV_PCM_TRIGGER_SUSPEND:
289 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
290 tegra30_i2s_stop_playback(i2s);
291 else
292 tegra30_i2s_stop_capture(i2s);
293 break;
294 default:
295 return -EINVAL;
296 }
297
298 return 0;
299}
300
301static int tegra30_i2s_probe(struct snd_soc_dai *dai)
302{
303 struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
304
305 dai->capture_dma_data = &i2s->capture_dma_data;
306 dai->playback_dma_data = &i2s->playback_dma_data;
307
308 return 0;
309}
310
311static struct snd_soc_dai_ops tegra30_i2s_dai_ops = {
312 .startup = tegra30_i2s_startup,
313 .shutdown = tegra30_i2s_shutdown,
314 .set_fmt = tegra30_i2s_set_fmt,
315 .hw_params = tegra30_i2s_hw_params,
316 .trigger = tegra30_i2s_trigger,
317};
318
319static const struct snd_soc_dai_driver tegra30_i2s_dai_template = {
320 .probe = tegra30_i2s_probe,
321 .playback = {
322 .stream_name = "Playback",
323 .channels_min = 2,
324 .channels_max = 2,
325 .rates = SNDRV_PCM_RATE_8000_96000,
326 .formats = SNDRV_PCM_FMTBIT_S16_LE,
327 },
328 .capture = {
329 .stream_name = "Capture",
330 .channels_min = 2,
331 .channels_max = 2,
332 .rates = SNDRV_PCM_RATE_8000_96000,
333 .formats = SNDRV_PCM_FMTBIT_S16_LE,
334 },
335 .ops = &tegra30_i2s_dai_ops,
336 .symmetric_rates = 1,
337};
338
339static bool tegra30_i2s_wr_rd_reg(struct device *dev, unsigned int reg)
340{
341 switch (reg) {
342 case TEGRA30_I2S_CTRL:
343 case TEGRA30_I2S_TIMING:
344 case TEGRA30_I2S_OFFSET:
345 case TEGRA30_I2S_CH_CTRL:
346 case TEGRA30_I2S_SLOT_CTRL:
347 case TEGRA30_I2S_CIF_RX_CTRL:
348 case TEGRA30_I2S_CIF_TX_CTRL:
349 case TEGRA30_I2S_FLOWCTL:
350 case TEGRA30_I2S_TX_STEP:
351 case TEGRA30_I2S_FLOW_STATUS:
352 case TEGRA30_I2S_FLOW_TOTAL:
353 case TEGRA30_I2S_FLOW_OVER:
354 case TEGRA30_I2S_FLOW_UNDER:
355 case TEGRA30_I2S_LCOEF_1_4_0:
356 case TEGRA30_I2S_LCOEF_1_4_1:
357 case TEGRA30_I2S_LCOEF_1_4_2:
358 case TEGRA30_I2S_LCOEF_1_4_3:
359 case TEGRA30_I2S_LCOEF_1_4_4:
360 case TEGRA30_I2S_LCOEF_1_4_5:
361 case TEGRA30_I2S_LCOEF_2_4_0:
362 case TEGRA30_I2S_LCOEF_2_4_1:
363 case TEGRA30_I2S_LCOEF_2_4_2:
364 return true;
365 default:
366 return false;
367 };
368}
369
370static bool tegra30_i2s_volatile_reg(struct device *dev, unsigned int reg)
371{
372 switch (reg) {
373 case TEGRA30_I2S_FLOW_STATUS:
374 case TEGRA30_I2S_FLOW_TOTAL:
375 case TEGRA30_I2S_FLOW_OVER:
376 case TEGRA30_I2S_FLOW_UNDER:
377 return true;
378 default:
379 return false;
380 };
381}
382
383static const struct regmap_config tegra30_i2s_regmap_config = {
384 .reg_bits = 32,
385 .reg_stride = 4,
386 .val_bits = 32,
387 .max_register = TEGRA30_I2S_LCOEF_2_4_2,
388 .writeable_reg = tegra30_i2s_wr_rd_reg,
389 .readable_reg = tegra30_i2s_wr_rd_reg,
390 .volatile_reg = tegra30_i2s_volatile_reg,
391 .cache_type = REGCACHE_RBTREE,
392};
393
394static int tegra30_i2s_platform_probe(struct platform_device *pdev)
395{
396 struct tegra30_i2s *i2s;
397 u32 cif_ids[2];
398 struct resource *mem, *memregion;
399 void __iomem *regs;
400 int ret;
401
402 i2s = devm_kzalloc(&pdev->dev, sizeof(struct tegra30_i2s), GFP_KERNEL);
403 if (!i2s) {
404 dev_err(&pdev->dev, "Can't allocate tegra30_i2s\n");
405 ret = -ENOMEM;
406 goto err;
407 }
408 dev_set_drvdata(&pdev->dev, i2s);
409
410 i2s->dai = tegra30_i2s_dai_template;
411 i2s->dai.name = dev_name(&pdev->dev);
412
413 ret = of_property_read_u32_array(pdev->dev.of_node,
414 "nvidia,ahub-cif-ids", cif_ids,
415 ARRAY_SIZE(cif_ids));
416 if (ret < 0)
417 goto err;
418
419 i2s->playback_i2s_cif = cif_ids[0];
420 i2s->capture_i2s_cif = cif_ids[1];
421
422 i2s->clk_i2s = clk_get(&pdev->dev, NULL);
423 if (IS_ERR(i2s->clk_i2s)) {
424 dev_err(&pdev->dev, "Can't retrieve i2s clock\n");
425 ret = PTR_ERR(i2s->clk_i2s);
426 goto err;
427 }
428
429 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
430 if (!mem) {
431 dev_err(&pdev->dev, "No memory resource\n");
432 ret = -ENODEV;
433 goto err_clk_put;
434 }
435
436 memregion = devm_request_mem_region(&pdev->dev, mem->start,
437 resource_size(mem), DRV_NAME);
438 if (!memregion) {
439 dev_err(&pdev->dev, "Memory region already claimed\n");
440 ret = -EBUSY;
441 goto err_clk_put;
442 }
443
444 regs = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
445 if (!regs) {
446 dev_err(&pdev->dev, "ioremap failed\n");
447 ret = -ENOMEM;
448 goto err_clk_put;
449 }
450
451 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
452 &tegra30_i2s_regmap_config);
453 if (IS_ERR(i2s->regmap)) {
454 dev_err(&pdev->dev, "regmap init failed\n");
455 ret = PTR_ERR(i2s->regmap);
456 goto err_clk_put;
457 }
458 regcache_cache_only(i2s->regmap, true);
459
460 pm_runtime_enable(&pdev->dev);
461 if (!pm_runtime_enabled(&pdev->dev)) {
462 ret = tegra30_i2s_runtime_resume(&pdev->dev);
463 if (ret)
464 goto err_pm_disable;
465 }
466
467 ret = snd_soc_register_dai(&pdev->dev, &i2s->dai);
468 if (ret) {
469 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
470 ret = -ENOMEM;
471 goto err_suspend;
472 }
473
474 ret = tegra_pcm_platform_register(&pdev->dev);
475 if (ret) {
476 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
477 goto err_unregister_dai;
478 }
479
480 return 0;
481
482err_unregister_dai:
483 snd_soc_unregister_dai(&pdev->dev);
484err_suspend:
485 if (!pm_runtime_status_suspended(&pdev->dev))
486 tegra30_i2s_runtime_suspend(&pdev->dev);
487err_pm_disable:
488 pm_runtime_disable(&pdev->dev);
489err_clk_put:
490 clk_put(i2s->clk_i2s);
491err:
492 return ret;
493}
494
495static int tegra30_i2s_platform_remove(struct platform_device *pdev)
496{
497 struct tegra30_i2s *i2s = dev_get_drvdata(&pdev->dev);
498
499 pm_runtime_disable(&pdev->dev);
500 if (!pm_runtime_status_suspended(&pdev->dev))
501 tegra30_i2s_runtime_suspend(&pdev->dev);
502
503 tegra_pcm_platform_unregister(&pdev->dev);
504 snd_soc_unregister_dai(&pdev->dev);
505
506 clk_put(i2s->clk_i2s);
507
508 return 0;
509}
510
511static const struct of_device_id tegra30_i2s_of_match[] = {
512 { .compatible = "nvidia,tegra30-i2s", },
513 {},
514};
515
516static const struct dev_pm_ops tegra30_i2s_pm_ops = {
517 SET_RUNTIME_PM_OPS(tegra30_i2s_runtime_suspend,
518 tegra30_i2s_runtime_resume, NULL)
519};
520
521static struct platform_driver tegra30_i2s_driver = {
522 .driver = {
523 .name = DRV_NAME,
524 .owner = THIS_MODULE,
525 .of_match_table = tegra30_i2s_of_match,
526 .pm = &tegra30_i2s_pm_ops,
527 },
528 .probe = tegra30_i2s_platform_probe,
529 .remove = tegra30_i2s_platform_remove,
530};
531module_platform_driver(tegra30_i2s_driver);
532
533MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
534MODULE_DESCRIPTION("Tegra30 I2S ASoC driver");
535MODULE_LICENSE("GPL");
536MODULE_ALIAS("platform:" DRV_NAME);
537MODULE_DEVICE_TABLE(of, tegra30_i2s_of_match);
538
