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13
14#include <linux/module.h>
15#include <linux/moduleparam.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/pm.h>
19#include <linux/gcd.h>
20#include <linux/gpio.h>
21#include <linux/i2c.h>
22#include <linux/input.h>
23#include <linux/pm_runtime.h>
24#include <linux/regmap.h>
25#include <linux/regulator/consumer.h>
26#include <linux/slab.h>
27#include <linux/workqueue.h>
28#include <sound/core.h>
29#include <sound/jack.h>
30#include <sound/pcm.h>
31#include <sound/pcm_params.h>
32#include <sound/soc.h>
33#include <sound/initval.h>
34#include <sound/tlv.h>
35#include <sound/wm8962.h>
36#include <trace/events/asoc.h>
37
38#include "wm8962.h"
39
40#define WM8962_NUM_SUPPLIES 8
41static const char *wm8962_supply_names[WM8962_NUM_SUPPLIES] = {
42 "DCVDD",
43 "DBVDD",
44 "AVDD",
45 "CPVDD",
46 "MICVDD",
47 "PLLVDD",
48 "SPKVDD1",
49 "SPKVDD2",
50};
51
52
53struct wm8962_priv {
54 struct regmap *regmap;
55 struct snd_soc_codec *codec;
56
57 int sysclk;
58 int sysclk_rate;
59
60 int bclk;
61 int lrclk;
62
63 struct completion fll_lock;
64 int fll_src;
65 int fll_fref;
66 int fll_fout;
67
68 u16 dsp2_ena;
69
70 struct delayed_work mic_work;
71 struct snd_soc_jack *jack;
72
73 struct regulator_bulk_data supplies[WM8962_NUM_SUPPLIES];
74 struct notifier_block disable_nb[WM8962_NUM_SUPPLIES];
75
76#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
77 struct input_dev *beep;
78 struct work_struct beep_work;
79 int beep_rate;
80#endif
81
82#ifdef CONFIG_GPIOLIB
83 struct gpio_chip gpio_chip;
84#endif
85
86 int irq;
87};
88
89
90
91
92
93#define WM8962_REGULATOR_EVENT(n) \
94static int wm8962_regulator_event_##n(struct notifier_block *nb, \
95 unsigned long event, void *data) \
96{ \
97 struct wm8962_priv *wm8962 = container_of(nb, struct wm8962_priv, \
98 disable_nb[n]); \
99 if (event & REGULATOR_EVENT_DISABLE) { \
100 regcache_mark_dirty(wm8962->regmap); \
101 } \
102 return 0; \
103}
104
105WM8962_REGULATOR_EVENT(0)
106WM8962_REGULATOR_EVENT(1)
107WM8962_REGULATOR_EVENT(2)
108WM8962_REGULATOR_EVENT(3)
109WM8962_REGULATOR_EVENT(4)
110WM8962_REGULATOR_EVENT(5)
111WM8962_REGULATOR_EVENT(6)
112WM8962_REGULATOR_EVENT(7)
113
114static struct reg_default wm8962_reg[] = {
115 { 0, 0x009F },
116 { 1, 0x049F },
117 { 2, 0x0000 },
118 { 3, 0x0000 },
119
120 { 5, 0x0018 },
121 { 6, 0x2008 },
122 { 7, 0x000A },
123
124 { 9, 0x0300 },
125 { 10, 0x00C0 },
126 { 11, 0x00C0 },
127
128 { 14, 0x0040 },
129 { 15, 0x6243 },
130
131 { 17, 0x007B },
132
133 { 19, 0x1C32 },
134 { 20, 0x3200 },
135 { 21, 0x00C0 },
136 { 22, 0x00C0 },
137 { 23, 0x0160 },
138 { 24, 0x0000 },
139 { 25, 0x0000 },
140 { 26, 0x0000 },
141 { 27, 0x0010 },
142 { 28, 0x0000 },
143
144 { 30, 0x005E },
145 { 31, 0x0000 },
146 { 32, 0x0145 },
147 { 33, 0x0145 },
148 { 34, 0x0009 },
149 { 35, 0x0003 },
150 { 37, 0x0008 },
151 { 38, 0x0008 },
152
153 { 40, 0x0000 },
154 { 41, 0x0000 },
155
156 { 51, 0x0003 },
157
158 { 56, 0x0506 },
159 { 57, 0x0000 },
160 { 58, 0x0000 },
161
162 { 60, 0x0300 },
163 { 61, 0x0300 },
164
165 { 64, 0x0810 },
166
167 { 68, 0x001B },
168 { 69, 0x0000 },
169
170 { 71, 0x01FB },
171 { 72, 0x0000 },
172
173 { 82, 0x0004 },
174
175 { 87, 0x0000 },
176
177 { 90, 0x0000 },
178
179 { 93, 0x0000 },
180 { 94, 0x0000 },
181
182 { 99, 0x0000 },
183 { 100, 0x0000 },
184 { 101, 0x0000 },
185 { 102, 0x013F },
186 { 103, 0x013F },
187
188 { 105, 0x0000 },
189 { 106, 0x0000 },
190 { 107, 0x013F },
191 { 108, 0x013F },
192 { 109, 0x0003 },
193 { 110, 0x0002 },
194
195 { 115, 0x0006 },
196 { 116, 0x0026 },
197
198 { 119, 0x0000 },
199
200 { 124, 0x0011 },
201 { 125, 0x004B },
202 { 126, 0x000D },
203 { 127, 0x0000 },
204
205 { 131, 0x0000 },
206
207 { 136, 0x0067 },
208 { 137, 0x001C },
209 { 138, 0x0071 },
210 { 139, 0x00C7 },
211 { 140, 0x0067 },
212 { 141, 0x0048 },
213 { 142, 0x0022 },
214 { 143, 0x0097 },
215
216 { 155, 0x000C },
217 { 156, 0x0039 },
218 { 157, 0x0180 },
219
220 { 159, 0x0032 },
221 { 160, 0x0018 },
222 { 161, 0x007D },
223 { 162, 0x0008 },
224
225 { 252, 0x0005 },
226
227 { 256, 0x0000 },
228 { 257, 0x0000 },
229 { 258, 0x0000 },
230 { 259, 0x0000 },
231 { 260, 0x0000 },
232 { 261, 0x0000 },
233 { 262, 0x0000 },
234
235 { 264, 0x0000 },
236 { 265, 0x0000 },
237
238 { 268, 0x0000 },
239 { 269, 0x0000 },
240 { 270, 0x0000 },
241 { 271, 0x0000 },
242
243 { 276, 0x000C },
244 { 277, 0x0925 },
245 { 278, 0x0000 },
246 { 279, 0x0000 },
247 { 280, 0x0000 },
248
249 { 285, 0x0000 },
250
251 { 335, 0x0004 },
252 { 336, 0x6318 },
253 { 337, 0x6300 },
254 { 338, 0x0FCA },
255 { 339, 0x0400 },
256 { 340, 0x00D8 },
257 { 341, 0x1EB5 },
258 { 342, 0xF145 },
259 { 343, 0x0B75 },
260 { 344, 0x01C5 },
261 { 345, 0x1C58 },
262 { 346, 0xF373 },
263 { 347, 0x0A54 },
264 { 348, 0x0558 },
265 { 349, 0x168E },
266 { 350, 0xF829 },
267 { 351, 0x07AD },
268 { 352, 0x1103 },
269 { 353, 0x0564 },
270 { 354, 0x0559 },
271 { 355, 0x4000 },
272 { 356, 0x6318 },
273 { 357, 0x6300 },
274 { 358, 0x0FCA },
275 { 359, 0x0400 },
276 { 360, 0x00D8 },
277 { 361, 0x1EB5 },
278 { 362, 0xF145 },
279 { 363, 0x0B75 },
280 { 364, 0x01C5 },
281 { 365, 0x1C58 },
282 { 366, 0xF373 },
283 { 367, 0x0A54 },
284 { 368, 0x0558 },
285 { 369, 0x168E },
286 { 370, 0xF829 },
287 { 371, 0x07AD },
288 { 372, 0x1103 },
289 { 373, 0x0564 },
290 { 374, 0x0559 },
291 { 375, 0x4000 },
292
293 { 513, 0x0000 },
294 { 514, 0x0000 },
295
296 { 516, 0x8100 },
297 { 517, 0x8100 },
298
299 { 568, 0x0030 },
300 { 569, 0xFFED },
301
302 { 576, 0x0000 },
303
304 { 584, 0x002D },
305
306 { 586, 0x0000 },
307
308 { 768, 0x1C00 },
309
310 { 8192, 0x0000 },
311
312 { 9216, 0x0030 },
313 { 9217, 0x0000 },
314 { 9218, 0x0000 },
315
316 { 12288, 0x0000 },
317 { 12289, 0x0000 },
318
319 { 13312, 0x0000 },
320 { 13313, 0x0000 },
321
322 { 14336, 0x0000 },
323 { 14337, 0x0000 },
324
325 { 15360, 0x000A },
326
327 { 16384, 0x0000 },
328 { 16385, 0x0000 },
329 { 16386, 0x0000 },
330 { 16387, 0x0000 },
331 { 16388, 0x0000 },
332 { 16389, 0x0000 },
333
334 { 16896, 0x0002 },
335 { 16897, 0xBD12 },
336 { 16898, 0x007C },
337 { 16899, 0x586C },
338 { 16900, 0x0053 },
339 { 16901, 0x8121 },
340 { 16902, 0x003F },
341 { 16903, 0x8BD8 },
342 { 16904, 0x0032 },
343 { 16905, 0xF52D },
344 { 16906, 0x0065 },
345 { 16907, 0xAC8C },
346 { 16908, 0x006B },
347 { 16909, 0xE087 },
348 { 16910, 0x0072 },
349 { 16911, 0x1483 },
350 { 16912, 0x0072 },
351 { 16913, 0x1483 },
352 { 16914, 0x0043 },
353 { 16915, 0x3525 },
354 { 16916, 0x0006 },
355 { 16917, 0x6A4A },
356 { 16918, 0x0043 },
357 { 16919, 0x6079 },
358 { 16920, 0x0008 },
359 { 16921, 0x0000 },
360 { 16922, 0x0001 },
361 { 16923, 0x0000 },
362 { 16924, 0x0059 },
363 { 16925, 0x999A },
364
365 { 17048, 0x0083 },
366 { 17049, 0x98AD },
367
368 { 17920, 0x007F },
369 { 17921, 0xFFFF },
370 { 17922, 0x0000 },
371 { 17923, 0x0000 },
372 { 17924, 0x0000 },
373 { 17925, 0x0000 },
374 { 17926, 0x0000 },
375 { 17927, 0x0000 },
376 { 17928, 0x0000 },
377 { 17929, 0x0000 },
378 { 17930, 0x0000 },
379 { 17931, 0x0000 },
380 { 17932, 0x0000 },
381 { 17933, 0x0000 },
382 { 17934, 0x0000 },
383 { 17935, 0x0000 },
384 { 17936, 0x0000 },
385 { 17937, 0x0000 },
386 { 17938, 0x0000 },
387 { 17939, 0x0000 },
388 { 17940, 0x0000 },
389 { 17941, 0x0000 },
390 { 17942, 0x0000 },
391 { 17943, 0x0000 },
392 { 17944, 0x0000 },
393 { 17945, 0x0000 },
394 { 17946, 0x0000 },
395 { 17947, 0x0000 },
396 { 17948, 0x0000 },
397 { 17949, 0x0000 },
398 { 17950, 0x0000 },
399 { 17951, 0x0000 },
400 { 17952, 0x0000 },
401 { 17953, 0x0000 },
402 { 17954, 0x0000 },
403 { 17955, 0x0000 },
404 { 17956, 0x0000 },
405 { 17957, 0x0000 },
406 { 17958, 0x0000 },
407 { 17959, 0x0000 },
408 { 17960, 0x0000 },
409 { 17961, 0x0000 },
410 { 17962, 0x0000 },
411 { 17963, 0x0000 },
412 { 17964, 0x0000 },
413 { 17965, 0x0000 },
414 { 17966, 0x0000 },
415 { 17967, 0x0000 },
416 { 17968, 0x0000 },
417 { 17969, 0x0000 },
418 { 17970, 0x0000 },
419 { 17971, 0x0000 },
420 { 17972, 0x0000 },
421 { 17973, 0x0000 },
422 { 17974, 0x0000 },
423 { 17975, 0x0000 },
424 { 17976, 0x0000 },
425 { 17977, 0x0000 },
426 { 17978, 0x0000 },
427 { 17979, 0x0000 },
428 { 17980, 0x0000 },
429 { 17981, 0x0000 },
430 { 17982, 0x0000 },
431 { 17983, 0x0000 },
432
433 { 18432, 0x0020 },
434 { 18433, 0x0000 },
435 { 18434, 0x0040 },
436 { 18435, 0x0000 },
437
438 { 18944, 0x007F },
439 { 18945, 0xFFFF },
440 { 18946, 0x0000 },
441 { 18947, 0x0000 },
442 { 18948, 0x0000 },
443 { 18949, 0x0000 },
444 { 18950, 0x0000 },
445 { 18951, 0x0000 },
446 { 18952, 0x0000 },
447 { 18953, 0x0000 },
448 { 18954, 0x0000 },
449 { 18955, 0x0000 },
450 { 18956, 0x0000 },
451 { 18957, 0x0000 },
452 { 18958, 0x0000 },
453 { 18959, 0x0000 },
454 { 18960, 0x0000 },
455 { 18961, 0x0000 },
456 { 18962, 0x0000 },
457 { 18963, 0x0000 },
458 { 18964, 0x0000 },
459 { 18965, 0x0000 },
460 { 18966, 0x0000 },
461 { 18967, 0x0000 },
462 { 18968, 0x0000 },
463 { 18969, 0x0000 },
464 { 18970, 0x0000 },
465 { 18971, 0x0000 },
466 { 18972, 0x0000 },
467 { 18973, 0x0000 },
468 { 18974, 0x0000 },
469 { 18975, 0x0000 },
470 { 18976, 0x0000 },
471 { 18977, 0x0000 },
472 { 18978, 0x0000 },
473 { 18979, 0x0000 },
474 { 18980, 0x0000 },
475 { 18981, 0x0000 },
476 { 18982, 0x0000 },
477 { 18983, 0x0000 },
478 { 18984, 0x0000 },
479 { 18985, 0x0000 },
480 { 18986, 0x0000 },
481 { 18987, 0x0000 },
482 { 18988, 0x0000 },
483 { 18989, 0x0000 },
484 { 18990, 0x0000 },
485 { 18991, 0x0000 },
486 { 18992, 0x0000 },
487 { 18993, 0x0000 },
488 { 18994, 0x0000 },
489 { 18995, 0x0000 },
490 { 18996, 0x0000 },
491 { 18997, 0x0000 },
492 { 18998, 0x0000 },
493 { 18999, 0x0000 },
494 { 19000, 0x0000 },
495 { 19001, 0x0000 },
496 { 19002, 0x0000 },
497 { 19003, 0x0000 },
498 { 19004, 0x0000 },
499 { 19005, 0x0000 },
500 { 19006, 0x0000 },
501 { 19007, 0x0000 },
502
503 { 19456, 0x007F },
504 { 19457, 0xFFFF },
505 { 19458, 0x0000 },
506 { 19459, 0x0000 },
507 { 19460, 0x0000 },
508 { 19461, 0x0000 },
509 { 19462, 0x0000 },
510 { 19463, 0x0000 },
511 { 19464, 0x0000 },
512 { 19465, 0x0000 },
513 { 19466, 0x0000 },
514 { 19467, 0x0000 },
515 { 19468, 0x0000 },
516 { 19469, 0x0000 },
517 { 19470, 0x0000 },
518 { 19471, 0x0000 },
519 { 19472, 0x0000 },
520 { 19473, 0x0000 },
521 { 19474, 0x0000 },
522 { 19475, 0x0000 },
523 { 19476, 0x0000 },
524 { 19477, 0x0000 },
525 { 19478, 0x0000 },
526 { 19479, 0x0000 },
527 { 19480, 0x0000 },
528 { 19481, 0x0000 },
529 { 19482, 0x0000 },
530 { 19483, 0x0000 },
531 { 19484, 0x0000 },
532 { 19485, 0x0000 },
533 { 19486, 0x0000 },
534 { 19487, 0x0000 },
535 { 19488, 0x0000 },
536 { 19489, 0x0000 },
537 { 19490, 0x0000 },
538 { 19491, 0x0000 },
539 { 19492, 0x0000 },
540 { 19493, 0x0000 },
541 { 19494, 0x0000 },
542 { 19495, 0x0000 },
543 { 19496, 0x0000 },
544 { 19497, 0x0000 },
545 { 19498, 0x0000 },
546 { 19499, 0x0000 },
547 { 19500, 0x0000 },
548 { 19501, 0x0000 },
549 { 19502, 0x0000 },
550 { 19503, 0x0000 },
551 { 19504, 0x0000 },
552 { 19505, 0x0000 },
553 { 19506, 0x0000 },
554 { 19507, 0x0000 },
555 { 19508, 0x0000 },
556 { 19509, 0x0000 },
557 { 19510, 0x0000 },
558 { 19511, 0x0000 },
559 { 19512, 0x0000 },
560 { 19513, 0x0000 },
561 { 19514, 0x0000 },
562 { 19515, 0x0000 },
563 { 19516, 0x0000 },
564 { 19517, 0x0000 },
565 { 19518, 0x0000 },
566 { 19519, 0x0000 },
567
568 { 19968, 0x0020 },
569 { 19969, 0x0000 },
570 { 19970, 0x0040 },
571 { 19971, 0x0000 },
572
573 { 20480, 0x007F },
574 { 20481, 0xFFFF },
575 { 20482, 0x0000 },
576 { 20483, 0x0000 },
577 { 20484, 0x0000 },
578 { 20485, 0x0000 },
579 { 20486, 0x0000 },
580 { 20487, 0x0000 },
581 { 20488, 0x0000 },
582 { 20489, 0x0000 },
583 { 20490, 0x0000 },
584 { 20491, 0x0000 },
585 { 20492, 0x0000 },
586 { 20493, 0x0000 },
587 { 20494, 0x0000 },
588 { 20495, 0x0000 },
589 { 20496, 0x0000 },
590 { 20497, 0x0000 },
591 { 20498, 0x0000 },
592 { 20499, 0x0000 },
593 { 20500, 0x0000 },
594 { 20501, 0x0000 },
595 { 20502, 0x0000 },
596 { 20503, 0x0000 },
597 { 20504, 0x0000 },
598 { 20505, 0x0000 },
599 { 20506, 0x0000 },
600 { 20507, 0x0000 },
601 { 20508, 0x0000 },
602 { 20509, 0x0000 },
603 { 20510, 0x0000 },
604 { 20511, 0x0000 },
605 { 20512, 0x0000 },
606 { 20513, 0x0000 },
607 { 20514, 0x0000 },
608 { 20515, 0x0000 },
609 { 20516, 0x0000 },
610 { 20517, 0x0000 },
611 { 20518, 0x0000 },
612 { 20519, 0x0000 },
613 { 20520, 0x0000 },
614 { 20521, 0x0000 },
615 { 20522, 0x0000 },
616 { 20523, 0x0000 },
617 { 20524, 0x0000 },
618 { 20525, 0x0000 },
619 { 20526, 0x0000 },
620 { 20527, 0x0000 },
621 { 20528, 0x0000 },
622 { 20529, 0x0000 },
623 { 20530, 0x0000 },
624 { 20531, 0x0000 },
625 { 20532, 0x0000 },
626 { 20533, 0x0000 },
627 { 20534, 0x0000 },
628 { 20535, 0x0000 },
629 { 20536, 0x0000 },
630 { 20537, 0x0000 },
631 { 20538, 0x0000 },
632 { 20539, 0x0000 },
633 { 20540, 0x0000 },
634 { 20541, 0x0000 },
635 { 20542, 0x0000 },
636 { 20543, 0x0000 },
637
638 { 20992, 0x008C },
639 { 20993, 0x0200 },
640 { 20994, 0x0035 },
641 { 20995, 0x0700 },
642 { 20996, 0x003A },
643 { 20997, 0x4100 },
644 { 20998, 0x008B },
645 { 20999, 0x7D00 },
646 { 21000, 0x003A },
647 { 21001, 0x4100 },
648 { 21002, 0x008C },
649 { 21003, 0xFEE8 },
650 { 21004, 0x0078 },
651 { 21005, 0x0000 },
652 { 21006, 0x003F },
653 { 21007, 0xB260 },
654 { 21008, 0x002D },
655 { 21009, 0x1818 },
656 { 21010, 0x0020 },
657 { 21011, 0x0000 },
658 { 21012, 0x00F1 },
659 { 21013, 0x8340 },
660 { 21014, 0x00FB },
661 { 21015, 0x8300 },
662 { 21016, 0x00EE },
663 { 21017, 0xAEC0 },
664 { 21018, 0x00FB },
665 { 21019, 0xAC40 },
666 { 21020, 0x00F1 },
667 { 21021, 0x7F80 },
668 { 21022, 0x00F4 },
669 { 21023, 0x3B40 },
670 { 21024, 0x00F5 },
671 { 21025, 0xFB00 },
672 { 21026, 0x00EA },
673 { 21027, 0x10C0 },
674 { 21028, 0x00FC },
675 { 21029, 0xC580 },
676 { 21030, 0x00E2 },
677 { 21031, 0x75C0 },
678 { 21032, 0x0004 },
679 { 21033, 0xB480 },
680 { 21034, 0x00D4 },
681 { 21035, 0xF980 },
682 { 21036, 0x0004 },
683 { 21037, 0x9140 },
684 { 21038, 0x00D8 },
685 { 21039, 0xA480 },
686 { 21040, 0x0002 },
687 { 21041, 0x3DC0 },
688 { 21042, 0x00CF },
689 { 21043, 0x7A80 },
690 { 21044, 0x00DC },
691 { 21045, 0x0600 },
692 { 21046, 0x00F2 },
693 { 21047, 0xDAC0 },
694 { 21048, 0x00BA },
695 { 21049, 0xF340 },
696 { 21050, 0x000A },
697 { 21051, 0x7940 },
698 { 21052, 0x001C },
699 { 21053, 0x0680 },
700 { 21054, 0x00FD },
701 { 21055, 0x2D00 },
702 { 21056, 0x001C },
703 { 21057, 0xE840 },
704 { 21058, 0x000D },
705 { 21059, 0xDC40 },
706 { 21060, 0x00FC },
707 { 21061, 0x9D00 },
708 { 21062, 0x0009 },
709 { 21063, 0x5580 },
710 { 21064, 0x00FE },
711 { 21065, 0x7E80 },
712 { 21066, 0x000E },
713 { 21067, 0xAB40 },
714 { 21068, 0x00F9 },
715 { 21069, 0x9880 },
716 { 21070, 0x0009 },
717 { 21071, 0x87C0 },
718 { 21072, 0x00FD },
719 { 21073, 0x2C40 },
720 { 21074, 0x0009 },
721 { 21075, 0x4800 },
722 { 21076, 0x0003 },
723 { 21077, 0x5F40 },
724 { 21078, 0x0000 },
725 { 21079, 0x8700 },
726 { 21080, 0x00FA },
727 { 21081, 0xE4C0 },
728 { 21082, 0x0000 },
729 { 21083, 0x0B40 },
730 { 21084, 0x0004 },
731 { 21085, 0xE180 },
732 { 21086, 0x0001 },
733 { 21087, 0x1F40 },
734 { 21088, 0x00F8 },
735 { 21089, 0xB000 },
736 { 21090, 0x00FB },
737 { 21091, 0xCBC0 },
738 { 21092, 0x0004 },
739 { 21093, 0xF380 },
740 { 21094, 0x0007 },
741 { 21095, 0xDF40 },
742 { 21096, 0x00FF },
743 { 21097, 0x0700 },
744 { 21098, 0x00EF },
745 { 21099, 0xD700 },
746 { 21100, 0x00FB },
747 { 21101, 0xAF40 },
748 { 21102, 0x0010 },
749 { 21103, 0x8A80 },
750 { 21104, 0x0011 },
751 { 21105, 0x07C0 },
752 { 21106, 0x00E0 },
753 { 21107, 0x0800 },
754 { 21108, 0x00D2 },
755 { 21109, 0x7600 },
756 { 21110, 0x0020 },
757 { 21111, 0xCF40 },
758 { 21112, 0x0030 },
759 { 21113, 0x2340 },
760 { 21114, 0x00FD },
761 { 21115, 0x69C0 },
762 { 21116, 0x0028 },
763 { 21117, 0x3500 },
764 { 21118, 0x0006 },
765 { 21119, 0x3300 },
766 { 21120, 0x00D9 },
767 { 21121, 0xF6C0 },
768 { 21122, 0x00F3 },
769 { 21123, 0x3340 },
770 { 21124, 0x000F },
771 { 21125, 0x4200 },
772 { 21126, 0x0004 },
773 { 21127, 0x0C80 },
774 { 21128, 0x00FB },
775 { 21129, 0x3F80 },
776 { 21130, 0x00F7 },
777 { 21131, 0x57C0 },
778 { 21132, 0x0003 },
779 { 21133, 0x5400 },
780 { 21134, 0x0000 },
781 { 21135, 0xC6C0 },
782 { 21136, 0x0003 },
783 { 21137, 0x12C0 },
784 { 21138, 0x00FD },
785 { 21139, 0x8580 },
786};
787
788static bool wm8962_volatile_register(struct device *dev, unsigned int reg)
789{
790 switch (reg) {
791 case WM8962_CLOCKING1:
792 case WM8962_CLOCKING2:
793 case WM8962_SOFTWARE_RESET:
794 case WM8962_ALC2:
795 case WM8962_THERMAL_SHUTDOWN_STATUS:
796 case WM8962_ADDITIONAL_CONTROL_4:
797 case WM8962_CLASS_D_CONTROL_1:
798 case WM8962_DC_SERVO_6:
799 case WM8962_INTERRUPT_STATUS_1:
800 case WM8962_INTERRUPT_STATUS_2:
801 case WM8962_DSP2_EXECCONTROL:
802 return true;
803 default:
804 return false;
805 }
806}
807
808static bool wm8962_readable_register(struct device *dev, unsigned int reg)
809{
810 switch (reg) {
811 case WM8962_LEFT_INPUT_VOLUME:
812 case WM8962_RIGHT_INPUT_VOLUME:
813 case WM8962_HPOUTL_VOLUME:
814 case WM8962_HPOUTR_VOLUME:
815 case WM8962_CLOCKING1:
816 case WM8962_ADC_DAC_CONTROL_1:
817 case WM8962_ADC_DAC_CONTROL_2:
818 case WM8962_AUDIO_INTERFACE_0:
819 case WM8962_CLOCKING2:
820 case WM8962_AUDIO_INTERFACE_1:
821 case WM8962_LEFT_DAC_VOLUME:
822 case WM8962_RIGHT_DAC_VOLUME:
823 case WM8962_AUDIO_INTERFACE_2:
824 case WM8962_SOFTWARE_RESET:
825 case WM8962_ALC1:
826 case WM8962_ALC2:
827 case WM8962_ALC3:
828 case WM8962_NOISE_GATE:
829 case WM8962_LEFT_ADC_VOLUME:
830 case WM8962_RIGHT_ADC_VOLUME:
831 case WM8962_ADDITIONAL_CONTROL_1:
832 case WM8962_ADDITIONAL_CONTROL_2:
833 case WM8962_PWR_MGMT_1:
834 case WM8962_PWR_MGMT_2:
835 case WM8962_ADDITIONAL_CONTROL_3:
836 case WM8962_ANTI_POP:
837 case WM8962_CLOCKING_3:
838 case WM8962_INPUT_MIXER_CONTROL_1:
839 case WM8962_LEFT_INPUT_MIXER_VOLUME:
840 case WM8962_RIGHT_INPUT_MIXER_VOLUME:
841 case WM8962_INPUT_MIXER_CONTROL_2:
842 case WM8962_INPUT_BIAS_CONTROL:
843 case WM8962_LEFT_INPUT_PGA_CONTROL:
844 case WM8962_RIGHT_INPUT_PGA_CONTROL:
845 case WM8962_SPKOUTL_VOLUME:
846 case WM8962_SPKOUTR_VOLUME:
847 case WM8962_THERMAL_SHUTDOWN_STATUS:
848 case WM8962_ADDITIONAL_CONTROL_4:
849 case WM8962_CLASS_D_CONTROL_1:
850 case WM8962_CLASS_D_CONTROL_2:
851 case WM8962_CLOCKING_4:
852 case WM8962_DAC_DSP_MIXING_1:
853 case WM8962_DAC_DSP_MIXING_2:
854 case WM8962_DC_SERVO_0:
855 case WM8962_DC_SERVO_1:
856 case WM8962_DC_SERVO_4:
857 case WM8962_DC_SERVO_6:
858 case WM8962_ANALOGUE_PGA_BIAS:
859 case WM8962_ANALOGUE_HP_0:
860 case WM8962_ANALOGUE_HP_2:
861 case WM8962_CHARGE_PUMP_1:
862 case WM8962_CHARGE_PUMP_B:
863 case WM8962_WRITE_SEQUENCER_CONTROL_1:
864 case WM8962_WRITE_SEQUENCER_CONTROL_2:
865 case WM8962_WRITE_SEQUENCER_CONTROL_3:
866 case WM8962_CONTROL_INTERFACE:
867 case WM8962_MIXER_ENABLES:
868 case WM8962_HEADPHONE_MIXER_1:
869 case WM8962_HEADPHONE_MIXER_2:
870 case WM8962_HEADPHONE_MIXER_3:
871 case WM8962_HEADPHONE_MIXER_4:
872 case WM8962_SPEAKER_MIXER_1:
873 case WM8962_SPEAKER_MIXER_2:
874 case WM8962_SPEAKER_MIXER_3:
875 case WM8962_SPEAKER_MIXER_4:
876 case WM8962_SPEAKER_MIXER_5:
877 case WM8962_BEEP_GENERATOR_1:
878 case WM8962_OSCILLATOR_TRIM_3:
879 case WM8962_OSCILLATOR_TRIM_4:
880 case WM8962_OSCILLATOR_TRIM_7:
881 case WM8962_ANALOGUE_CLOCKING1:
882 case WM8962_ANALOGUE_CLOCKING2:
883 case WM8962_ANALOGUE_CLOCKING3:
884 case WM8962_PLL_SOFTWARE_RESET:
885 case WM8962_PLL2:
886 case WM8962_PLL_4:
887 case WM8962_PLL_9:
888 case WM8962_PLL_10:
889 case WM8962_PLL_11:
890 case WM8962_PLL_12:
891 case WM8962_PLL_13:
892 case WM8962_PLL_14:
893 case WM8962_PLL_15:
894 case WM8962_PLL_16:
895 case WM8962_FLL_CONTROL_1:
896 case WM8962_FLL_CONTROL_2:
897 case WM8962_FLL_CONTROL_3:
898 case WM8962_FLL_CONTROL_5:
899 case WM8962_FLL_CONTROL_6:
900 case WM8962_FLL_CONTROL_7:
901 case WM8962_FLL_CONTROL_8:
902 case WM8962_GENERAL_TEST_1:
903 case WM8962_DF1:
904 case WM8962_DF2:
905 case WM8962_DF3:
906 case WM8962_DF4:
907 case WM8962_DF5:
908 case WM8962_DF6:
909 case WM8962_DF7:
910 case WM8962_LHPF1:
911 case WM8962_LHPF2:
912 case WM8962_THREED1:
913 case WM8962_THREED2:
914 case WM8962_THREED3:
915 case WM8962_THREED4:
916 case WM8962_DRC_1:
917 case WM8962_DRC_2:
918 case WM8962_DRC_3:
919 case WM8962_DRC_4:
920 case WM8962_DRC_5:
921 case WM8962_TLOOPBACK:
922 case WM8962_EQ1:
923 case WM8962_EQ2:
924 case WM8962_EQ3:
925 case WM8962_EQ4:
926 case WM8962_EQ5:
927 case WM8962_EQ6:
928 case WM8962_EQ7:
929 case WM8962_EQ8:
930 case WM8962_EQ9:
931 case WM8962_EQ10:
932 case WM8962_EQ11:
933 case WM8962_EQ12:
934 case WM8962_EQ13:
935 case WM8962_EQ14:
936 case WM8962_EQ15:
937 case WM8962_EQ16:
938 case WM8962_EQ17:
939 case WM8962_EQ18:
940 case WM8962_EQ19:
941 case WM8962_EQ20:
942 case WM8962_EQ21:
943 case WM8962_EQ22:
944 case WM8962_EQ23:
945 case WM8962_EQ24:
946 case WM8962_EQ25:
947 case WM8962_EQ26:
948 case WM8962_EQ27:
949 case WM8962_EQ28:
950 case WM8962_EQ29:
951 case WM8962_EQ30:
952 case WM8962_EQ31:
953 case WM8962_EQ32:
954 case WM8962_EQ33:
955 case WM8962_EQ34:
956 case WM8962_EQ35:
957 case WM8962_EQ36:
958 case WM8962_EQ37:
959 case WM8962_EQ38:
960 case WM8962_EQ39:
961 case WM8962_EQ40:
962 case WM8962_EQ41:
963 case WM8962_GPIO_BASE:
964 case WM8962_GPIO_2:
965 case WM8962_GPIO_3:
966 case WM8962_GPIO_5:
967 case WM8962_GPIO_6:
968 case WM8962_INTERRUPT_STATUS_1:
969 case WM8962_INTERRUPT_STATUS_2:
970 case WM8962_INTERRUPT_STATUS_1_MASK:
971 case WM8962_INTERRUPT_STATUS_2_MASK:
972 case WM8962_INTERRUPT_CONTROL:
973 case WM8962_IRQ_DEBOUNCE:
974 case WM8962_MICINT_SOURCE_POL:
975 case WM8962_DSP2_POWER_MANAGEMENT:
976 case WM8962_DSP2_EXECCONTROL:
977 case WM8962_DSP2_INSTRUCTION_RAM_0:
978 case WM8962_DSP2_ADDRESS_RAM_2:
979 case WM8962_DSP2_ADDRESS_RAM_1:
980 case WM8962_DSP2_ADDRESS_RAM_0:
981 case WM8962_DSP2_DATA1_RAM_1:
982 case WM8962_DSP2_DATA1_RAM_0:
983 case WM8962_DSP2_DATA2_RAM_1:
984 case WM8962_DSP2_DATA2_RAM_0:
985 case WM8962_DSP2_DATA3_RAM_1:
986 case WM8962_DSP2_DATA3_RAM_0:
987 case WM8962_DSP2_COEFF_RAM_0:
988 case WM8962_RETUNEADC_SHARED_COEFF_1:
989 case WM8962_RETUNEADC_SHARED_COEFF_0:
990 case WM8962_RETUNEDAC_SHARED_COEFF_1:
991 case WM8962_RETUNEDAC_SHARED_COEFF_0:
992 case WM8962_SOUNDSTAGE_ENABLES_1:
993 case WM8962_SOUNDSTAGE_ENABLES_0:
994 case WM8962_HDBASS_AI_1:
995 case WM8962_HDBASS_AI_0:
996 case WM8962_HDBASS_AR_1:
997 case WM8962_HDBASS_AR_0:
998 case WM8962_HDBASS_B_1:
999 case WM8962_HDBASS_B_0:
1000 case WM8962_HDBASS_K_1:
1001 case WM8962_HDBASS_K_0:
1002 case WM8962_HDBASS_N1_1:
1003 case WM8962_HDBASS_N1_0:
1004 case WM8962_HDBASS_N2_1:
1005 case WM8962_HDBASS_N2_0:
1006 case WM8962_HDBASS_N3_1:
1007 case WM8962_HDBASS_N3_0:
1008 case WM8962_HDBASS_N4_1:
1009 case WM8962_HDBASS_N4_0:
1010 case WM8962_HDBASS_N5_1:
1011 case WM8962_HDBASS_N5_0:
1012 case WM8962_HDBASS_X1_1:
1013 case WM8962_HDBASS_X1_0:
1014 case WM8962_HDBASS_X2_1:
1015 case WM8962_HDBASS_X2_0:
1016 case WM8962_HDBASS_X3_1:
1017 case WM8962_HDBASS_X3_0:
1018 case WM8962_HDBASS_ATK_1:
1019 case WM8962_HDBASS_ATK_0:
1020 case WM8962_HDBASS_DCY_1:
1021 case WM8962_HDBASS_DCY_0:
1022 case WM8962_HDBASS_PG_1:
1023 case WM8962_HDBASS_PG_0:
1024 case WM8962_HPF_C_1:
1025 case WM8962_HPF_C_0:
1026 case WM8962_ADCL_RETUNE_C1_1:
1027 case WM8962_ADCL_RETUNE_C1_0:
1028 case WM8962_ADCL_RETUNE_C2_1:
1029 case WM8962_ADCL_RETUNE_C2_0:
1030 case WM8962_ADCL_RETUNE_C3_1:
1031 case WM8962_ADCL_RETUNE_C3_0:
1032 case WM8962_ADCL_RETUNE_C4_1:
1033 case WM8962_ADCL_RETUNE_C4_0:
1034 case WM8962_ADCL_RETUNE_C5_1:
1035 case WM8962_ADCL_RETUNE_C5_0:
1036 case WM8962_ADCL_RETUNE_C6_1:
1037 case WM8962_ADCL_RETUNE_C6_0:
1038 case WM8962_ADCL_RETUNE_C7_1:
1039 case WM8962_ADCL_RETUNE_C7_0:
1040 case WM8962_ADCL_RETUNE_C8_1:
1041 case WM8962_ADCL_RETUNE_C8_0:
1042 case WM8962_ADCL_RETUNE_C9_1:
1043 case WM8962_ADCL_RETUNE_C9_0:
1044 case WM8962_ADCL_RETUNE_C10_1:
1045 case WM8962_ADCL_RETUNE_C10_0:
1046 case WM8962_ADCL_RETUNE_C11_1:
1047 case WM8962_ADCL_RETUNE_C11_0:
1048 case WM8962_ADCL_RETUNE_C12_1:
1049 case WM8962_ADCL_RETUNE_C12_0:
1050 case WM8962_ADCL_RETUNE_C13_1:
1051 case WM8962_ADCL_RETUNE_C13_0:
1052 case WM8962_ADCL_RETUNE_C14_1:
1053 case WM8962_ADCL_RETUNE_C14_0:
1054 case WM8962_ADCL_RETUNE_C15_1:
1055 case WM8962_ADCL_RETUNE_C15_0:
1056 case WM8962_ADCL_RETUNE_C16_1:
1057 case WM8962_ADCL_RETUNE_C16_0:
1058 case WM8962_ADCL_RETUNE_C17_1:
1059 case WM8962_ADCL_RETUNE_C17_0:
1060 case WM8962_ADCL_RETUNE_C18_1:
1061 case WM8962_ADCL_RETUNE_C18_0:
1062 case WM8962_ADCL_RETUNE_C19_1:
1063 case WM8962_ADCL_RETUNE_C19_0:
1064 case WM8962_ADCL_RETUNE_C20_1:
1065 case WM8962_ADCL_RETUNE_C20_0:
1066 case WM8962_ADCL_RETUNE_C21_1:
1067 case WM8962_ADCL_RETUNE_C21_0:
1068 case WM8962_ADCL_RETUNE_C22_1:
1069 case WM8962_ADCL_RETUNE_C22_0:
1070 case WM8962_ADCL_RETUNE_C23_1:
1071 case WM8962_ADCL_RETUNE_C23_0:
1072 case WM8962_ADCL_RETUNE_C24_1:
1073 case WM8962_ADCL_RETUNE_C24_0:
1074 case WM8962_ADCL_RETUNE_C25_1:
1075 case WM8962_ADCL_RETUNE_C25_0:
1076 case WM8962_ADCL_RETUNE_C26_1:
1077 case WM8962_ADCL_RETUNE_C26_0:
1078 case WM8962_ADCL_RETUNE_C27_1:
1079 case WM8962_ADCL_RETUNE_C27_0:
1080 case WM8962_ADCL_RETUNE_C28_1:
1081 case WM8962_ADCL_RETUNE_C28_0:
1082 case WM8962_ADCL_RETUNE_C29_1:
1083 case WM8962_ADCL_RETUNE_C29_0:
1084 case WM8962_ADCL_RETUNE_C30_1:
1085 case WM8962_ADCL_RETUNE_C30_0:
1086 case WM8962_ADCL_RETUNE_C31_1:
1087 case WM8962_ADCL_RETUNE_C31_0:
1088 case WM8962_ADCL_RETUNE_C32_1:
1089 case WM8962_ADCL_RETUNE_C32_0:
1090 case WM8962_RETUNEADC_PG2_1:
1091 case WM8962_RETUNEADC_PG2_0:
1092 case WM8962_RETUNEADC_PG_1:
1093 case WM8962_RETUNEADC_PG_0:
1094 case WM8962_ADCR_RETUNE_C1_1:
1095 case WM8962_ADCR_RETUNE_C1_0:
1096 case WM8962_ADCR_RETUNE_C2_1:
1097 case WM8962_ADCR_RETUNE_C2_0:
1098 case WM8962_ADCR_RETUNE_C3_1:
1099 case WM8962_ADCR_RETUNE_C3_0:
1100 case WM8962_ADCR_RETUNE_C4_1:
1101 case WM8962_ADCR_RETUNE_C4_0:
1102 case WM8962_ADCR_RETUNE_C5_1:
1103 case WM8962_ADCR_RETUNE_C5_0:
1104 case WM8962_ADCR_RETUNE_C6_1:
1105 case WM8962_ADCR_RETUNE_C6_0:
1106 case WM8962_ADCR_RETUNE_C7_1:
1107 case WM8962_ADCR_RETUNE_C7_0:
1108 case WM8962_ADCR_RETUNE_C8_1:
1109 case WM8962_ADCR_RETUNE_C8_0:
1110 case WM8962_ADCR_RETUNE_C9_1:
1111 case WM8962_ADCR_RETUNE_C9_0:
1112 case WM8962_ADCR_RETUNE_C10_1:
1113 case WM8962_ADCR_RETUNE_C10_0:
1114 case WM8962_ADCR_RETUNE_C11_1:
1115 case WM8962_ADCR_RETUNE_C11_0:
1116 case WM8962_ADCR_RETUNE_C12_1:
1117 case WM8962_ADCR_RETUNE_C12_0:
1118 case WM8962_ADCR_RETUNE_C13_1:
1119 case WM8962_ADCR_RETUNE_C13_0:
1120 case WM8962_ADCR_RETUNE_C14_1:
1121 case WM8962_ADCR_RETUNE_C14_0:
1122 case WM8962_ADCR_RETUNE_C15_1:
1123 case WM8962_ADCR_RETUNE_C15_0:
1124 case WM8962_ADCR_RETUNE_C16_1:
1125 case WM8962_ADCR_RETUNE_C16_0:
1126 case WM8962_ADCR_RETUNE_C17_1:
1127 case WM8962_ADCR_RETUNE_C17_0:
1128 case WM8962_ADCR_RETUNE_C18_1:
1129 case WM8962_ADCR_RETUNE_C18_0:
1130 case WM8962_ADCR_RETUNE_C19_1:
1131 case WM8962_ADCR_RETUNE_C19_0:
1132 case WM8962_ADCR_RETUNE_C20_1:
1133 case WM8962_ADCR_RETUNE_C20_0:
1134 case WM8962_ADCR_RETUNE_C21_1:
1135 case WM8962_ADCR_RETUNE_C21_0:
1136 case WM8962_ADCR_RETUNE_C22_1:
1137 case WM8962_ADCR_RETUNE_C22_0:
1138 case WM8962_ADCR_RETUNE_C23_1:
1139 case WM8962_ADCR_RETUNE_C23_0:
1140 case WM8962_ADCR_RETUNE_C24_1:
1141 case WM8962_ADCR_RETUNE_C24_0:
1142 case WM8962_ADCR_RETUNE_C25_1:
1143 case WM8962_ADCR_RETUNE_C25_0:
1144 case WM8962_ADCR_RETUNE_C26_1:
1145 case WM8962_ADCR_RETUNE_C26_0:
1146 case WM8962_ADCR_RETUNE_C27_1:
1147 case WM8962_ADCR_RETUNE_C27_0:
1148 case WM8962_ADCR_RETUNE_C28_1:
1149 case WM8962_ADCR_RETUNE_C28_0:
1150 case WM8962_ADCR_RETUNE_C29_1:
1151 case WM8962_ADCR_RETUNE_C29_0:
1152 case WM8962_ADCR_RETUNE_C30_1:
1153 case WM8962_ADCR_RETUNE_C30_0:
1154 case WM8962_ADCR_RETUNE_C31_1:
1155 case WM8962_ADCR_RETUNE_C31_0:
1156 case WM8962_ADCR_RETUNE_C32_1:
1157 case WM8962_ADCR_RETUNE_C32_0:
1158 case WM8962_DACL_RETUNE_C1_1:
1159 case WM8962_DACL_RETUNE_C1_0:
1160 case WM8962_DACL_RETUNE_C2_1:
1161 case WM8962_DACL_RETUNE_C2_0:
1162 case WM8962_DACL_RETUNE_C3_1:
1163 case WM8962_DACL_RETUNE_C3_0:
1164 case WM8962_DACL_RETUNE_C4_1:
1165 case WM8962_DACL_RETUNE_C4_0:
1166 case WM8962_DACL_RETUNE_C5_1:
1167 case WM8962_DACL_RETUNE_C5_0:
1168 case WM8962_DACL_RETUNE_C6_1:
1169 case WM8962_DACL_RETUNE_C6_0:
1170 case WM8962_DACL_RETUNE_C7_1:
1171 case WM8962_DACL_RETUNE_C7_0:
1172 case WM8962_DACL_RETUNE_C8_1:
1173 case WM8962_DACL_RETUNE_C8_0:
1174 case WM8962_DACL_RETUNE_C9_1:
1175 case WM8962_DACL_RETUNE_C9_0:
1176 case WM8962_DACL_RETUNE_C10_1:
1177 case WM8962_DACL_RETUNE_C10_0:
1178 case WM8962_DACL_RETUNE_C11_1:
1179 case WM8962_DACL_RETUNE_C11_0:
1180 case WM8962_DACL_RETUNE_C12_1:
1181 case WM8962_DACL_RETUNE_C12_0:
1182 case WM8962_DACL_RETUNE_C13_1:
1183 case WM8962_DACL_RETUNE_C13_0:
1184 case WM8962_DACL_RETUNE_C14_1:
1185 case WM8962_DACL_RETUNE_C14_0:
1186 case WM8962_DACL_RETUNE_C15_1:
1187 case WM8962_DACL_RETUNE_C15_0:
1188 case WM8962_DACL_RETUNE_C16_1:
1189 case WM8962_DACL_RETUNE_C16_0:
1190 case WM8962_DACL_RETUNE_C17_1:
1191 case WM8962_DACL_RETUNE_C17_0:
1192 case WM8962_DACL_RETUNE_C18_1:
1193 case WM8962_DACL_RETUNE_C18_0:
1194 case WM8962_DACL_RETUNE_C19_1:
1195 case WM8962_DACL_RETUNE_C19_0:
1196 case WM8962_DACL_RETUNE_C20_1:
1197 case WM8962_DACL_RETUNE_C20_0:
1198 case WM8962_DACL_RETUNE_C21_1:
1199 case WM8962_DACL_RETUNE_C21_0:
1200 case WM8962_DACL_RETUNE_C22_1:
1201 case WM8962_DACL_RETUNE_C22_0:
1202 case WM8962_DACL_RETUNE_C23_1:
1203 case WM8962_DACL_RETUNE_C23_0:
1204 case WM8962_DACL_RETUNE_C24_1:
1205 case WM8962_DACL_RETUNE_C24_0:
1206 case WM8962_DACL_RETUNE_C25_1:
1207 case WM8962_DACL_RETUNE_C25_0:
1208 case WM8962_DACL_RETUNE_C26_1:
1209 case WM8962_DACL_RETUNE_C26_0:
1210 case WM8962_DACL_RETUNE_C27_1:
1211 case WM8962_DACL_RETUNE_C27_0:
1212 case WM8962_DACL_RETUNE_C28_1:
1213 case WM8962_DACL_RETUNE_C28_0:
1214 case WM8962_DACL_RETUNE_C29_1:
1215 case WM8962_DACL_RETUNE_C29_0:
1216 case WM8962_DACL_RETUNE_C30_1:
1217 case WM8962_DACL_RETUNE_C30_0:
1218 case WM8962_DACL_RETUNE_C31_1:
1219 case WM8962_DACL_RETUNE_C31_0:
1220 case WM8962_DACL_RETUNE_C32_1:
1221 case WM8962_DACL_RETUNE_C32_0:
1222 case WM8962_RETUNEDAC_PG2_1:
1223 case WM8962_RETUNEDAC_PG2_0:
1224 case WM8962_RETUNEDAC_PG_1:
1225 case WM8962_RETUNEDAC_PG_0:
1226 case WM8962_DACR_RETUNE_C1_1:
1227 case WM8962_DACR_RETUNE_C1_0:
1228 case WM8962_DACR_RETUNE_C2_1:
1229 case WM8962_DACR_RETUNE_C2_0:
1230 case WM8962_DACR_RETUNE_C3_1:
1231 case WM8962_DACR_RETUNE_C3_0:
1232 case WM8962_DACR_RETUNE_C4_1:
1233 case WM8962_DACR_RETUNE_C4_0:
1234 case WM8962_DACR_RETUNE_C5_1:
1235 case WM8962_DACR_RETUNE_C5_0:
1236 case WM8962_DACR_RETUNE_C6_1:
1237 case WM8962_DACR_RETUNE_C6_0:
1238 case WM8962_DACR_RETUNE_C7_1:
1239 case WM8962_DACR_RETUNE_C7_0:
1240 case WM8962_DACR_RETUNE_C8_1:
1241 case WM8962_DACR_RETUNE_C8_0:
1242 case WM8962_DACR_RETUNE_C9_1:
1243 case WM8962_DACR_RETUNE_C9_0:
1244 case WM8962_DACR_RETUNE_C10_1:
1245 case WM8962_DACR_RETUNE_C10_0:
1246 case WM8962_DACR_RETUNE_C11_1:
1247 case WM8962_DACR_RETUNE_C11_0:
1248 case WM8962_DACR_RETUNE_C12_1:
1249 case WM8962_DACR_RETUNE_C12_0:
1250 case WM8962_DACR_RETUNE_C13_1:
1251 case WM8962_DACR_RETUNE_C13_0:
1252 case WM8962_DACR_RETUNE_C14_1:
1253 case WM8962_DACR_RETUNE_C14_0:
1254 case WM8962_DACR_RETUNE_C15_1:
1255 case WM8962_DACR_RETUNE_C15_0:
1256 case WM8962_DACR_RETUNE_C16_1:
1257 case WM8962_DACR_RETUNE_C16_0:
1258 case WM8962_DACR_RETUNE_C17_1:
1259 case WM8962_DACR_RETUNE_C17_0:
1260 case WM8962_DACR_RETUNE_C18_1:
1261 case WM8962_DACR_RETUNE_C18_0:
1262 case WM8962_DACR_RETUNE_C19_1:
1263 case WM8962_DACR_RETUNE_C19_0:
1264 case WM8962_DACR_RETUNE_C20_1:
1265 case WM8962_DACR_RETUNE_C20_0:
1266 case WM8962_DACR_RETUNE_C21_1:
1267 case WM8962_DACR_RETUNE_C21_0:
1268 case WM8962_DACR_RETUNE_C22_1:
1269 case WM8962_DACR_RETUNE_C22_0:
1270 case WM8962_DACR_RETUNE_C23_1:
1271 case WM8962_DACR_RETUNE_C23_0:
1272 case WM8962_DACR_RETUNE_C24_1:
1273 case WM8962_DACR_RETUNE_C24_0:
1274 case WM8962_DACR_RETUNE_C25_1:
1275 case WM8962_DACR_RETUNE_C25_0:
1276 case WM8962_DACR_RETUNE_C26_1:
1277 case WM8962_DACR_RETUNE_C26_0:
1278 case WM8962_DACR_RETUNE_C27_1:
1279 case WM8962_DACR_RETUNE_C27_0:
1280 case WM8962_DACR_RETUNE_C28_1:
1281 case WM8962_DACR_RETUNE_C28_0:
1282 case WM8962_DACR_RETUNE_C29_1:
1283 case WM8962_DACR_RETUNE_C29_0:
1284 case WM8962_DACR_RETUNE_C30_1:
1285 case WM8962_DACR_RETUNE_C30_0:
1286 case WM8962_DACR_RETUNE_C31_1:
1287 case WM8962_DACR_RETUNE_C31_0:
1288 case WM8962_DACR_RETUNE_C32_1:
1289 case WM8962_DACR_RETUNE_C32_0:
1290 case WM8962_VSS_XHD2_1:
1291 case WM8962_VSS_XHD2_0:
1292 case WM8962_VSS_XHD3_1:
1293 case WM8962_VSS_XHD3_0:
1294 case WM8962_VSS_XHN1_1:
1295 case WM8962_VSS_XHN1_0:
1296 case WM8962_VSS_XHN2_1:
1297 case WM8962_VSS_XHN2_0:
1298 case WM8962_VSS_XHN3_1:
1299 case WM8962_VSS_XHN3_0:
1300 case WM8962_VSS_XLA_1:
1301 case WM8962_VSS_XLA_0:
1302 case WM8962_VSS_XLB_1:
1303 case WM8962_VSS_XLB_0:
1304 case WM8962_VSS_XLG_1:
1305 case WM8962_VSS_XLG_0:
1306 case WM8962_VSS_PG2_1:
1307 case WM8962_VSS_PG2_0:
1308 case WM8962_VSS_PG_1:
1309 case WM8962_VSS_PG_0:
1310 case WM8962_VSS_XTD1_1:
1311 case WM8962_VSS_XTD1_0:
1312 case WM8962_VSS_XTD2_1:
1313 case WM8962_VSS_XTD2_0:
1314 case WM8962_VSS_XTD3_1:
1315 case WM8962_VSS_XTD3_0:
1316 case WM8962_VSS_XTD4_1:
1317 case WM8962_VSS_XTD4_0:
1318 case WM8962_VSS_XTD5_1:
1319 case WM8962_VSS_XTD5_0:
1320 case WM8962_VSS_XTD6_1:
1321 case WM8962_VSS_XTD6_0:
1322 case WM8962_VSS_XTD7_1:
1323 case WM8962_VSS_XTD7_0:
1324 case WM8962_VSS_XTD8_1:
1325 case WM8962_VSS_XTD8_0:
1326 case WM8962_VSS_XTD9_1:
1327 case WM8962_VSS_XTD9_0:
1328 case WM8962_VSS_XTD10_1:
1329 case WM8962_VSS_XTD10_0:
1330 case WM8962_VSS_XTD11_1:
1331 case WM8962_VSS_XTD11_0:
1332 case WM8962_VSS_XTD12_1:
1333 case WM8962_VSS_XTD12_0:
1334 case WM8962_VSS_XTD13_1:
1335 case WM8962_VSS_XTD13_0:
1336 case WM8962_VSS_XTD14_1:
1337 case WM8962_VSS_XTD14_0:
1338 case WM8962_VSS_XTD15_1:
1339 case WM8962_VSS_XTD15_0:
1340 case WM8962_VSS_XTD16_1:
1341 case WM8962_VSS_XTD16_0:
1342 case WM8962_VSS_XTD17_1:
1343 case WM8962_VSS_XTD17_0:
1344 case WM8962_VSS_XTD18_1:
1345 case WM8962_VSS_XTD18_0:
1346 case WM8962_VSS_XTD19_1:
1347 case WM8962_VSS_XTD19_0:
1348 case WM8962_VSS_XTD20_1:
1349 case WM8962_VSS_XTD20_0:
1350 case WM8962_VSS_XTD21_1:
1351 case WM8962_VSS_XTD21_0:
1352 case WM8962_VSS_XTD22_1:
1353 case WM8962_VSS_XTD22_0:
1354 case WM8962_VSS_XTD23_1:
1355 case WM8962_VSS_XTD23_0:
1356 case WM8962_VSS_XTD24_1:
1357 case WM8962_VSS_XTD24_0:
1358 case WM8962_VSS_XTD25_1:
1359 case WM8962_VSS_XTD25_0:
1360 case WM8962_VSS_XTD26_1:
1361 case WM8962_VSS_XTD26_0:
1362 case WM8962_VSS_XTD27_1:
1363 case WM8962_VSS_XTD27_0:
1364 case WM8962_VSS_XTD28_1:
1365 case WM8962_VSS_XTD28_0:
1366 case WM8962_VSS_XTD29_1:
1367 case WM8962_VSS_XTD29_0:
1368 case WM8962_VSS_XTD30_1:
1369 case WM8962_VSS_XTD30_0:
1370 case WM8962_VSS_XTD31_1:
1371 case WM8962_VSS_XTD31_0:
1372 case WM8962_VSS_XTD32_1:
1373 case WM8962_VSS_XTD32_0:
1374 case WM8962_VSS_XTS1_1:
1375 case WM8962_VSS_XTS1_0:
1376 case WM8962_VSS_XTS2_1:
1377 case WM8962_VSS_XTS2_0:
1378 case WM8962_VSS_XTS3_1:
1379 case WM8962_VSS_XTS3_0:
1380 case WM8962_VSS_XTS4_1:
1381 case WM8962_VSS_XTS4_0:
1382 case WM8962_VSS_XTS5_1:
1383 case WM8962_VSS_XTS5_0:
1384 case WM8962_VSS_XTS6_1:
1385 case WM8962_VSS_XTS6_0:
1386 case WM8962_VSS_XTS7_1:
1387 case WM8962_VSS_XTS7_0:
1388 case WM8962_VSS_XTS8_1:
1389 case WM8962_VSS_XTS8_0:
1390 case WM8962_VSS_XTS9_1:
1391 case WM8962_VSS_XTS9_0:
1392 case WM8962_VSS_XTS10_1:
1393 case WM8962_VSS_XTS10_0:
1394 case WM8962_VSS_XTS11_1:
1395 case WM8962_VSS_XTS11_0:
1396 case WM8962_VSS_XTS12_1:
1397 case WM8962_VSS_XTS12_0:
1398 case WM8962_VSS_XTS13_1:
1399 case WM8962_VSS_XTS13_0:
1400 case WM8962_VSS_XTS14_1:
1401 case WM8962_VSS_XTS14_0:
1402 case WM8962_VSS_XTS15_1:
1403 case WM8962_VSS_XTS15_0:
1404 case WM8962_VSS_XTS16_1:
1405 case WM8962_VSS_XTS16_0:
1406 case WM8962_VSS_XTS17_1:
1407 case WM8962_VSS_XTS17_0:
1408 case WM8962_VSS_XTS18_1:
1409 case WM8962_VSS_XTS18_0:
1410 case WM8962_VSS_XTS19_1:
1411 case WM8962_VSS_XTS19_0:
1412 case WM8962_VSS_XTS20_1:
1413 case WM8962_VSS_XTS20_0:
1414 case WM8962_VSS_XTS21_1:
1415 case WM8962_VSS_XTS21_0:
1416 case WM8962_VSS_XTS22_1:
1417 case WM8962_VSS_XTS22_0:
1418 case WM8962_VSS_XTS23_1:
1419 case WM8962_VSS_XTS23_0:
1420 case WM8962_VSS_XTS24_1:
1421 case WM8962_VSS_XTS24_0:
1422 case WM8962_VSS_XTS25_1:
1423 case WM8962_VSS_XTS25_0:
1424 case WM8962_VSS_XTS26_1:
1425 case WM8962_VSS_XTS26_0:
1426 case WM8962_VSS_XTS27_1:
1427 case WM8962_VSS_XTS27_0:
1428 case WM8962_VSS_XTS28_1:
1429 case WM8962_VSS_XTS28_0:
1430 case WM8962_VSS_XTS29_1:
1431 case WM8962_VSS_XTS29_0:
1432 case WM8962_VSS_XTS30_1:
1433 case WM8962_VSS_XTS30_0:
1434 case WM8962_VSS_XTS31_1:
1435 case WM8962_VSS_XTS31_0:
1436 case WM8962_VSS_XTS32_1:
1437 case WM8962_VSS_XTS32_0:
1438 return true;
1439 default:
1440 return false;
1441 }
1442}
1443
1444static int wm8962_reset(struct wm8962_priv *wm8962)
1445{
1446 int ret;
1447
1448 ret = regmap_write(wm8962->regmap, WM8962_SOFTWARE_RESET, 0x6243);
1449 if (ret != 0)
1450 return ret;
1451
1452 return regmap_write(wm8962->regmap, WM8962_PLL_SOFTWARE_RESET, 0);
1453}
1454
1455static const DECLARE_TLV_DB_SCALE(inpga_tlv, -2325, 75, 0);
1456static const DECLARE_TLV_DB_SCALE(mixin_tlv, -1500, 300, 0);
1457static const unsigned int mixinpga_tlv[] = {
1458 TLV_DB_RANGE_HEAD(5),
1459 0, 1, TLV_DB_SCALE_ITEM(0, 600, 0),
1460 2, 2, TLV_DB_SCALE_ITEM(1300, 1300, 0),
1461 3, 4, TLV_DB_SCALE_ITEM(1800, 200, 0),
1462 5, 5, TLV_DB_SCALE_ITEM(2400, 0, 0),
1463 6, 7, TLV_DB_SCALE_ITEM(2700, 300, 0),
1464};
1465static const DECLARE_TLV_DB_SCALE(beep_tlv, -9600, 600, 1);
1466static const DECLARE_TLV_DB_SCALE(digital_tlv, -7200, 75, 1);
1467static const DECLARE_TLV_DB_SCALE(st_tlv, -3600, 300, 0);
1468static const DECLARE_TLV_DB_SCALE(inmix_tlv, -600, 600, 0);
1469static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
1470static const DECLARE_TLV_DB_SCALE(out_tlv, -12100, 100, 1);
1471static const DECLARE_TLV_DB_SCALE(hp_tlv, -700, 100, 0);
1472static const unsigned int classd_tlv[] = {
1473 TLV_DB_RANGE_HEAD(2),
1474 0, 6, TLV_DB_SCALE_ITEM(0, 150, 0),
1475 7, 7, TLV_DB_SCALE_ITEM(1200, 0, 0),
1476};
1477static const DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
1478
1479static int wm8962_dsp2_write_config(struct snd_soc_codec *codec)
1480{
1481 return regcache_sync_region(codec->control_data,
1482 WM8962_HDBASS_AI_1, WM8962_MAX_REGISTER);
1483}
1484
1485static int wm8962_dsp2_set_enable(struct snd_soc_codec *codec, u16 val)
1486{
1487 u16 adcl = snd_soc_read(codec, WM8962_LEFT_ADC_VOLUME);
1488 u16 adcr = snd_soc_read(codec, WM8962_RIGHT_ADC_VOLUME);
1489 u16 dac = snd_soc_read(codec, WM8962_ADC_DAC_CONTROL_1);
1490
1491
1492 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, 0);
1493 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, WM8962_ADC_VU);
1494 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1495 WM8962_DAC_MUTE, WM8962_DAC_MUTE);
1496
1497 snd_soc_write(codec, WM8962_SOUNDSTAGE_ENABLES_0, val);
1498
1499
1500 snd_soc_write(codec, WM8962_LEFT_ADC_VOLUME, adcl);
1501 snd_soc_write(codec, WM8962_RIGHT_ADC_VOLUME, adcr);
1502 snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
1503 WM8962_DAC_MUTE, dac);
1504
1505 return 0;
1506}
1507
1508static int wm8962_dsp2_start(struct snd_soc_codec *codec)
1509{
1510 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1511
1512 wm8962_dsp2_write_config(codec);
1513
1514 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_RUNR);
1515
1516 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1517
1518 return 0;
1519}
1520
1521static int wm8962_dsp2_stop(struct snd_soc_codec *codec)
1522{
1523 wm8962_dsp2_set_enable(codec, 0);
1524
1525 snd_soc_write(codec, WM8962_DSP2_EXECCONTROL, WM8962_DSP2_STOP);
1526
1527 return 0;
1528}
1529
1530#define WM8962_DSP2_ENABLE(xname, xshift) \
1531{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1532 .info = wm8962_dsp2_ena_info, \
1533 .get = wm8962_dsp2_ena_get, .put = wm8962_dsp2_ena_put, \
1534 .private_value = xshift }
1535
1536static int wm8962_dsp2_ena_info(struct snd_kcontrol *kcontrol,
1537 struct snd_ctl_elem_info *uinfo)
1538{
1539 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1540
1541 uinfo->count = 1;
1542 uinfo->value.integer.min = 0;
1543 uinfo->value.integer.max = 1;
1544
1545 return 0;
1546}
1547
1548static int wm8962_dsp2_ena_get(struct snd_kcontrol *kcontrol,
1549 struct snd_ctl_elem_value *ucontrol)
1550{
1551 int shift = kcontrol->private_value;
1552 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1553 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1554
1555 ucontrol->value.integer.value[0] = !!(wm8962->dsp2_ena & 1 << shift);
1556
1557 return 0;
1558}
1559
1560static int wm8962_dsp2_ena_put(struct snd_kcontrol *kcontrol,
1561 struct snd_ctl_elem_value *ucontrol)
1562{
1563 int shift = kcontrol->private_value;
1564 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1565 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1566 int old = wm8962->dsp2_ena;
1567 int ret = 0;
1568 int dsp2_running = snd_soc_read(codec, WM8962_DSP2_POWER_MANAGEMENT) &
1569 WM8962_DSP2_ENA;
1570
1571 mutex_lock(&codec->mutex);
1572
1573 if (ucontrol->value.integer.value[0])
1574 wm8962->dsp2_ena |= 1 << shift;
1575 else
1576 wm8962->dsp2_ena &= ~(1 << shift);
1577
1578 if (wm8962->dsp2_ena == old)
1579 goto out;
1580
1581 ret = 1;
1582
1583 if (dsp2_running) {
1584 if (wm8962->dsp2_ena)
1585 wm8962_dsp2_set_enable(codec, wm8962->dsp2_ena);
1586 else
1587 wm8962_dsp2_stop(codec);
1588 }
1589
1590out:
1591 mutex_unlock(&codec->mutex);
1592
1593 return ret;
1594}
1595
1596
1597
1598
1599static int wm8962_put_hp_sw(struct snd_kcontrol *kcontrol,
1600 struct snd_ctl_elem_value *ucontrol)
1601{
1602 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1603 u16 *reg_cache = codec->reg_cache;
1604 int ret;
1605
1606
1607 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1608 if (ret == 0)
1609 return 0;
1610
1611
1612 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTL_PGA_ENA)
1613 return snd_soc_write(codec, WM8962_HPOUTL_VOLUME,
1614 reg_cache[WM8962_HPOUTL_VOLUME]);
1615
1616
1617 if (snd_soc_read(codec, WM8962_PWR_MGMT_2) & WM8962_HPOUTR_PGA_ENA)
1618 return snd_soc_write(codec, WM8962_HPOUTR_VOLUME,
1619 reg_cache[WM8962_HPOUTR_VOLUME]);
1620
1621 return 0;
1622}
1623
1624
1625
1626
1627static int wm8962_put_spk_sw(struct snd_kcontrol *kcontrol,
1628 struct snd_ctl_elem_value *ucontrol)
1629{
1630 struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
1631 int ret;
1632
1633
1634 ret = snd_soc_put_volsw(kcontrol, ucontrol);
1635 if (ret == 0)
1636 return 0;
1637
1638
1639 ret = snd_soc_read(codec, WM8962_PWR_MGMT_2);
1640 if (ret & WM8962_SPKOUTL_PGA_ENA) {
1641 snd_soc_write(codec, WM8962_SPKOUTL_VOLUME,
1642 snd_soc_read(codec, WM8962_SPKOUTL_VOLUME));
1643 return 1;
1644 }
1645
1646
1647 if (ret & WM8962_SPKOUTR_PGA_ENA)
1648 snd_soc_write(codec, WM8962_SPKOUTR_VOLUME,
1649 snd_soc_read(codec, WM8962_SPKOUTR_VOLUME));
1650
1651 return 1;
1652}
1653
1654static const char *cap_hpf_mode_text[] = {
1655 "Hi-fi", "Application"
1656};
1657
1658static const struct soc_enum cap_hpf_mode =
1659 SOC_ENUM_SINGLE(WM8962_ADC_DAC_CONTROL_2, 10, 2, cap_hpf_mode_text);
1660
1661
1662static const char *cap_lhpf_mode_text[] = {
1663 "LPF", "HPF"
1664};
1665
1666static const struct soc_enum cap_lhpf_mode =
1667 SOC_ENUM_SINGLE(WM8962_LHPF1, 1, 2, cap_lhpf_mode_text);
1668
1669static const struct snd_kcontrol_new wm8962_snd_controls[] = {
1670SOC_DOUBLE("Input Mixer Switch", WM8962_INPUT_MIXER_CONTROL_1, 3, 2, 1, 1),
1671
1672SOC_SINGLE_TLV("MIXINL IN2L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 6, 7, 0,
1673 mixin_tlv),
1674SOC_SINGLE_TLV("MIXINL PGA Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 3, 7, 0,
1675 mixinpga_tlv),
1676SOC_SINGLE_TLV("MIXINL IN3L Volume", WM8962_LEFT_INPUT_MIXER_VOLUME, 0, 7, 0,
1677 mixin_tlv),
1678
1679SOC_SINGLE_TLV("MIXINR IN2R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 6, 7, 0,
1680 mixin_tlv),
1681SOC_SINGLE_TLV("MIXINR PGA Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 3, 7, 0,
1682 mixinpga_tlv),
1683SOC_SINGLE_TLV("MIXINR IN3R Volume", WM8962_RIGHT_INPUT_MIXER_VOLUME, 0, 7, 0,
1684 mixin_tlv),
1685
1686SOC_DOUBLE_R_TLV("Digital Capture Volume", WM8962_LEFT_ADC_VOLUME,
1687 WM8962_RIGHT_ADC_VOLUME, 1, 127, 0, digital_tlv),
1688SOC_DOUBLE_R_TLV("Capture Volume", WM8962_LEFT_INPUT_VOLUME,
1689 WM8962_RIGHT_INPUT_VOLUME, 0, 63, 0, inpga_tlv),
1690SOC_DOUBLE_R("Capture Switch", WM8962_LEFT_INPUT_VOLUME,
1691 WM8962_RIGHT_INPUT_VOLUME, 7, 1, 1),
1692SOC_DOUBLE_R("Capture ZC Switch", WM8962_LEFT_INPUT_VOLUME,
1693 WM8962_RIGHT_INPUT_VOLUME, 6, 1, 1),
1694SOC_SINGLE("Capture HPF Switch", WM8962_ADC_DAC_CONTROL_1, 0, 1, 1),
1695SOC_ENUM("Capture HPF Mode", cap_hpf_mode),
1696SOC_SINGLE("Capture HPF Cutoff", WM8962_ADC_DAC_CONTROL_2, 7, 7, 0),
1697SOC_SINGLE("Capture LHPF Switch", WM8962_LHPF1, 0, 1, 0),
1698SOC_ENUM("Capture LHPF Mode", cap_lhpf_mode),
1699
1700SOC_DOUBLE_R_TLV("Sidetone Volume", WM8962_DAC_DSP_MIXING_1,
1701 WM8962_DAC_DSP_MIXING_2, 4, 12, 0, st_tlv),
1702
1703SOC_DOUBLE_R_TLV("Digital Playback Volume", WM8962_LEFT_DAC_VOLUME,
1704 WM8962_RIGHT_DAC_VOLUME, 1, 127, 0, digital_tlv),
1705SOC_SINGLE("DAC High Performance Switch", WM8962_ADC_DAC_CONTROL_2, 0, 1, 0),
1706SOC_SINGLE("DAC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 5, 1, 0),
1707SOC_SINGLE("ADC L/R Swap Switch", WM8962_AUDIO_INTERFACE_0, 8, 1, 0),
1708
1709SOC_SINGLE("ADC High Performance Switch", WM8962_ADDITIONAL_CONTROL_1,
1710 5, 1, 0),
1711
1712SOC_SINGLE_TLV("Beep Volume", WM8962_BEEP_GENERATOR_1, 4, 15, 0, beep_tlv),
1713
1714SOC_DOUBLE_R_TLV("Headphone Volume", WM8962_HPOUTL_VOLUME,
1715 WM8962_HPOUTR_VOLUME, 0, 127, 0, out_tlv),
1716SOC_DOUBLE_EXT("Headphone Switch", WM8962_PWR_MGMT_2, 1, 0, 1, 1,
1717 snd_soc_get_volsw, wm8962_put_hp_sw),
1718SOC_DOUBLE_R("Headphone ZC Switch", WM8962_HPOUTL_VOLUME, WM8962_HPOUTR_VOLUME,
1719 7, 1, 0),
1720SOC_DOUBLE_TLV("Headphone Aux Volume", WM8962_ANALOGUE_HP_2, 3, 6, 7, 0,
1721 hp_tlv),
1722
1723SOC_DOUBLE_R("Headphone Mixer Switch", WM8962_HEADPHONE_MIXER_3,
1724 WM8962_HEADPHONE_MIXER_4, 8, 1, 1),
1725
1726SOC_SINGLE_TLV("HPMIXL IN4L Volume", WM8962_HEADPHONE_MIXER_3,
1727 3, 7, 0, bypass_tlv),
1728SOC_SINGLE_TLV("HPMIXL IN4R Volume", WM8962_HEADPHONE_MIXER_3,
1729 0, 7, 0, bypass_tlv),
1730SOC_SINGLE_TLV("HPMIXL MIXINL Volume", WM8962_HEADPHONE_MIXER_3,
1731 7, 1, 1, inmix_tlv),
1732SOC_SINGLE_TLV("HPMIXL MIXINR Volume", WM8962_HEADPHONE_MIXER_3,
1733 6, 1, 1, inmix_tlv),
1734
1735SOC_SINGLE_TLV("HPMIXR IN4L Volume", WM8962_HEADPHONE_MIXER_4,
1736 3, 7, 0, bypass_tlv),
1737SOC_SINGLE_TLV("HPMIXR IN4R Volume", WM8962_HEADPHONE_MIXER_4,
1738 0, 7, 0, bypass_tlv),
1739SOC_SINGLE_TLV("HPMIXR MIXINL Volume", WM8962_HEADPHONE_MIXER_4,
1740 7, 1, 1, inmix_tlv),
1741SOC_SINGLE_TLV("HPMIXR MIXINR Volume", WM8962_HEADPHONE_MIXER_4,
1742 6, 1, 1, inmix_tlv),
1743
1744SOC_SINGLE_TLV("Speaker Boost Volume", WM8962_CLASS_D_CONTROL_2, 0, 7, 0,
1745 classd_tlv),
1746
1747SOC_SINGLE("EQ Switch", WM8962_EQ1, WM8962_EQ_ENA_SHIFT, 1, 0),
1748SOC_DOUBLE_R_TLV("EQ1 Volume", WM8962_EQ2, WM8962_EQ22,
1749 WM8962_EQL_B1_GAIN_SHIFT, 31, 0, eq_tlv),
1750SOC_DOUBLE_R_TLV("EQ2 Volume", WM8962_EQ2, WM8962_EQ22,
1751 WM8962_EQL_B2_GAIN_SHIFT, 31, 0, eq_tlv),
1752SOC_DOUBLE_R_TLV("EQ3 Volume", WM8962_EQ2, WM8962_EQ22,
1753 WM8962_EQL_B3_GAIN_SHIFT, 31, 0, eq_tlv),
1754SOC_DOUBLE_R_TLV("EQ4 Volume", WM8962_EQ3, WM8962_EQ23,
1755 WM8962_EQL_B4_GAIN_SHIFT, 31, 0, eq_tlv),
1756SOC_DOUBLE_R_TLV("EQ5 Volume", WM8962_EQ3, WM8962_EQ23,
1757 WM8962_EQL_B5_GAIN_SHIFT, 31, 0, eq_tlv),
1758
1759SOC_SINGLE("3D Switch", WM8962_THREED1, 0, 1, 0),
1760SND_SOC_BYTES_MASK("3D Coefficients", WM8962_THREED1, 4, WM8962_THREED_ENA),
1761
1762SOC_SINGLE("DF1 Switch", WM8962_DF1, 0, 1, 0),
1763SND_SOC_BYTES_MASK("DF1 Coefficients", WM8962_DF1, 7, WM8962_DF1_ENA),
1764
1765SOC_SINGLE("DRC Switch", WM8962_DRC_1, 0, 1, 0),
1766SND_SOC_BYTES_MASK("DRC Coefficients", WM8962_DRC_1, 5, WM8962_DRC_ENA),
1767
1768WM8962_DSP2_ENABLE("VSS Switch", WM8962_VSS_ENA_SHIFT),
1769SND_SOC_BYTES("VSS Coefficients", WM8962_VSS_XHD2_1, 148),
1770WM8962_DSP2_ENABLE("HPF1 Switch", WM8962_HPF1_ENA_SHIFT),
1771WM8962_DSP2_ENABLE("HPF2 Switch", WM8962_HPF2_ENA_SHIFT),
1772SND_SOC_BYTES("HPF Coefficients", WM8962_LHPF2, 1),
1773WM8962_DSP2_ENABLE("HD Bass Switch", WM8962_HDBASS_ENA_SHIFT),
1774SND_SOC_BYTES("HD Bass Coefficients", WM8962_HDBASS_AI_1, 30),
1775};
1776
1777static const struct snd_kcontrol_new wm8962_spk_mono_controls[] = {
1778SOC_SINGLE_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME, 0, 127, 0, out_tlv),
1779SOC_SINGLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 1, 1,
1780 snd_soc_get_volsw, wm8962_put_spk_sw),
1781SOC_SINGLE("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, 7, 1, 0),
1782
1783SOC_SINGLE("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3, 8, 1, 1),
1784SOC_SINGLE_TLV("Speaker Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1785 3, 7, 0, bypass_tlv),
1786SOC_SINGLE_TLV("Speaker Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1787 0, 7, 0, bypass_tlv),
1788SOC_SINGLE_TLV("Speaker Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1789 7, 1, 1, inmix_tlv),
1790SOC_SINGLE_TLV("Speaker Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1791 6, 1, 1, inmix_tlv),
1792SOC_SINGLE_TLV("Speaker Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1793 7, 1, 0, inmix_tlv),
1794SOC_SINGLE_TLV("Speaker Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1795 6, 1, 0, inmix_tlv),
1796};
1797
1798static const struct snd_kcontrol_new wm8962_spk_stereo_controls[] = {
1799SOC_DOUBLE_R_TLV("Speaker Volume", WM8962_SPKOUTL_VOLUME,
1800 WM8962_SPKOUTR_VOLUME, 0, 127, 0, out_tlv),
1801SOC_DOUBLE_EXT("Speaker Switch", WM8962_CLASS_D_CONTROL_1, 1, 0, 1, 1,
1802 snd_soc_get_volsw, wm8962_put_spk_sw),
1803SOC_DOUBLE_R("Speaker ZC Switch", WM8962_SPKOUTL_VOLUME, WM8962_SPKOUTR_VOLUME,
1804 7, 1, 0),
1805
1806SOC_DOUBLE_R("Speaker Mixer Switch", WM8962_SPEAKER_MIXER_3,
1807 WM8962_SPEAKER_MIXER_4, 8, 1, 1),
1808
1809SOC_SINGLE_TLV("SPKOUTL Mixer IN4L Volume", WM8962_SPEAKER_MIXER_3,
1810 3, 7, 0, bypass_tlv),
1811SOC_SINGLE_TLV("SPKOUTL Mixer IN4R Volume", WM8962_SPEAKER_MIXER_3,
1812 0, 7, 0, bypass_tlv),
1813SOC_SINGLE_TLV("SPKOUTL Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_3,
1814 7, 1, 1, inmix_tlv),
1815SOC_SINGLE_TLV("SPKOUTL Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_3,
1816 6, 1, 1, inmix_tlv),
1817SOC_SINGLE_TLV("SPKOUTL Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1818 7, 1, 0, inmix_tlv),
1819SOC_SINGLE_TLV("SPKOUTL Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1820 6, 1, 0, inmix_tlv),
1821
1822SOC_SINGLE_TLV("SPKOUTR Mixer IN4L Volume", WM8962_SPEAKER_MIXER_4,
1823 3, 7, 0, bypass_tlv),
1824SOC_SINGLE_TLV("SPKOUTR Mixer IN4R Volume", WM8962_SPEAKER_MIXER_4,
1825 0, 7, 0, bypass_tlv),
1826SOC_SINGLE_TLV("SPKOUTR Mixer MIXINL Volume", WM8962_SPEAKER_MIXER_4,
1827 7, 1, 1, inmix_tlv),
1828SOC_SINGLE_TLV("SPKOUTR Mixer MIXINR Volume", WM8962_SPEAKER_MIXER_4,
1829 6, 1, 1, inmix_tlv),
1830SOC_SINGLE_TLV("SPKOUTR Mixer DACL Volume", WM8962_SPEAKER_MIXER_5,
1831 5, 1, 0, inmix_tlv),
1832SOC_SINGLE_TLV("SPKOUTR Mixer DACR Volume", WM8962_SPEAKER_MIXER_5,
1833 4, 1, 0, inmix_tlv),
1834};
1835
1836static int cp_event(struct snd_soc_dapm_widget *w,
1837 struct snd_kcontrol *kcontrol, int event)
1838{
1839 switch (event) {
1840 case SND_SOC_DAPM_POST_PMU:
1841 msleep(5);
1842 break;
1843
1844 default:
1845 BUG();
1846 return -EINVAL;
1847 }
1848
1849 return 0;
1850}
1851
1852static int hp_event(struct snd_soc_dapm_widget *w,
1853 struct snd_kcontrol *kcontrol, int event)
1854{
1855 struct snd_soc_codec *codec = w->codec;
1856 int timeout;
1857 int reg;
1858 int expected = (WM8962_DCS_STARTUP_DONE_HP1L |
1859 WM8962_DCS_STARTUP_DONE_HP1R);
1860
1861 switch (event) {
1862 case SND_SOC_DAPM_POST_PMU:
1863 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1864 WM8962_HP1L_ENA | WM8962_HP1R_ENA,
1865 WM8962_HP1L_ENA | WM8962_HP1R_ENA);
1866 udelay(20);
1867
1868 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1869 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY,
1870 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY);
1871
1872
1873 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1874 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1875 WM8962_HP1L_DCS_STARTUP |
1876 WM8962_HP1R_DCS_STARTUP,
1877 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1878 WM8962_HP1L_DCS_STARTUP |
1879 WM8962_HP1R_DCS_STARTUP);
1880
1881
1882 timeout = 0;
1883 do {
1884 msleep(1);
1885 reg = snd_soc_read(codec, WM8962_DC_SERVO_6);
1886 if (reg < 0) {
1887 dev_err(codec->dev,
1888 "Failed to read DCS status: %d\n",
1889 reg);
1890 continue;
1891 }
1892 dev_dbg(codec->dev, "DCS status: %x\n", reg);
1893 } while (++timeout < 200 && (reg & expected) != expected);
1894
1895 if ((reg & expected) != expected)
1896 dev_err(codec->dev, "DC servo timed out\n");
1897 else
1898 dev_dbg(codec->dev, "DC servo complete after %dms\n",
1899 timeout);
1900
1901 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1902 WM8962_HP1L_ENA_OUTP |
1903 WM8962_HP1R_ENA_OUTP,
1904 WM8962_HP1L_ENA_OUTP |
1905 WM8962_HP1R_ENA_OUTP);
1906 udelay(20);
1907
1908 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1909 WM8962_HP1L_RMV_SHORT |
1910 WM8962_HP1R_RMV_SHORT,
1911 WM8962_HP1L_RMV_SHORT |
1912 WM8962_HP1R_RMV_SHORT);
1913 break;
1914
1915 case SND_SOC_DAPM_PRE_PMD:
1916 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1917 WM8962_HP1L_RMV_SHORT |
1918 WM8962_HP1R_RMV_SHORT, 0);
1919
1920 udelay(20);
1921
1922 snd_soc_update_bits(codec, WM8962_DC_SERVO_1,
1923 WM8962_HP1L_DCS_ENA | WM8962_HP1R_DCS_ENA |
1924 WM8962_HP1L_DCS_STARTUP |
1925 WM8962_HP1R_DCS_STARTUP,
1926 0);
1927
1928 snd_soc_update_bits(codec, WM8962_ANALOGUE_HP_0,
1929 WM8962_HP1L_ENA | WM8962_HP1R_ENA |
1930 WM8962_HP1L_ENA_DLY | WM8962_HP1R_ENA_DLY |
1931 WM8962_HP1L_ENA_OUTP |
1932 WM8962_HP1R_ENA_OUTP, 0);
1933
1934 break;
1935
1936 default:
1937 BUG();
1938 return -EINVAL;
1939
1940 }
1941
1942 return 0;
1943}
1944
1945
1946static int out_pga_event(struct snd_soc_dapm_widget *w,
1947 struct snd_kcontrol *kcontrol, int event)
1948{
1949 struct snd_soc_codec *codec = w->codec;
1950 int reg;
1951
1952 switch (w->shift) {
1953 case WM8962_HPOUTR_PGA_ENA_SHIFT:
1954 reg = WM8962_HPOUTR_VOLUME;
1955 break;
1956 case WM8962_HPOUTL_PGA_ENA_SHIFT:
1957 reg = WM8962_HPOUTL_VOLUME;
1958 break;
1959 case WM8962_SPKOUTR_PGA_ENA_SHIFT:
1960 reg = WM8962_SPKOUTR_VOLUME;
1961 break;
1962 case WM8962_SPKOUTL_PGA_ENA_SHIFT:
1963 reg = WM8962_SPKOUTL_VOLUME;
1964 break;
1965 default:
1966 BUG();
1967 return -EINVAL;
1968 }
1969
1970 switch (event) {
1971 case SND_SOC_DAPM_POST_PMU:
1972 return snd_soc_write(codec, reg, snd_soc_read(codec, reg));
1973 default:
1974 BUG();
1975 return -EINVAL;
1976 }
1977}
1978
1979static int dsp2_event(struct snd_soc_dapm_widget *w,
1980 struct snd_kcontrol *kcontrol, int event)
1981{
1982 struct snd_soc_codec *codec = w->codec;
1983 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
1984
1985 switch (event) {
1986 case SND_SOC_DAPM_POST_PMU:
1987 if (wm8962->dsp2_ena)
1988 wm8962_dsp2_start(codec);
1989 break;
1990
1991 case SND_SOC_DAPM_PRE_PMD:
1992 if (wm8962->dsp2_ena)
1993 wm8962_dsp2_stop(codec);
1994 break;
1995
1996 default:
1997 BUG();
1998 return -EINVAL;
1999 }
2000
2001 return 0;
2002}
2003
2004static const char *st_text[] = { "None", "Left", "Right" };
2005
2006static const struct soc_enum str_enum =
2007 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_1, 2, 3, st_text);
2008
2009static const struct snd_kcontrol_new str_mux =
2010 SOC_DAPM_ENUM("Right Sidetone", str_enum);
2011
2012static const struct soc_enum stl_enum =
2013 SOC_ENUM_SINGLE(WM8962_DAC_DSP_MIXING_2, 2, 3, st_text);
2014
2015static const struct snd_kcontrol_new stl_mux =
2016 SOC_DAPM_ENUM("Left Sidetone", stl_enum);
2017
2018static const char *outmux_text[] = { "DAC", "Mixer" };
2019
2020static const struct soc_enum spkoutr_enum =
2021 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_2, 7, 2, outmux_text);
2022
2023static const struct snd_kcontrol_new spkoutr_mux =
2024 SOC_DAPM_ENUM("SPKOUTR Mux", spkoutr_enum);
2025
2026static const struct soc_enum spkoutl_enum =
2027 SOC_ENUM_SINGLE(WM8962_SPEAKER_MIXER_1, 7, 2, outmux_text);
2028
2029static const struct snd_kcontrol_new spkoutl_mux =
2030 SOC_DAPM_ENUM("SPKOUTL Mux", spkoutl_enum);
2031
2032static const struct soc_enum hpoutr_enum =
2033 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_2, 7, 2, outmux_text);
2034
2035static const struct snd_kcontrol_new hpoutr_mux =
2036 SOC_DAPM_ENUM("HPOUTR Mux", hpoutr_enum);
2037
2038static const struct soc_enum hpoutl_enum =
2039 SOC_ENUM_SINGLE(WM8962_HEADPHONE_MIXER_1, 7, 2, outmux_text);
2040
2041static const struct snd_kcontrol_new hpoutl_mux =
2042 SOC_DAPM_ENUM("HPOUTL Mux", hpoutl_enum);
2043
2044static const struct snd_kcontrol_new inpgal[] = {
2045SOC_DAPM_SINGLE("IN1L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 3, 1, 0),
2046SOC_DAPM_SINGLE("IN2L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 2, 1, 0),
2047SOC_DAPM_SINGLE("IN3L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 1, 1, 0),
2048SOC_DAPM_SINGLE("IN4L Switch", WM8962_LEFT_INPUT_PGA_CONTROL, 0, 1, 0),
2049};
2050
2051static const struct snd_kcontrol_new inpgar[] = {
2052SOC_DAPM_SINGLE("IN1R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 3, 1, 0),
2053SOC_DAPM_SINGLE("IN2R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 2, 1, 0),
2054SOC_DAPM_SINGLE("IN3R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 1, 1, 0),
2055SOC_DAPM_SINGLE("IN4R Switch", WM8962_RIGHT_INPUT_PGA_CONTROL, 0, 1, 0),
2056};
2057
2058static const struct snd_kcontrol_new mixinl[] = {
2059SOC_DAPM_SINGLE("IN2L Switch", WM8962_INPUT_MIXER_CONTROL_2, 5, 1, 0),
2060SOC_DAPM_SINGLE("IN3L Switch", WM8962_INPUT_MIXER_CONTROL_2, 4, 1, 0),
2061SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 3, 1, 0),
2062};
2063
2064static const struct snd_kcontrol_new mixinr[] = {
2065SOC_DAPM_SINGLE("IN2R Switch", WM8962_INPUT_MIXER_CONTROL_2, 2, 1, 0),
2066SOC_DAPM_SINGLE("IN3R Switch", WM8962_INPUT_MIXER_CONTROL_2, 1, 1, 0),
2067SOC_DAPM_SINGLE("PGA Switch", WM8962_INPUT_MIXER_CONTROL_2, 0, 1, 0),
2068};
2069
2070static const struct snd_kcontrol_new hpmixl[] = {
2071SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_1, 5, 1, 0),
2072SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_1, 4, 1, 0),
2073SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_1, 3, 1, 0),
2074SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_1, 2, 1, 0),
2075SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_1, 1, 1, 0),
2076SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_1, 0, 1, 0),
2077};
2078
2079static const struct snd_kcontrol_new hpmixr[] = {
2080SOC_DAPM_SINGLE("DACL Switch", WM8962_HEADPHONE_MIXER_2, 5, 1, 0),
2081SOC_DAPM_SINGLE("DACR Switch", WM8962_HEADPHONE_MIXER_2, 4, 1, 0),
2082SOC_DAPM_SINGLE("MIXINL Switch", WM8962_HEADPHONE_MIXER_2, 3, 1, 0),
2083SOC_DAPM_SINGLE("MIXINR Switch", WM8962_HEADPHONE_MIXER_2, 2, 1, 0),
2084SOC_DAPM_SINGLE("IN4L Switch", WM8962_HEADPHONE_MIXER_2, 1, 1, 0),
2085SOC_DAPM_SINGLE("IN4R Switch", WM8962_HEADPHONE_MIXER_2, 0, 1, 0),
2086};
2087
2088static const struct snd_kcontrol_new spkmixl[] = {
2089SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_1, 5, 1, 0),
2090SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_1, 4, 1, 0),
2091SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_1, 3, 1, 0),
2092SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_1, 2, 1, 0),
2093SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_1, 1, 1, 0),
2094SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_1, 0, 1, 0),
2095};
2096
2097static const struct snd_kcontrol_new spkmixr[] = {
2098SOC_DAPM_SINGLE("DACL Switch", WM8962_SPEAKER_MIXER_2, 5, 1, 0),
2099SOC_DAPM_SINGLE("DACR Switch", WM8962_SPEAKER_MIXER_2, 4, 1, 0),
2100SOC_DAPM_SINGLE("MIXINL Switch", WM8962_SPEAKER_MIXER_2, 3, 1, 0),
2101SOC_DAPM_SINGLE("MIXINR Switch", WM8962_SPEAKER_MIXER_2, 2, 1, 0),
2102SOC_DAPM_SINGLE("IN4L Switch", WM8962_SPEAKER_MIXER_2, 1, 1, 0),
2103SOC_DAPM_SINGLE("IN4R Switch", WM8962_SPEAKER_MIXER_2, 0, 1, 0),
2104};
2105
2106static const struct snd_soc_dapm_widget wm8962_dapm_widgets[] = {
2107SND_SOC_DAPM_INPUT("IN1L"),
2108SND_SOC_DAPM_INPUT("IN1R"),
2109SND_SOC_DAPM_INPUT("IN2L"),
2110SND_SOC_DAPM_INPUT("IN2R"),
2111SND_SOC_DAPM_INPUT("IN3L"),
2112SND_SOC_DAPM_INPUT("IN3R"),
2113SND_SOC_DAPM_INPUT("IN4L"),
2114SND_SOC_DAPM_INPUT("IN4R"),
2115SND_SOC_DAPM_SIGGEN("Beep"),
2116SND_SOC_DAPM_INPUT("DMICDAT"),
2117
2118SND_SOC_DAPM_SUPPLY("MICBIAS", WM8962_PWR_MGMT_1, 1, 0, NULL, 0),
2119
2120SND_SOC_DAPM_SUPPLY("Class G", WM8962_CHARGE_PUMP_B, 0, 1, NULL, 0),
2121SND_SOC_DAPM_SUPPLY("SYSCLK", WM8962_CLOCKING2, 5, 0, NULL, 0),
2122SND_SOC_DAPM_SUPPLY("Charge Pump", WM8962_CHARGE_PUMP_1, 0, 0, cp_event,
2123 SND_SOC_DAPM_POST_PMU),
2124SND_SOC_DAPM_SUPPLY("TOCLK", WM8962_ADDITIONAL_CONTROL_1, 0, 0, NULL, 0),
2125SND_SOC_DAPM_SUPPLY_S("DSP2", 1, WM8962_DSP2_POWER_MANAGEMENT,
2126 WM8962_DSP2_ENA_SHIFT, 0, dsp2_event,
2127 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2128SND_SOC_DAPM_SUPPLY("TEMP_HP", WM8962_ADDITIONAL_CONTROL_4, 2, 0, NULL, 0),
2129SND_SOC_DAPM_SUPPLY("TEMP_SPK", WM8962_ADDITIONAL_CONTROL_4, 1, 0, NULL, 0),
2130
2131SND_SOC_DAPM_MIXER("INPGAL", WM8962_LEFT_INPUT_PGA_CONTROL, 4, 0,
2132 inpgal, ARRAY_SIZE(inpgal)),
2133SND_SOC_DAPM_MIXER("INPGAR", WM8962_RIGHT_INPUT_PGA_CONTROL, 4, 0,
2134 inpgar, ARRAY_SIZE(inpgar)),
2135SND_SOC_DAPM_MIXER("MIXINL", WM8962_PWR_MGMT_1, 5, 0,
2136 mixinl, ARRAY_SIZE(mixinl)),
2137SND_SOC_DAPM_MIXER("MIXINR", WM8962_PWR_MGMT_1, 4, 0,
2138 mixinr, ARRAY_SIZE(mixinr)),
2139
2140SND_SOC_DAPM_AIF_IN("DMIC_ENA", NULL, 0, WM8962_PWR_MGMT_1, 10, 0),
2141
2142SND_SOC_DAPM_ADC("ADCL", "Capture", WM8962_PWR_MGMT_1, 3, 0),
2143SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2144
2145SND_SOC_DAPM_MUX("STL", SND_SOC_NOPM, 0, 0, &stl_mux),
2146SND_SOC_DAPM_MUX("STR", SND_SOC_NOPM, 0, 0, &str_mux),
2147
2148SND_SOC_DAPM_DAC("DACL", "Playback", WM8962_PWR_MGMT_2, 8, 0),
2149SND_SOC_DAPM_DAC("DACR", "Playback", WM8962_PWR_MGMT_2, 7, 0),
2150
2151SND_SOC_DAPM_PGA("Left Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2152SND_SOC_DAPM_PGA("Right Bypass", SND_SOC_NOPM, 0, 0, NULL, 0),
2153
2154SND_SOC_DAPM_MIXER("HPMIXL", WM8962_MIXER_ENABLES, 3, 0,
2155 hpmixl, ARRAY_SIZE(hpmixl)),
2156SND_SOC_DAPM_MIXER("HPMIXR", WM8962_MIXER_ENABLES, 2, 0,
2157 hpmixr, ARRAY_SIZE(hpmixr)),
2158
2159SND_SOC_DAPM_MUX_E("HPOUTL PGA", WM8962_PWR_MGMT_2, 6, 0, &hpoutl_mux,
2160 out_pga_event, SND_SOC_DAPM_POST_PMU),
2161SND_SOC_DAPM_MUX_E("HPOUTR PGA", WM8962_PWR_MGMT_2, 5, 0, &hpoutr_mux,
2162 out_pga_event, SND_SOC_DAPM_POST_PMU),
2163
2164SND_SOC_DAPM_PGA_E("HPOUT", SND_SOC_NOPM, 0, 0, NULL, 0, hp_event,
2165 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
2166
2167SND_SOC_DAPM_OUTPUT("HPOUTL"),
2168SND_SOC_DAPM_OUTPUT("HPOUTR"),
2169};
2170
2171static const struct snd_soc_dapm_widget wm8962_dapm_spk_mono_widgets[] = {
2172SND_SOC_DAPM_MIXER("Speaker Mixer", WM8962_MIXER_ENABLES, 1, 0,
2173 spkmixl, ARRAY_SIZE(spkmixl)),
2174SND_SOC_DAPM_MUX_E("Speaker PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2175 out_pga_event, SND_SOC_DAPM_POST_PMU),
2176SND_SOC_DAPM_PGA("Speaker Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2177SND_SOC_DAPM_OUTPUT("SPKOUT"),
2178};
2179
2180static const struct snd_soc_dapm_widget wm8962_dapm_spk_stereo_widgets[] = {
2181SND_SOC_DAPM_MIXER("SPKOUTL Mixer", WM8962_MIXER_ENABLES, 1, 0,
2182 spkmixl, ARRAY_SIZE(spkmixl)),
2183SND_SOC_DAPM_MIXER("SPKOUTR Mixer", WM8962_MIXER_ENABLES, 0, 0,
2184 spkmixr, ARRAY_SIZE(spkmixr)),
2185
2186SND_SOC_DAPM_MUX_E("SPKOUTL PGA", WM8962_PWR_MGMT_2, 4, 0, &spkoutl_mux,
2187 out_pga_event, SND_SOC_DAPM_POST_PMU),
2188SND_SOC_DAPM_MUX_E("SPKOUTR PGA", WM8962_PWR_MGMT_2, 3, 0, &spkoutr_mux,
2189 out_pga_event, SND_SOC_DAPM_POST_PMU),
2190
2191SND_SOC_DAPM_PGA("SPKOUTR Output", WM8962_CLASS_D_CONTROL_1, 7, 0, NULL, 0),
2192SND_SOC_DAPM_PGA("SPKOUTL Output", WM8962_CLASS_D_CONTROL_1, 6, 0, NULL, 0),
2193
2194SND_SOC_DAPM_OUTPUT("SPKOUTL"),
2195SND_SOC_DAPM_OUTPUT("SPKOUTR"),
2196};
2197
2198static const struct snd_soc_dapm_route wm8962_intercon[] = {
2199 { "INPGAL", "IN1L Switch", "IN1L" },
2200 { "INPGAL", "IN2L Switch", "IN2L" },
2201 { "INPGAL", "IN3L Switch", "IN3L" },
2202 { "INPGAL", "IN4L Switch", "IN4L" },
2203
2204 { "INPGAR", "IN1R Switch", "IN1R" },
2205 { "INPGAR", "IN2R Switch", "IN2R" },
2206 { "INPGAR", "IN3R Switch", "IN3R" },
2207 { "INPGAR", "IN4R Switch", "IN4R" },
2208
2209 { "MIXINL", "IN2L Switch", "IN2L" },
2210 { "MIXINL", "IN3L Switch", "IN3L" },
2211 { "MIXINL", "PGA Switch", "INPGAL" },
2212
2213 { "MIXINR", "IN2R Switch", "IN2R" },
2214 { "MIXINR", "IN3R Switch", "IN3R" },
2215 { "MIXINR", "PGA Switch", "INPGAR" },
2216
2217 { "MICBIAS", NULL, "SYSCLK" },
2218
2219 { "DMIC_ENA", NULL, "DMICDAT" },
2220
2221 { "ADCL", NULL, "SYSCLK" },
2222 { "ADCL", NULL, "TOCLK" },
2223 { "ADCL", NULL, "MIXINL" },
2224 { "ADCL", NULL, "DMIC_ENA" },
2225 { "ADCL", NULL, "DSP2" },
2226
2227 { "ADCR", NULL, "SYSCLK" },
2228 { "ADCR", NULL, "TOCLK" },
2229 { "ADCR", NULL, "MIXINR" },
2230 { "ADCR", NULL, "DMIC_ENA" },
2231 { "ADCR", NULL, "DSP2" },
2232
2233 { "STL", "Left", "ADCL" },
2234 { "STL", "Right", "ADCR" },
2235 { "STL", NULL, "Class G" },
2236
2237 { "STR", "Left", "ADCL" },
2238 { "STR", "Right", "ADCR" },
2239 { "STR", NULL, "Class G" },
2240
2241 { "DACL", NULL, "SYSCLK" },
2242 { "DACL", NULL, "TOCLK" },
2243 { "DACL", NULL, "Beep" },
2244 { "DACL", NULL, "STL" },
2245 { "DACL", NULL, "DSP2" },
2246
2247 { "DACR", NULL, "SYSCLK" },
2248 { "DACR", NULL, "TOCLK" },
2249 { "DACR", NULL, "Beep" },
2250 { "DACR", NULL, "STR" },
2251 { "DACR", NULL, "DSP2" },
2252
2253 { "HPMIXL", "IN4L Switch", "IN4L" },
2254 { "HPMIXL", "IN4R Switch", "IN4R" },
2255 { "HPMIXL", "DACL Switch", "DACL" },
2256 { "HPMIXL", "DACR Switch", "DACR" },
2257 { "HPMIXL", "MIXINL Switch", "MIXINL" },
2258 { "HPMIXL", "MIXINR Switch", "MIXINR" },
2259
2260 { "HPMIXR", "IN4L Switch", "IN4L" },
2261 { "HPMIXR", "IN4R Switch", "IN4R" },
2262 { "HPMIXR", "DACL Switch", "DACL" },
2263 { "HPMIXR", "DACR Switch", "DACR" },
2264 { "HPMIXR", "MIXINL Switch", "MIXINL" },
2265 { "HPMIXR", "MIXINR Switch", "MIXINR" },
2266
2267 { "Left Bypass", NULL, "HPMIXL" },
2268 { "Left Bypass", NULL, "Class G" },
2269
2270 { "Right Bypass", NULL, "HPMIXR" },
2271 { "Right Bypass", NULL, "Class G" },
2272
2273 { "HPOUTL PGA", "Mixer", "Left Bypass" },
2274 { "HPOUTL PGA", "DAC", "DACL" },
2275
2276 { "HPOUTR PGA", "Mixer", "Right Bypass" },
2277 { "HPOUTR PGA", "DAC", "DACR" },
2278
2279 { "HPOUT", NULL, "HPOUTL PGA" },
2280 { "HPOUT", NULL, "HPOUTR PGA" },
2281 { "HPOUT", NULL, "Charge Pump" },
2282 { "HPOUT", NULL, "SYSCLK" },
2283 { "HPOUT", NULL, "TOCLK" },
2284
2285 { "HPOUTL", NULL, "HPOUT" },
2286 { "HPOUTR", NULL, "HPOUT" },
2287
2288 { "HPOUTL", NULL, "TEMP_HP" },
2289 { "HPOUTR", NULL, "TEMP_HP" },
2290};
2291
2292static const struct snd_soc_dapm_route wm8962_spk_mono_intercon[] = {
2293 { "Speaker Mixer", "IN4L Switch", "IN4L" },
2294 { "Speaker Mixer", "IN4R Switch", "IN4R" },
2295 { "Speaker Mixer", "DACL Switch", "DACL" },
2296 { "Speaker Mixer", "DACR Switch", "DACR" },
2297 { "Speaker Mixer", "MIXINL Switch", "MIXINL" },
2298 { "Speaker Mixer", "MIXINR Switch", "MIXINR" },
2299
2300 { "Speaker PGA", "Mixer", "Speaker Mixer" },
2301 { "Speaker PGA", "DAC", "DACL" },
2302
2303 { "Speaker Output", NULL, "Speaker PGA" },
2304 { "Speaker Output", NULL, "SYSCLK" },
2305 { "Speaker Output", NULL, "TOCLK" },
2306 { "Speaker Output", NULL, "TEMP_SPK" },
2307
2308 { "SPKOUT", NULL, "Speaker Output" },
2309};
2310
2311static const struct snd_soc_dapm_route wm8962_spk_stereo_intercon[] = {
2312 { "SPKOUTL Mixer", "IN4L Switch", "IN4L" },
2313 { "SPKOUTL Mixer", "IN4R Switch", "IN4R" },
2314 { "SPKOUTL Mixer", "DACL Switch", "DACL" },
2315 { "SPKOUTL Mixer", "DACR Switch", "DACR" },
2316 { "SPKOUTL Mixer", "MIXINL Switch", "MIXINL" },
2317 { "SPKOUTL Mixer", "MIXINR Switch", "MIXINR" },
2318
2319 { "SPKOUTR Mixer", "IN4L Switch", "IN4L" },
2320 { "SPKOUTR Mixer", "IN4R Switch", "IN4R" },
2321 { "SPKOUTR Mixer", "DACL Switch", "DACL" },
2322 { "SPKOUTR Mixer", "DACR Switch", "DACR" },
2323 { "SPKOUTR Mixer", "MIXINL Switch", "MIXINL" },
2324 { "SPKOUTR Mixer", "MIXINR Switch", "MIXINR" },
2325
2326 { "SPKOUTL PGA", "Mixer", "SPKOUTL Mixer" },
2327 { "SPKOUTL PGA", "DAC", "DACL" },
2328
2329 { "SPKOUTR PGA", "Mixer", "SPKOUTR Mixer" },
2330 { "SPKOUTR PGA", "DAC", "DACR" },
2331
2332 { "SPKOUTL Output", NULL, "SPKOUTL PGA" },
2333 { "SPKOUTL Output", NULL, "SYSCLK" },
2334 { "SPKOUTL Output", NULL, "TOCLK" },
2335 { "SPKOUTL Output", NULL, "TEMP_SPK" },
2336
2337 { "SPKOUTR Output", NULL, "SPKOUTR PGA" },
2338 { "SPKOUTR Output", NULL, "SYSCLK" },
2339 { "SPKOUTR Output", NULL, "TOCLK" },
2340 { "SPKOUTR Output", NULL, "TEMP_SPK" },
2341
2342 { "SPKOUTL", NULL, "SPKOUTL Output" },
2343 { "SPKOUTR", NULL, "SPKOUTR Output" },
2344};
2345
2346static int wm8962_add_widgets(struct snd_soc_codec *codec)
2347{
2348 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
2349 struct snd_soc_dapm_context *dapm = &codec->dapm;
2350
2351 snd_soc_add_codec_controls(codec, wm8962_snd_controls,
2352 ARRAY_SIZE(wm8962_snd_controls));
2353 if (pdata && pdata->spk_mono)
2354 snd_soc_add_codec_controls(codec, wm8962_spk_mono_controls,
2355 ARRAY_SIZE(wm8962_spk_mono_controls));
2356 else
2357 snd_soc_add_codec_controls(codec, wm8962_spk_stereo_controls,
2358 ARRAY_SIZE(wm8962_spk_stereo_controls));
2359
2360
2361 snd_soc_dapm_new_controls(dapm, wm8962_dapm_widgets,
2362 ARRAY_SIZE(wm8962_dapm_widgets));
2363 if (pdata && pdata->spk_mono)
2364 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_mono_widgets,
2365 ARRAY_SIZE(wm8962_dapm_spk_mono_widgets));
2366 else
2367 snd_soc_dapm_new_controls(dapm, wm8962_dapm_spk_stereo_widgets,
2368 ARRAY_SIZE(wm8962_dapm_spk_stereo_widgets));
2369
2370 snd_soc_dapm_add_routes(dapm, wm8962_intercon,
2371 ARRAY_SIZE(wm8962_intercon));
2372 if (pdata && pdata->spk_mono)
2373 snd_soc_dapm_add_routes(dapm, wm8962_spk_mono_intercon,
2374 ARRAY_SIZE(wm8962_spk_mono_intercon));
2375 else
2376 snd_soc_dapm_add_routes(dapm, wm8962_spk_stereo_intercon,
2377 ARRAY_SIZE(wm8962_spk_stereo_intercon));
2378
2379
2380 snd_soc_dapm_disable_pin(dapm, "Beep");
2381
2382 return 0;
2383}
2384
2385
2386static const int bclk_divs[] = {
2387 1, -1, 2, 3, 4, -1, 6, 8, -1, 12, 16, 24, -1, 32, 32, 32
2388};
2389
2390static const int sysclk_rates[] = {
2391 64, 128, 192, 256, 384, 512, 768, 1024, 1408, 1536, 3072, 6144
2392};
2393
2394static void wm8962_configure_bclk(struct snd_soc_codec *codec)
2395{
2396 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2397 int dspclk, i;
2398 int clocking2 = 0;
2399 int clocking4 = 0;
2400 int aif2 = 0;
2401
2402 if (!wm8962->sysclk_rate) {
2403 dev_dbg(codec->dev, "No SYSCLK configured\n");
2404 return;
2405 }
2406
2407 if (!wm8962->bclk || !wm8962->lrclk) {
2408 dev_dbg(codec->dev, "No audio clocks configured\n");
2409 return;
2410 }
2411
2412 for (i = 0; i < ARRAY_SIZE(sysclk_rates); i++) {
2413 if (sysclk_rates[i] == wm8962->sysclk_rate / wm8962->lrclk) {
2414 clocking4 |= i << WM8962_SYSCLK_RATE_SHIFT;
2415 break;
2416 }
2417 }
2418
2419 if (i == ARRAY_SIZE(sysclk_rates)) {
2420 dev_err(codec->dev, "Unsupported sysclk ratio %d\n",
2421 wm8962->sysclk_rate / wm8962->lrclk);
2422 return;
2423 }
2424
2425 dev_dbg(codec->dev, "Selected sysclk ratio %d\n", sysclk_rates[i]);
2426
2427 snd_soc_update_bits(codec, WM8962_CLOCKING_4,
2428 WM8962_SYSCLK_RATE_MASK, clocking4);
2429
2430 dspclk = snd_soc_read(codec, WM8962_CLOCKING1);
2431 if (dspclk < 0) {
2432 dev_err(codec->dev, "Failed to read DSPCLK: %d\n", dspclk);
2433 return;
2434 }
2435
2436 dspclk = (dspclk & WM8962_DSPCLK_DIV_MASK) >> WM8962_DSPCLK_DIV_SHIFT;
2437 switch (dspclk) {
2438 case 0:
2439 dspclk = wm8962->sysclk_rate;
2440 break;
2441 case 1:
2442 dspclk = wm8962->sysclk_rate / 2;
2443 break;
2444 case 2:
2445 dspclk = wm8962->sysclk_rate / 4;
2446 break;
2447 default:
2448 dev_warn(codec->dev, "Unknown DSPCLK divisor read back\n");
2449 dspclk = wm8962->sysclk;
2450 }
2451
2452 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk);
2453
2454
2455 for (i = 0; i < ARRAY_SIZE(bclk_divs); i++) {
2456 if (bclk_divs[i] < 0)
2457 continue;
2458
2459 if (dspclk / bclk_divs[i] == wm8962->bclk) {
2460 dev_dbg(codec->dev, "Selected BCLK_DIV %d for %dHz\n",
2461 bclk_divs[i], wm8962->bclk);
2462 clocking2 |= i;
2463 break;
2464 }
2465 }
2466 if (i == ARRAY_SIZE(bclk_divs)) {
2467 dev_err(codec->dev, "Unsupported BCLK ratio %d\n",
2468 dspclk / wm8962->bclk);
2469 return;
2470 }
2471
2472 aif2 |= wm8962->bclk / wm8962->lrclk;
2473 dev_dbg(codec->dev, "Selected LRCLK divisor %d for %dHz\n",
2474 wm8962->bclk / wm8962->lrclk, wm8962->lrclk);
2475
2476 snd_soc_update_bits(codec, WM8962_CLOCKING2,
2477 WM8962_BCLK_DIV_MASK, clocking2);
2478 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_2,
2479 WM8962_AIF_RATE_MASK, aif2);
2480}
2481
2482static int wm8962_set_bias_level(struct snd_soc_codec *codec,
2483 enum snd_soc_bias_level level)
2484{
2485 if (level == codec->dapm.bias_level)
2486 return 0;
2487
2488 switch (level) {
2489 case SND_SOC_BIAS_ON:
2490 break;
2491
2492 case SND_SOC_BIAS_PREPARE:
2493
2494 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2495 WM8962_VMID_SEL_MASK, 0x80);
2496
2497 wm8962_configure_bclk(codec);
2498 break;
2499
2500 case SND_SOC_BIAS_STANDBY:
2501
2502 snd_soc_update_bits(codec, WM8962_PWR_MGMT_1,
2503 WM8962_VMID_SEL_MASK, 0x100);
2504
2505 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF)
2506 msleep(100);
2507 break;
2508
2509 case SND_SOC_BIAS_OFF:
2510 break;
2511 }
2512
2513 codec->dapm.bias_level = level;
2514 return 0;
2515}
2516
2517static const struct {
2518 int rate;
2519 int reg;
2520} sr_vals[] = {
2521 { 48000, 0 },
2522 { 44100, 0 },
2523 { 32000, 1 },
2524 { 22050, 2 },
2525 { 24000, 2 },
2526 { 16000, 3 },
2527 { 11025, 4 },
2528 { 12000, 4 },
2529 { 8000, 5 },
2530 { 88200, 6 },
2531 { 96000, 6 },
2532};
2533
2534static int wm8962_hw_params(struct snd_pcm_substream *substream,
2535 struct snd_pcm_hw_params *params,
2536 struct snd_soc_dai *dai)
2537{
2538 struct snd_soc_codec *codec = dai->codec;
2539 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2540 int i;
2541 int aif0 = 0;
2542 int adctl3 = 0;
2543
2544 wm8962->bclk = snd_soc_params_to_bclk(params);
2545 if (params_channels(params) == 1)
2546 wm8962->bclk *= 2;
2547
2548 wm8962->lrclk = params_rate(params);
2549
2550 for (i = 0; i < ARRAY_SIZE(sr_vals); i++) {
2551 if (sr_vals[i].rate == wm8962->lrclk) {
2552 adctl3 |= sr_vals[i].reg;
2553 break;
2554 }
2555 }
2556 if (i == ARRAY_SIZE(sr_vals)) {
2557 dev_err(codec->dev, "Unsupported rate %dHz\n", wm8962->lrclk);
2558 return -EINVAL;
2559 }
2560
2561 if (wm8962->lrclk % 8000 == 0)
2562 adctl3 |= WM8962_SAMPLE_RATE_INT_MODE;
2563
2564 switch (params_format(params)) {
2565 case SNDRV_PCM_FORMAT_S16_LE:
2566 break;
2567 case SNDRV_PCM_FORMAT_S20_3LE:
2568 aif0 |= 0x4;
2569 break;
2570 case SNDRV_PCM_FORMAT_S24_LE:
2571 aif0 |= 0x8;
2572 break;
2573 case SNDRV_PCM_FORMAT_S32_LE:
2574 aif0 |= 0xc;
2575 break;
2576 default:
2577 return -EINVAL;
2578 }
2579
2580 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2581 WM8962_WL_MASK, aif0);
2582 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_3,
2583 WM8962_SAMPLE_RATE_INT_MODE |
2584 WM8962_SAMPLE_RATE_MASK, adctl3);
2585
2586 dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n",
2587 wm8962->bclk, wm8962->lrclk);
2588
2589 if (codec->dapm.bias_level == SND_SOC_BIAS_ON)
2590 wm8962_configure_bclk(codec);
2591
2592 return 0;
2593}
2594
2595static int wm8962_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
2596 unsigned int freq, int dir)
2597{
2598 struct snd_soc_codec *codec = dai->codec;
2599 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2600 int src;
2601
2602 switch (clk_id) {
2603 case WM8962_SYSCLK_MCLK:
2604 wm8962->sysclk = WM8962_SYSCLK_MCLK;
2605 src = 0;
2606 break;
2607 case WM8962_SYSCLK_FLL:
2608 wm8962->sysclk = WM8962_SYSCLK_FLL;
2609 src = 1 << WM8962_SYSCLK_SRC_SHIFT;
2610 break;
2611 default:
2612 return -EINVAL;
2613 }
2614
2615 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_SRC_MASK,
2616 src);
2617
2618 wm8962->sysclk_rate = freq;
2619
2620 wm8962_configure_bclk(codec);
2621
2622 return 0;
2623}
2624
2625static int wm8962_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
2626{
2627 struct snd_soc_codec *codec = dai->codec;
2628 int aif0 = 0;
2629
2630 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
2631 case SND_SOC_DAIFMT_DSP_B:
2632 aif0 |= WM8962_LRCLK_INV | 3;
2633 case SND_SOC_DAIFMT_DSP_A:
2634 aif0 |= 3;
2635
2636 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2637 case SND_SOC_DAIFMT_NB_NF:
2638 case SND_SOC_DAIFMT_IB_NF:
2639 break;
2640 default:
2641 return -EINVAL;
2642 }
2643 break;
2644
2645 case SND_SOC_DAIFMT_RIGHT_J:
2646 break;
2647 case SND_SOC_DAIFMT_LEFT_J:
2648 aif0 |= 1;
2649 break;
2650 case SND_SOC_DAIFMT_I2S:
2651 aif0 |= 2;
2652 break;
2653 default:
2654 return -EINVAL;
2655 }
2656
2657 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
2658 case SND_SOC_DAIFMT_NB_NF:
2659 break;
2660 case SND_SOC_DAIFMT_IB_NF:
2661 aif0 |= WM8962_BCLK_INV;
2662 break;
2663 case SND_SOC_DAIFMT_NB_IF:
2664 aif0 |= WM8962_LRCLK_INV;
2665 break;
2666 case SND_SOC_DAIFMT_IB_IF:
2667 aif0 |= WM8962_BCLK_INV | WM8962_LRCLK_INV;
2668 break;
2669 default:
2670 return -EINVAL;
2671 }
2672
2673 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
2674 case SND_SOC_DAIFMT_CBM_CFM:
2675 aif0 |= WM8962_MSTR;
2676 break;
2677 case SND_SOC_DAIFMT_CBS_CFS:
2678 break;
2679 default:
2680 return -EINVAL;
2681 }
2682
2683 snd_soc_update_bits(codec, WM8962_AUDIO_INTERFACE_0,
2684 WM8962_FMT_MASK | WM8962_BCLK_INV | WM8962_MSTR |
2685 WM8962_LRCLK_INV, aif0);
2686
2687 return 0;
2688}
2689
2690struct _fll_div {
2691 u16 fll_fratio;
2692 u16 fll_outdiv;
2693 u16 fll_refclk_div;
2694 u16 n;
2695 u16 theta;
2696 u16 lambda;
2697};
2698
2699
2700
2701#define FIXED_FLL_SIZE ((1 << 16) * 10)
2702
2703static struct {
2704 unsigned int min;
2705 unsigned int max;
2706 u16 fll_fratio;
2707 int ratio;
2708} fll_fratios[] = {
2709 { 0, 64000, 4, 16 },
2710 { 64000, 128000, 3, 8 },
2711 { 128000, 256000, 2, 4 },
2712 { 256000, 1000000, 1, 2 },
2713 { 1000000, 13500000, 0, 1 },
2714};
2715
2716static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
2717 unsigned int Fout)
2718{
2719 unsigned int target;
2720 unsigned int div;
2721 unsigned int fratio, gcd_fll;
2722 int i;
2723
2724
2725 div = 1;
2726 fll_div->fll_refclk_div = 0;
2727 while ((Fref / div) > 13500000) {
2728 div *= 2;
2729 fll_div->fll_refclk_div++;
2730
2731 if (div > 4) {
2732 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
2733 Fref);
2734 return -EINVAL;
2735 }
2736 }
2737
2738 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
2739
2740
2741 Fref /= div;
2742
2743
2744 div = 2;
2745 while (Fout * div < 90000000) {
2746 div++;
2747 if (div > 64) {
2748 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
2749 Fout);
2750 return -EINVAL;
2751 }
2752 }
2753 target = Fout * div;
2754 fll_div->fll_outdiv = div - 1;
2755
2756 pr_debug("FLL Fvco=%dHz\n", target);
2757
2758
2759 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
2760 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
2761 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
2762 fratio = fll_fratios[i].ratio;
2763 break;
2764 }
2765 }
2766 if (i == ARRAY_SIZE(fll_fratios)) {
2767 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
2768 return -EINVAL;
2769 }
2770
2771 fll_div->n = target / (fratio * Fref);
2772
2773 if (target % Fref == 0) {
2774 fll_div->theta = 0;
2775 fll_div->lambda = 0;
2776 } else {
2777 gcd_fll = gcd(target, fratio * Fref);
2778
2779 fll_div->theta = (target - (fll_div->n * fratio * Fref))
2780 / gcd_fll;
2781 fll_div->lambda = (fratio * Fref) / gcd_fll;
2782 }
2783
2784 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
2785 fll_div->n, fll_div->theta, fll_div->lambda);
2786 pr_debug("FLL_FRATIO=%x FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
2787 fll_div->fll_fratio, fll_div->fll_outdiv,
2788 fll_div->fll_refclk_div);
2789
2790 return 0;
2791}
2792
2793static int wm8962_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
2794 unsigned int Fref, unsigned int Fout)
2795{
2796 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
2797 struct _fll_div fll_div;
2798 unsigned long timeout;
2799 int ret;
2800 int fll1 = 0;
2801
2802
2803 if (source == wm8962->fll_src && Fref == wm8962->fll_fref &&
2804 Fout == wm8962->fll_fout)
2805 return 0;
2806
2807 if (Fout == 0) {
2808 dev_dbg(codec->dev, "FLL disabled\n");
2809
2810 wm8962->fll_fref = 0;
2811 wm8962->fll_fout = 0;
2812
2813 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2814 WM8962_FLL_ENA, 0);
2815
2816 pm_runtime_put(codec->dev);
2817
2818 return 0;
2819 }
2820
2821 ret = fll_factors(&fll_div, Fref, Fout);
2822 if (ret != 0)
2823 return ret;
2824
2825
2826 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2827
2828 switch (fll_id) {
2829 case WM8962_FLL_MCLK:
2830 case WM8962_FLL_BCLK:
2831 case WM8962_FLL_OSC:
2832 fll1 |= (fll_id - 1) << WM8962_FLL_REFCLK_SRC_SHIFT;
2833 break;
2834 case WM8962_FLL_INT:
2835 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2836 WM8962_FLL_OSC_ENA, WM8962_FLL_OSC_ENA);
2837 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_5,
2838 WM8962_FLL_FRC_NCO, WM8962_FLL_FRC_NCO);
2839 break;
2840 default:
2841 dev_err(codec->dev, "Unknown FLL source %d\n", ret);
2842 return -EINVAL;
2843 }
2844
2845 if (fll_div.theta || fll_div.lambda)
2846 fll1 |= WM8962_FLL_FRAC;
2847
2848
2849 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1, WM8962_FLL_ENA, 0);
2850
2851 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_2,
2852 WM8962_FLL_OUTDIV_MASK |
2853 WM8962_FLL_REFCLK_DIV_MASK,
2854 (fll_div.fll_outdiv << WM8962_FLL_OUTDIV_SHIFT) |
2855 (fll_div.fll_refclk_div));
2856
2857 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_3,
2858 WM8962_FLL_FRATIO_MASK, fll_div.fll_fratio);
2859
2860 snd_soc_write(codec, WM8962_FLL_CONTROL_6, fll_div.theta);
2861 snd_soc_write(codec, WM8962_FLL_CONTROL_7, fll_div.lambda);
2862 snd_soc_write(codec, WM8962_FLL_CONTROL_8, fll_div.n);
2863
2864 try_wait_for_completion(&wm8962->fll_lock);
2865
2866 pm_runtime_get_sync(codec->dev);
2867
2868 snd_soc_update_bits(codec, WM8962_FLL_CONTROL_1,
2869 WM8962_FLL_FRAC | WM8962_FLL_REFCLK_SRC_MASK |
2870 WM8962_FLL_ENA, fll1 | WM8962_FLL_ENA);
2871
2872 dev_dbg(codec->dev, "FLL configured for %dHz->%dHz\n", Fref, Fout);
2873
2874 ret = 0;
2875
2876
2877
2878
2879 if (wm8962->irq)
2880 timeout = msecs_to_jiffies(5);
2881 else
2882 timeout = msecs_to_jiffies(1);
2883
2884 timeout = wait_for_completion_timeout(&wm8962->fll_lock,
2885 timeout);
2886
2887 if (timeout == 0 && wm8962->irq) {
2888 dev_err(codec->dev, "FLL lock timed out");
2889 ret = -ETIMEDOUT;
2890 }
2891
2892 wm8962->fll_fref = Fref;
2893 wm8962->fll_fout = Fout;
2894 wm8962->fll_src = source;
2895
2896 return ret;
2897}
2898
2899static int wm8962_mute(struct snd_soc_dai *dai, int mute)
2900{
2901 struct snd_soc_codec *codec = dai->codec;
2902 int val;
2903
2904 if (mute)
2905 val = WM8962_DAC_MUTE;
2906 else
2907 val = 0;
2908
2909 return snd_soc_update_bits(codec, WM8962_ADC_DAC_CONTROL_1,
2910 WM8962_DAC_MUTE, val);
2911}
2912
2913#define WM8962_RATES SNDRV_PCM_RATE_8000_96000
2914
2915#define WM8962_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2916 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2917
2918static const struct snd_soc_dai_ops wm8962_dai_ops = {
2919 .hw_params = wm8962_hw_params,
2920 .set_sysclk = wm8962_set_dai_sysclk,
2921 .set_fmt = wm8962_set_dai_fmt,
2922 .digital_mute = wm8962_mute,
2923};
2924
2925static struct snd_soc_dai_driver wm8962_dai = {
2926 .name = "wm8962",
2927 .playback = {
2928 .stream_name = "Playback",
2929 .channels_min = 1,
2930 .channels_max = 2,
2931 .rates = WM8962_RATES,
2932 .formats = WM8962_FORMATS,
2933 },
2934 .capture = {
2935 .stream_name = "Capture",
2936 .channels_min = 1,
2937 .channels_max = 2,
2938 .rates = WM8962_RATES,
2939 .formats = WM8962_FORMATS,
2940 },
2941 .ops = &wm8962_dai_ops,
2942 .symmetric_rates = 1,
2943};
2944
2945static void wm8962_mic_work(struct work_struct *work)
2946{
2947 struct wm8962_priv *wm8962 = container_of(work,
2948 struct wm8962_priv,
2949 mic_work.work);
2950 struct snd_soc_codec *codec = wm8962->codec;
2951 int status = 0;
2952 int irq_pol = 0;
2953 int reg;
2954
2955 reg = snd_soc_read(codec, WM8962_ADDITIONAL_CONTROL_4);
2956
2957 if (reg & WM8962_MICDET_STS) {
2958 status |= SND_JACK_MICROPHONE;
2959 irq_pol |= WM8962_MICD_IRQ_POL;
2960 }
2961
2962 if (reg & WM8962_MICSHORT_STS) {
2963 status |= SND_JACK_BTN_0;
2964 irq_pol |= WM8962_MICSCD_IRQ_POL;
2965 }
2966
2967 snd_soc_jack_report(wm8962->jack, status,
2968 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
2969
2970 snd_soc_update_bits(codec, WM8962_MICINT_SOURCE_POL,
2971 WM8962_MICSCD_IRQ_POL |
2972 WM8962_MICD_IRQ_POL, irq_pol);
2973}
2974
2975static irqreturn_t wm8962_irq(int irq, void *data)
2976{
2977 struct device *dev = data;
2978 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
2979 unsigned int mask;
2980 unsigned int active;
2981 int reg, ret;
2982
2983 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2_MASK,
2984 &mask);
2985 if (ret != 0) {
2986 dev_err(dev, "Failed to read interrupt mask: %d\n",
2987 ret);
2988 return IRQ_NONE;
2989 }
2990
2991 ret = regmap_read(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, &active);
2992 if (ret != 0) {
2993 dev_err(dev, "Failed to read interrupt: %d\n", ret);
2994 return IRQ_NONE;
2995 }
2996
2997 active &= ~mask;
2998
2999 if (!active)
3000 return IRQ_NONE;
3001
3002
3003 ret = regmap_write(wm8962->regmap, WM8962_INTERRUPT_STATUS_2, active);
3004 if (ret != 0)
3005 dev_warn(dev, "Failed to ack interrupt: %d\n", ret);
3006
3007 if (active & WM8962_FLL_LOCK_EINT) {
3008 dev_dbg(dev, "FLL locked\n");
3009 complete(&wm8962->fll_lock);
3010 }
3011
3012 if (active & WM8962_FIFOS_ERR_EINT)
3013 dev_err(dev, "FIFO error\n");
3014
3015 if (active & WM8962_TEMP_SHUT_EINT) {
3016 dev_crit(dev, "Thermal shutdown\n");
3017
3018 ret = regmap_read(wm8962->regmap,
3019 WM8962_THERMAL_SHUTDOWN_STATUS, ®);
3020 if (ret != 0) {
3021 dev_warn(dev, "Failed to read thermal status: %d\n",
3022 ret);
3023 reg = 0;
3024 }
3025
3026 if (reg & WM8962_TEMP_ERR_HP)
3027 dev_crit(dev, "Headphone thermal error\n");
3028 if (reg & WM8962_TEMP_WARN_HP)
3029 dev_crit(dev, "Headphone thermal warning\n");
3030 if (reg & WM8962_TEMP_ERR_SPK)
3031 dev_crit(dev, "Speaker thermal error\n");
3032 if (reg & WM8962_TEMP_WARN_SPK)
3033 dev_crit(dev, "Speaker thermal warning\n");
3034 }
3035
3036 if (active & (WM8962_MICSCD_EINT | WM8962_MICD_EINT)) {
3037 dev_dbg(dev, "Microphone event detected\n");
3038
3039#ifndef CONFIG_SND_SOC_WM8962_MODULE
3040 trace_snd_soc_jack_irq(dev_name(dev));
3041#endif
3042
3043 pm_wakeup_event(dev, 300);
3044
3045 schedule_delayed_work(&wm8962->mic_work,
3046 msecs_to_jiffies(250));
3047 }
3048
3049 return IRQ_HANDLED;
3050}
3051
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065int wm8962_mic_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
3066{
3067 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3068 int irq_mask, enable;
3069
3070 wm8962->jack = jack;
3071 if (jack) {
3072 irq_mask = 0;
3073 enable = WM8962_MICDET_ENA;
3074 } else {
3075 irq_mask = WM8962_MICD_EINT | WM8962_MICSCD_EINT;
3076 enable = 0;
3077 }
3078
3079 snd_soc_update_bits(codec, WM8962_INTERRUPT_STATUS_2_MASK,
3080 WM8962_MICD_EINT | WM8962_MICSCD_EINT, irq_mask);
3081 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3082 WM8962_MICDET_ENA, enable);
3083
3084
3085 snd_soc_jack_report(wm8962->jack, 0,
3086 SND_JACK_MICROPHONE | SND_JACK_BTN_0);
3087
3088 if (jack) {
3089 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
3090 snd_soc_dapm_force_enable_pin(&codec->dapm, "MICBIAS");
3091 } else {
3092 snd_soc_dapm_disable_pin(&codec->dapm, "SYSCLK");
3093 snd_soc_dapm_disable_pin(&codec->dapm, "MICBIAS");
3094 }
3095
3096 return 0;
3097}
3098EXPORT_SYMBOL_GPL(wm8962_mic_detect);
3099
3100#if defined(CONFIG_INPUT) || defined(CONFIG_INPUT_MODULE)
3101static int beep_rates[] = {
3102 500, 1000, 2000, 4000,
3103};
3104
3105static void wm8962_beep_work(struct work_struct *work)
3106{
3107 struct wm8962_priv *wm8962 =
3108 container_of(work, struct wm8962_priv, beep_work);
3109 struct snd_soc_codec *codec = wm8962->codec;
3110 struct snd_soc_dapm_context *dapm = &codec->dapm;
3111 int i;
3112 int reg = 0;
3113 int best = 0;
3114
3115 if (wm8962->beep_rate) {
3116 for (i = 0; i < ARRAY_SIZE(beep_rates); i++) {
3117 if (abs(wm8962->beep_rate - beep_rates[i]) <
3118 abs(wm8962->beep_rate - beep_rates[best]))
3119 best = i;
3120 }
3121
3122 dev_dbg(codec->dev, "Set beep rate %dHz for requested %dHz\n",
3123 beep_rates[best], wm8962->beep_rate);
3124
3125 reg = WM8962_BEEP_ENA | (best << WM8962_BEEP_RATE_SHIFT);
3126
3127 snd_soc_dapm_enable_pin(dapm, "Beep");
3128 } else {
3129 dev_dbg(codec->dev, "Disabling beep\n");
3130 snd_soc_dapm_disable_pin(dapm, "Beep");
3131 }
3132
3133 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1,
3134 WM8962_BEEP_ENA | WM8962_BEEP_RATE_MASK, reg);
3135
3136 snd_soc_dapm_sync(dapm);
3137}
3138
3139
3140
3141
3142static int wm8962_beep_event(struct input_dev *dev, unsigned int type,
3143 unsigned int code, int hz)
3144{
3145 struct snd_soc_codec *codec = input_get_drvdata(dev);
3146 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3147
3148 dev_dbg(codec->dev, "Beep event %x %x\n", code, hz);
3149
3150 switch (code) {
3151 case SND_BELL:
3152 if (hz)
3153 hz = 1000;
3154 case SND_TONE:
3155 break;
3156 default:
3157 return -1;
3158 }
3159
3160
3161 wm8962->beep_rate = hz;
3162 schedule_work(&wm8962->beep_work);
3163 return 0;
3164}
3165
3166static ssize_t wm8962_beep_set(struct device *dev,
3167 struct device_attribute *attr,
3168 const char *buf, size_t count)
3169{
3170 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3171 long int time;
3172 int ret;
3173
3174 ret = strict_strtol(buf, 10, &time);
3175 if (ret != 0)
3176 return ret;
3177
3178 input_event(wm8962->beep, EV_SND, SND_TONE, time);
3179
3180 return count;
3181}
3182
3183static DEVICE_ATTR(beep, 0200, NULL, wm8962_beep_set);
3184
3185static void wm8962_init_beep(struct snd_soc_codec *codec)
3186{
3187 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3188 int ret;
3189
3190 wm8962->beep = devm_input_allocate_device(codec->dev);
3191 if (!wm8962->beep) {
3192 dev_err(codec->dev, "Failed to allocate beep device\n");
3193 return;
3194 }
3195
3196 INIT_WORK(&wm8962->beep_work, wm8962_beep_work);
3197 wm8962->beep_rate = 0;
3198
3199 wm8962->beep->name = "WM8962 Beep Generator";
3200 wm8962->beep->phys = dev_name(codec->dev);
3201 wm8962->beep->id.bustype = BUS_I2C;
3202
3203 wm8962->beep->evbit[0] = BIT_MASK(EV_SND);
3204 wm8962->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
3205 wm8962->beep->event = wm8962_beep_event;
3206 wm8962->beep->dev.parent = codec->dev;
3207 input_set_drvdata(wm8962->beep, codec);
3208
3209 ret = input_register_device(wm8962->beep);
3210 if (ret != 0) {
3211 wm8962->beep = NULL;
3212 dev_err(codec->dev, "Failed to register beep device\n");
3213 }
3214
3215 ret = device_create_file(codec->dev, &dev_attr_beep);
3216 if (ret != 0) {
3217 dev_err(codec->dev, "Failed to create keyclick file: %d\n",
3218 ret);
3219 }
3220}
3221
3222static void wm8962_free_beep(struct snd_soc_codec *codec)
3223{
3224 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3225
3226 device_remove_file(codec->dev, &dev_attr_beep);
3227 cancel_work_sync(&wm8962->beep_work);
3228 wm8962->beep = NULL;
3229
3230 snd_soc_update_bits(codec, WM8962_BEEP_GENERATOR_1, WM8962_BEEP_ENA,0);
3231}
3232#else
3233static void wm8962_init_beep(struct snd_soc_codec *codec)
3234{
3235}
3236
3237static void wm8962_free_beep(struct snd_soc_codec *codec)
3238{
3239}
3240#endif
3241
3242static void wm8962_set_gpio_mode(struct snd_soc_codec *codec, int gpio)
3243{
3244 int mask = 0;
3245 int val = 0;
3246
3247
3248
3249 switch (gpio) {
3250 case 2:
3251 mask = WM8962_CLKOUT2_SEL_MASK;
3252 val = 1 << WM8962_CLKOUT2_SEL_SHIFT;
3253 break;
3254 case 3:
3255 mask = WM8962_CLKOUT3_SEL_MASK;
3256 val = 1 << WM8962_CLKOUT3_SEL_SHIFT;
3257 break;
3258 default:
3259 break;
3260 }
3261
3262 if (mask)
3263 snd_soc_update_bits(codec, WM8962_ANALOGUE_CLOCKING1,
3264 mask, val);
3265}
3266
3267#ifdef CONFIG_GPIOLIB
3268static inline struct wm8962_priv *gpio_to_wm8962(struct gpio_chip *chip)
3269{
3270 return container_of(chip, struct wm8962_priv, gpio_chip);
3271}
3272
3273static int wm8962_gpio_request(struct gpio_chip *chip, unsigned offset)
3274{
3275 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3276 struct snd_soc_codec *codec = wm8962->codec;
3277
3278
3279
3280
3281
3282 switch (offset + 1) {
3283 case 2:
3284 case 3:
3285 case 5:
3286 case 6:
3287 break;
3288 default:
3289 return -EINVAL;
3290 }
3291
3292 wm8962_set_gpio_mode(codec, offset + 1);
3293
3294 return 0;
3295}
3296
3297static void wm8962_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
3298{
3299 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3300 struct snd_soc_codec *codec = wm8962->codec;
3301
3302 snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3303 WM8962_GP2_LVL, !!value << WM8962_GP2_LVL_SHIFT);
3304}
3305
3306static int wm8962_gpio_direction_out(struct gpio_chip *chip,
3307 unsigned offset, int value)
3308{
3309 struct wm8962_priv *wm8962 = gpio_to_wm8962(chip);
3310 struct snd_soc_codec *codec = wm8962->codec;
3311 int ret, val;
3312
3313
3314 val = (1 << WM8962_GP2_FN_SHIFT) | (value << WM8962_GP2_LVL_SHIFT);
3315
3316 ret = snd_soc_update_bits(codec, WM8962_GPIO_BASE + offset,
3317 WM8962_GP2_FN_MASK | WM8962_GP2_LVL, val);
3318 if (ret < 0)
3319 return ret;
3320
3321 return 0;
3322}
3323
3324static struct gpio_chip wm8962_template_chip = {
3325 .label = "wm8962",
3326 .owner = THIS_MODULE,
3327 .request = wm8962_gpio_request,
3328 .direction_output = wm8962_gpio_direction_out,
3329 .set = wm8962_gpio_set,
3330 .can_sleep = 1,
3331};
3332
3333static void wm8962_init_gpio(struct snd_soc_codec *codec)
3334{
3335 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3336 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3337 int ret;
3338
3339 wm8962->gpio_chip = wm8962_template_chip;
3340 wm8962->gpio_chip.ngpio = WM8962_MAX_GPIO;
3341 wm8962->gpio_chip.dev = codec->dev;
3342
3343 if (pdata && pdata->gpio_base)
3344 wm8962->gpio_chip.base = pdata->gpio_base;
3345 else
3346 wm8962->gpio_chip.base = -1;
3347
3348 ret = gpiochip_add(&wm8962->gpio_chip);
3349 if (ret != 0)
3350 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
3351}
3352
3353static void wm8962_free_gpio(struct snd_soc_codec *codec)
3354{
3355 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3356 int ret;
3357
3358 ret = gpiochip_remove(&wm8962->gpio_chip);
3359 if (ret != 0)
3360 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
3361}
3362#else
3363static void wm8962_init_gpio(struct snd_soc_codec *codec)
3364{
3365}
3366
3367static void wm8962_free_gpio(struct snd_soc_codec *codec)
3368{
3369}
3370#endif
3371
3372static int wm8962_probe(struct snd_soc_codec *codec)
3373{
3374 int ret;
3375 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3376 struct wm8962_pdata *pdata = dev_get_platdata(codec->dev);
3377 u16 *reg_cache = codec->reg_cache;
3378 int i, trigger, irq_pol;
3379 bool dmicclk, dmicdat;
3380
3381 wm8962->codec = codec;
3382 codec->control_data = wm8962->regmap;
3383
3384 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_REGMAP);
3385 if (ret != 0) {
3386 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
3387 return ret;
3388 }
3389
3390 wm8962->disable_nb[0].notifier_call = wm8962_regulator_event_0;
3391 wm8962->disable_nb[1].notifier_call = wm8962_regulator_event_1;
3392 wm8962->disable_nb[2].notifier_call = wm8962_regulator_event_2;
3393 wm8962->disable_nb[3].notifier_call = wm8962_regulator_event_3;
3394 wm8962->disable_nb[4].notifier_call = wm8962_regulator_event_4;
3395 wm8962->disable_nb[5].notifier_call = wm8962_regulator_event_5;
3396 wm8962->disable_nb[6].notifier_call = wm8962_regulator_event_6;
3397 wm8962->disable_nb[7].notifier_call = wm8962_regulator_event_7;
3398
3399
3400 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++) {
3401 ret = regulator_register_notifier(wm8962->supplies[i].consumer,
3402 &wm8962->disable_nb[i]);
3403 if (ret != 0) {
3404 dev_err(codec->dev,
3405 "Failed to register regulator notifier: %d\n",
3406 ret);
3407 }
3408 }
3409
3410
3411
3412
3413 snd_soc_update_bits(codec, WM8962_CLOCKING2, WM8962_SYSCLK_ENA, 0);
3414
3415
3416 snd_soc_update_bits(codec, WM8962_CLOCKING2,
3417 WM8962_CLKREG_OVD, WM8962_CLKREG_OVD);
3418
3419
3420 snd_soc_update_bits(codec, WM8962_PLL2,
3421 WM8962_OSC_ENA | WM8962_PLL2_ENA | WM8962_PLL3_ENA,
3422 0);
3423
3424 if (pdata) {
3425
3426 for (i = 0; i < ARRAY_SIZE(pdata->gpio_init); i++)
3427 if (pdata->gpio_init[i]) {
3428 wm8962_set_gpio_mode(codec, i + 1);
3429 snd_soc_write(codec, 0x200 + i,
3430 pdata->gpio_init[i] & 0xffff);
3431 }
3432
3433
3434 if (pdata->spk_mono)
3435 reg_cache[WM8962_CLASS_D_CONTROL_2]
3436 |= WM8962_SPK_MONO;
3437
3438
3439
3440 if (pdata->mic_cfg)
3441 snd_soc_update_bits(codec, WM8962_ADDITIONAL_CONTROL_4,
3442 WM8962_MICDET_ENA |
3443 WM8962_MICDET_THR_MASK |
3444 WM8962_MICSHORT_THR_MASK |
3445 WM8962_MICBIAS_LVL,
3446 pdata->mic_cfg);
3447 }
3448
3449
3450 snd_soc_update_bits(codec, WM8962_LEFT_INPUT_VOLUME,
3451 WM8962_IN_VU, WM8962_IN_VU);
3452 snd_soc_update_bits(codec, WM8962_RIGHT_INPUT_VOLUME,
3453 WM8962_IN_VU, WM8962_IN_VU);
3454 snd_soc_update_bits(codec, WM8962_LEFT_ADC_VOLUME,
3455 WM8962_ADC_VU, WM8962_ADC_VU);
3456 snd_soc_update_bits(codec, WM8962_RIGHT_ADC_VOLUME,
3457 WM8962_ADC_VU, WM8962_ADC_VU);
3458 snd_soc_update_bits(codec, WM8962_LEFT_DAC_VOLUME,
3459 WM8962_DAC_VU, WM8962_DAC_VU);
3460 snd_soc_update_bits(codec, WM8962_RIGHT_DAC_VOLUME,
3461 WM8962_DAC_VU, WM8962_DAC_VU);
3462 snd_soc_update_bits(codec, WM8962_SPKOUTL_VOLUME,
3463 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3464 snd_soc_update_bits(codec, WM8962_SPKOUTR_VOLUME,
3465 WM8962_SPKOUT_VU, WM8962_SPKOUT_VU);
3466 snd_soc_update_bits(codec, WM8962_HPOUTL_VOLUME,
3467 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3468 snd_soc_update_bits(codec, WM8962_HPOUTR_VOLUME,
3469 WM8962_HPOUT_VU, WM8962_HPOUT_VU);
3470
3471
3472 snd_soc_update_bits(codec, WM8962_EQ1, WM8962_EQ_SHARED_COEFF, 0);
3473
3474
3475 snd_soc_update_bits(codec, WM8962_IRQ_DEBOUNCE,
3476 WM8962_FLL_LOCK_DB | WM8962_PLL3_LOCK_DB |
3477 WM8962_PLL2_LOCK_DB | WM8962_TEMP_SHUT_DB,
3478 0);
3479
3480 wm8962_add_widgets(codec);
3481
3482
3483 dmicclk = false;
3484 dmicdat = false;
3485 for (i = 0; i < WM8962_MAX_GPIO; i++) {
3486 switch (snd_soc_read(codec, WM8962_GPIO_BASE + i)
3487 & WM8962_GP2_FN_MASK) {
3488 case WM8962_GPIO_FN_DMICCLK:
3489 dmicclk = true;
3490 break;
3491 case WM8962_GPIO_FN_DMICDAT:
3492 dmicdat = true;
3493 break;
3494 default:
3495 break;
3496 }
3497 }
3498 if (!dmicclk || !dmicdat) {
3499 dev_dbg(codec->dev, "DMIC not in use, disabling\n");
3500 snd_soc_dapm_nc_pin(&codec->dapm, "DMICDAT");
3501 }
3502 if (dmicclk != dmicdat)
3503 dev_warn(codec->dev, "DMIC GPIOs partially configured\n");
3504
3505 wm8962_init_beep(codec);
3506 wm8962_init_gpio(codec);
3507
3508 if (wm8962->irq) {
3509 if (pdata && pdata->irq_active_low) {
3510 trigger = IRQF_TRIGGER_LOW;
3511 irq_pol = WM8962_IRQ_POL;
3512 } else {
3513 trigger = IRQF_TRIGGER_HIGH;
3514 irq_pol = 0;
3515 }
3516
3517 snd_soc_update_bits(codec, WM8962_INTERRUPT_CONTROL,
3518 WM8962_IRQ_POL, irq_pol);
3519
3520 ret = request_threaded_irq(wm8962->irq, NULL, wm8962_irq,
3521 trigger | IRQF_ONESHOT,
3522 "wm8962", codec->dev);
3523 if (ret != 0) {
3524 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
3525 wm8962->irq, ret);
3526 wm8962->irq = 0;
3527
3528 } else {
3529
3530 snd_soc_update_bits(codec,
3531 WM8962_INTERRUPT_STATUS_2_MASK,
3532 WM8962_FLL_LOCK_EINT |
3533 WM8962_TEMP_SHUT_EINT |
3534 WM8962_FIFOS_ERR_EINT, 0);
3535 }
3536 }
3537
3538 return 0;
3539}
3540
3541static int wm8962_remove(struct snd_soc_codec *codec)
3542{
3543 struct wm8962_priv *wm8962 = snd_soc_codec_get_drvdata(codec);
3544 int i;
3545
3546 if (wm8962->irq)
3547 free_irq(wm8962->irq, codec);
3548
3549 cancel_delayed_work_sync(&wm8962->mic_work);
3550
3551 wm8962_free_gpio(codec);
3552 wm8962_free_beep(codec);
3553 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3554 regulator_unregister_notifier(wm8962->supplies[i].consumer,
3555 &wm8962->disable_nb[i]);
3556
3557 return 0;
3558}
3559
3560static struct snd_soc_codec_driver soc_codec_dev_wm8962 = {
3561 .probe = wm8962_probe,
3562 .remove = wm8962_remove,
3563 .set_bias_level = wm8962_set_bias_level,
3564 .set_pll = wm8962_set_fll,
3565 .idle_bias_off = true,
3566};
3567
3568
3569static const struct reg_default wm8962_dc_measure[] = {
3570 { 0xfd, 0x1 },
3571 { 0xcc, 0x40 },
3572 { 0xfd, 0 },
3573};
3574
3575static const struct regmap_config wm8962_regmap = {
3576 .reg_bits = 16,
3577 .val_bits = 16,
3578
3579 .max_register = WM8962_MAX_REGISTER,
3580 .reg_defaults = wm8962_reg,
3581 .num_reg_defaults = ARRAY_SIZE(wm8962_reg),
3582 .volatile_reg = wm8962_volatile_register,
3583 .readable_reg = wm8962_readable_register,
3584 .cache_type = REGCACHE_RBTREE,
3585};
3586
3587static int wm8962_i2c_probe(struct i2c_client *i2c,
3588 const struct i2c_device_id *id)
3589{
3590 struct wm8962_pdata *pdata = dev_get_platdata(&i2c->dev);
3591 struct wm8962_priv *wm8962;
3592 unsigned int reg;
3593 int ret, i;
3594
3595 wm8962 = devm_kzalloc(&i2c->dev, sizeof(struct wm8962_priv),
3596 GFP_KERNEL);
3597 if (wm8962 == NULL)
3598 return -ENOMEM;
3599
3600 i2c_set_clientdata(i2c, wm8962);
3601
3602 INIT_DELAYED_WORK(&wm8962->mic_work, wm8962_mic_work);
3603 init_completion(&wm8962->fll_lock);
3604 wm8962->irq = i2c->irq;
3605
3606 for (i = 0; i < ARRAY_SIZE(wm8962->supplies); i++)
3607 wm8962->supplies[i].supply = wm8962_supply_names[i];
3608
3609 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm8962->supplies),
3610 wm8962->supplies);
3611 if (ret != 0) {
3612 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
3613 goto err;
3614 }
3615
3616 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3617 wm8962->supplies);
3618 if (ret != 0) {
3619 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
3620 return ret;
3621 }
3622
3623 wm8962->regmap = devm_regmap_init_i2c(i2c, &wm8962_regmap);
3624 if (IS_ERR(wm8962->regmap)) {
3625 ret = PTR_ERR(wm8962->regmap);
3626 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
3627 goto err_enable;
3628 }
3629
3630
3631
3632
3633
3634
3635 regcache_cache_bypass(wm8962->regmap, true);
3636
3637 ret = regmap_read(wm8962->regmap, WM8962_SOFTWARE_RESET, ®);
3638 if (ret < 0) {
3639 dev_err(&i2c->dev, "Failed to read ID register\n");
3640 goto err_enable;
3641 }
3642 if (reg != 0x6243) {
3643 dev_err(&i2c->dev,
3644 "Device is not a WM8962, ID %x != 0x6243\n", reg);
3645 ret = -EINVAL;
3646 goto err_enable;
3647 }
3648
3649 ret = regmap_read(wm8962->regmap, WM8962_RIGHT_INPUT_VOLUME, ®);
3650 if (ret < 0) {
3651 dev_err(&i2c->dev, "Failed to read device revision: %d\n",
3652 ret);
3653 goto err_enable;
3654 }
3655
3656 dev_info(&i2c->dev, "customer id %x revision %c\n",
3657 (reg & WM8962_CUST_ID_MASK) >> WM8962_CUST_ID_SHIFT,
3658 ((reg & WM8962_CHIP_REV_MASK) >> WM8962_CHIP_REV_SHIFT)
3659 + 'A');
3660
3661 regcache_cache_bypass(wm8962->regmap, false);
3662
3663 ret = wm8962_reset(wm8962);
3664 if (ret < 0) {
3665 dev_err(&i2c->dev, "Failed to issue reset\n");
3666 goto err_enable;
3667 }
3668
3669 if (pdata && pdata->in4_dc_measure) {
3670 ret = regmap_register_patch(wm8962->regmap,
3671 wm8962_dc_measure,
3672 ARRAY_SIZE(wm8962_dc_measure));
3673 if (ret != 0)
3674 dev_err(&i2c->dev,
3675 "Failed to configure for DC mesurement: %d\n",
3676 ret);
3677 }
3678
3679 pm_runtime_enable(&i2c->dev);
3680 pm_request_idle(&i2c->dev);
3681
3682 ret = snd_soc_register_codec(&i2c->dev,
3683 &soc_codec_dev_wm8962, &wm8962_dai, 1);
3684 if (ret < 0)
3685 goto err_enable;
3686
3687
3688 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3689
3690 return 0;
3691
3692err_enable:
3693 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies), wm8962->supplies);
3694err:
3695 return ret;
3696}
3697
3698static int wm8962_i2c_remove(struct i2c_client *client)
3699{
3700 snd_soc_unregister_codec(&client->dev);
3701 return 0;
3702}
3703
3704#ifdef CONFIG_PM_RUNTIME
3705static int wm8962_runtime_resume(struct device *dev)
3706{
3707 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3708 int ret;
3709
3710 ret = regulator_bulk_enable(ARRAY_SIZE(wm8962->supplies),
3711 wm8962->supplies);
3712 if (ret != 0) {
3713 dev_err(dev,
3714 "Failed to enable supplies: %d\n", ret);
3715 return ret;
3716 }
3717
3718 regcache_cache_only(wm8962->regmap, false);
3719
3720 wm8962_reset(wm8962);
3721
3722 regcache_sync(wm8962->regmap);
3723
3724 return 0;
3725}
3726
3727static int wm8962_runtime_suspend(struct device *dev)
3728{
3729 struct wm8962_priv *wm8962 = dev_get_drvdata(dev);
3730
3731 regmap_update_bits(wm8962->regmap, WM8962_PWR_MGMT_1,
3732 WM8962_VMID_SEL_MASK | WM8962_BIAS_ENA, 0);
3733
3734 regmap_update_bits(wm8962->regmap, WM8962_ANTI_POP,
3735 WM8962_STARTUP_BIAS_ENA |
3736 WM8962_VMID_BUF_ENA, 0);
3737
3738 regcache_cache_only(wm8962->regmap, true);
3739
3740 regulator_bulk_disable(ARRAY_SIZE(wm8962->supplies),
3741 wm8962->supplies);
3742
3743 return 0;
3744}
3745#endif
3746
3747static struct dev_pm_ops wm8962_pm = {
3748 SET_RUNTIME_PM_OPS(wm8962_runtime_suspend, wm8962_runtime_resume, NULL)
3749};
3750
3751static const struct i2c_device_id wm8962_i2c_id[] = {
3752 { "wm8962", 0 },
3753 { }
3754};
3755MODULE_DEVICE_TABLE(i2c, wm8962_i2c_id);
3756
3757static const struct of_device_id wm8962_of_match[] = {
3758 { .compatible = "wlf,wm8962", },
3759 { }
3760};
3761MODULE_DEVICE_TABLE(of, wm8962_of_match);
3762
3763static struct i2c_driver wm8962_i2c_driver = {
3764 .driver = {
3765 .name = "wm8962",
3766 .owner = THIS_MODULE,
3767 .of_match_table = wm8962_of_match,
3768 .pm = &wm8962_pm,
3769 },
3770 .probe = wm8962_i2c_probe,
3771 .remove = wm8962_i2c_remove,
3772 .id_table = wm8962_i2c_id,
3773};
3774
3775module_i2c_driver(wm8962_i2c_driver);
3776
3777MODULE_DESCRIPTION("ASoC WM8962 driver");
3778MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
3779MODULE_LICENSE("GPL");
3780
