linux/sound/soc/codecs/sgtl5000.c
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   1/*
   2 * sgtl5000.c  --  SGTL5000 ALSA SoC Audio driver
   3 *
   4 * Copyright 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#include <linux/module.h>
  12#include <linux/moduleparam.h>
  13#include <linux/init.h>
  14#include <linux/delay.h>
  15#include <linux/slab.h>
  16#include <linux/pm.h>
  17#include <linux/i2c.h>
  18#include <linux/clk.h>
  19#include <linux/log2.h>
  20#include <linux/regmap.h>
  21#include <linux/regulator/driver.h>
  22#include <linux/regulator/machine.h>
  23#include <linux/regulator/consumer.h>
  24#include <linux/of_device.h>
  25#include <sound/core.h>
  26#include <sound/tlv.h>
  27#include <sound/pcm.h>
  28#include <sound/pcm_params.h>
  29#include <sound/soc.h>
  30#include <sound/soc-dapm.h>
  31#include <sound/initval.h>
  32
  33#include "sgtl5000.h"
  34
  35#define SGTL5000_DAP_REG_OFFSET 0x0100
  36#define SGTL5000_MAX_REG_OFFSET 0x013A
  37
  38/* default value of sgtl5000 registers */
  39static const struct reg_default sgtl5000_reg_defaults[] = {
  40        { SGTL5000_CHIP_DIG_POWER,              0x0000 },
  41        { SGTL5000_CHIP_CLK_CTRL,               0x0008 },
  42        { SGTL5000_CHIP_I2S_CTRL,               0x0010 },
  43        { SGTL5000_CHIP_SSS_CTRL,               0x0010 },
  44        { SGTL5000_CHIP_ADCDAC_CTRL,            0x020c },
  45        { SGTL5000_CHIP_DAC_VOL,                0x3c3c },
  46        { SGTL5000_CHIP_PAD_STRENGTH,           0x015f },
  47        { SGTL5000_CHIP_ANA_ADC_CTRL,           0x0000 },
  48        { SGTL5000_CHIP_ANA_HP_CTRL,            0x1818 },
  49        { SGTL5000_CHIP_ANA_CTRL,               0x0111 },
  50        { SGTL5000_CHIP_LINREG_CTRL,            0x0000 },
  51        { SGTL5000_CHIP_REF_CTRL,               0x0000 },
  52        { SGTL5000_CHIP_MIC_CTRL,               0x0000 },
  53        { SGTL5000_CHIP_LINE_OUT_CTRL,          0x0000 },
  54        { SGTL5000_CHIP_LINE_OUT_VOL,           0x0404 },
  55        { SGTL5000_CHIP_ANA_POWER,              0x7060 },
  56        { SGTL5000_CHIP_PLL_CTRL,               0x5000 },
  57        { SGTL5000_CHIP_CLK_TOP_CTRL,           0x0000 },
  58        { SGTL5000_CHIP_ANA_STATUS,             0x0000 },
  59        { SGTL5000_CHIP_SHORT_CTRL,             0x0000 },
  60        { SGTL5000_CHIP_ANA_TEST2,              0x0000 },
  61        { SGTL5000_DAP_CTRL,                    0x0000 },
  62        { SGTL5000_DAP_PEQ,                     0x0000 },
  63        { SGTL5000_DAP_BASS_ENHANCE,            0x0040 },
  64        { SGTL5000_DAP_BASS_ENHANCE_CTRL,       0x051f },
  65        { SGTL5000_DAP_AUDIO_EQ,                0x0000 },
  66        { SGTL5000_DAP_SURROUND,                0x0040 },
  67        { SGTL5000_DAP_EQ_BASS_BAND0,           0x002f },
  68        { SGTL5000_DAP_EQ_BASS_BAND1,           0x002f },
  69        { SGTL5000_DAP_EQ_BASS_BAND2,           0x002f },
  70        { SGTL5000_DAP_EQ_BASS_BAND3,           0x002f },
  71        { SGTL5000_DAP_EQ_BASS_BAND4,           0x002f },
  72        { SGTL5000_DAP_MAIN_CHAN,               0x8000 },
  73        { SGTL5000_DAP_MIX_CHAN,                0x0000 },
  74        { SGTL5000_DAP_AVC_CTRL,                0x0510 },
  75        { SGTL5000_DAP_AVC_THRESHOLD,           0x1473 },
  76        { SGTL5000_DAP_AVC_ATTACK,              0x0028 },
  77        { SGTL5000_DAP_AVC_DECAY,               0x0050 },
  78};
  79
  80/* regulator supplies for sgtl5000, VDDD is an optional external supply */
  81enum sgtl5000_regulator_supplies {
  82        VDDA,
  83        VDDIO,
  84        VDDD,
  85        SGTL5000_SUPPLY_NUM
  86};
  87
  88/* vddd is optional supply */
  89static const char *supply_names[SGTL5000_SUPPLY_NUM] = {
  90        "VDDA",
  91        "VDDIO",
  92        "VDDD"
  93};
  94
  95#define LDO_CONSUMER_NAME       "VDDD_LDO"
  96#define LDO_VOLTAGE             1200000
  97
  98static struct regulator_consumer_supply ldo_consumer[] = {
  99        REGULATOR_SUPPLY(LDO_CONSUMER_NAME, NULL),
 100};
 101
 102static struct regulator_init_data ldo_init_data = {
 103        .constraints = {
 104                .min_uV                 = 1200000,
 105                .max_uV                 = 1200000,
 106                .valid_modes_mask       = REGULATOR_MODE_NORMAL,
 107                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
 108        },
 109        .num_consumer_supplies = 1,
 110        .consumer_supplies = &ldo_consumer[0],
 111};
 112
 113/*
 114 * sgtl5000 internal ldo regulator,
 115 * enabled when VDDD not provided
 116 */
 117struct ldo_regulator {
 118        struct regulator_desc desc;
 119        struct regulator_dev *dev;
 120        int voltage;
 121        void *codec_data;
 122        bool enabled;
 123};
 124
 125enum sgtl5000_micbias_resistor {
 126        SGTL5000_MICBIAS_OFF = 0,
 127        SGTL5000_MICBIAS_2K = 2,
 128        SGTL5000_MICBIAS_4K = 4,
 129        SGTL5000_MICBIAS_8K = 8,
 130};
 131
 132/* sgtl5000 private structure in codec */
 133struct sgtl5000_priv {
 134        int sysclk;     /* sysclk rate */
 135        int master;     /* i2s master or not */
 136        int fmt;        /* i2s data format */
 137        struct regulator_bulk_data supplies[SGTL5000_SUPPLY_NUM];
 138        struct ldo_regulator *ldo;
 139        struct regmap *regmap;
 140        struct clk *mclk;
 141        int revision;
 142        u8 micbias_resistor;
 143        u8 micbias_voltage;
 144};
 145
 146/*
 147 * mic_bias power on/off share the same register bits with
 148 * output impedance of mic bias, when power on mic bias, we
 149 * need reclaim it to impedance value.
 150 * 0x0 = Powered off
 151 * 0x1 = 2Kohm
 152 * 0x2 = 4Kohm
 153 * 0x3 = 8Kohm
 154 */
 155static int mic_bias_event(struct snd_soc_dapm_widget *w,
 156        struct snd_kcontrol *kcontrol, int event)
 157{
 158        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 159        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 160
 161        switch (event) {
 162        case SND_SOC_DAPM_POST_PMU:
 163                /* change mic bias resistor */
 164                snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
 165                        SGTL5000_BIAS_R_MASK,
 166                        sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
 167                break;
 168
 169        case SND_SOC_DAPM_PRE_PMD:
 170                snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
 171                                SGTL5000_BIAS_R_MASK, 0);
 172                break;
 173        }
 174        return 0;
 175}
 176
 177/*
 178 * As manual described, ADC/DAC only works when VAG powerup,
 179 * So enabled VAG before ADC/DAC up.
 180 * In power down case, we need wait 400ms when vag fully ramped down.
 181 */
 182static int power_vag_event(struct snd_soc_dapm_widget *w,
 183        struct snd_kcontrol *kcontrol, int event)
 184{
 185        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 186        const u32 mask = SGTL5000_DAC_POWERUP | SGTL5000_ADC_POWERUP;
 187
 188        switch (event) {
 189        case SND_SOC_DAPM_POST_PMU:
 190                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
 191                        SGTL5000_VAG_POWERUP, SGTL5000_VAG_POWERUP);
 192                msleep(400);
 193                break;
 194
 195        case SND_SOC_DAPM_PRE_PMD:
 196                /*
 197                 * Don't clear VAG_POWERUP, when both DAC and ADC are
 198                 * operational to prevent inadvertently starving the
 199                 * other one of them.
 200                 */
 201                if ((snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER) &
 202                                mask) != mask) {
 203                        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
 204                                SGTL5000_VAG_POWERUP, 0);
 205                        msleep(400);
 206                }
 207                break;
 208        default:
 209                break;
 210        }
 211
 212        return 0;
 213}
 214
 215/* input sources for ADC */
 216static const char *adc_mux_text[] = {
 217        "MIC_IN", "LINE_IN"
 218};
 219
 220static SOC_ENUM_SINGLE_DECL(adc_enum,
 221                            SGTL5000_CHIP_ANA_CTRL, 2,
 222                            adc_mux_text);
 223
 224static const struct snd_kcontrol_new adc_mux =
 225SOC_DAPM_ENUM("Capture Mux", adc_enum);
 226
 227/* input sources for DAC */
 228static const char *dac_mux_text[] = {
 229        "DAC", "LINE_IN"
 230};
 231
 232static SOC_ENUM_SINGLE_DECL(dac_enum,
 233                            SGTL5000_CHIP_ANA_CTRL, 6,
 234                            dac_mux_text);
 235
 236static const struct snd_kcontrol_new dac_mux =
 237SOC_DAPM_ENUM("Headphone Mux", dac_enum);
 238
 239static const struct snd_soc_dapm_widget sgtl5000_dapm_widgets[] = {
 240        SND_SOC_DAPM_INPUT("LINE_IN"),
 241        SND_SOC_DAPM_INPUT("MIC_IN"),
 242
 243        SND_SOC_DAPM_OUTPUT("HP_OUT"),
 244        SND_SOC_DAPM_OUTPUT("LINE_OUT"),
 245
 246        SND_SOC_DAPM_SUPPLY("Mic Bias", SGTL5000_CHIP_MIC_CTRL, 8, 0,
 247                            mic_bias_event,
 248                            SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 249
 250        SND_SOC_DAPM_PGA("HP", SGTL5000_CHIP_ANA_POWER, 4, 0, NULL, 0),
 251        SND_SOC_DAPM_PGA("LO", SGTL5000_CHIP_ANA_POWER, 0, 0, NULL, 0),
 252
 253        SND_SOC_DAPM_MUX("Capture Mux", SND_SOC_NOPM, 0, 0, &adc_mux),
 254        SND_SOC_DAPM_MUX("Headphone Mux", SND_SOC_NOPM, 0, 0, &dac_mux),
 255
 256        /* aif for i2s input */
 257        SND_SOC_DAPM_AIF_IN("AIFIN", "Playback",
 258                                0, SGTL5000_CHIP_DIG_POWER,
 259                                0, 0),
 260
 261        /* aif for i2s output */
 262        SND_SOC_DAPM_AIF_OUT("AIFOUT", "Capture",
 263                                0, SGTL5000_CHIP_DIG_POWER,
 264                                1, 0),
 265
 266        SND_SOC_DAPM_ADC("ADC", "Capture", SGTL5000_CHIP_ANA_POWER, 1, 0),
 267        SND_SOC_DAPM_DAC("DAC", "Playback", SGTL5000_CHIP_ANA_POWER, 3, 0),
 268
 269        SND_SOC_DAPM_PRE("VAG_POWER_PRE", power_vag_event),
 270        SND_SOC_DAPM_POST("VAG_POWER_POST", power_vag_event),
 271};
 272
 273/* routes for sgtl5000 */
 274static const struct snd_soc_dapm_route sgtl5000_dapm_routes[] = {
 275        {"Capture Mux", "LINE_IN", "LINE_IN"},  /* line_in --> adc_mux */
 276        {"Capture Mux", "MIC_IN", "MIC_IN"},    /* mic_in --> adc_mux */
 277
 278        {"ADC", NULL, "Capture Mux"},           /* adc_mux --> adc */
 279        {"AIFOUT", NULL, "ADC"},                /* adc --> i2s_out */
 280
 281        {"DAC", NULL, "AIFIN"},                 /* i2s-->dac,skip audio mux */
 282        {"Headphone Mux", "DAC", "DAC"},        /* dac --> hp_mux */
 283        {"LO", NULL, "DAC"},                    /* dac --> line_out */
 284
 285        {"Headphone Mux", "LINE_IN", "LINE_IN"},/* line_in --> hp_mux */
 286        {"HP", NULL, "Headphone Mux"},          /* hp_mux --> hp */
 287
 288        {"LINE_OUT", NULL, "LO"},
 289        {"HP_OUT", NULL, "HP"},
 290};
 291
 292/* custom function to fetch info of PCM playback volume */
 293static int dac_info_volsw(struct snd_kcontrol *kcontrol,
 294                          struct snd_ctl_elem_info *uinfo)
 295{
 296        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 297        uinfo->count = 2;
 298        uinfo->value.integer.min = 0;
 299        uinfo->value.integer.max = 0xfc - 0x3c;
 300        return 0;
 301}
 302
 303/*
 304 * custom function to get of PCM playback volume
 305 *
 306 * dac volume register
 307 * 15-------------8-7--------------0
 308 * | R channel vol | L channel vol |
 309 *  -------------------------------
 310 *
 311 * PCM volume with 0.5017 dB steps from 0 to -90 dB
 312 *
 313 * register values map to dB
 314 * 0x3B and less = Reserved
 315 * 0x3C = 0 dB
 316 * 0x3D = -0.5 dB
 317 * 0xF0 = -90 dB
 318 * 0xFC and greater = Muted
 319 *
 320 * register value map to userspace value
 321 *
 322 * register value       0x3c(0dB)         0xf0(-90dB)0xfc
 323 *                      ------------------------------
 324 * userspace value      0xc0                         0
 325 */
 326static int dac_get_volsw(struct snd_kcontrol *kcontrol,
 327                         struct snd_ctl_elem_value *ucontrol)
 328{
 329        struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 330        int reg;
 331        int l;
 332        int r;
 333
 334        reg = snd_soc_read(codec, SGTL5000_CHIP_DAC_VOL);
 335
 336        /* get left channel volume */
 337        l = (reg & SGTL5000_DAC_VOL_LEFT_MASK) >> SGTL5000_DAC_VOL_LEFT_SHIFT;
 338
 339        /* get right channel volume */
 340        r = (reg & SGTL5000_DAC_VOL_RIGHT_MASK) >> SGTL5000_DAC_VOL_RIGHT_SHIFT;
 341
 342        /* make sure value fall in (0x3c,0xfc) */
 343        l = clamp(l, 0x3c, 0xfc);
 344        r = clamp(r, 0x3c, 0xfc);
 345
 346        /* invert it and map to userspace value */
 347        l = 0xfc - l;
 348        r = 0xfc - r;
 349
 350        ucontrol->value.integer.value[0] = l;
 351        ucontrol->value.integer.value[1] = r;
 352
 353        return 0;
 354}
 355
 356/*
 357 * custom function to put of PCM playback volume
 358 *
 359 * dac volume register
 360 * 15-------------8-7--------------0
 361 * | R channel vol | L channel vol |
 362 *  -------------------------------
 363 *
 364 * PCM volume with 0.5017 dB steps from 0 to -90 dB
 365 *
 366 * register values map to dB
 367 * 0x3B and less = Reserved
 368 * 0x3C = 0 dB
 369 * 0x3D = -0.5 dB
 370 * 0xF0 = -90 dB
 371 * 0xFC and greater = Muted
 372 *
 373 * userspace value map to register value
 374 *
 375 * userspace value      0xc0                         0
 376 *                      ------------------------------
 377 * register value       0x3c(0dB)       0xf0(-90dB)0xfc
 378 */
 379static int dac_put_volsw(struct snd_kcontrol *kcontrol,
 380                         struct snd_ctl_elem_value *ucontrol)
 381{
 382        struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 383        int reg;
 384        int l;
 385        int r;
 386
 387        l = ucontrol->value.integer.value[0];
 388        r = ucontrol->value.integer.value[1];
 389
 390        /* make sure userspace volume fall in (0, 0xfc-0x3c) */
 391        l = clamp(l, 0, 0xfc - 0x3c);
 392        r = clamp(r, 0, 0xfc - 0x3c);
 393
 394        /* invert it, get the value can be set to register */
 395        l = 0xfc - l;
 396        r = 0xfc - r;
 397
 398        /* shift to get the register value */
 399        reg = l << SGTL5000_DAC_VOL_LEFT_SHIFT |
 400                r << SGTL5000_DAC_VOL_RIGHT_SHIFT;
 401
 402        snd_soc_write(codec, SGTL5000_CHIP_DAC_VOL, reg);
 403
 404        return 0;
 405}
 406
 407static const DECLARE_TLV_DB_SCALE(capture_6db_attenuate, -600, 600, 0);
 408
 409/* tlv for mic gain, 0db 20db 30db 40db */
 410static const DECLARE_TLV_DB_RANGE(mic_gain_tlv,
 411        0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
 412        1, 3, TLV_DB_SCALE_ITEM(2000, 1000, 0)
 413);
 414
 415/* tlv for hp volume, -51.5db to 12.0db, step .5db */
 416static const DECLARE_TLV_DB_SCALE(headphone_volume, -5150, 50, 0);
 417
 418static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
 419        /* SOC_DOUBLE_S8_TLV with invert */
 420        {
 421                .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 422                .name = "PCM Playback Volume",
 423                .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |
 424                        SNDRV_CTL_ELEM_ACCESS_READWRITE,
 425                .info = dac_info_volsw,
 426                .get = dac_get_volsw,
 427                .put = dac_put_volsw,
 428        },
 429
 430        SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
 431        SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
 432                        SGTL5000_CHIP_ANA_ADC_CTRL,
 433                        8, 1, 0, capture_6db_attenuate),
 434        SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
 435
 436        SOC_DOUBLE_TLV("Headphone Playback Volume",
 437                        SGTL5000_CHIP_ANA_HP_CTRL,
 438                        0, 8,
 439                        0x7f, 1,
 440                        headphone_volume),
 441        SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
 442                        5, 1, 0),
 443
 444        SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
 445                        0, 3, 0, mic_gain_tlv),
 446};
 447
 448/* mute the codec used by alsa core */
 449static int sgtl5000_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 450{
 451        struct snd_soc_codec *codec = codec_dai->codec;
 452        u16 adcdac_ctrl = SGTL5000_DAC_MUTE_LEFT | SGTL5000_DAC_MUTE_RIGHT;
 453
 454        snd_soc_update_bits(codec, SGTL5000_CHIP_ADCDAC_CTRL,
 455                        adcdac_ctrl, mute ? adcdac_ctrl : 0);
 456
 457        return 0;
 458}
 459
 460/* set codec format */
 461static int sgtl5000_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 462{
 463        struct snd_soc_codec *codec = codec_dai->codec;
 464        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 465        u16 i2sctl = 0;
 466
 467        sgtl5000->master = 0;
 468        /*
 469         * i2s clock and frame master setting.
 470         * ONLY support:
 471         *  - clock and frame slave,
 472         *  - clock and frame master
 473         */
 474        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 475        case SND_SOC_DAIFMT_CBS_CFS:
 476                break;
 477        case SND_SOC_DAIFMT_CBM_CFM:
 478                i2sctl |= SGTL5000_I2S_MASTER;
 479                sgtl5000->master = 1;
 480                break;
 481        default:
 482                return -EINVAL;
 483        }
 484
 485        /* setting i2s data format */
 486        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 487        case SND_SOC_DAIFMT_DSP_A:
 488                i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
 489                break;
 490        case SND_SOC_DAIFMT_DSP_B:
 491                i2sctl |= SGTL5000_I2S_MODE_PCM << SGTL5000_I2S_MODE_SHIFT;
 492                i2sctl |= SGTL5000_I2S_LRALIGN;
 493                break;
 494        case SND_SOC_DAIFMT_I2S:
 495                i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
 496                break;
 497        case SND_SOC_DAIFMT_RIGHT_J:
 498                i2sctl |= SGTL5000_I2S_MODE_RJ << SGTL5000_I2S_MODE_SHIFT;
 499                i2sctl |= SGTL5000_I2S_LRPOL;
 500                break;
 501        case SND_SOC_DAIFMT_LEFT_J:
 502                i2sctl |= SGTL5000_I2S_MODE_I2S_LJ << SGTL5000_I2S_MODE_SHIFT;
 503                i2sctl |= SGTL5000_I2S_LRALIGN;
 504                break;
 505        default:
 506                return -EINVAL;
 507        }
 508
 509        sgtl5000->fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 510
 511        /* Clock inversion */
 512        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 513        case SND_SOC_DAIFMT_NB_NF:
 514                break;
 515        case SND_SOC_DAIFMT_IB_NF:
 516                i2sctl |= SGTL5000_I2S_SCLK_INV;
 517                break;
 518        default:
 519                return -EINVAL;
 520        }
 521
 522        snd_soc_write(codec, SGTL5000_CHIP_I2S_CTRL, i2sctl);
 523
 524        return 0;
 525}
 526
 527/* set codec sysclk */
 528static int sgtl5000_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 529                                   int clk_id, unsigned int freq, int dir)
 530{
 531        struct snd_soc_codec *codec = codec_dai->codec;
 532        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 533
 534        switch (clk_id) {
 535        case SGTL5000_SYSCLK:
 536                sgtl5000->sysclk = freq;
 537                break;
 538        default:
 539                return -EINVAL;
 540        }
 541
 542        return 0;
 543}
 544
 545/*
 546 * set clock according to i2s frame clock,
 547 * sgtl5000 provides 2 clock sources:
 548 * 1. sys_mclk: sample freq can only be configured to
 549 *      1/256, 1/384, 1/512 of sys_mclk.
 550 * 2. pll: can derive any audio clocks.
 551 *
 552 * clock setting rules:
 553 * 1. in slave mode, only sys_mclk can be used
 554 * 2. as constraint by sys_mclk, sample freq should be set to 32 kHz, 44.1 kHz
 555 * and above.
 556 * 3. usage of sys_mclk is preferred over pll to save power.
 557 */
 558static int sgtl5000_set_clock(struct snd_soc_codec *codec, int frame_rate)
 559{
 560        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 561        int clk_ctl = 0;
 562        int sys_fs;     /* sample freq */
 563
 564        /*
 565         * sample freq should be divided by frame clock,
 566         * if frame clock is lower than 44.1 kHz, sample freq should be set to
 567         * 32 kHz or 44.1 kHz.
 568         */
 569        switch (frame_rate) {
 570        case 8000:
 571        case 16000:
 572                sys_fs = 32000;
 573                break;
 574        case 11025:
 575        case 22050:
 576                sys_fs = 44100;
 577                break;
 578        default:
 579                sys_fs = frame_rate;
 580                break;
 581        }
 582
 583        /* set divided factor of frame clock */
 584        switch (sys_fs / frame_rate) {
 585        case 4:
 586                clk_ctl |= SGTL5000_RATE_MODE_DIV_4 << SGTL5000_RATE_MODE_SHIFT;
 587                break;
 588        case 2:
 589                clk_ctl |= SGTL5000_RATE_MODE_DIV_2 << SGTL5000_RATE_MODE_SHIFT;
 590                break;
 591        case 1:
 592                clk_ctl |= SGTL5000_RATE_MODE_DIV_1 << SGTL5000_RATE_MODE_SHIFT;
 593                break;
 594        default:
 595                return -EINVAL;
 596        }
 597
 598        /* set the sys_fs according to frame rate */
 599        switch (sys_fs) {
 600        case 32000:
 601                clk_ctl |= SGTL5000_SYS_FS_32k << SGTL5000_SYS_FS_SHIFT;
 602                break;
 603        case 44100:
 604                clk_ctl |= SGTL5000_SYS_FS_44_1k << SGTL5000_SYS_FS_SHIFT;
 605                break;
 606        case 48000:
 607                clk_ctl |= SGTL5000_SYS_FS_48k << SGTL5000_SYS_FS_SHIFT;
 608                break;
 609        case 96000:
 610                clk_ctl |= SGTL5000_SYS_FS_96k << SGTL5000_SYS_FS_SHIFT;
 611                break;
 612        default:
 613                dev_err(codec->dev, "frame rate %d not supported\n",
 614                        frame_rate);
 615                return -EINVAL;
 616        }
 617
 618        /*
 619         * calculate the divider of mclk/sample_freq,
 620         * factor of freq = 96 kHz can only be 256, since mclk is in the range
 621         * of 8 MHz - 27 MHz
 622         */
 623        switch (sgtl5000->sysclk / frame_rate) {
 624        case 256:
 625                clk_ctl |= SGTL5000_MCLK_FREQ_256FS <<
 626                        SGTL5000_MCLK_FREQ_SHIFT;
 627                break;
 628        case 384:
 629                clk_ctl |= SGTL5000_MCLK_FREQ_384FS <<
 630                        SGTL5000_MCLK_FREQ_SHIFT;
 631                break;
 632        case 512:
 633                clk_ctl |= SGTL5000_MCLK_FREQ_512FS <<
 634                        SGTL5000_MCLK_FREQ_SHIFT;
 635                break;
 636        default:
 637                /* if mclk does not satisfy the divider, use pll */
 638                if (sgtl5000->master) {
 639                        clk_ctl |= SGTL5000_MCLK_FREQ_PLL <<
 640                                SGTL5000_MCLK_FREQ_SHIFT;
 641                } else {
 642                        dev_err(codec->dev,
 643                                "PLL not supported in slave mode\n");
 644                        dev_err(codec->dev, "%d ratio is not supported. "
 645                                "SYS_MCLK needs to be 256, 384 or 512 * fs\n",
 646                                sgtl5000->sysclk / frame_rate);
 647                        return -EINVAL;
 648                }
 649        }
 650
 651        /* if using pll, please check manual 6.4.2 for detail */
 652        if ((clk_ctl & SGTL5000_MCLK_FREQ_MASK) == SGTL5000_MCLK_FREQ_PLL) {
 653                u64 out, t;
 654                int div2;
 655                int pll_ctl;
 656                unsigned int in, int_div, frac_div;
 657
 658                if (sgtl5000->sysclk > 17000000) {
 659                        div2 = 1;
 660                        in = sgtl5000->sysclk / 2;
 661                } else {
 662                        div2 = 0;
 663                        in = sgtl5000->sysclk;
 664                }
 665                if (sys_fs == 44100)
 666                        out = 180633600;
 667                else
 668                        out = 196608000;
 669                t = do_div(out, in);
 670                int_div = out;
 671                t *= 2048;
 672                do_div(t, in);
 673                frac_div = t;
 674                pll_ctl = int_div << SGTL5000_PLL_INT_DIV_SHIFT |
 675                    frac_div << SGTL5000_PLL_FRAC_DIV_SHIFT;
 676
 677                snd_soc_write(codec, SGTL5000_CHIP_PLL_CTRL, pll_ctl);
 678                if (div2)
 679                        snd_soc_update_bits(codec,
 680                                SGTL5000_CHIP_CLK_TOP_CTRL,
 681                                SGTL5000_INPUT_FREQ_DIV2,
 682                                SGTL5000_INPUT_FREQ_DIV2);
 683                else
 684                        snd_soc_update_bits(codec,
 685                                SGTL5000_CHIP_CLK_TOP_CTRL,
 686                                SGTL5000_INPUT_FREQ_DIV2,
 687                                0);
 688
 689                /* power up pll */
 690                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
 691                        SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
 692                        SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP);
 693
 694                /* if using pll, clk_ctrl must be set after pll power up */
 695                snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
 696        } else {
 697                /* otherwise, clk_ctrl must be set before pll power down */
 698                snd_soc_write(codec, SGTL5000_CHIP_CLK_CTRL, clk_ctl);
 699
 700                /* power down pll */
 701                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
 702                        SGTL5000_PLL_POWERUP | SGTL5000_VCOAMP_POWERUP,
 703                        0);
 704        }
 705
 706        return 0;
 707}
 708
 709/*
 710 * Set PCM DAI bit size and sample rate.
 711 * input: params_rate, params_fmt
 712 */
 713static int sgtl5000_pcm_hw_params(struct snd_pcm_substream *substream,
 714                                  struct snd_pcm_hw_params *params,
 715                                  struct snd_soc_dai *dai)
 716{
 717        struct snd_soc_codec *codec = dai->codec;
 718        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 719        int channels = params_channels(params);
 720        int i2s_ctl = 0;
 721        int stereo;
 722        int ret;
 723
 724        /* sysclk should already set */
 725        if (!sgtl5000->sysclk) {
 726                dev_err(codec->dev, "%s: set sysclk first!\n", __func__);
 727                return -EFAULT;
 728        }
 729
 730        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 731                stereo = SGTL5000_DAC_STEREO;
 732        else
 733                stereo = SGTL5000_ADC_STEREO;
 734
 735        /* set mono to save power */
 736        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER, stereo,
 737                        channels == 1 ? 0 : stereo);
 738
 739        /* set codec clock base on lrclk */
 740        ret = sgtl5000_set_clock(codec, params_rate(params));
 741        if (ret)
 742                return ret;
 743
 744        /* set i2s data format */
 745        switch (params_width(params)) {
 746        case 16:
 747                if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
 748                        return -EINVAL;
 749                i2s_ctl |= SGTL5000_I2S_DLEN_16 << SGTL5000_I2S_DLEN_SHIFT;
 750                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_32FS <<
 751                    SGTL5000_I2S_SCLKFREQ_SHIFT;
 752                break;
 753        case 20:
 754                i2s_ctl |= SGTL5000_I2S_DLEN_20 << SGTL5000_I2S_DLEN_SHIFT;
 755                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
 756                    SGTL5000_I2S_SCLKFREQ_SHIFT;
 757                break;
 758        case 24:
 759                i2s_ctl |= SGTL5000_I2S_DLEN_24 << SGTL5000_I2S_DLEN_SHIFT;
 760                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
 761                    SGTL5000_I2S_SCLKFREQ_SHIFT;
 762                break;
 763        case 32:
 764                if (sgtl5000->fmt == SND_SOC_DAIFMT_RIGHT_J)
 765                        return -EINVAL;
 766                i2s_ctl |= SGTL5000_I2S_DLEN_32 << SGTL5000_I2S_DLEN_SHIFT;
 767                i2s_ctl |= SGTL5000_I2S_SCLKFREQ_64FS <<
 768                    SGTL5000_I2S_SCLKFREQ_SHIFT;
 769                break;
 770        default:
 771                return -EINVAL;
 772        }
 773
 774        snd_soc_update_bits(codec, SGTL5000_CHIP_I2S_CTRL,
 775                            SGTL5000_I2S_DLEN_MASK | SGTL5000_I2S_SCLKFREQ_MASK,
 776                            i2s_ctl);
 777
 778        return 0;
 779}
 780
 781#ifdef CONFIG_REGULATOR
 782static int ldo_regulator_is_enabled(struct regulator_dev *dev)
 783{
 784        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
 785
 786        return ldo->enabled;
 787}
 788
 789static int ldo_regulator_enable(struct regulator_dev *dev)
 790{
 791        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
 792        struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
 793        int reg;
 794
 795        if (ldo_regulator_is_enabled(dev))
 796                return 0;
 797
 798        /* set regulator value firstly */
 799        reg = (1600 - ldo->voltage / 1000) / 50;
 800        reg = clamp(reg, 0x0, 0xf);
 801
 802        /* amend the voltage value, unit: uV */
 803        ldo->voltage = (1600 - reg * 50) * 1000;
 804
 805        /* set voltage to register */
 806        snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
 807                                SGTL5000_LINREG_VDDD_MASK, reg);
 808
 809        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
 810                                SGTL5000_LINEREG_D_POWERUP,
 811                                SGTL5000_LINEREG_D_POWERUP);
 812
 813        /* when internal ldo is enabled, simple digital power can be disabled */
 814        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
 815                                SGTL5000_LINREG_SIMPLE_POWERUP,
 816                                0);
 817
 818        ldo->enabled = 1;
 819        return 0;
 820}
 821
 822static int ldo_regulator_disable(struct regulator_dev *dev)
 823{
 824        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
 825        struct snd_soc_codec *codec = (struct snd_soc_codec *)ldo->codec_data;
 826
 827        snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
 828                                SGTL5000_LINEREG_D_POWERUP,
 829                                0);
 830
 831        /* clear voltage info */
 832        snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
 833                                SGTL5000_LINREG_VDDD_MASK, 0);
 834
 835        ldo->enabled = 0;
 836
 837        return 0;
 838}
 839
 840static int ldo_regulator_get_voltage(struct regulator_dev *dev)
 841{
 842        struct ldo_regulator *ldo = rdev_get_drvdata(dev);
 843
 844        return ldo->voltage;
 845}
 846
 847static struct regulator_ops ldo_regulator_ops = {
 848        .is_enabled = ldo_regulator_is_enabled,
 849        .enable = ldo_regulator_enable,
 850        .disable = ldo_regulator_disable,
 851        .get_voltage = ldo_regulator_get_voltage,
 852};
 853
 854static int ldo_regulator_register(struct snd_soc_codec *codec,
 855                                struct regulator_init_data *init_data,
 856                                int voltage)
 857{
 858        struct ldo_regulator *ldo;
 859        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 860        struct regulator_config config = { };
 861
 862        ldo = kzalloc(sizeof(struct ldo_regulator), GFP_KERNEL);
 863
 864        if (!ldo)
 865                return -ENOMEM;
 866
 867        ldo->desc.name = kstrdup(dev_name(codec->dev), GFP_KERNEL);
 868        if (!ldo->desc.name) {
 869                kfree(ldo);
 870                dev_err(codec->dev, "failed to allocate decs name memory\n");
 871                return -ENOMEM;
 872        }
 873
 874        ldo->desc.type  = REGULATOR_VOLTAGE;
 875        ldo->desc.owner = THIS_MODULE;
 876        ldo->desc.ops   = &ldo_regulator_ops;
 877        ldo->desc.n_voltages = 1;
 878
 879        ldo->codec_data = codec;
 880        ldo->voltage = voltage;
 881
 882        config.dev = codec->dev;
 883        config.driver_data = ldo;
 884        config.init_data = init_data;
 885
 886        ldo->dev = regulator_register(&ldo->desc, &config);
 887        if (IS_ERR(ldo->dev)) {
 888                int ret = PTR_ERR(ldo->dev);
 889
 890                dev_err(codec->dev, "failed to register regulator\n");
 891                kfree(ldo->desc.name);
 892                kfree(ldo);
 893
 894                return ret;
 895        }
 896        sgtl5000->ldo = ldo;
 897
 898        return 0;
 899}
 900
 901static int ldo_regulator_remove(struct snd_soc_codec *codec)
 902{
 903        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 904        struct ldo_regulator *ldo = sgtl5000->ldo;
 905
 906        if (!ldo)
 907                return 0;
 908
 909        regulator_unregister(ldo->dev);
 910        kfree(ldo->desc.name);
 911        kfree(ldo);
 912
 913        return 0;
 914}
 915#else
 916static int ldo_regulator_register(struct snd_soc_codec *codec,
 917                                struct regulator_init_data *init_data,
 918                                int voltage)
 919{
 920        dev_err(codec->dev, "this setup needs regulator support in the kernel\n");
 921        return -EINVAL;
 922}
 923
 924static int ldo_regulator_remove(struct snd_soc_codec *codec)
 925{
 926        return 0;
 927}
 928#endif
 929
 930/*
 931 * set dac bias
 932 * common state changes:
 933 * startup:
 934 * off --> standby --> prepare --> on
 935 * standby --> prepare --> on
 936 *
 937 * stop:
 938 * on --> prepare --> standby
 939 */
 940static int sgtl5000_set_bias_level(struct snd_soc_codec *codec,
 941                                   enum snd_soc_bias_level level)
 942{
 943        int ret;
 944        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
 945
 946        switch (level) {
 947        case SND_SOC_BIAS_ON:
 948        case SND_SOC_BIAS_PREPARE:
 949                break;
 950        case SND_SOC_BIAS_STANDBY:
 951                if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
 952                        ret = regulator_bulk_enable(
 953                                                ARRAY_SIZE(sgtl5000->supplies),
 954                                                sgtl5000->supplies);
 955                        if (ret)
 956                                return ret;
 957                        udelay(10);
 958
 959                        regcache_cache_only(sgtl5000->regmap, false);
 960
 961                        ret = regcache_sync(sgtl5000->regmap);
 962                        if (ret != 0) {
 963                                dev_err(codec->dev,
 964                                        "Failed to restore cache: %d\n", ret);
 965
 966                                regcache_cache_only(sgtl5000->regmap, true);
 967                                regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
 968                                                       sgtl5000->supplies);
 969
 970                                return ret;
 971                        }
 972                }
 973
 974                break;
 975        case SND_SOC_BIAS_OFF:
 976                regcache_cache_only(sgtl5000->regmap, true);
 977                regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
 978                                        sgtl5000->supplies);
 979                break;
 980        }
 981
 982        return 0;
 983}
 984
 985#define SGTL5000_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
 986                        SNDRV_PCM_FMTBIT_S20_3LE |\
 987                        SNDRV_PCM_FMTBIT_S24_LE |\
 988                        SNDRV_PCM_FMTBIT_S32_LE)
 989
 990static const struct snd_soc_dai_ops sgtl5000_ops = {
 991        .hw_params = sgtl5000_pcm_hw_params,
 992        .digital_mute = sgtl5000_digital_mute,
 993        .set_fmt = sgtl5000_set_dai_fmt,
 994        .set_sysclk = sgtl5000_set_dai_sysclk,
 995};
 996
 997static struct snd_soc_dai_driver sgtl5000_dai = {
 998        .name = "sgtl5000",
 999        .playback = {
1000                .stream_name = "Playback",
1001                .channels_min = 1,
1002                .channels_max = 2,
1003                /*
1004                 * only support 8~48K + 96K,
1005                 * TODO modify hw_param to support more
1006                 */
1007                .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1008                .formats = SGTL5000_FORMATS,
1009        },
1010        .capture = {
1011                .stream_name = "Capture",
1012                .channels_min = 1,
1013                .channels_max = 2,
1014                .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_96000,
1015                .formats = SGTL5000_FORMATS,
1016        },
1017        .ops = &sgtl5000_ops,
1018        .symmetric_rates = 1,
1019};
1020
1021static bool sgtl5000_volatile(struct device *dev, unsigned int reg)
1022{
1023        switch (reg) {
1024        case SGTL5000_CHIP_ID:
1025        case SGTL5000_CHIP_ADCDAC_CTRL:
1026        case SGTL5000_CHIP_ANA_STATUS:
1027                return true;
1028        }
1029
1030        return false;
1031}
1032
1033static bool sgtl5000_readable(struct device *dev, unsigned int reg)
1034{
1035        switch (reg) {
1036        case SGTL5000_CHIP_ID:
1037        case SGTL5000_CHIP_DIG_POWER:
1038        case SGTL5000_CHIP_CLK_CTRL:
1039        case SGTL5000_CHIP_I2S_CTRL:
1040        case SGTL5000_CHIP_SSS_CTRL:
1041        case SGTL5000_CHIP_ADCDAC_CTRL:
1042        case SGTL5000_CHIP_DAC_VOL:
1043        case SGTL5000_CHIP_PAD_STRENGTH:
1044        case SGTL5000_CHIP_ANA_ADC_CTRL:
1045        case SGTL5000_CHIP_ANA_HP_CTRL:
1046        case SGTL5000_CHIP_ANA_CTRL:
1047        case SGTL5000_CHIP_LINREG_CTRL:
1048        case SGTL5000_CHIP_REF_CTRL:
1049        case SGTL5000_CHIP_MIC_CTRL:
1050        case SGTL5000_CHIP_LINE_OUT_CTRL:
1051        case SGTL5000_CHIP_LINE_OUT_VOL:
1052        case SGTL5000_CHIP_ANA_POWER:
1053        case SGTL5000_CHIP_PLL_CTRL:
1054        case SGTL5000_CHIP_CLK_TOP_CTRL:
1055        case SGTL5000_CHIP_ANA_STATUS:
1056        case SGTL5000_CHIP_SHORT_CTRL:
1057        case SGTL5000_CHIP_ANA_TEST2:
1058        case SGTL5000_DAP_CTRL:
1059        case SGTL5000_DAP_PEQ:
1060        case SGTL5000_DAP_BASS_ENHANCE:
1061        case SGTL5000_DAP_BASS_ENHANCE_CTRL:
1062        case SGTL5000_DAP_AUDIO_EQ:
1063        case SGTL5000_DAP_SURROUND:
1064        case SGTL5000_DAP_FLT_COEF_ACCESS:
1065        case SGTL5000_DAP_COEF_WR_B0_MSB:
1066        case SGTL5000_DAP_COEF_WR_B0_LSB:
1067        case SGTL5000_DAP_EQ_BASS_BAND0:
1068        case SGTL5000_DAP_EQ_BASS_BAND1:
1069        case SGTL5000_DAP_EQ_BASS_BAND2:
1070        case SGTL5000_DAP_EQ_BASS_BAND3:
1071        case SGTL5000_DAP_EQ_BASS_BAND4:
1072        case SGTL5000_DAP_MAIN_CHAN:
1073        case SGTL5000_DAP_MIX_CHAN:
1074        case SGTL5000_DAP_AVC_CTRL:
1075        case SGTL5000_DAP_AVC_THRESHOLD:
1076        case SGTL5000_DAP_AVC_ATTACK:
1077        case SGTL5000_DAP_AVC_DECAY:
1078        case SGTL5000_DAP_COEF_WR_B1_MSB:
1079        case SGTL5000_DAP_COEF_WR_B1_LSB:
1080        case SGTL5000_DAP_COEF_WR_B2_MSB:
1081        case SGTL5000_DAP_COEF_WR_B2_LSB:
1082        case SGTL5000_DAP_COEF_WR_A1_MSB:
1083        case SGTL5000_DAP_COEF_WR_A1_LSB:
1084        case SGTL5000_DAP_COEF_WR_A2_MSB:
1085        case SGTL5000_DAP_COEF_WR_A2_LSB:
1086                return true;
1087
1088        default:
1089                return false;
1090        }
1091}
1092
1093/*
1094 * This precalculated table contains all (vag_val * 100 / lo_calcntrl) results
1095 * to select an appropriate lo_vol_* in SGTL5000_CHIP_LINE_OUT_VOL
1096 * The calculatation was done for all possible register values which
1097 * is the array index and the following formula: 10^((idx\xE2\x88\x9215)/40) * 100
1098 */
1099static const u8 vol_quot_table[] = {
1100        42, 45, 47, 50, 53, 56, 60, 63,
1101        67, 71, 75, 79, 84, 89, 94, 100,
1102        106, 112, 119, 126, 133, 141, 150, 158,
1103        168, 178, 188, 200, 211, 224, 237, 251
1104};
1105
1106/*
1107 * sgtl5000 has 3 internal power supplies:
1108 * 1. VAG, normally set to vdda/2
1109 * 2. charge pump, set to different value
1110 *      according to voltage of vdda and vddio
1111 * 3. line out VAG, normally set to vddio/2
1112 *
1113 * and should be set according to:
1114 * 1. vddd provided by external or not
1115 * 2. vdda and vddio voltage value. > 3.1v or not
1116 * 3. chip revision >=0x11 or not. If >=0x11, not use external vddd.
1117 */
1118static int sgtl5000_set_power_regs(struct snd_soc_codec *codec)
1119{
1120        int vddd;
1121        int vdda;
1122        int vddio;
1123        u16 ana_pwr;
1124        u16 lreg_ctrl;
1125        int vag;
1126        int lo_vag;
1127        int vol_quot;
1128        int lo_vol;
1129        size_t i;
1130        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1131
1132        vdda  = regulator_get_voltage(sgtl5000->supplies[VDDA].consumer);
1133        vddio = regulator_get_voltage(sgtl5000->supplies[VDDIO].consumer);
1134        vddd  = regulator_get_voltage(sgtl5000->supplies[VDDD].consumer);
1135
1136        vdda  = vdda / 1000;
1137        vddio = vddio / 1000;
1138        vddd  = vddd / 1000;
1139
1140        if (vdda <= 0 || vddio <= 0 || vddd < 0) {
1141                dev_err(codec->dev, "regulator voltage not set correctly\n");
1142
1143                return -EINVAL;
1144        }
1145
1146        /* according to datasheet, maximum voltage of supplies */
1147        if (vdda > 3600 || vddio > 3600 || vddd > 1980) {
1148                dev_err(codec->dev,
1149                        "exceed max voltage vdda %dmV vddio %dmV vddd %dmV\n",
1150                        vdda, vddio, vddd);
1151
1152                return -EINVAL;
1153        }
1154
1155        /* reset value */
1156        ana_pwr = snd_soc_read(codec, SGTL5000_CHIP_ANA_POWER);
1157        ana_pwr |= SGTL5000_DAC_STEREO |
1158                        SGTL5000_ADC_STEREO |
1159                        SGTL5000_REFTOP_POWERUP;
1160        lreg_ctrl = snd_soc_read(codec, SGTL5000_CHIP_LINREG_CTRL);
1161
1162        if (vddio < 3100 && vdda < 3100) {
1163                /* enable internal oscillator used for charge pump */
1164                snd_soc_update_bits(codec, SGTL5000_CHIP_CLK_TOP_CTRL,
1165                                        SGTL5000_INT_OSC_EN,
1166                                        SGTL5000_INT_OSC_EN);
1167                /* Enable VDDC charge pump */
1168                ana_pwr |= SGTL5000_VDDC_CHRGPMP_POWERUP;
1169        } else if (vddio >= 3100 && vdda >= 3100) {
1170                ana_pwr &= ~SGTL5000_VDDC_CHRGPMP_POWERUP;
1171                /* VDDC use VDDIO rail */
1172                lreg_ctrl |= SGTL5000_VDDC_ASSN_OVRD;
1173                lreg_ctrl |= SGTL5000_VDDC_MAN_ASSN_VDDIO <<
1174                            SGTL5000_VDDC_MAN_ASSN_SHIFT;
1175        }
1176
1177        snd_soc_write(codec, SGTL5000_CHIP_LINREG_CTRL, lreg_ctrl);
1178
1179        snd_soc_write(codec, SGTL5000_CHIP_ANA_POWER, ana_pwr);
1180
1181        /* set voltage to register */
1182        snd_soc_update_bits(codec, SGTL5000_CHIP_LINREG_CTRL,
1183                                SGTL5000_LINREG_VDDD_MASK, 0x8);
1184
1185        /*
1186         * if vddd linear reg has been enabled,
1187         * simple digital supply should be clear to get
1188         * proper VDDD voltage.
1189         */
1190        if (ana_pwr & SGTL5000_LINEREG_D_POWERUP)
1191                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1192                                SGTL5000_LINREG_SIMPLE_POWERUP,
1193                                0);
1194        else
1195                snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_POWER,
1196                                SGTL5000_LINREG_SIMPLE_POWERUP |
1197                                SGTL5000_STARTUP_POWERUP,
1198                                0);
1199
1200        /*
1201         * set ADC/DAC VAG to vdda / 2,
1202         * should stay in range (0.8v, 1.575v)
1203         */
1204        vag = vdda / 2;
1205        if (vag <= SGTL5000_ANA_GND_BASE)
1206                vag = 0;
1207        else if (vag >= SGTL5000_ANA_GND_BASE + SGTL5000_ANA_GND_STP *
1208                 (SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT))
1209                vag = SGTL5000_ANA_GND_MASK >> SGTL5000_ANA_GND_SHIFT;
1210        else
1211                vag = (vag - SGTL5000_ANA_GND_BASE) / SGTL5000_ANA_GND_STP;
1212
1213        snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1214                        SGTL5000_ANA_GND_MASK, vag << SGTL5000_ANA_GND_SHIFT);
1215
1216        /* set line out VAG to vddio / 2, in range (0.8v, 1.675v) */
1217        lo_vag = vddio / 2;
1218        if (lo_vag <= SGTL5000_LINE_OUT_GND_BASE)
1219                lo_vag = 0;
1220        else if (lo_vag >= SGTL5000_LINE_OUT_GND_BASE +
1221                SGTL5000_LINE_OUT_GND_STP * SGTL5000_LINE_OUT_GND_MAX)
1222                lo_vag = SGTL5000_LINE_OUT_GND_MAX;
1223        else
1224                lo_vag = (lo_vag - SGTL5000_LINE_OUT_GND_BASE) /
1225                    SGTL5000_LINE_OUT_GND_STP;
1226
1227        snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_CTRL,
1228                        SGTL5000_LINE_OUT_CURRENT_MASK |
1229                        SGTL5000_LINE_OUT_GND_MASK,
1230                        lo_vag << SGTL5000_LINE_OUT_GND_SHIFT |
1231                        SGTL5000_LINE_OUT_CURRENT_360u <<
1232                                SGTL5000_LINE_OUT_CURRENT_SHIFT);
1233
1234        /*
1235         * Set lineout output level in range (0..31)
1236         * the same value is used for right and left channel
1237         *
1238         * Searching for a suitable index solving this formula:
1239         * idx = 40 * log10(vag_val / lo_cagcntrl) + 15
1240         */
1241        vol_quot = (vag * 100) / lo_vag;
1242        lo_vol = 0;
1243        for (i = 0; i < ARRAY_SIZE(vol_quot_table); i++) {
1244                if (vol_quot >= vol_quot_table[i])
1245                        lo_vol = i;
1246                else
1247                        break;
1248        }
1249
1250        snd_soc_update_bits(codec, SGTL5000_CHIP_LINE_OUT_VOL,
1251                SGTL5000_LINE_OUT_VOL_RIGHT_MASK |
1252                SGTL5000_LINE_OUT_VOL_LEFT_MASK,
1253                lo_vol << SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT |
1254                lo_vol << SGTL5000_LINE_OUT_VOL_LEFT_SHIFT);
1255
1256        return 0;
1257}
1258
1259static int sgtl5000_replace_vddd_with_ldo(struct snd_soc_codec *codec)
1260{
1261        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1262        int ret;
1263
1264        /* set internal ldo to 1.2v */
1265        ret = ldo_regulator_register(codec, &ldo_init_data, LDO_VOLTAGE);
1266        if (ret) {
1267                dev_err(codec->dev,
1268                        "Failed to register vddd internal supplies: %d\n", ret);
1269                return ret;
1270        }
1271
1272        sgtl5000->supplies[VDDD].supply = LDO_CONSUMER_NAME;
1273
1274        dev_info(codec->dev, "Using internal LDO instead of VDDD\n");
1275        return 0;
1276}
1277
1278static int sgtl5000_enable_regulators(struct snd_soc_codec *codec)
1279{
1280        int ret;
1281        int i;
1282        int external_vddd = 0;
1283        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1284        struct regulator *vddd;
1285
1286        for (i = 0; i < ARRAY_SIZE(sgtl5000->supplies); i++)
1287                sgtl5000->supplies[i].supply = supply_names[i];
1288
1289        /* External VDDD only works before revision 0x11 */
1290        if (sgtl5000->revision < 0x11) {
1291                vddd = regulator_get_optional(codec->dev, "VDDD");
1292                if (IS_ERR(vddd)) {
1293                        /* See if it's just not registered yet */
1294                        if (PTR_ERR(vddd) == -EPROBE_DEFER)
1295                                return -EPROBE_DEFER;
1296                } else {
1297                        external_vddd = 1;
1298                        regulator_put(vddd);
1299                }
1300        }
1301
1302        if (!external_vddd) {
1303                ret = sgtl5000_replace_vddd_with_ldo(codec);
1304                if (ret)
1305                        return ret;
1306        }
1307
1308        ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(sgtl5000->supplies),
1309                                 sgtl5000->supplies);
1310        if (ret)
1311                goto err_ldo_remove;
1312
1313        ret = regulator_bulk_enable(ARRAY_SIZE(sgtl5000->supplies),
1314                                        sgtl5000->supplies);
1315        if (ret)
1316                goto err_regulator_free;
1317
1318        /* wait for all power rails bring up */
1319        udelay(10);
1320
1321        return 0;
1322
1323err_regulator_free:
1324        regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1325                                sgtl5000->supplies);
1326err_ldo_remove:
1327        if (!external_vddd)
1328                ldo_regulator_remove(codec);
1329        return ret;
1330
1331}
1332
1333static int sgtl5000_probe(struct snd_soc_codec *codec)
1334{
1335        int ret;
1336        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1337
1338        ret = sgtl5000_enable_regulators(codec);
1339        if (ret)
1340                return ret;
1341
1342        /* power up sgtl5000 */
1343        ret = sgtl5000_set_power_regs(codec);
1344        if (ret)
1345                goto err;
1346
1347        /* enable small pop, introduce 400ms delay in turning off */
1348        snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
1349                                SGTL5000_SMALL_POP, 1);
1350
1351        /* disable short cut detector */
1352        snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
1353
1354        /*
1355         * set i2s as default input of sound switch
1356         * TODO: add sound switch to control and dapm widge.
1357         */
1358        snd_soc_write(codec, SGTL5000_CHIP_SSS_CTRL,
1359                        SGTL5000_DAC_SEL_I2S_IN << SGTL5000_DAC_SEL_SHIFT);
1360        snd_soc_write(codec, SGTL5000_CHIP_DIG_POWER,
1361                        SGTL5000_ADC_EN | SGTL5000_DAC_EN);
1362
1363        /* enable dac volume ramp by default */
1364        snd_soc_write(codec, SGTL5000_CHIP_ADCDAC_CTRL,
1365                        SGTL5000_DAC_VOL_RAMP_EN |
1366                        SGTL5000_DAC_MUTE_RIGHT |
1367                        SGTL5000_DAC_MUTE_LEFT);
1368
1369        snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
1370
1371        snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
1372                        SGTL5000_HP_ZCD_EN |
1373                        SGTL5000_ADC_ZCD_EN);
1374
1375        snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1376                        SGTL5000_BIAS_R_MASK,
1377                        sgtl5000->micbias_resistor << SGTL5000_BIAS_R_SHIFT);
1378
1379        snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
1380                        SGTL5000_BIAS_VOLT_MASK,
1381                        sgtl5000->micbias_voltage << SGTL5000_BIAS_VOLT_SHIFT);
1382        /*
1383         * disable DAP
1384         * TODO:
1385         * Enable DAP in kcontrol and dapm.
1386         */
1387        snd_soc_write(codec, SGTL5000_DAP_CTRL, 0);
1388
1389        return 0;
1390
1391err:
1392        regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1393                                                sgtl5000->supplies);
1394        regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1395                                sgtl5000->supplies);
1396        ldo_regulator_remove(codec);
1397
1398        return ret;
1399}
1400
1401static int sgtl5000_remove(struct snd_soc_codec *codec)
1402{
1403        struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
1404
1405        regulator_bulk_disable(ARRAY_SIZE(sgtl5000->supplies),
1406                                                sgtl5000->supplies);
1407        regulator_bulk_free(ARRAY_SIZE(sgtl5000->supplies),
1408                                sgtl5000->supplies);
1409        ldo_regulator_remove(codec);
1410
1411        return 0;
1412}
1413
1414static struct snd_soc_codec_driver sgtl5000_driver = {
1415        .probe = sgtl5000_probe,
1416        .remove = sgtl5000_remove,
1417        .set_bias_level = sgtl5000_set_bias_level,
1418        .suspend_bias_off = true,
1419        .controls = sgtl5000_snd_controls,
1420        .num_controls = ARRAY_SIZE(sgtl5000_snd_controls),
1421        .dapm_widgets = sgtl5000_dapm_widgets,
1422        .num_dapm_widgets = ARRAY_SIZE(sgtl5000_dapm_widgets),
1423        .dapm_routes = sgtl5000_dapm_routes,
1424        .num_dapm_routes = ARRAY_SIZE(sgtl5000_dapm_routes),
1425};
1426
1427static const struct regmap_config sgtl5000_regmap = {
1428        .reg_bits = 16,
1429        .val_bits = 16,
1430        .reg_stride = 2,
1431
1432        .max_register = SGTL5000_MAX_REG_OFFSET,
1433        .volatile_reg = sgtl5000_volatile,
1434        .readable_reg = sgtl5000_readable,
1435
1436        .cache_type = REGCACHE_RBTREE,
1437        .reg_defaults = sgtl5000_reg_defaults,
1438        .num_reg_defaults = ARRAY_SIZE(sgtl5000_reg_defaults),
1439};
1440
1441/*
1442 * Write all the default values from sgtl5000_reg_defaults[] array into the
1443 * sgtl5000 registers, to make sure we always start with the sane registers
1444 * values as stated in the datasheet.
1445 *
1446 * Since sgtl5000 does not have a reset line, nor a reset command in software,
1447 * we follow this approach to guarantee we always start from the default values
1448 * and avoid problems like, not being able to probe after an audio playback
1449 * followed by a system reset or a 'reboot' command in Linux
1450 */
1451static int sgtl5000_fill_defaults(struct sgtl5000_priv *sgtl5000)
1452{
1453        int i, ret, val, index;
1454
1455        for (i = 0; i < ARRAY_SIZE(sgtl5000_reg_defaults); i++) {
1456                val = sgtl5000_reg_defaults[i].def;
1457                index = sgtl5000_reg_defaults[i].reg;
1458                ret = regmap_write(sgtl5000->regmap, index, val);
1459                if (ret)
1460                        return ret;
1461        }
1462
1463        return 0;
1464}
1465
1466static int sgtl5000_i2c_probe(struct i2c_client *client,
1467                              const struct i2c_device_id *id)
1468{
1469        struct sgtl5000_priv *sgtl5000;
1470        int ret, reg, rev;
1471        struct device_node *np = client->dev.of_node;
1472        u32 value;
1473
1474        sgtl5000 = devm_kzalloc(&client->dev, sizeof(*sgtl5000), GFP_KERNEL);
1475        if (!sgtl5000)
1476                return -ENOMEM;
1477
1478        sgtl5000->regmap = devm_regmap_init_i2c(client, &sgtl5000_regmap);
1479        if (IS_ERR(sgtl5000->regmap)) {
1480                ret = PTR_ERR(sgtl5000->regmap);
1481                dev_err(&client->dev, "Failed to allocate regmap: %d\n", ret);
1482                return ret;
1483        }
1484
1485        sgtl5000->mclk = devm_clk_get(&client->dev, NULL);
1486        if (IS_ERR(sgtl5000->mclk)) {
1487                ret = PTR_ERR(sgtl5000->mclk);
1488                dev_err(&client->dev, "Failed to get mclock: %d\n", ret);
1489                /* Defer the probe to see if the clk will be provided later */
1490                if (ret == -ENOENT)
1491                        return -EPROBE_DEFER;
1492                return ret;
1493        }
1494
1495        ret = clk_prepare_enable(sgtl5000->mclk);
1496        if (ret)
1497                return ret;
1498
1499        /* Need 8 clocks before I2C accesses */
1500        udelay(1);
1501
1502        /* read chip information */
1503        ret = regmap_read(sgtl5000->regmap, SGTL5000_CHIP_ID, &reg);
1504        if (ret)
1505                goto disable_clk;
1506
1507        if (((reg & SGTL5000_PARTID_MASK) >> SGTL5000_PARTID_SHIFT) !=
1508            SGTL5000_PARTID_PART_ID) {
1509                dev_err(&client->dev,
1510                        "Device with ID register %x is not a sgtl5000\n", reg);
1511                ret = -ENODEV;
1512                goto disable_clk;
1513        }
1514
1515        rev = (reg & SGTL5000_REVID_MASK) >> SGTL5000_REVID_SHIFT;
1516        dev_info(&client->dev, "sgtl5000 revision 0x%x\n", rev);
1517        sgtl5000->revision = rev;
1518
1519        if (np) {
1520                if (!of_property_read_u32(np,
1521                        "micbias-resistor-k-ohms", &value)) {
1522                        switch (value) {
1523                        case SGTL5000_MICBIAS_OFF:
1524                                sgtl5000->micbias_resistor = 0;
1525                                break;
1526                        case SGTL5000_MICBIAS_2K:
1527                                sgtl5000->micbias_resistor = 1;
1528                                break;
1529                        case SGTL5000_MICBIAS_4K:
1530                                sgtl5000->micbias_resistor = 2;
1531                                break;
1532                        case SGTL5000_MICBIAS_8K:
1533                                sgtl5000->micbias_resistor = 3;
1534                                break;
1535                        default:
1536                                sgtl5000->micbias_resistor = 2;
1537                                dev_err(&client->dev,
1538                                        "Unsuitable MicBias resistor\n");
1539                        }
1540                } else {
1541                        /* default is 4Kohms */
1542                        sgtl5000->micbias_resistor = 2;
1543                }
1544                if (!of_property_read_u32(np,
1545                        "micbias-voltage-m-volts", &value)) {
1546                        /* 1250mV => 0 */
1547                        /* steps of 250mV */
1548                        if ((value >= 1250) && (value <= 3000))
1549                                sgtl5000->micbias_voltage = (value / 250) - 5;
1550                        else {
1551                                sgtl5000->micbias_voltage = 0;
1552                                dev_err(&client->dev,
1553                                        "Unsuitable MicBias voltage\n");
1554                        }
1555                } else {
1556                        sgtl5000->micbias_voltage = 0;
1557                }
1558        }
1559
1560        i2c_set_clientdata(client, sgtl5000);
1561
1562        /* Ensure sgtl5000 will start with sane register values */
1563        ret = sgtl5000_fill_defaults(sgtl5000);
1564        if (ret)
1565                goto disable_clk;
1566
1567        ret = snd_soc_register_codec(&client->dev,
1568                        &sgtl5000_driver, &sgtl5000_dai, 1);
1569        if (ret)
1570                goto disable_clk;
1571
1572        return 0;
1573
1574disable_clk:
1575        clk_disable_unprepare(sgtl5000->mclk);
1576        return ret;
1577}
1578
1579static int sgtl5000_i2c_remove(struct i2c_client *client)
1580{
1581        struct sgtl5000_priv *sgtl5000 = i2c_get_clientdata(client);
1582
1583        snd_soc_unregister_codec(&client->dev);
1584        clk_disable_unprepare(sgtl5000->mclk);
1585        return 0;
1586}
1587
1588static const struct i2c_device_id sgtl5000_id[] = {
1589        {"sgtl5000", 0},
1590        {},
1591};
1592
1593MODULE_DEVICE_TABLE(i2c, sgtl5000_id);
1594
1595static const struct of_device_id sgtl5000_dt_ids[] = {
1596        { .compatible = "fsl,sgtl5000", },
1597        { /* sentinel */ }
1598};
1599MODULE_DEVICE_TABLE(of, sgtl5000_dt_ids);
1600
1601static struct i2c_driver sgtl5000_i2c_driver = {
1602        .driver = {
1603                   .name = "sgtl5000",
1604                   .of_match_table = sgtl5000_dt_ids,
1605                   },
1606        .probe = sgtl5000_i2c_probe,
1607        .remove = sgtl5000_i2c_remove,
1608        .id_table = sgtl5000_id,
1609};
1610
1611module_i2c_driver(sgtl5000_i2c_driver);
1612
1613MODULE_DESCRIPTION("Freescale SGTL5000 ALSA SoC Codec Driver");
1614MODULE_AUTHOR("Zeng Zhaoming <zengzm.kernel@gmail.com>");
1615MODULE_LICENSE("GPL");
1616
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