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37#include <linux/delay.h>
38#include <linux/interrupt.h>
39#include <linux/kernel.h>
40#include <linux/module.h>
41#include <linux/dma-mapping.h>
42#include <linux/moduleparam.h>
43#include <linux/init.h>
44#include <linux/slab.h>
45#include <linux/pci.h>
46#include <linux/mutex.h>
47#include <linux/reboot.h>
48#include <linux/io.h>
49#ifdef CONFIG_X86
50
51#include <asm/pgtable.h>
52#include <asm/cacheflush.h>
53#endif
54#include <sound/core.h>
55#include <sound/initval.h>
56#include "hda_codec.h"
57
58
59static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
60static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
61static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
62static char *model[SNDRV_CARDS];
63static int position_fix[SNDRV_CARDS];
64static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
65static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
66static int probe_only[SNDRV_CARDS];
67static int single_cmd;
68static int enable_msi = -1;
69#ifdef CONFIG_SND_HDA_PATCH_LOADER
70static char *patch[SNDRV_CARDS];
71#endif
72#ifdef CONFIG_SND_HDA_INPUT_BEEP
73static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
74 CONFIG_SND_HDA_INPUT_BEEP_MODE};
75#endif
76
77module_param_array(index, int, NULL, 0444);
78MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
79module_param_array(id, charp, NULL, 0444);
80MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
81module_param_array(enable, bool, NULL, 0444);
82MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
83module_param_array(model, charp, NULL, 0444);
84MODULE_PARM_DESC(model, "Use the given board model.");
85module_param_array(position_fix, int, NULL, 0444);
86MODULE_PARM_DESC(position_fix, "DMA pointer read method."
87 "(0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO).");
88module_param_array(bdl_pos_adj, int, NULL, 0644);
89MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
90module_param_array(probe_mask, int, NULL, 0444);
91MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
92module_param_array(probe_only, int, NULL, 0444);
93MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
94module_param(single_cmd, bool, 0444);
95MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
96 "(for debugging only).");
97module_param(enable_msi, int, 0444);
98MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
99#ifdef CONFIG_SND_HDA_PATCH_LOADER
100module_param_array(patch, charp, NULL, 0444);
101MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
102#endif
103#ifdef CONFIG_SND_HDA_INPUT_BEEP
104module_param_array(beep_mode, int, NULL, 0444);
105MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
106 "(0=off, 1=on, 2=mute switch on/off) (default=1).");
107#endif
108
109#ifdef CONFIG_SND_HDA_POWER_SAVE
110static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
111module_param(power_save, int, 0644);
112MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
113 "(in second, 0 = disable).");
114
115
116
117
118
119static int power_save_controller = 1;
120module_param(power_save_controller, bool, 0644);
121MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
122#endif
123
124static int align_buffer_size = 1;
125module_param(align_buffer_size, bool, 0644);
126MODULE_PARM_DESC(align_buffer_size,
127 "Force buffer and period sizes to be multiple of 128 bytes.");
128
129#ifdef CONFIG_X86
130static bool hda_snoop = true;
131module_param_named(snoop, hda_snoop, bool, 0444);
132MODULE_PARM_DESC(snoop, "Enable/disable snooping");
133#define azx_snoop(chip) (chip)->snoop
134#else
135#define hda_snoop true
136#define azx_snoop(chip) true
137#endif
138
139
140MODULE_LICENSE("GPL");
141MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
142 "{Intel, ICH6M},"
143 "{Intel, ICH7},"
144 "{Intel, ESB2},"
145 "{Intel, ICH8},"
146 "{Intel, ICH9},"
147 "{Intel, ICH10},"
148 "{Intel, PCH},"
149 "{Intel, CPT},"
150 "{Intel, PPT},"
151 "{Intel, PBG},"
152 "{Intel, SCH},"
153 "{ATI, SB450},"
154 "{ATI, SB600},"
155 "{ATI, RS600},"
156 "{ATI, RS690},"
157 "{ATI, RS780},"
158 "{ATI, R600},"
159 "{ATI, RV630},"
160 "{ATI, RV610},"
161 "{ATI, RV670},"
162 "{ATI, RV635},"
163 "{ATI, RV620},"
164 "{ATI, RV770},"
165 "{VIA, VT8251},"
166 "{VIA, VT8237A},"
167 "{SiS, SIS966},"
168 "{ULI, M5461}}");
169MODULE_DESCRIPTION("Intel HDA driver");
170
171#ifdef CONFIG_SND_VERBOSE_PRINTK
172#define SFX
173#else
174#define SFX "hda-intel: "
175#endif
176
177
178
179
180#define ICH6_REG_GCAP 0x00
181#define ICH6_GCAP_64OK (1 << 0)
182#define ICH6_GCAP_NSDO (3 << 1)
183#define ICH6_GCAP_BSS (31 << 3)
184#define ICH6_GCAP_ISS (15 << 8)
185#define ICH6_GCAP_OSS (15 << 12)
186#define ICH6_REG_VMIN 0x02
187#define ICH6_REG_VMAJ 0x03
188#define ICH6_REG_OUTPAY 0x04
189#define ICH6_REG_INPAY 0x06
190#define ICH6_REG_GCTL 0x08
191#define ICH6_GCTL_RESET (1 << 0)
192#define ICH6_GCTL_FCNTRL (1 << 1)
193#define ICH6_GCTL_UNSOL (1 << 8)
194#define ICH6_REG_WAKEEN 0x0c
195#define ICH6_REG_STATESTS 0x0e
196#define ICH6_REG_GSTS 0x10
197#define ICH6_GSTS_FSTS (1 << 1)
198#define ICH6_REG_INTCTL 0x20
199#define ICH6_REG_INTSTS 0x24
200#define ICH6_REG_WALLCLK 0x30
201#define ICH6_REG_OLD_SSYNC 0x34
202#define ICH6_REG_SSYNC 0x38
203#define ICH6_REG_CORBLBASE 0x40
204#define ICH6_REG_CORBUBASE 0x44
205#define ICH6_REG_CORBWP 0x48
206#define ICH6_REG_CORBRP 0x4a
207#define ICH6_CORBRP_RST (1 << 15)
208#define ICH6_REG_CORBCTL 0x4c
209#define ICH6_CORBCTL_RUN (1 << 1)
210#define ICH6_CORBCTL_CMEIE (1 << 0)
211#define ICH6_REG_CORBSTS 0x4d
212#define ICH6_CORBSTS_CMEI (1 << 0)
213#define ICH6_REG_CORBSIZE 0x4e
214
215#define ICH6_REG_RIRBLBASE 0x50
216#define ICH6_REG_RIRBUBASE 0x54
217#define ICH6_REG_RIRBWP 0x58
218#define ICH6_RIRBWP_RST (1 << 15)
219#define ICH6_REG_RINTCNT 0x5a
220#define ICH6_REG_RIRBCTL 0x5c
221#define ICH6_RBCTL_IRQ_EN (1 << 0)
222#define ICH6_RBCTL_DMA_EN (1 << 1)
223#define ICH6_RBCTL_OVERRUN_EN (1 << 2)
224#define ICH6_REG_RIRBSTS 0x5d
225#define ICH6_RBSTS_IRQ (1 << 0)
226#define ICH6_RBSTS_OVERRUN (1 << 2)
227#define ICH6_REG_RIRBSIZE 0x5e
228
229#define ICH6_REG_IC 0x60
230#define ICH6_REG_IR 0x64
231#define ICH6_REG_IRS 0x68
232#define ICH6_IRS_VALID (1<<1)
233#define ICH6_IRS_BUSY (1<<0)
234
235#define ICH6_REG_DPLBASE 0x70
236#define ICH6_REG_DPUBASE 0x74
237#define ICH6_DPLBASE_ENABLE 0x1
238
239
240enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
241
242
243#define ICH6_REG_SD_CTL 0x00
244#define ICH6_REG_SD_STS 0x03
245#define ICH6_REG_SD_LPIB 0x04
246#define ICH6_REG_SD_CBL 0x08
247#define ICH6_REG_SD_LVI 0x0c
248#define ICH6_REG_SD_FIFOW 0x0e
249#define ICH6_REG_SD_FIFOSIZE 0x10
250#define ICH6_REG_SD_FORMAT 0x12
251#define ICH6_REG_SD_BDLPL 0x18
252#define ICH6_REG_SD_BDLPU 0x1c
253
254
255#define ICH6_PCIREG_TCSEL 0x44
256
257
258
259
260
261
262
263#define ICH6_NUM_CAPTURE 4
264#define ICH6_NUM_PLAYBACK 4
265
266
267#define ULI_NUM_CAPTURE 5
268#define ULI_NUM_PLAYBACK 6
269
270
271#define ATIHDMI_NUM_CAPTURE 0
272#define ATIHDMI_NUM_PLAYBACK 1
273
274
275#define TERA_NUM_CAPTURE 3
276#define TERA_NUM_PLAYBACK 4
277
278
279#define MAX_AZX_DEV 16
280
281
282#define BDL_SIZE 4096
283#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
284#define AZX_MAX_FRAG 32
285
286#define AZX_MAX_BUF_SIZE (1024*1024*1024)
287
288
289#define RIRB_INT_RESPONSE 0x01
290#define RIRB_INT_OVERRUN 0x04
291#define RIRB_INT_MASK 0x05
292
293
294#define AZX_MAX_CODECS 8
295#define AZX_DEFAULT_CODECS 4
296#define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
297
298
299#define SD_CTL_STREAM_RESET 0x01
300#define SD_CTL_DMA_START 0x02
301#define SD_CTL_STRIPE (3 << 16)
302#define SD_CTL_TRAFFIC_PRIO (1 << 18)
303#define SD_CTL_DIR (1 << 19)
304#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
305#define SD_CTL_STREAM_TAG_SHIFT 20
306
307
308#define SD_INT_DESC_ERR 0x10
309#define SD_INT_FIFO_ERR 0x08
310#define SD_INT_COMPLETE 0x04
311#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
312 SD_INT_COMPLETE)
313
314
315#define SD_STS_FIFO_READY 0x20
316
317
318#define ICH6_INT_ALL_STREAM 0xff
319#define ICH6_INT_CTRL_EN 0x40000000
320#define ICH6_INT_GLOBAL_EN 0x80000000
321
322
323#define ICH6_MAX_CORB_ENTRIES 256
324#define ICH6_MAX_RIRB_ENTRIES 256
325
326
327enum {
328 POS_FIX_AUTO,
329 POS_FIX_LPIB,
330 POS_FIX_POSBUF,
331 POS_FIX_VIACOMBO,
332};
333
334
335#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
336#define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
337
338
339#define NVIDIA_HDA_TRANSREG_ADDR 0x4e
340#define NVIDIA_HDA_ENABLE_COHBITS 0x0f
341#define NVIDIA_HDA_ISTRM_COH 0x4d
342#define NVIDIA_HDA_OSTRM_COH 0x4c
343#define NVIDIA_HDA_ENABLE_COHBIT 0x01
344
345
346#define INTEL_SCH_HDA_DEVC 0x78
347#define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
348
349
350#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
351
352#define VIA_HDAC_DEVICE_ID 0x3288
353
354
355#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
356
357
358
359
360struct azx_dev {
361 struct snd_dma_buffer bdl;
362 u32 *posbuf;
363
364 unsigned int bufsize;
365 unsigned int period_bytes;
366 unsigned int frags;
367 unsigned int fifo_size;
368 unsigned long start_wallclk;
369 unsigned long period_wallclk;
370
371 void __iomem *sd_addr;
372
373 u32 sd_int_sta_mask;
374
375
376 struct snd_pcm_substream *substream;
377
378
379 unsigned int format_val;
380
381
382 unsigned char stream_tag;
383 unsigned char index;
384 int assigned_key;
385
386 unsigned int opened :1;
387 unsigned int running :1;
388 unsigned int irq_pending :1;
389
390
391
392
393
394 unsigned int insufficient :1;
395 unsigned int wc_marked:1;
396};
397
398
399struct azx_rb {
400 u32 *buf;
401
402
403 dma_addr_t addr;
404
405 unsigned short rp, wp;
406 int cmds[AZX_MAX_CODECS];
407 u32 res[AZX_MAX_CODECS];
408};
409
410struct azx {
411 struct snd_card *card;
412 struct pci_dev *pci;
413 int dev_index;
414
415
416 int driver_type;
417 unsigned int driver_caps;
418 int playback_streams;
419 int playback_index_offset;
420 int capture_streams;
421 int capture_index_offset;
422 int num_streams;
423
424
425 unsigned long addr;
426 void __iomem *remap_addr;
427 int irq;
428
429
430 spinlock_t reg_lock;
431 struct mutex open_mutex;
432
433
434 struct azx_dev *azx_dev;
435
436
437 struct snd_pcm *pcm[HDA_MAX_PCMS];
438
439
440 unsigned short codec_mask;
441 int codec_probe_mask;
442 struct hda_bus *bus;
443 unsigned int beep_mode;
444
445
446 struct azx_rb corb;
447 struct azx_rb rirb;
448
449
450 struct snd_dma_buffer rb;
451 struct snd_dma_buffer posbuf;
452
453
454 int position_fix[2];
455 int poll_count;
456 unsigned int running :1;
457 unsigned int initialized :1;
458 unsigned int single_cmd :1;
459 unsigned int polling_mode :1;
460 unsigned int msi :1;
461 unsigned int irq_pending_warned :1;
462 unsigned int probing :1;
463 unsigned int snoop:1;
464 unsigned int align_buffer_size:1;
465
466
467 unsigned int last_cmd[AZX_MAX_CODECS];
468
469
470 struct work_struct irq_pending_work;
471
472
473 struct notifier_block reboot_notifier;
474};
475
476
477enum {
478 AZX_DRIVER_ICH,
479 AZX_DRIVER_PCH,
480 AZX_DRIVER_SCH,
481 AZX_DRIVER_ATI,
482 AZX_DRIVER_ATIHDMI,
483 AZX_DRIVER_VIA,
484 AZX_DRIVER_SIS,
485 AZX_DRIVER_ULI,
486 AZX_DRIVER_NVIDIA,
487 AZX_DRIVER_TERA,
488 AZX_DRIVER_CTX,
489 AZX_DRIVER_GENERIC,
490 AZX_NUM_DRIVERS,
491};
492
493
494
495#define AZX_DCAPS_NO_TCSEL (1 << 8)
496#define AZX_DCAPS_NO_MSI (1 << 9)
497#define AZX_DCAPS_ATI_SNOOP (1 << 10)
498#define AZX_DCAPS_NVIDIA_SNOOP (1 << 11)
499#define AZX_DCAPS_SCH_SNOOP (1 << 12)
500#define AZX_DCAPS_RIRB_DELAY (1 << 13)
501#define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)
502#define AZX_DCAPS_CTX_WORKAROUND (1 << 15)
503#define AZX_DCAPS_POSFIX_LPIB (1 << 16)
504#define AZX_DCAPS_POSFIX_VIA (1 << 17)
505#define AZX_DCAPS_NO_64BIT (1 << 18)
506#define AZX_DCAPS_SYNC_WRITE (1 << 19)
507#define AZX_DCAPS_OLD_SSYNC (1 << 20)
508#define AZX_DCAPS_BUFSIZE (1 << 21)
509
510
511#define AZX_DCAPS_PRESET_ATI_SB \
512 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
513 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
514
515
516#define AZX_DCAPS_PRESET_ATI_HDMI \
517 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
518
519
520#define AZX_DCAPS_PRESET_NVIDIA \
521 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI)
522
523static char *driver_short_names[] __devinitdata = {
524 [AZX_DRIVER_ICH] = "HDA Intel",
525 [AZX_DRIVER_PCH] = "HDA Intel PCH",
526 [AZX_DRIVER_SCH] = "HDA Intel MID",
527 [AZX_DRIVER_ATI] = "HDA ATI SB",
528 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
529 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
530 [AZX_DRIVER_SIS] = "HDA SIS966",
531 [AZX_DRIVER_ULI] = "HDA ULI M5461",
532 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
533 [AZX_DRIVER_TERA] = "HDA Teradici",
534 [AZX_DRIVER_CTX] = "HDA Creative",
535 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
536};
537
538
539
540
541#define azx_writel(chip,reg,value) \
542 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
543#define azx_readl(chip,reg) \
544 readl((chip)->remap_addr + ICH6_REG_##reg)
545#define azx_writew(chip,reg,value) \
546 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
547#define azx_readw(chip,reg) \
548 readw((chip)->remap_addr + ICH6_REG_##reg)
549#define azx_writeb(chip,reg,value) \
550 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
551#define azx_readb(chip,reg) \
552 readb((chip)->remap_addr + ICH6_REG_##reg)
553
554#define azx_sd_writel(dev,reg,value) \
555 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
556#define azx_sd_readl(dev,reg) \
557 readl((dev)->sd_addr + ICH6_REG_##reg)
558#define azx_sd_writew(dev,reg,value) \
559 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
560#define azx_sd_readw(dev,reg) \
561 readw((dev)->sd_addr + ICH6_REG_##reg)
562#define azx_sd_writeb(dev,reg,value) \
563 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
564#define azx_sd_readb(dev,reg) \
565 readb((dev)->sd_addr + ICH6_REG_##reg)
566
567
568#define get_azx_dev(substream) (substream->runtime->private_data)
569
570#ifdef CONFIG_X86
571static void __mark_pages_wc(struct azx *chip, void *addr, size_t size, bool on)
572{
573 if (azx_snoop(chip))
574 return;
575 if (addr && size) {
576 int pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
577 if (on)
578 set_memory_wc((unsigned long)addr, pages);
579 else
580 set_memory_wb((unsigned long)addr, pages);
581 }
582}
583
584static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
585 bool on)
586{
587 __mark_pages_wc(chip, buf->area, buf->bytes, on);
588}
589static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
590 struct snd_pcm_runtime *runtime, bool on)
591{
592 if (azx_dev->wc_marked != on) {
593 __mark_pages_wc(chip, runtime->dma_area, runtime->dma_bytes, on);
594 azx_dev->wc_marked = on;
595 }
596}
597#else
598
599static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
600 bool on)
601{
602}
603static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
604 struct snd_pcm_runtime *runtime, bool on)
605{
606}
607#endif
608
609static int azx_acquire_irq(struct azx *chip, int do_disconnect);
610static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
611
612
613
614
615
616
617
618static int azx_alloc_cmd_io(struct azx *chip)
619{
620 int err;
621
622
623 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
624 snd_dma_pci_data(chip->pci),
625 PAGE_SIZE, &chip->rb);
626 if (err < 0) {
627 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
628 return err;
629 }
630 mark_pages_wc(chip, &chip->rb, true);
631 return 0;
632}
633
634static void azx_init_cmd_io(struct azx *chip)
635{
636 spin_lock_irq(&chip->reg_lock);
637
638 chip->corb.addr = chip->rb.addr;
639 chip->corb.buf = (u32 *)chip->rb.area;
640 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
641 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
642
643
644 azx_writeb(chip, CORBSIZE, 0x02);
645
646 azx_writew(chip, CORBWP, 0);
647
648 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
649
650 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
651
652
653 chip->rirb.addr = chip->rb.addr + 2048;
654 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
655 chip->rirb.wp = chip->rirb.rp = 0;
656 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
657 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
658 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
659
660
661 azx_writeb(chip, RIRBSIZE, 0x02);
662
663 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
664
665 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
666 azx_writew(chip, RINTCNT, 0xc0);
667 else
668 azx_writew(chip, RINTCNT, 1);
669
670 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
671 spin_unlock_irq(&chip->reg_lock);
672}
673
674static void azx_free_cmd_io(struct azx *chip)
675{
676 spin_lock_irq(&chip->reg_lock);
677
678 azx_writeb(chip, RIRBCTL, 0);
679 azx_writeb(chip, CORBCTL, 0);
680 spin_unlock_irq(&chip->reg_lock);
681}
682
683static unsigned int azx_command_addr(u32 cmd)
684{
685 unsigned int addr = cmd >> 28;
686
687 if (addr >= AZX_MAX_CODECS) {
688 snd_BUG();
689 addr = 0;
690 }
691
692 return addr;
693}
694
695static unsigned int azx_response_addr(u32 res)
696{
697 unsigned int addr = res & 0xf;
698
699 if (addr >= AZX_MAX_CODECS) {
700 snd_BUG();
701 addr = 0;
702 }
703
704 return addr;
705}
706
707
708static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
709{
710 struct azx *chip = bus->private_data;
711 unsigned int addr = azx_command_addr(val);
712 unsigned int wp;
713
714 spin_lock_irq(&chip->reg_lock);
715
716
717 wp = azx_readb(chip, CORBWP);
718 wp++;
719 wp %= ICH6_MAX_CORB_ENTRIES;
720
721 chip->rirb.cmds[addr]++;
722 chip->corb.buf[wp] = cpu_to_le32(val);
723 azx_writel(chip, CORBWP, wp);
724
725 spin_unlock_irq(&chip->reg_lock);
726
727 return 0;
728}
729
730#define ICH6_RIRB_EX_UNSOL_EV (1<<4)
731
732
733static void azx_update_rirb(struct azx *chip)
734{
735 unsigned int rp, wp;
736 unsigned int addr;
737 u32 res, res_ex;
738
739 wp = azx_readb(chip, RIRBWP);
740 if (wp == chip->rirb.wp)
741 return;
742 chip->rirb.wp = wp;
743
744 while (chip->rirb.rp != wp) {
745 chip->rirb.rp++;
746 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
747
748 rp = chip->rirb.rp << 1;
749 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
750 res = le32_to_cpu(chip->rirb.buf[rp]);
751 addr = azx_response_addr(res_ex);
752 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
753 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
754 else if (chip->rirb.cmds[addr]) {
755 chip->rirb.res[addr] = res;
756 smp_wmb();
757 chip->rirb.cmds[addr]--;
758 } else
759 snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
760 "last cmd=%#08x\n",
761 res, res_ex,
762 chip->last_cmd[addr]);
763 }
764}
765
766
767static unsigned int azx_rirb_get_response(struct hda_bus *bus,
768 unsigned int addr)
769{
770 struct azx *chip = bus->private_data;
771 unsigned long timeout;
772 int do_poll = 0;
773
774 again:
775 timeout = jiffies + msecs_to_jiffies(1000);
776 for (;;) {
777 if (chip->polling_mode || do_poll) {
778 spin_lock_irq(&chip->reg_lock);
779 azx_update_rirb(chip);
780 spin_unlock_irq(&chip->reg_lock);
781 }
782 if (!chip->rirb.cmds[addr]) {
783 smp_rmb();
784 bus->rirb_error = 0;
785
786 if (!do_poll)
787 chip->poll_count = 0;
788 return chip->rirb.res[addr];
789 }
790 if (time_after(jiffies, timeout))
791 break;
792 if (bus->needs_damn_long_delay)
793 msleep(2);
794 else {
795 udelay(10);
796 cond_resched();
797 }
798 }
799
800 if (!chip->polling_mode && chip->poll_count < 2) {
801 snd_printdd(SFX "azx_get_response timeout, "
802 "polling the codec once: last cmd=0x%08x\n",
803 chip->last_cmd[addr]);
804 do_poll = 1;
805 chip->poll_count++;
806 goto again;
807 }
808
809
810 if (!chip->polling_mode) {
811 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
812 "switching to polling mode: last cmd=0x%08x\n",
813 chip->last_cmd[addr]);
814 chip->polling_mode = 1;
815 goto again;
816 }
817
818 if (chip->msi) {
819 snd_printk(KERN_WARNING SFX "No response from codec, "
820 "disabling MSI: last cmd=0x%08x\n",
821 chip->last_cmd[addr]);
822 free_irq(chip->irq, chip);
823 chip->irq = -1;
824 pci_disable_msi(chip->pci);
825 chip->msi = 0;
826 if (azx_acquire_irq(chip, 1) < 0) {
827 bus->rirb_error = 1;
828 return -1;
829 }
830 goto again;
831 }
832
833 if (chip->probing) {
834
835
836
837
838 return -1;
839 }
840
841
842
843
844 bus->rirb_error = 1;
845 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
846 bus->response_reset = 1;
847 return -1;
848 }
849
850 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
851 "switching to single_cmd mode: last cmd=0x%08x\n",
852 chip->last_cmd[addr]);
853 chip->single_cmd = 1;
854 bus->response_reset = 0;
855
856 azx_free_cmd_io(chip);
857
858 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
859 return -1;
860}
861
862
863
864
865
866
867
868
869
870
871
872
873static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
874{
875 int timeout = 50;
876
877 while (timeout--) {
878
879 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
880
881 chip->rirb.res[addr] = azx_readl(chip, IR);
882 return 0;
883 }
884 udelay(1);
885 }
886 if (printk_ratelimit())
887 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
888 azx_readw(chip, IRS));
889 chip->rirb.res[addr] = -1;
890 return -EIO;
891}
892
893
894static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
895{
896 struct azx *chip = bus->private_data;
897 unsigned int addr = azx_command_addr(val);
898 int timeout = 50;
899
900 bus->rirb_error = 0;
901 while (timeout--) {
902
903 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
904
905 azx_writew(chip, IRS, azx_readw(chip, IRS) |
906 ICH6_IRS_VALID);
907 azx_writel(chip, IC, val);
908 azx_writew(chip, IRS, azx_readw(chip, IRS) |
909 ICH6_IRS_BUSY);
910 return azx_single_wait_for_response(chip, addr);
911 }
912 udelay(1);
913 }
914 if (printk_ratelimit())
915 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
916 azx_readw(chip, IRS), val);
917 return -EIO;
918}
919
920
921static unsigned int azx_single_get_response(struct hda_bus *bus,
922 unsigned int addr)
923{
924 struct azx *chip = bus->private_data;
925 return chip->rirb.res[addr];
926}
927
928
929
930
931
932
933
934
935
936static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
937{
938 struct azx *chip = bus->private_data;
939
940 chip->last_cmd[azx_command_addr(val)] = val;
941 if (chip->single_cmd)
942 return azx_single_send_cmd(bus, val);
943 else
944 return azx_corb_send_cmd(bus, val);
945}
946
947
948static unsigned int azx_get_response(struct hda_bus *bus,
949 unsigned int addr)
950{
951 struct azx *chip = bus->private_data;
952 if (chip->single_cmd)
953 return azx_single_get_response(bus, addr);
954 else
955 return azx_rirb_get_response(bus, addr);
956}
957
958#ifdef CONFIG_SND_HDA_POWER_SAVE
959static void azx_power_notify(struct hda_bus *bus);
960#endif
961
962
963static int azx_reset(struct azx *chip, int full_reset)
964{
965 int count;
966
967 if (!full_reset)
968 goto __skip;
969
970
971 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
972
973
974 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
975
976 count = 50;
977 while (azx_readb(chip, GCTL) && --count)
978 msleep(1);
979
980
981
982
983 msleep(1);
984
985
986 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
987
988 count = 50;
989 while (!azx_readb(chip, GCTL) && --count)
990 msleep(1);
991
992
993 msleep(1);
994
995 __skip:
996
997 if (!azx_readb(chip, GCTL)) {
998 snd_printd(SFX "azx_reset: controller not ready!\n");
999 return -EBUSY;
1000 }
1001
1002
1003 if (!chip->single_cmd)
1004 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1005 ICH6_GCTL_UNSOL);
1006
1007
1008 if (!chip->codec_mask) {
1009 chip->codec_mask = azx_readw(chip, STATESTS);
1010 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
1011 }
1012
1013 return 0;
1014}
1015
1016
1017
1018
1019
1020
1021
1022static void azx_int_enable(struct azx *chip)
1023{
1024
1025 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1026 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1027}
1028
1029
1030static void azx_int_disable(struct azx *chip)
1031{
1032 int i;
1033
1034
1035 for (i = 0; i < chip->num_streams; i++) {
1036 struct azx_dev *azx_dev = &chip->azx_dev[i];
1037 azx_sd_writeb(azx_dev, SD_CTL,
1038 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1039 }
1040
1041
1042 azx_writeb(chip, INTCTL, 0);
1043
1044
1045 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1046 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1047}
1048
1049
1050static void azx_int_clear(struct azx *chip)
1051{
1052 int i;
1053
1054
1055 for (i = 0; i < chip->num_streams; i++) {
1056 struct azx_dev *azx_dev = &chip->azx_dev[i];
1057 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1058 }
1059
1060
1061 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1062
1063
1064 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1065
1066
1067 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1068}
1069
1070
1071static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1072{
1073
1074
1075
1076 azx_dev->insufficient = 1;
1077
1078
1079 azx_writel(chip, INTCTL,
1080 azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1081
1082 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1083 SD_CTL_DMA_START | SD_INT_MASK);
1084}
1085
1086
1087static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1088{
1089 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1090 ~(SD_CTL_DMA_START | SD_INT_MASK));
1091 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1092}
1093
1094
1095static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1096{
1097 azx_stream_clear(chip, azx_dev);
1098
1099 azx_writel(chip, INTCTL,
1100 azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1101}
1102
1103
1104
1105
1106
1107static void azx_init_chip(struct azx *chip, int full_reset)
1108{
1109 if (chip->initialized)
1110 return;
1111
1112
1113 azx_reset(chip, full_reset);
1114
1115
1116 azx_int_clear(chip);
1117 azx_int_enable(chip);
1118
1119
1120 if (!chip->single_cmd)
1121 azx_init_cmd_io(chip);
1122
1123
1124 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1125 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1126
1127 chip->initialized = 1;
1128}
1129
1130
1131
1132
1133
1134static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1135 unsigned char mask, unsigned char val)
1136{
1137 unsigned char data;
1138
1139 pci_read_config_byte(pci, reg, &data);
1140 data &= ~mask;
1141 data |= (val & mask);
1142 pci_write_config_byte(pci, reg, data);
1143}
1144
1145static void azx_init_pci(struct azx *chip)
1146{
1147
1148 if (chip->snoop && chip->driver_type == AZX_DRIVER_VIA) {
1149 u8 snoop;
1150 pci_read_config_byte(chip->pci, 0x42, &snoop);
1151 if (!(snoop & 0x80) && chip->pci->revision == 0x30) {
1152 chip->snoop = 0;
1153 snd_printdd(SFX "Force to non-snoop mode\n");
1154 }
1155 }
1156
1157
1158
1159
1160
1161
1162
1163 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1164 snd_printdd(SFX "Clearing TCSEL\n");
1165 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1166 }
1167
1168
1169
1170
1171 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1172 snd_printdd(SFX "Setting ATI snoop: %d\n", azx_snoop(chip));
1173 update_pci_byte(chip->pci,
1174 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1175 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1176 }
1177
1178
1179 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1180 snd_printdd(SFX "Setting Nvidia snoop: %d\n", azx_snoop(chip));
1181 update_pci_byte(chip->pci,
1182 NVIDIA_HDA_TRANSREG_ADDR,
1183 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1184 update_pci_byte(chip->pci,
1185 NVIDIA_HDA_ISTRM_COH,
1186 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1187 update_pci_byte(chip->pci,
1188 NVIDIA_HDA_OSTRM_COH,
1189 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1190 }
1191
1192
1193 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1194 unsigned short snoop;
1195 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1196 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1197 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1198 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1199 if (!azx_snoop(chip))
1200 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1201 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1202 pci_read_config_word(chip->pci,
1203 INTEL_SCH_HDA_DEVC, &snoop);
1204 }
1205 snd_printdd(SFX "SCH snoop: %s\n",
1206 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1207 ? "Disabled" : "Enabled");
1208 }
1209}
1210
1211
1212static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1213
1214
1215
1216
1217static irqreturn_t azx_interrupt(int irq, void *dev_id)
1218{
1219 struct azx *chip = dev_id;
1220 struct azx_dev *azx_dev;
1221 u32 status;
1222 u8 sd_status;
1223 int i, ok;
1224
1225 spin_lock(&chip->reg_lock);
1226
1227 status = azx_readl(chip, INTSTS);
1228 if (status == 0) {
1229 spin_unlock(&chip->reg_lock);
1230 return IRQ_NONE;
1231 }
1232
1233 for (i = 0; i < chip->num_streams; i++) {
1234 azx_dev = &chip->azx_dev[i];
1235 if (status & azx_dev->sd_int_sta_mask) {
1236 sd_status = azx_sd_readb(azx_dev, SD_STS);
1237 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1238 if (!azx_dev->substream || !azx_dev->running ||
1239 !(sd_status & SD_INT_COMPLETE))
1240 continue;
1241
1242 ok = azx_position_ok(chip, azx_dev);
1243 if (ok == 1) {
1244 azx_dev->irq_pending = 0;
1245 spin_unlock(&chip->reg_lock);
1246 snd_pcm_period_elapsed(azx_dev->substream);
1247 spin_lock(&chip->reg_lock);
1248 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1249
1250 azx_dev->irq_pending = 1;
1251 queue_work(chip->bus->workq,
1252 &chip->irq_pending_work);
1253 }
1254 }
1255 }
1256
1257
1258 status = azx_readb(chip, RIRBSTS);
1259 if (status & RIRB_INT_MASK) {
1260 if (status & RIRB_INT_RESPONSE) {
1261 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1262 udelay(80);
1263 azx_update_rirb(chip);
1264 }
1265 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1266 }
1267
1268#if 0
1269
1270 if (azx_readb(chip, STATESTS) & 0x04)
1271 azx_writeb(chip, STATESTS, 0x04);
1272#endif
1273 spin_unlock(&chip->reg_lock);
1274
1275 return IRQ_HANDLED;
1276}
1277
1278
1279
1280
1281
1282static int setup_bdle(struct snd_pcm_substream *substream,
1283 struct azx_dev *azx_dev, u32 **bdlp,
1284 int ofs, int size, int with_ioc)
1285{
1286 u32 *bdl = *bdlp;
1287
1288 while (size > 0) {
1289 dma_addr_t addr;
1290 int chunk;
1291
1292 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1293 return -EINVAL;
1294
1295 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1296
1297 bdl[0] = cpu_to_le32((u32)addr);
1298 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1299
1300 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1301 bdl[2] = cpu_to_le32(chunk);
1302
1303
1304
1305 size -= chunk;
1306 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1307 bdl += 4;
1308 azx_dev->frags++;
1309 ofs += chunk;
1310 }
1311 *bdlp = bdl;
1312 return ofs;
1313}
1314
1315
1316
1317
1318static int azx_setup_periods(struct azx *chip,
1319 struct snd_pcm_substream *substream,
1320 struct azx_dev *azx_dev)
1321{
1322 u32 *bdl;
1323 int i, ofs, periods, period_bytes;
1324 int pos_adj;
1325
1326
1327 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1328 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1329
1330 period_bytes = azx_dev->period_bytes;
1331 periods = azx_dev->bufsize / period_bytes;
1332
1333
1334 bdl = (u32 *)azx_dev->bdl.area;
1335 ofs = 0;
1336 azx_dev->frags = 0;
1337 pos_adj = bdl_pos_adj[chip->dev_index];
1338 if (pos_adj > 0) {
1339 struct snd_pcm_runtime *runtime = substream->runtime;
1340 int pos_align = pos_adj;
1341 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1342 if (!pos_adj)
1343 pos_adj = pos_align;
1344 else
1345 pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1346 pos_align;
1347 pos_adj = frames_to_bytes(runtime, pos_adj);
1348 if (pos_adj >= period_bytes) {
1349 snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1350 bdl_pos_adj[chip->dev_index]);
1351 pos_adj = 0;
1352 } else {
1353 ofs = setup_bdle(substream, azx_dev,
1354 &bdl, ofs, pos_adj,
1355 !substream->runtime->no_period_wakeup);
1356 if (ofs < 0)
1357 goto error;
1358 }
1359 } else
1360 pos_adj = 0;
1361 for (i = 0; i < periods; i++) {
1362 if (i == periods - 1 && pos_adj)
1363 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1364 period_bytes - pos_adj, 0);
1365 else
1366 ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1367 period_bytes,
1368 !substream->runtime->no_period_wakeup);
1369 if (ofs < 0)
1370 goto error;
1371 }
1372 return 0;
1373
1374 error:
1375 snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1376 azx_dev->bufsize, period_bytes);
1377 return -EINVAL;
1378}
1379
1380
1381static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1382{
1383 unsigned char val;
1384 int timeout;
1385
1386 azx_stream_clear(chip, azx_dev);
1387
1388 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1389 SD_CTL_STREAM_RESET);
1390 udelay(3);
1391 timeout = 300;
1392 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1393 --timeout)
1394 ;
1395 val &= ~SD_CTL_STREAM_RESET;
1396 azx_sd_writeb(azx_dev, SD_CTL, val);
1397 udelay(3);
1398
1399 timeout = 300;
1400
1401 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1402 --timeout)
1403 ;
1404
1405
1406 *azx_dev->posbuf = 0;
1407}
1408
1409
1410
1411
1412static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1413{
1414 unsigned int val;
1415
1416 azx_stream_clear(chip, azx_dev);
1417
1418 val = azx_sd_readl(azx_dev, SD_CTL);
1419 val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1420 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1421 if (!azx_snoop(chip))
1422 val |= SD_CTL_TRAFFIC_PRIO;
1423 azx_sd_writel(azx_dev, SD_CTL, val);
1424
1425
1426 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1427
1428
1429
1430 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1431
1432
1433 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1434
1435
1436
1437 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1438
1439 azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1440
1441
1442 if (chip->position_fix[0] != POS_FIX_LPIB ||
1443 chip->position_fix[1] != POS_FIX_LPIB) {
1444 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1445 azx_writel(chip, DPLBASE,
1446 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1447 }
1448
1449
1450 azx_sd_writel(azx_dev, SD_CTL,
1451 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1452
1453 return 0;
1454}
1455
1456
1457
1458
1459static int probe_codec(struct azx *chip, int addr)
1460{
1461 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1462 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1463 unsigned int res;
1464
1465 mutex_lock(&chip->bus->cmd_mutex);
1466 chip->probing = 1;
1467 azx_send_cmd(chip->bus, cmd);
1468 res = azx_get_response(chip->bus, addr);
1469 chip->probing = 0;
1470 mutex_unlock(&chip->bus->cmd_mutex);
1471 if (res == -1)
1472 return -EIO;
1473 snd_printdd(SFX "codec #%d probed OK\n", addr);
1474 return 0;
1475}
1476
1477static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1478 struct hda_pcm *cpcm);
1479static void azx_stop_chip(struct azx *chip);
1480
1481static void azx_bus_reset(struct hda_bus *bus)
1482{
1483 struct azx *chip = bus->private_data;
1484
1485 bus->in_reset = 1;
1486 azx_stop_chip(chip);
1487 azx_init_chip(chip, 1);
1488#ifdef CONFIG_PM
1489 if (chip->initialized) {
1490 int i;
1491
1492 for (i = 0; i < HDA_MAX_PCMS; i++)
1493 snd_pcm_suspend_all(chip->pcm[i]);
1494 snd_hda_suspend(chip->bus);
1495 snd_hda_resume(chip->bus);
1496 }
1497#endif
1498 bus->in_reset = 0;
1499}
1500
1501
1502
1503
1504
1505
1506static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1507 [AZX_DRIVER_NVIDIA] = 8,
1508 [AZX_DRIVER_TERA] = 1,
1509};
1510
1511static int __devinit azx_codec_create(struct azx *chip, const char *model)
1512{
1513 struct hda_bus_template bus_temp;
1514 int c, codecs, err;
1515 int max_slots;
1516
1517 memset(&bus_temp, 0, sizeof(bus_temp));
1518 bus_temp.private_data = chip;
1519 bus_temp.modelname = model;
1520 bus_temp.pci = chip->pci;
1521 bus_temp.ops.command = azx_send_cmd;
1522 bus_temp.ops.get_response = azx_get_response;
1523 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1524 bus_temp.ops.bus_reset = azx_bus_reset;
1525#ifdef CONFIG_SND_HDA_POWER_SAVE
1526 bus_temp.power_save = &power_save;
1527 bus_temp.ops.pm_notify = azx_power_notify;
1528#endif
1529
1530 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1531 if (err < 0)
1532 return err;
1533
1534 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1535 snd_printd(SFX "Enable delay in RIRB handling\n");
1536 chip->bus->needs_damn_long_delay = 1;
1537 }
1538
1539 codecs = 0;
1540 max_slots = azx_max_codecs[chip->driver_type];
1541 if (!max_slots)
1542 max_slots = AZX_DEFAULT_CODECS;
1543
1544
1545 for (c = 0; c < max_slots; c++) {
1546 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1547 if (probe_codec(chip, c) < 0) {
1548
1549
1550
1551 snd_printk(KERN_WARNING SFX
1552 "Codec #%d probe error; "
1553 "disabling it...\n", c);
1554 chip->codec_mask &= ~(1 << c);
1555
1556
1557
1558
1559
1560
1561
1562 azx_stop_chip(chip);
1563 azx_init_chip(chip, 1);
1564 }
1565 }
1566 }
1567
1568
1569
1570
1571
1572 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1573 snd_printd(SFX "Enable sync_write for stable communication\n");
1574 chip->bus->sync_write = 1;
1575 chip->bus->allow_bus_reset = 1;
1576 }
1577
1578
1579 for (c = 0; c < max_slots; c++) {
1580 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1581 struct hda_codec *codec;
1582 err = snd_hda_codec_new(chip->bus, c, &codec);
1583 if (err < 0)
1584 continue;
1585 codec->beep_mode = chip->beep_mode;
1586 codecs++;
1587 }
1588 }
1589 if (!codecs) {
1590 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1591 return -ENXIO;
1592 }
1593 return 0;
1594}
1595
1596
1597static int __devinit azx_codec_configure(struct azx *chip)
1598{
1599 struct hda_codec *codec;
1600 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1601 snd_hda_codec_configure(codec);
1602 }
1603 return 0;
1604}
1605
1606
1607
1608
1609
1610
1611
1612static inline struct azx_dev *
1613azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1614{
1615 int dev, i, nums;
1616 struct azx_dev *res = NULL;
1617
1618 int key = (substream->pcm->device << 16) | (substream->number << 2) |
1619 (substream->stream + 1);
1620
1621 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1622 dev = chip->playback_index_offset;
1623 nums = chip->playback_streams;
1624 } else {
1625 dev = chip->capture_index_offset;
1626 nums = chip->capture_streams;
1627 }
1628 for (i = 0; i < nums; i++, dev++)
1629 if (!chip->azx_dev[dev].opened) {
1630 res = &chip->azx_dev[dev];
1631 if (res->assigned_key == key)
1632 break;
1633 }
1634 if (res) {
1635 res->opened = 1;
1636 res->assigned_key = key;
1637 }
1638 return res;
1639}
1640
1641
1642static inline void azx_release_device(struct azx_dev *azx_dev)
1643{
1644 azx_dev->opened = 0;
1645}
1646
1647static struct snd_pcm_hardware azx_pcm_hw = {
1648 .info = (SNDRV_PCM_INFO_MMAP |
1649 SNDRV_PCM_INFO_INTERLEAVED |
1650 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1651 SNDRV_PCM_INFO_MMAP_VALID |
1652
1653
1654 SNDRV_PCM_INFO_PAUSE |
1655 SNDRV_PCM_INFO_SYNC_START |
1656 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
1657 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1658 .rates = SNDRV_PCM_RATE_48000,
1659 .rate_min = 48000,
1660 .rate_max = 48000,
1661 .channels_min = 2,
1662 .channels_max = 2,
1663 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1664 .period_bytes_min = 128,
1665 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1666 .periods_min = 2,
1667 .periods_max = AZX_MAX_FRAG,
1668 .fifo_size = 0,
1669};
1670
1671struct azx_pcm {
1672 struct azx *chip;
1673 struct hda_codec *codec;
1674 struct hda_pcm_stream *hinfo[2];
1675};
1676
1677static int azx_pcm_open(struct snd_pcm_substream *substream)
1678{
1679 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1680 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1681 struct azx *chip = apcm->chip;
1682 struct azx_dev *azx_dev;
1683 struct snd_pcm_runtime *runtime = substream->runtime;
1684 unsigned long flags;
1685 int err;
1686 int buff_step;
1687
1688 mutex_lock(&chip->open_mutex);
1689 azx_dev = azx_assign_device(chip, substream);
1690 if (azx_dev == NULL) {
1691 mutex_unlock(&chip->open_mutex);
1692 return -EBUSY;
1693 }
1694 runtime->hw = azx_pcm_hw;
1695 runtime->hw.channels_min = hinfo->channels_min;
1696 runtime->hw.channels_max = hinfo->channels_max;
1697 runtime->hw.formats = hinfo->formats;
1698 runtime->hw.rates = hinfo->rates;
1699 snd_pcm_limit_hw_rates(runtime);
1700 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1701 if (chip->align_buffer_size)
1702
1703
1704
1705
1706
1707
1708 buff_step = 128;
1709 else
1710
1711
1712
1713
1714 buff_step = 4;
1715
1716 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1717 buff_step);
1718 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1719 buff_step);
1720 snd_hda_power_up(apcm->codec);
1721 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1722 if (err < 0) {
1723 azx_release_device(azx_dev);
1724 snd_hda_power_down(apcm->codec);
1725 mutex_unlock(&chip->open_mutex);
1726 return err;
1727 }
1728 snd_pcm_limit_hw_rates(runtime);
1729
1730 if (snd_BUG_ON(!runtime->hw.channels_min) ||
1731 snd_BUG_ON(!runtime->hw.channels_max) ||
1732 snd_BUG_ON(!runtime->hw.formats) ||
1733 snd_BUG_ON(!runtime->hw.rates)) {
1734 azx_release_device(azx_dev);
1735 hinfo->ops.close(hinfo, apcm->codec, substream);
1736 snd_hda_power_down(apcm->codec);
1737 mutex_unlock(&chip->open_mutex);
1738 return -EINVAL;
1739 }
1740 spin_lock_irqsave(&chip->reg_lock, flags);
1741 azx_dev->substream = substream;
1742 azx_dev->running = 0;
1743 spin_unlock_irqrestore(&chip->reg_lock, flags);
1744
1745 runtime->private_data = azx_dev;
1746 snd_pcm_set_sync(substream);
1747 mutex_unlock(&chip->open_mutex);
1748 return 0;
1749}
1750
1751static int azx_pcm_close(struct snd_pcm_substream *substream)
1752{
1753 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1754 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1755 struct azx *chip = apcm->chip;
1756 struct azx_dev *azx_dev = get_azx_dev(substream);
1757 unsigned long flags;
1758
1759 mutex_lock(&chip->open_mutex);
1760 spin_lock_irqsave(&chip->reg_lock, flags);
1761 azx_dev->substream = NULL;
1762 azx_dev->running = 0;
1763 spin_unlock_irqrestore(&chip->reg_lock, flags);
1764 azx_release_device(azx_dev);
1765 hinfo->ops.close(hinfo, apcm->codec, substream);
1766 snd_hda_power_down(apcm->codec);
1767 mutex_unlock(&chip->open_mutex);
1768 return 0;
1769}
1770
1771static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1772 struct snd_pcm_hw_params *hw_params)
1773{
1774 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1775 struct azx *chip = apcm->chip;
1776 struct snd_pcm_runtime *runtime = substream->runtime;
1777 struct azx_dev *azx_dev = get_azx_dev(substream);
1778 int ret;
1779
1780 mark_runtime_wc(chip, azx_dev, runtime, false);
1781 azx_dev->bufsize = 0;
1782 azx_dev->period_bytes = 0;
1783 azx_dev->format_val = 0;
1784 ret = snd_pcm_lib_malloc_pages(substream,
1785 params_buffer_bytes(hw_params));
1786 if (ret < 0)
1787 return ret;
1788 mark_runtime_wc(chip, azx_dev, runtime, true);
1789 return ret;
1790}
1791
1792static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1793{
1794 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1795 struct azx_dev *azx_dev = get_azx_dev(substream);
1796 struct azx *chip = apcm->chip;
1797 struct snd_pcm_runtime *runtime = substream->runtime;
1798 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1799
1800
1801 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1802 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1803 azx_sd_writel(azx_dev, SD_CTL, 0);
1804 azx_dev->bufsize = 0;
1805 azx_dev->period_bytes = 0;
1806 azx_dev->format_val = 0;
1807
1808 snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
1809
1810 mark_runtime_wc(chip, azx_dev, runtime, false);
1811 return snd_pcm_lib_free_pages(substream);
1812}
1813
1814static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1815{
1816 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1817 struct azx *chip = apcm->chip;
1818 struct azx_dev *azx_dev = get_azx_dev(substream);
1819 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1820 struct snd_pcm_runtime *runtime = substream->runtime;
1821 unsigned int bufsize, period_bytes, format_val, stream_tag;
1822 int err;
1823 struct hda_spdif_out *spdif =
1824 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
1825 unsigned short ctls = spdif ? spdif->ctls : 0;
1826
1827 azx_stream_reset(chip, azx_dev);
1828 format_val = snd_hda_calc_stream_format(runtime->rate,
1829 runtime->channels,
1830 runtime->format,
1831 hinfo->maxbps,
1832 ctls);
1833 if (!format_val) {
1834 snd_printk(KERN_ERR SFX
1835 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1836 runtime->rate, runtime->channels, runtime->format);
1837 return -EINVAL;
1838 }
1839
1840 bufsize = snd_pcm_lib_buffer_bytes(substream);
1841 period_bytes = snd_pcm_lib_period_bytes(substream);
1842
1843 snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1844 bufsize, format_val);
1845
1846 if (bufsize != azx_dev->bufsize ||
1847 period_bytes != azx_dev->period_bytes ||
1848 format_val != azx_dev->format_val) {
1849 azx_dev->bufsize = bufsize;
1850 azx_dev->period_bytes = period_bytes;
1851 azx_dev->format_val = format_val;
1852 err = azx_setup_periods(chip, substream, azx_dev);
1853 if (err < 0)
1854 return err;
1855 }
1856
1857
1858 azx_dev->period_wallclk = (((runtime->period_size * 24000) /
1859 runtime->rate) * 1000);
1860 azx_setup_controller(chip, azx_dev);
1861 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1862 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1863 else
1864 azx_dev->fifo_size = 0;
1865
1866 stream_tag = azx_dev->stream_tag;
1867
1868 if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
1869 stream_tag > chip->capture_streams)
1870 stream_tag -= chip->capture_streams;
1871 return snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
1872 azx_dev->format_val, substream);
1873}
1874
1875static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1876{
1877 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1878 struct azx *chip = apcm->chip;
1879 struct azx_dev *azx_dev;
1880 struct snd_pcm_substream *s;
1881 int rstart = 0, start, nsync = 0, sbits = 0;
1882 int nwait, timeout;
1883
1884 switch (cmd) {
1885 case SNDRV_PCM_TRIGGER_START:
1886 rstart = 1;
1887 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1888 case SNDRV_PCM_TRIGGER_RESUME:
1889 start = 1;
1890 break;
1891 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1892 case SNDRV_PCM_TRIGGER_SUSPEND:
1893 case SNDRV_PCM_TRIGGER_STOP:
1894 start = 0;
1895 break;
1896 default:
1897 return -EINVAL;
1898 }
1899
1900 snd_pcm_group_for_each_entry(s, substream) {
1901 if (s->pcm->card != substream->pcm->card)
1902 continue;
1903 azx_dev = get_azx_dev(s);
1904 sbits |= 1 << azx_dev->index;
1905 nsync++;
1906 snd_pcm_trigger_done(s, substream);
1907 }
1908
1909 spin_lock(&chip->reg_lock);
1910 if (nsync > 1) {
1911
1912 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1913 azx_writel(chip, OLD_SSYNC,
1914 azx_readl(chip, OLD_SSYNC) | sbits);
1915 else
1916 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
1917 }
1918 snd_pcm_group_for_each_entry(s, substream) {
1919 if (s->pcm->card != substream->pcm->card)
1920 continue;
1921 azx_dev = get_azx_dev(s);
1922 if (start) {
1923 azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
1924 if (!rstart)
1925 azx_dev->start_wallclk -=
1926 azx_dev->period_wallclk;
1927 azx_stream_start(chip, azx_dev);
1928 } else {
1929 azx_stream_stop(chip, azx_dev);
1930 }
1931 azx_dev->running = start;
1932 }
1933 spin_unlock(&chip->reg_lock);
1934 if (start) {
1935 if (nsync == 1)
1936 return 0;
1937
1938 for (timeout = 5000; timeout; timeout--) {
1939 nwait = 0;
1940 snd_pcm_group_for_each_entry(s, substream) {
1941 if (s->pcm->card != substream->pcm->card)
1942 continue;
1943 azx_dev = get_azx_dev(s);
1944 if (!(azx_sd_readb(azx_dev, SD_STS) &
1945 SD_STS_FIFO_READY))
1946 nwait++;
1947 }
1948 if (!nwait)
1949 break;
1950 cpu_relax();
1951 }
1952 } else {
1953
1954 for (timeout = 5000; timeout; timeout--) {
1955 nwait = 0;
1956 snd_pcm_group_for_each_entry(s, substream) {
1957 if (s->pcm->card != substream->pcm->card)
1958 continue;
1959 azx_dev = get_azx_dev(s);
1960 if (azx_sd_readb(azx_dev, SD_CTL) &
1961 SD_CTL_DMA_START)
1962 nwait++;
1963 }
1964 if (!nwait)
1965 break;
1966 cpu_relax();
1967 }
1968 }
1969 if (nsync > 1) {
1970 spin_lock(&chip->reg_lock);
1971
1972 if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
1973 azx_writel(chip, OLD_SSYNC,
1974 azx_readl(chip, OLD_SSYNC) & ~sbits);
1975 else
1976 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
1977 spin_unlock(&chip->reg_lock);
1978 }
1979 return 0;
1980}
1981
1982
1983static unsigned int azx_via_get_position(struct azx *chip,
1984 struct azx_dev *azx_dev)
1985{
1986 unsigned int link_pos, mini_pos, bound_pos;
1987 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1988 unsigned int fifo_size;
1989
1990 link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1991 if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1992
1993 return link_pos;
1994 }
1995
1996
1997
1998
1999
2000 mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2001 mod_dma_pos %= azx_dev->period_bytes;
2002
2003
2004
2005
2006 fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2007
2008 if (azx_dev->insufficient) {
2009
2010 if (link_pos <= fifo_size)
2011 return 0;
2012
2013 azx_dev->insufficient = 0;
2014 }
2015
2016 if (link_pos <= fifo_size)
2017 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2018 else
2019 mini_pos = link_pos - fifo_size;
2020
2021
2022 mod_mini_pos = mini_pos % azx_dev->period_bytes;
2023 mod_link_pos = link_pos % azx_dev->period_bytes;
2024 if (mod_link_pos >= fifo_size)
2025 bound_pos = link_pos - mod_link_pos;
2026 else if (mod_dma_pos >= mod_mini_pos)
2027 bound_pos = mini_pos - mod_mini_pos;
2028 else {
2029 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2030 if (bound_pos >= azx_dev->bufsize)
2031 bound_pos = 0;
2032 }
2033
2034
2035 return bound_pos + mod_dma_pos;
2036}
2037
2038static unsigned int azx_get_position(struct azx *chip,
2039 struct azx_dev *azx_dev,
2040 bool with_check)
2041{
2042 unsigned int pos;
2043 int stream = azx_dev->substream->stream;
2044
2045 switch (chip->position_fix[stream]) {
2046 case POS_FIX_LPIB:
2047
2048 pos = azx_sd_readl(azx_dev, SD_LPIB);
2049 break;
2050 case POS_FIX_VIACOMBO:
2051 pos = azx_via_get_position(chip, azx_dev);
2052 break;
2053 default:
2054
2055 pos = le32_to_cpu(*azx_dev->posbuf);
2056 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2057 if (!pos || pos == (u32)-1) {
2058 printk(KERN_WARNING
2059 "hda-intel: Invalid position buffer, "
2060 "using LPIB read method instead.\n");
2061 chip->position_fix[stream] = POS_FIX_LPIB;
2062 pos = azx_sd_readl(azx_dev, SD_LPIB);
2063 } else
2064 chip->position_fix[stream] = POS_FIX_POSBUF;
2065 }
2066 break;
2067 }
2068
2069 if (pos >= azx_dev->bufsize)
2070 pos = 0;
2071 return pos;
2072}
2073
2074static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2075{
2076 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2077 struct azx *chip = apcm->chip;
2078 struct azx_dev *azx_dev = get_azx_dev(substream);
2079 return bytes_to_frames(substream->runtime,
2080 azx_get_position(chip, azx_dev, false));
2081}
2082
2083
2084
2085
2086
2087
2088
2089
2090
2091
2092static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2093{
2094 u32 wallclk;
2095 unsigned int pos;
2096 int stream;
2097
2098 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2099 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2100 return -1;
2101
2102 stream = azx_dev->substream->stream;
2103 pos = azx_get_position(chip, azx_dev, true);
2104
2105 if (WARN_ONCE(!azx_dev->period_bytes,
2106 "hda-intel: zero azx_dev->period_bytes"))
2107 return -1;
2108 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2109 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2110
2111 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2112 azx_dev->start_wallclk += wallclk;
2113 return 1;
2114}
2115
2116
2117
2118
2119static void azx_irq_pending_work(struct work_struct *work)
2120{
2121 struct azx *chip = container_of(work, struct azx, irq_pending_work);
2122 int i, pending, ok;
2123
2124 if (!chip->irq_pending_warned) {
2125 printk(KERN_WARNING
2126 "hda-intel: IRQ timing workaround is activated "
2127 "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2128 chip->card->number);
2129 chip->irq_pending_warned = 1;
2130 }
2131
2132 for (;;) {
2133 pending = 0;
2134 spin_lock_irq(&chip->reg_lock);
2135 for (i = 0; i < chip->num_streams; i++) {
2136 struct azx_dev *azx_dev = &chip->azx_dev[i];
2137 if (!azx_dev->irq_pending ||
2138 !azx_dev->substream ||
2139 !azx_dev->running)
2140 continue;
2141 ok = azx_position_ok(chip, azx_dev);
2142 if (ok > 0) {
2143 azx_dev->irq_pending = 0;
2144 spin_unlock(&chip->reg_lock);
2145 snd_pcm_period_elapsed(azx_dev->substream);
2146 spin_lock(&chip->reg_lock);
2147 } else if (ok < 0) {
2148 pending = 0;
2149 } else
2150 pending++;
2151 }
2152 spin_unlock_irq(&chip->reg_lock);
2153 if (!pending)
2154 return;
2155 msleep(1);
2156 }
2157}
2158
2159
2160static void azx_clear_irq_pending(struct azx *chip)
2161{
2162 int i;
2163
2164 spin_lock_irq(&chip->reg_lock);
2165 for (i = 0; i < chip->num_streams; i++)
2166 chip->azx_dev[i].irq_pending = 0;
2167 spin_unlock_irq(&chip->reg_lock);
2168}
2169
2170#ifdef CONFIG_X86
2171static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2172 struct vm_area_struct *area)
2173{
2174 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2175 struct azx *chip = apcm->chip;
2176 if (!azx_snoop(chip))
2177 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2178 return snd_pcm_lib_default_mmap(substream, area);
2179}
2180#else
2181#define azx_pcm_mmap NULL
2182#endif
2183
2184static struct snd_pcm_ops azx_pcm_ops = {
2185 .open = azx_pcm_open,
2186 .close = azx_pcm_close,
2187 .ioctl = snd_pcm_lib_ioctl,
2188 .hw_params = azx_pcm_hw_params,
2189 .hw_free = azx_pcm_hw_free,
2190 .prepare = azx_pcm_prepare,
2191 .trigger = azx_pcm_trigger,
2192 .pointer = azx_pcm_pointer,
2193 .mmap = azx_pcm_mmap,
2194 .page = snd_pcm_sgbuf_ops_page,
2195};
2196
2197static void azx_pcm_free(struct snd_pcm *pcm)
2198{
2199 struct azx_pcm *apcm = pcm->private_data;
2200 if (apcm) {
2201 apcm->chip->pcm[pcm->device] = NULL;
2202 kfree(apcm);
2203 }
2204}
2205
2206#define MAX_PREALLOC_SIZE (32 * 1024 * 1024)
2207
2208static int
2209azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2210 struct hda_pcm *cpcm)
2211{
2212 struct azx *chip = bus->private_data;
2213 struct snd_pcm *pcm;
2214 struct azx_pcm *apcm;
2215 int pcm_dev = cpcm->device;
2216 unsigned int size;
2217 int s, err;
2218
2219 if (pcm_dev >= HDA_MAX_PCMS) {
2220 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
2221 pcm_dev);
2222 return -EINVAL;
2223 }
2224 if (chip->pcm[pcm_dev]) {
2225 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
2226 return -EBUSY;
2227 }
2228 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2229 cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2230 cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2231 &pcm);
2232 if (err < 0)
2233 return err;
2234 strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2235 apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2236 if (apcm == NULL)
2237 return -ENOMEM;
2238 apcm->chip = chip;
2239 apcm->codec = codec;
2240 pcm->private_data = apcm;
2241 pcm->private_free = azx_pcm_free;
2242 if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2243 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2244 chip->pcm[pcm_dev] = pcm;
2245 cpcm->pcm = pcm;
2246 for (s = 0; s < 2; s++) {
2247 apcm->hinfo[s] = &cpcm->stream[s];
2248 if (cpcm->stream[s].substreams)
2249 snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2250 }
2251
2252 size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2253 if (size > MAX_PREALLOC_SIZE)
2254 size = MAX_PREALLOC_SIZE;
2255 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2256 snd_dma_pci_data(chip->pci),
2257 size, MAX_PREALLOC_SIZE);
2258 return 0;
2259}
2260
2261
2262
2263
2264static int __devinit azx_mixer_create(struct azx *chip)
2265{
2266 return snd_hda_build_controls(chip->bus);
2267}
2268
2269
2270
2271
2272
2273static int __devinit azx_init_stream(struct azx *chip)
2274{
2275 int i;
2276
2277
2278
2279
2280
2281 for (i = 0; i < chip->num_streams; i++) {
2282 struct azx_dev *azx_dev = &chip->azx_dev[i];
2283 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2284
2285 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2286
2287 azx_dev->sd_int_sta_mask = 1 << i;
2288
2289 azx_dev->index = i;
2290 azx_dev->stream_tag = i + 1;
2291 }
2292
2293 return 0;
2294}
2295
2296static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2297{
2298 if (request_irq(chip->pci->irq, azx_interrupt,
2299 chip->msi ? 0 : IRQF_SHARED,
2300 KBUILD_MODNAME, chip)) {
2301 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2302 "disabling device\n", chip->pci->irq);
2303 if (do_disconnect)
2304 snd_card_disconnect(chip->card);
2305 return -1;
2306 }
2307 chip->irq = chip->pci->irq;
2308 pci_intx(chip->pci, !chip->msi);
2309 return 0;
2310}
2311
2312
2313static void azx_stop_chip(struct azx *chip)
2314{
2315 if (!chip->initialized)
2316 return;
2317
2318
2319 azx_int_disable(chip);
2320 azx_int_clear(chip);
2321
2322
2323 azx_free_cmd_io(chip);
2324
2325
2326 azx_writel(chip, DPLBASE, 0);
2327 azx_writel(chip, DPUBASE, 0);
2328
2329 chip->initialized = 0;
2330}
2331
2332#ifdef CONFIG_SND_HDA_POWER_SAVE
2333
2334static void azx_power_notify(struct hda_bus *bus)
2335{
2336 struct azx *chip = bus->private_data;
2337 struct hda_codec *c;
2338 int power_on = 0;
2339
2340 list_for_each_entry(c, &bus->codec_list, list) {
2341 if (c->power_on) {
2342 power_on = 1;
2343 break;
2344 }
2345 }
2346 if (power_on)
2347 azx_init_chip(chip, 1);
2348 else if (chip->running && power_save_controller &&
2349 !bus->power_keep_link_on)
2350 azx_stop_chip(chip);
2351}
2352#endif
2353
2354#ifdef CONFIG_PM
2355
2356
2357
2358
2359static int snd_hda_codecs_inuse(struct hda_bus *bus)
2360{
2361 struct hda_codec *codec;
2362
2363 list_for_each_entry(codec, &bus->codec_list, list) {
2364 if (snd_hda_codec_needs_resume(codec))
2365 return 1;
2366 }
2367 return 0;
2368}
2369
2370static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2371{
2372 struct snd_card *card = pci_get_drvdata(pci);
2373 struct azx *chip = card->private_data;
2374 int i;
2375
2376 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2377 azx_clear_irq_pending(chip);
2378 for (i = 0; i < HDA_MAX_PCMS; i++)
2379 snd_pcm_suspend_all(chip->pcm[i]);
2380 if (chip->initialized)
2381 snd_hda_suspend(chip->bus);
2382 azx_stop_chip(chip);
2383 if (chip->irq >= 0) {
2384 free_irq(chip->irq, chip);
2385 chip->irq = -1;
2386 }
2387 if (chip->msi)
2388 pci_disable_msi(chip->pci);
2389 pci_disable_device(pci);
2390 pci_save_state(pci);
2391 pci_set_power_state(pci, pci_choose_state(pci, state));
2392 return 0;
2393}
2394
2395static int azx_resume(struct pci_dev *pci)
2396{
2397 struct snd_card *card = pci_get_drvdata(pci);
2398 struct azx *chip = card->private_data;
2399
2400 pci_set_power_state(pci, PCI_D0);
2401 pci_restore_state(pci);
2402 if (pci_enable_device(pci) < 0) {
2403 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2404 "disabling device\n");
2405 snd_card_disconnect(card);
2406 return -EIO;
2407 }
2408 pci_set_master(pci);
2409 if (chip->msi)
2410 if (pci_enable_msi(pci) < 0)
2411 chip->msi = 0;
2412 if (azx_acquire_irq(chip, 1) < 0)
2413 return -EIO;
2414 azx_init_pci(chip);
2415
2416 if (snd_hda_codecs_inuse(chip->bus))
2417 azx_init_chip(chip, 1);
2418
2419 snd_hda_resume(chip->bus);
2420 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2421 return 0;
2422}
2423#endif
2424
2425
2426
2427
2428
2429static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2430{
2431 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2432 snd_hda_bus_reboot_notify(chip->bus);
2433 azx_stop_chip(chip);
2434 return NOTIFY_OK;
2435}
2436
2437static void azx_notifier_register(struct azx *chip)
2438{
2439 chip->reboot_notifier.notifier_call = azx_halt;
2440 register_reboot_notifier(&chip->reboot_notifier);
2441}
2442
2443static void azx_notifier_unregister(struct azx *chip)
2444{
2445 if (chip->reboot_notifier.notifier_call)
2446 unregister_reboot_notifier(&chip->reboot_notifier);
2447}
2448
2449
2450
2451
2452static int azx_free(struct azx *chip)
2453{
2454 int i;
2455
2456 azx_notifier_unregister(chip);
2457
2458 if (chip->initialized) {
2459 azx_clear_irq_pending(chip);
2460 for (i = 0; i < chip->num_streams; i++)
2461 azx_stream_stop(chip, &chip->azx_dev[i]);
2462 azx_stop_chip(chip);
2463 }
2464
2465 if (chip->irq >= 0)
2466 free_irq(chip->irq, (void*)chip);
2467 if (chip->msi)
2468 pci_disable_msi(chip->pci);
2469 if (chip->remap_addr)
2470 iounmap(chip->remap_addr);
2471
2472 if (chip->azx_dev) {
2473 for (i = 0; i < chip->num_streams; i++)
2474 if (chip->azx_dev[i].bdl.area) {
2475 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
2476 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2477 }
2478 }
2479 if (chip->rb.area) {
2480 mark_pages_wc(chip, &chip->rb, false);
2481 snd_dma_free_pages(&chip->rb);
2482 }
2483 if (chip->posbuf.area) {
2484 mark_pages_wc(chip, &chip->posbuf, false);
2485 snd_dma_free_pages(&chip->posbuf);
2486 }
2487 pci_release_regions(chip->pci);
2488 pci_disable_device(chip->pci);
2489 kfree(chip->azx_dev);
2490 kfree(chip);
2491
2492 return 0;
2493}
2494
2495static int azx_dev_free(struct snd_device *device)
2496{
2497 return azx_free(device->device_data);
2498}
2499
2500
2501
2502
2503static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2504 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2505 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2506 SND_PCI_QUIRK(0x1028, 0x02c6, "Dell Inspiron 1010", POS_FIX_LPIB),
2507 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2508 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2509 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
2510 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
2511 SND_PCI_QUIRK(0x1043, 0x83ce, "ASUS 1101HA", POS_FIX_LPIB),
2512 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
2513 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
2514 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
2515 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
2516 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2517 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
2518 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
2519 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
2520 {}
2521};
2522
2523static int __devinit check_position_fix(struct azx *chip, int fix)
2524{
2525 const struct snd_pci_quirk *q;
2526
2527 switch (fix) {
2528 case POS_FIX_LPIB:
2529 case POS_FIX_POSBUF:
2530 case POS_FIX_VIACOMBO:
2531 return fix;
2532 }
2533
2534 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2535 if (q) {
2536 printk(KERN_INFO
2537 "hda_intel: position_fix set to %d "
2538 "for device %04x:%04x\n",
2539 q->value, q->subvendor, q->subdevice);
2540 return q->value;
2541 }
2542
2543
2544 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
2545 snd_printd(SFX "Using VIACOMBO position fix\n");
2546 return POS_FIX_VIACOMBO;
2547 }
2548 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
2549 snd_printd(SFX "Using LPIB position fix\n");
2550 return POS_FIX_LPIB;
2551 }
2552 return POS_FIX_AUTO;
2553}
2554
2555
2556
2557
2558static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2559
2560
2561
2562 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2563 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2564 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2565
2566 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2567
2568 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2569
2570 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2571 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2572 {}
2573};
2574
2575#define AZX_FORCE_CODEC_MASK 0x100
2576
2577static void __devinit check_probe_mask(struct azx *chip, int dev)
2578{
2579 const struct snd_pci_quirk *q;
2580
2581 chip->codec_probe_mask = probe_mask[dev];
2582 if (chip->codec_probe_mask == -1) {
2583 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2584 if (q) {
2585 printk(KERN_INFO
2586 "hda_intel: probe_mask set to 0x%x "
2587 "for device %04x:%04x\n",
2588 q->value, q->subvendor, q->subdevice);
2589 chip->codec_probe_mask = q->value;
2590 }
2591 }
2592
2593
2594 if (chip->codec_probe_mask != -1 &&
2595 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2596 chip->codec_mask = chip->codec_probe_mask & 0xff;
2597 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2598 chip->codec_mask);
2599 }
2600}
2601
2602
2603
2604
2605static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2606 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0),
2607 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0),
2608 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0),
2609 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0),
2610 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0),
2611 {}
2612};
2613
2614static void __devinit check_msi(struct azx *chip)
2615{
2616 const struct snd_pci_quirk *q;
2617
2618 if (enable_msi >= 0) {
2619 chip->msi = !!enable_msi;
2620 return;
2621 }
2622 chip->msi = 1;
2623 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2624 if (q) {
2625 printk(KERN_INFO
2626 "hda_intel: msi for device %04x:%04x set to %d\n",
2627 q->subvendor, q->subdevice, q->value);
2628 chip->msi = q->value;
2629 return;
2630 }
2631
2632
2633 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2634 printk(KERN_INFO "hda_intel: Disabling MSI\n");
2635 chip->msi = 0;
2636 }
2637}
2638
2639
2640
2641
2642
2643static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2644 int dev, unsigned int driver_caps,
2645 struct azx **rchip)
2646{
2647 struct azx *chip;
2648 int i, err;
2649 unsigned short gcap;
2650 static struct snd_device_ops ops = {
2651 .dev_free = azx_dev_free,
2652 };
2653
2654 *rchip = NULL;
2655
2656 err = pci_enable_device(pci);
2657 if (err < 0)
2658 return err;
2659
2660 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2661 if (!chip) {
2662 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2663 pci_disable_device(pci);
2664 return -ENOMEM;
2665 }
2666
2667 spin_lock_init(&chip->reg_lock);
2668 mutex_init(&chip->open_mutex);
2669 chip->card = card;
2670 chip->pci = pci;
2671 chip->irq = -1;
2672 chip->driver_caps = driver_caps;
2673 chip->driver_type = driver_caps & 0xff;
2674 check_msi(chip);
2675 chip->dev_index = dev;
2676 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2677
2678 chip->position_fix[0] = chip->position_fix[1] =
2679 check_position_fix(chip, position_fix[dev]);
2680 check_probe_mask(chip, dev);
2681
2682 chip->single_cmd = single_cmd;
2683 chip->snoop = hda_snoop;
2684
2685 if (bdl_pos_adj[dev] < 0) {
2686 switch (chip->driver_type) {
2687 case AZX_DRIVER_ICH:
2688 case AZX_DRIVER_PCH:
2689 bdl_pos_adj[dev] = 1;
2690 break;
2691 default:
2692 bdl_pos_adj[dev] = 32;
2693 break;
2694 }
2695 }
2696
2697#if BITS_PER_LONG != 64
2698
2699 if (chip->driver_type == AZX_DRIVER_ULI) {
2700 u16 tmp3;
2701 pci_read_config_word(pci, 0x40, &tmp3);
2702 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2703 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2704 }
2705#endif
2706
2707 err = pci_request_regions(pci, "ICH HD audio");
2708 if (err < 0) {
2709 kfree(chip);
2710 pci_disable_device(pci);
2711 return err;
2712 }
2713
2714 chip->addr = pci_resource_start(pci, 0);
2715 chip->remap_addr = pci_ioremap_bar(pci, 0);
2716 if (chip->remap_addr == NULL) {
2717 snd_printk(KERN_ERR SFX "ioremap error\n");
2718 err = -ENXIO;
2719 goto errout;
2720 }
2721
2722 if (chip->msi)
2723 if (pci_enable_msi(pci) < 0)
2724 chip->msi = 0;
2725
2726 if (azx_acquire_irq(chip, 0) < 0) {
2727 err = -EBUSY;
2728 goto errout;
2729 }
2730
2731 pci_set_master(pci);
2732 synchronize_irq(chip->irq);
2733
2734 gcap = azx_readw(chip, GCAP);
2735 snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2736
2737
2738 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2739 struct pci_dev *p_smbus;
2740 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2741 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2742 NULL);
2743 if (p_smbus) {
2744 if (p_smbus->revision < 0x30)
2745 gcap &= ~ICH6_GCAP_64OK;
2746 pci_dev_put(p_smbus);
2747 }
2748 }
2749
2750
2751 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2752 snd_printd(SFX "Disabling 64bit DMA\n");
2753 gcap &= ~ICH6_GCAP_64OK;
2754 }
2755
2756
2757 chip->align_buffer_size = align_buffer_size;
2758 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2759 chip->align_buffer_size = 0;
2760
2761
2762 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2763 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2764 else {
2765 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2766 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2767 }
2768
2769
2770
2771
2772 chip->capture_streams = (gcap >> 8) & 0x0f;
2773 chip->playback_streams = (gcap >> 12) & 0x0f;
2774 if (!chip->playback_streams && !chip->capture_streams) {
2775
2776
2777 switch (chip->driver_type) {
2778 case AZX_DRIVER_ULI:
2779 chip->playback_streams = ULI_NUM_PLAYBACK;
2780 chip->capture_streams = ULI_NUM_CAPTURE;
2781 break;
2782 case AZX_DRIVER_ATIHDMI:
2783 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2784 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2785 break;
2786 case AZX_DRIVER_GENERIC:
2787 default:
2788 chip->playback_streams = ICH6_NUM_PLAYBACK;
2789 chip->capture_streams = ICH6_NUM_CAPTURE;
2790 break;
2791 }
2792 }
2793 chip->capture_index_offset = 0;
2794 chip->playback_index_offset = chip->capture_streams;
2795 chip->num_streams = chip->playback_streams + chip->capture_streams;
2796 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2797 GFP_KERNEL);
2798 if (!chip->azx_dev) {
2799 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2800 goto errout;
2801 }
2802
2803 for (i = 0; i < chip->num_streams; i++) {
2804
2805 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2806 snd_dma_pci_data(chip->pci),
2807 BDL_SIZE, &chip->azx_dev[i].bdl);
2808 if (err < 0) {
2809 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2810 goto errout;
2811 }
2812 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
2813 }
2814
2815 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2816 snd_dma_pci_data(chip->pci),
2817 chip->num_streams * 8, &chip->posbuf);
2818 if (err < 0) {
2819 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2820 goto errout;
2821 }
2822 mark_pages_wc(chip, &chip->posbuf, true);
2823
2824 err = azx_alloc_cmd_io(chip);
2825 if (err < 0)
2826 goto errout;
2827
2828
2829 azx_init_stream(chip);
2830
2831
2832 azx_init_pci(chip);
2833 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2834
2835
2836 if (!chip->codec_mask) {
2837 snd_printk(KERN_ERR SFX "no codecs found!\n");
2838 err = -ENODEV;
2839 goto errout;
2840 }
2841
2842 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2843 if (err <0) {
2844 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2845 goto errout;
2846 }
2847
2848 strcpy(card->driver, "HDA-Intel");
2849 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2850 sizeof(card->shortname));
2851 snprintf(card->longname, sizeof(card->longname),
2852 "%s at 0x%lx irq %i",
2853 card->shortname, chip->addr, chip->irq);
2854
2855 *rchip = chip;
2856 return 0;
2857
2858 errout:
2859 azx_free(chip);
2860 return err;
2861}
2862
2863static void power_down_all_codecs(struct azx *chip)
2864{
2865#ifdef CONFIG_SND_HDA_POWER_SAVE
2866
2867
2868
2869 struct hda_codec *codec;
2870 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2871 snd_hda_power_down(codec);
2872 }
2873#endif
2874}
2875
2876static int __devinit azx_probe(struct pci_dev *pci,
2877 const struct pci_device_id *pci_id)
2878{
2879 static int dev;
2880 struct snd_card *card;
2881 struct azx *chip;
2882 int err;
2883
2884 if (dev >= SNDRV_CARDS)
2885 return -ENODEV;
2886 if (!enable[dev]) {
2887 dev++;
2888 return -ENOENT;
2889 }
2890
2891 err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2892 if (err < 0) {
2893 snd_printk(KERN_ERR SFX "Error creating card!\n");
2894 return err;
2895 }
2896
2897
2898 snd_card_set_dev(card, &pci->dev);
2899
2900 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2901 if (err < 0)
2902 goto out_free;
2903 card->private_data = chip;
2904
2905#ifdef CONFIG_SND_HDA_INPUT_BEEP
2906 chip->beep_mode = beep_mode[dev];
2907#endif
2908
2909
2910 err = azx_codec_create(chip, model[dev]);
2911 if (err < 0)
2912 goto out_free;
2913#ifdef CONFIG_SND_HDA_PATCH_LOADER
2914 if (patch[dev] && *patch[dev]) {
2915 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2916 patch[dev]);
2917 err = snd_hda_load_patch(chip->bus, patch[dev]);
2918 if (err < 0)
2919 goto out_free;
2920 }
2921#endif
2922 if ((probe_only[dev] & 1) == 0) {
2923 err = azx_codec_configure(chip);
2924 if (err < 0)
2925 goto out_free;
2926 }
2927
2928
2929 err = snd_hda_build_pcms(chip->bus);
2930 if (err < 0)
2931 goto out_free;
2932
2933
2934 err = azx_mixer_create(chip);
2935 if (err < 0)
2936 goto out_free;
2937
2938 err = snd_card_register(card);
2939 if (err < 0)
2940 goto out_free;
2941
2942 pci_set_drvdata(pci, card);
2943 chip->running = 1;
2944 power_down_all_codecs(chip);
2945 azx_notifier_register(chip);
2946
2947 dev++;
2948 return err;
2949out_free:
2950 snd_card_free(card);
2951 return err;
2952}
2953
2954static void __devexit azx_remove(struct pci_dev *pci)
2955{
2956 snd_card_free(pci_get_drvdata(pci));
2957 pci_set_drvdata(pci, NULL);
2958}
2959
2960
2961static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2962
2963 { PCI_DEVICE(0x8086, 0x1c20),
2964 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2965 AZX_DCAPS_BUFSIZE },
2966
2967 { PCI_DEVICE(0x8086, 0x1d20),
2968 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2969 AZX_DCAPS_BUFSIZE},
2970
2971 { PCI_DEVICE(0x8086, 0x1e20),
2972 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_SCH_SNOOP |
2973 AZX_DCAPS_BUFSIZE},
2974
2975 { PCI_DEVICE(0x8086, 0x811b),
2976 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_SCH_SNOOP |
2977 AZX_DCAPS_BUFSIZE | AZX_DCAPS_POSFIX_LPIB },
2978
2979 { PCI_DEVICE(0x8086, 0x2668),
2980 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2981 AZX_DCAPS_BUFSIZE },
2982 { PCI_DEVICE(0x8086, 0x27d8),
2983 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2984 AZX_DCAPS_BUFSIZE },
2985 { PCI_DEVICE(0x8086, 0x269a),
2986 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2987 AZX_DCAPS_BUFSIZE },
2988 { PCI_DEVICE(0x8086, 0x284b),
2989 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2990 AZX_DCAPS_BUFSIZE },
2991 { PCI_DEVICE(0x8086, 0x293e),
2992 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2993 AZX_DCAPS_BUFSIZE },
2994 { PCI_DEVICE(0x8086, 0x293f),
2995 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2996 AZX_DCAPS_BUFSIZE },
2997 { PCI_DEVICE(0x8086, 0x3a3e),
2998 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2999 AZX_DCAPS_BUFSIZE },
3000 { PCI_DEVICE(0x8086, 0x3a6e),
3001 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
3002 AZX_DCAPS_BUFSIZE },
3003
3004 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
3005 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3006 .class_mask = 0xffffff,
3007 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
3008
3009 { PCI_DEVICE(0x1002, 0x437b),
3010 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3011 { PCI_DEVICE(0x1002, 0x4383),
3012 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
3013
3014 { PCI_DEVICE(0x1022, 0x780d),
3015 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
3016
3017 { PCI_DEVICE(0x1002, 0x793b),
3018 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3019 { PCI_DEVICE(0x1002, 0x7919),
3020 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3021 { PCI_DEVICE(0x1002, 0x960f),
3022 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3023 { PCI_DEVICE(0x1002, 0x970f),
3024 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3025 { PCI_DEVICE(0x1002, 0xaa00),
3026 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3027 { PCI_DEVICE(0x1002, 0xaa08),
3028 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3029 { PCI_DEVICE(0x1002, 0xaa10),
3030 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3031 { PCI_DEVICE(0x1002, 0xaa18),
3032 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3033 { PCI_DEVICE(0x1002, 0xaa20),
3034 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3035 { PCI_DEVICE(0x1002, 0xaa28),
3036 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3037 { PCI_DEVICE(0x1002, 0xaa30),
3038 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3039 { PCI_DEVICE(0x1002, 0xaa38),
3040 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3041 { PCI_DEVICE(0x1002, 0xaa40),
3042 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3043 { PCI_DEVICE(0x1002, 0xaa48),
3044 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
3045
3046 { PCI_DEVICE(0x1106, 0x3288),
3047 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
3048
3049 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
3050
3051 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
3052
3053 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
3054 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3055 .class_mask = 0xffffff,
3056 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
3057
3058 { PCI_DEVICE(0x6549, 0x1200),
3059 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
3060
3061#if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
3062
3063
3064
3065
3066 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
3067 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3068 .class_mask = 0xffffff,
3069 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3070 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3071#else
3072
3073 { PCI_DEVICE(0x1102, 0x0009),
3074 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
3075 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
3076#endif
3077
3078 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
3079
3080 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
3081
3082 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
3083 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3084 .class_mask = 0xffffff,
3085 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3086 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
3087 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
3088 .class_mask = 0xffffff,
3089 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
3090 { 0, }
3091};
3092MODULE_DEVICE_TABLE(pci, azx_ids);
3093
3094
3095static struct pci_driver driver = {
3096 .name = KBUILD_MODNAME,
3097 .id_table = azx_ids,
3098 .probe = azx_probe,
3099 .remove = __devexit_p(azx_remove),
3100#ifdef CONFIG_PM
3101 .suspend = azx_suspend,
3102 .resume = azx_resume,
3103#endif
3104};
3105
3106static int __init alsa_card_azx_init(void)
3107{
3108 return pci_register_driver(&driver);
3109}
3110
3111static void __exit alsa_card_azx_exit(void)
3112{
3113 pci_unregister_driver(&driver);
3114}
3115
3116module_init(alsa_card_azx_init)
3117module_exit(alsa_card_azx_exit)
3118