linux/drivers/watchdog/tegra_wdt.c
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   1/*
   2 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or modify it
   5 * under the terms and conditions of the GNU General Public License,
   6 * version 2, as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope it will be useful, but WITHOUT
   9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11 * more details.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/module.h>
  16#include <linux/interrupt.h>
  17#include <linux/io.h>
  18#include <linux/of.h>
  19#include <linux/platform_device.h>
  20#include <linux/watchdog.h>
  21
  22/* minimum and maximum watchdog trigger timeout, in seconds */
  23#define MIN_WDT_TIMEOUT                 1
  24#define MAX_WDT_TIMEOUT                 255
  25
  26/*
  27 * Base of the WDT registers, from the timer base address.  There are
  28 * actually 5 watchdogs that can be configured (by pairing with an available
  29 * timer), at bases 0x100 + (WDT ID) * 0x20, where WDT ID is 0 through 4.
  30 * This driver only configures the first watchdog (WDT ID 0).
  31 */
  32#define WDT_BASE                        0x100
  33#define WDT_ID                          0
  34
  35/*
  36 * Register base of the timer that's selected for pairing with the watchdog.
  37 * This driver arbitrarily uses timer 5, which is currently unused by
  38 * other drivers (in particular, the Tegra clocksource driver).  If this
  39 * needs to change, take care that the new timer is not used by the
  40 * clocksource driver.
  41 */
  42#define WDT_TIMER_BASE                  0x60
  43#define WDT_TIMER_ID                    5
  44
  45/* WDT registers */
  46#define WDT_CFG                         0x0
  47#define WDT_CFG_PERIOD_SHIFT            4
  48#define WDT_CFG_PERIOD_MASK             0xff
  49#define WDT_CFG_INT_EN                  (1 << 12)
  50#define WDT_CFG_PMC2CAR_RST_EN          (1 << 15)
  51#define WDT_STS                         0x4
  52#define WDT_STS_COUNT_SHIFT             4
  53#define WDT_STS_COUNT_MASK              0xff
  54#define WDT_STS_EXP_SHIFT               12
  55#define WDT_STS_EXP_MASK                0x3
  56#define WDT_CMD                         0x8
  57#define WDT_CMD_START_COUNTER           (1 << 0)
  58#define WDT_CMD_DISABLE_COUNTER         (1 << 1)
  59#define WDT_UNLOCK                      (0xc)
  60#define WDT_UNLOCK_PATTERN              (0xc45a << 0)
  61
  62/* Timer registers */
  63#define TIMER_PTV                       0x0
  64#define TIMER_EN                        (1 << 31)
  65#define TIMER_PERIODIC                  (1 << 30)
  66
  67struct tegra_wdt {
  68        struct watchdog_device  wdd;
  69        void __iomem            *wdt_regs;
  70        void __iomem            *tmr_regs;
  71};
  72
  73#define WDT_HEARTBEAT 120
  74static int heartbeat = WDT_HEARTBEAT;
  75module_param(heartbeat, int, 0);
  76MODULE_PARM_DESC(heartbeat,
  77        "Watchdog heartbeats in seconds. (default = "
  78        __MODULE_STRING(WDT_HEARTBEAT) ")");
  79
  80static bool nowayout = WATCHDOG_NOWAYOUT;
  81module_param(nowayout, bool, 0);
  82MODULE_PARM_DESC(nowayout,
  83        "Watchdog cannot be stopped once started (default="
  84        __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
  85
  86static int tegra_wdt_start(struct watchdog_device *wdd)
  87{
  88        struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
  89        u32 val;
  90
  91        /*
  92         * This thing has a fixed 1MHz clock.  Normally, we would set the
  93         * period to 1 second by writing 1000000ul, but the watchdog system
  94         * reset actually occurs on the 4th expiration of this counter,
  95         * so we set the period to 1/4 of this amount.
  96         */
  97        val = 1000000ul / 4;
  98        val |= (TIMER_EN | TIMER_PERIODIC);
  99        writel(val, wdt->tmr_regs + TIMER_PTV);
 100
 101        /*
 102         * Set number of periods and start counter.
 103         *
 104         * Interrupt handler is not required for user space
 105         * WDT accesses, since the caller is responsible to ping the
 106         * WDT to reset the counter before expiration, through ioctls.
 107         */
 108        val = WDT_TIMER_ID |
 109              (wdd->timeout << WDT_CFG_PERIOD_SHIFT) |
 110              WDT_CFG_PMC2CAR_RST_EN;
 111        writel(val, wdt->wdt_regs + WDT_CFG);
 112
 113        writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
 114
 115        return 0;
 116}
 117
 118static int tegra_wdt_stop(struct watchdog_device *wdd)
 119{
 120        struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
 121
 122        writel(WDT_UNLOCK_PATTERN, wdt->wdt_regs + WDT_UNLOCK);
 123        writel(WDT_CMD_DISABLE_COUNTER, wdt->wdt_regs + WDT_CMD);
 124        writel(0, wdt->tmr_regs + TIMER_PTV);
 125
 126        return 0;
 127}
 128
 129static int tegra_wdt_ping(struct watchdog_device *wdd)
 130{
 131        struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
 132
 133        writel(WDT_CMD_START_COUNTER, wdt->wdt_regs + WDT_CMD);
 134
 135        return 0;
 136}
 137
 138static int tegra_wdt_set_timeout(struct watchdog_device *wdd,
 139                                 unsigned int timeout)
 140{
 141        wdd->timeout = timeout;
 142
 143        if (watchdog_active(wdd))
 144                return tegra_wdt_start(wdd);
 145
 146        return 0;
 147}
 148
 149static unsigned int tegra_wdt_get_timeleft(struct watchdog_device *wdd)
 150{
 151        struct tegra_wdt *wdt = watchdog_get_drvdata(wdd);
 152        u32 val;
 153        int count;
 154        int exp;
 155
 156        val = readl(wdt->wdt_regs + WDT_STS);
 157
 158        /* Current countdown (from timeout) */
 159        count = (val >> WDT_STS_COUNT_SHIFT) & WDT_STS_COUNT_MASK;
 160
 161        /* Number of expirations (we are waiting for the 4th expiration) */
 162        exp = (val >> WDT_STS_EXP_SHIFT) & WDT_STS_EXP_MASK;
 163
 164        /*
 165         * The entire thing is divided by 4 because we are ticking down 4 times
 166         * faster due to needing to wait for the 4th expiration.
 167         */
 168        return (((3 - exp) * wdd->timeout) + count) / 4;
 169}
 170
 171static const struct watchdog_info tegra_wdt_info = {
 172        .options        = WDIOF_SETTIMEOUT |
 173                          WDIOF_MAGICCLOSE |
 174                          WDIOF_KEEPALIVEPING,
 175        .firmware_version = 0,
 176        .identity       = "Tegra Watchdog",
 177};
 178
 179static struct watchdog_ops tegra_wdt_ops = {
 180        .owner = THIS_MODULE,
 181        .start = tegra_wdt_start,
 182        .stop = tegra_wdt_stop,
 183        .ping = tegra_wdt_ping,
 184        .set_timeout = tegra_wdt_set_timeout,
 185        .get_timeleft = tegra_wdt_get_timeleft,
 186};
 187
 188static int tegra_wdt_probe(struct platform_device *pdev)
 189{
 190        struct watchdog_device *wdd;
 191        struct tegra_wdt *wdt;
 192        struct resource *res;
 193        void __iomem *regs;
 194        int ret;
 195
 196        /* This is the timer base. */
 197        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 198        regs = devm_ioremap_resource(&pdev->dev, res);
 199        if (IS_ERR(regs))
 200                return PTR_ERR(regs);
 201
 202        /*
 203         * Allocate our watchdog driver data, which has the
 204         * struct watchdog_device nested within it.
 205         */
 206        wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
 207        if (!wdt)
 208                return -ENOMEM;
 209
 210        /* Initialize struct tegra_wdt. */
 211        wdt->wdt_regs = regs + WDT_BASE;
 212        wdt->tmr_regs = regs + WDT_TIMER_BASE;
 213
 214        /* Initialize struct watchdog_device. */
 215        wdd = &wdt->wdd;
 216        wdd->timeout = heartbeat;
 217        wdd->info = &tegra_wdt_info;
 218        wdd->ops = &tegra_wdt_ops;
 219        wdd->min_timeout = MIN_WDT_TIMEOUT;
 220        wdd->max_timeout = MAX_WDT_TIMEOUT;
 221
 222        watchdog_set_drvdata(wdd, wdt);
 223
 224        watchdog_set_nowayout(wdd, nowayout);
 225
 226        ret = watchdog_register_device(wdd);
 227        if (ret) {
 228                dev_err(&pdev->dev,
 229                        "failed to register watchdog device\n");
 230                return ret;
 231        }
 232
 233        platform_set_drvdata(pdev, wdt);
 234
 235        dev_info(&pdev->dev,
 236                 "initialized (heartbeat = %d sec, nowayout = %d)\n",
 237                 heartbeat, nowayout);
 238
 239        return 0;
 240}
 241
 242static int tegra_wdt_remove(struct platform_device *pdev)
 243{
 244        struct tegra_wdt *wdt = platform_get_drvdata(pdev);
 245
 246        tegra_wdt_stop(&wdt->wdd);
 247
 248        watchdog_unregister_device(&wdt->wdd);
 249
 250        dev_info(&pdev->dev, "removed wdt\n");
 251
 252        return 0;
 253}
 254
 255#ifdef CONFIG_PM_SLEEP
 256static int tegra_wdt_runtime_suspend(struct device *dev)
 257{
 258        struct tegra_wdt *wdt = dev_get_drvdata(dev);
 259
 260        if (watchdog_active(&wdt->wdd))
 261                tegra_wdt_stop(&wdt->wdd);
 262
 263        return 0;
 264}
 265
 266static int tegra_wdt_runtime_resume(struct device *dev)
 267{
 268        struct tegra_wdt *wdt = dev_get_drvdata(dev);
 269
 270        if (watchdog_active(&wdt->wdd))
 271                tegra_wdt_start(&wdt->wdd);
 272
 273        return 0;
 274}
 275#endif
 276
 277static const struct of_device_id tegra_wdt_of_match[] = {
 278        { .compatible = "nvidia,tegra30-timer", },
 279        { },
 280};
 281MODULE_DEVICE_TABLE(of, tegra_wdt_of_match);
 282
 283static const struct dev_pm_ops tegra_wdt_pm_ops = {
 284        SET_SYSTEM_SLEEP_PM_OPS(tegra_wdt_runtime_suspend,
 285                                tegra_wdt_runtime_resume)
 286};
 287
 288static struct platform_driver tegra_wdt_driver = {
 289        .probe          = tegra_wdt_probe,
 290        .remove         = tegra_wdt_remove,
 291        .driver         = {
 292                .name   = "tegra-wdt",
 293                .pm     = &tegra_wdt_pm_ops,
 294                .of_match_table = tegra_wdt_of_match,
 295        },
 296};
 297module_platform_driver(tegra_wdt_driver);
 298
 299MODULE_AUTHOR("NVIDIA Corporation");
 300MODULE_DESCRIPTION("Tegra Watchdog Driver");
 301MODULE_LICENSE("GPL v2");
 302
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