linux/drivers/video/fbdev/omap2/dss/venc.c
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   1/*
   2 * linux/drivers/video/omap2/dss/venc.c
   3 *
   4 * Copyright (C) 2009 Nokia Corporation
   5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6 *
   7 * VENC settings from TI's DSS driver
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms of the GNU General Public License version 2 as published by
  11 * the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope that it will be useful, but WITHOUT
  14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  16 * more details.
  17 *
  18 * You should have received a copy of the GNU General Public License along with
  19 * this program.  If not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22#define DSS_SUBSYS_NAME "VENC"
  23
  24#include <linux/kernel.h>
  25#include <linux/module.h>
  26#include <linux/clk.h>
  27#include <linux/err.h>
  28#include <linux/io.h>
  29#include <linux/mutex.h>
  30#include <linux/completion.h>
  31#include <linux/delay.h>
  32#include <linux/string.h>
  33#include <linux/seq_file.h>
  34#include <linux/platform_device.h>
  35#include <linux/regulator/consumer.h>
  36#include <linux/pm_runtime.h>
  37#include <linux/of.h>
  38
  39#include <video/omapdss.h>
  40
  41#include "dss.h"
  42#include "dss_features.h"
  43
  44/* Venc registers */
  45#define VENC_REV_ID                             0x00
  46#define VENC_STATUS                             0x04
  47#define VENC_F_CONTROL                          0x08
  48#define VENC_VIDOUT_CTRL                        0x10
  49#define VENC_SYNC_CTRL                          0x14
  50#define VENC_LLEN                               0x1C
  51#define VENC_FLENS                              0x20
  52#define VENC_HFLTR_CTRL                         0x24
  53#define VENC_CC_CARR_WSS_CARR                   0x28
  54#define VENC_C_PHASE                            0x2C
  55#define VENC_GAIN_U                             0x30
  56#define VENC_GAIN_V                             0x34
  57#define VENC_GAIN_Y                             0x38
  58#define VENC_BLACK_LEVEL                        0x3C
  59#define VENC_BLANK_LEVEL                        0x40
  60#define VENC_X_COLOR                            0x44
  61#define VENC_M_CONTROL                          0x48
  62#define VENC_BSTAMP_WSS_DATA                    0x4C
  63#define VENC_S_CARR                             0x50
  64#define VENC_LINE21                             0x54
  65#define VENC_LN_SEL                             0x58
  66#define VENC_L21__WC_CTL                        0x5C
  67#define VENC_HTRIGGER_VTRIGGER                  0x60
  68#define VENC_SAVID__EAVID                       0x64
  69#define VENC_FLEN__FAL                          0x68
  70#define VENC_LAL__PHASE_RESET                   0x6C
  71#define VENC_HS_INT_START_STOP_X                0x70
  72#define VENC_HS_EXT_START_STOP_X                0x74
  73#define VENC_VS_INT_START_X                     0x78
  74#define VENC_VS_INT_STOP_X__VS_INT_START_Y      0x7C
  75#define VENC_VS_INT_STOP_Y__VS_EXT_START_X      0x80
  76#define VENC_VS_EXT_STOP_X__VS_EXT_START_Y      0x84
  77#define VENC_VS_EXT_STOP_Y                      0x88
  78#define VENC_AVID_START_STOP_X                  0x90
  79#define VENC_AVID_START_STOP_Y                  0x94
  80#define VENC_FID_INT_START_X__FID_INT_START_Y   0xA0
  81#define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X  0xA4
  82#define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y  0xA8
  83#define VENC_TVDETGP_INT_START_STOP_X           0xB0
  84#define VENC_TVDETGP_INT_START_STOP_Y           0xB4
  85#define VENC_GEN_CTRL                           0xB8
  86#define VENC_OUTPUT_CONTROL                     0xC4
  87#define VENC_OUTPUT_TEST                        0xC8
  88#define VENC_DAC_B__DAC_C                       0xC8
  89
  90struct venc_config {
  91        u32 f_control;
  92        u32 vidout_ctrl;
  93        u32 sync_ctrl;
  94        u32 llen;
  95        u32 flens;
  96        u32 hfltr_ctrl;
  97        u32 cc_carr_wss_carr;
  98        u32 c_phase;
  99        u32 gain_u;
 100        u32 gain_v;
 101        u32 gain_y;
 102        u32 black_level;
 103        u32 blank_level;
 104        u32 x_color;
 105        u32 m_control;
 106        u32 bstamp_wss_data;
 107        u32 s_carr;
 108        u32 line21;
 109        u32 ln_sel;
 110        u32 l21__wc_ctl;
 111        u32 htrigger_vtrigger;
 112        u32 savid__eavid;
 113        u32 flen__fal;
 114        u32 lal__phase_reset;
 115        u32 hs_int_start_stop_x;
 116        u32 hs_ext_start_stop_x;
 117        u32 vs_int_start_x;
 118        u32 vs_int_stop_x__vs_int_start_y;
 119        u32 vs_int_stop_y__vs_ext_start_x;
 120        u32 vs_ext_stop_x__vs_ext_start_y;
 121        u32 vs_ext_stop_y;
 122        u32 avid_start_stop_x;
 123        u32 avid_start_stop_y;
 124        u32 fid_int_start_x__fid_int_start_y;
 125        u32 fid_int_offset_y__fid_ext_start_x;
 126        u32 fid_ext_start_y__fid_ext_offset_y;
 127        u32 tvdetgp_int_start_stop_x;
 128        u32 tvdetgp_int_start_stop_y;
 129        u32 gen_ctrl;
 130};
 131
 132/* from TRM */
 133static const struct venc_config venc_config_pal_trm = {
 134        .f_control                              = 0,
 135        .vidout_ctrl                            = 1,
 136        .sync_ctrl                              = 0x40,
 137        .llen                                   = 0x35F, /* 863 */
 138        .flens                                  = 0x270, /* 624 */
 139        .hfltr_ctrl                             = 0,
 140        .cc_carr_wss_carr                       = 0x2F7225ED,
 141        .c_phase                                = 0,
 142        .gain_u                                 = 0x111,
 143        .gain_v                                 = 0x181,
 144        .gain_y                                 = 0x140,
 145        .black_level                            = 0x3B,
 146        .blank_level                            = 0x3B,
 147        .x_color                                = 0x7,
 148        .m_control                              = 0x2,
 149        .bstamp_wss_data                        = 0x3F,
 150        .s_carr                                 = 0x2A098ACB,
 151        .line21                                 = 0,
 152        .ln_sel                                 = 0x01290015,
 153        .l21__wc_ctl                            = 0x0000F603,
 154        .htrigger_vtrigger                      = 0,
 155
 156        .savid__eavid                           = 0x06A70108,
 157        .flen__fal                              = 0x00180270,
 158        .lal__phase_reset                       = 0x00040135,
 159        .hs_int_start_stop_x                    = 0x00880358,
 160        .hs_ext_start_stop_x                    = 0x000F035F,
 161        .vs_int_start_x                         = 0x01A70000,
 162        .vs_int_stop_x__vs_int_start_y          = 0x000001A7,
 163        .vs_int_stop_y__vs_ext_start_x          = 0x01AF0000,
 164        .vs_ext_stop_x__vs_ext_start_y          = 0x000101AF,
 165        .vs_ext_stop_y                          = 0x00000025,
 166        .avid_start_stop_x                      = 0x03530083,
 167        .avid_start_stop_y                      = 0x026C002E,
 168        .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 169        .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 170        .fid_ext_start_y__fid_ext_offset_y      = 0x01380001,
 171
 172        .tvdetgp_int_start_stop_x               = 0x00140001,
 173        .tvdetgp_int_start_stop_y               = 0x00010001,
 174        .gen_ctrl                               = 0x00FF0000,
 175};
 176
 177/* from TRM */
 178static const struct venc_config venc_config_ntsc_trm = {
 179        .f_control                              = 0,
 180        .vidout_ctrl                            = 1,
 181        .sync_ctrl                              = 0x8040,
 182        .llen                                   = 0x359,
 183        .flens                                  = 0x20C,
 184        .hfltr_ctrl                             = 0,
 185        .cc_carr_wss_carr                       = 0x043F2631,
 186        .c_phase                                = 0,
 187        .gain_u                                 = 0x102,
 188        .gain_v                                 = 0x16C,
 189        .gain_y                                 = 0x12F,
 190        .black_level                            = 0x43,
 191        .blank_level                            = 0x38,
 192        .x_color                                = 0x7,
 193        .m_control                              = 0x1,
 194        .bstamp_wss_data                        = 0x38,
 195        .s_carr                                 = 0x21F07C1F,
 196        .line21                                 = 0,
 197        .ln_sel                                 = 0x01310011,
 198        .l21__wc_ctl                            = 0x0000F003,
 199        .htrigger_vtrigger                      = 0,
 200
 201        .savid__eavid                           = 0x069300F4,
 202        .flen__fal                              = 0x0016020C,
 203        .lal__phase_reset                       = 0x00060107,
 204        .hs_int_start_stop_x                    = 0x008E0350,
 205        .hs_ext_start_stop_x                    = 0x000F0359,
 206        .vs_int_start_x                         = 0x01A00000,
 207        .vs_int_stop_x__vs_int_start_y          = 0x020701A0,
 208        .vs_int_stop_y__vs_ext_start_x          = 0x01AC0024,
 209        .vs_ext_stop_x__vs_ext_start_y          = 0x020D01AC,
 210        .vs_ext_stop_y                          = 0x00000006,
 211        .avid_start_stop_x                      = 0x03480078,
 212        .avid_start_stop_y                      = 0x02060024,
 213        .fid_int_start_x__fid_int_start_y       = 0x0001008A,
 214        .fid_int_offset_y__fid_ext_start_x      = 0x01AC0106,
 215        .fid_ext_start_y__fid_ext_offset_y      = 0x01060006,
 216
 217        .tvdetgp_int_start_stop_x               = 0x00140001,
 218        .tvdetgp_int_start_stop_y               = 0x00010001,
 219        .gen_ctrl                               = 0x00F90000,
 220};
 221
 222static const struct venc_config venc_config_pal_bdghi = {
 223        .f_control                              = 0,
 224        .vidout_ctrl                            = 0,
 225        .sync_ctrl                              = 0,
 226        .hfltr_ctrl                             = 0,
 227        .x_color                                = 0,
 228        .line21                                 = 0,
 229        .ln_sel                                 = 21,
 230        .htrigger_vtrigger                      = 0,
 231        .tvdetgp_int_start_stop_x               = 0x00140001,
 232        .tvdetgp_int_start_stop_y               = 0x00010001,
 233        .gen_ctrl                               = 0x00FB0000,
 234
 235        .llen                                   = 864-1,
 236        .flens                                  = 625-1,
 237        .cc_carr_wss_carr                       = 0x2F7625ED,
 238        .c_phase                                = 0xDF,
 239        .gain_u                                 = 0x111,
 240        .gain_v                                 = 0x181,
 241        .gain_y                                 = 0x140,
 242        .black_level                            = 0x3e,
 243        .blank_level                            = 0x3e,
 244        .m_control                              = 0<<2 | 1<<1,
 245        .bstamp_wss_data                        = 0x42,
 246        .s_carr                                 = 0x2a098acb,
 247        .l21__wc_ctl                            = 0<<13 | 0x16<<8 | 0<<0,
 248        .savid__eavid                           = 0x06A70108,
 249        .flen__fal                              = 23<<16 | 624<<0,
 250        .lal__phase_reset                       = 2<<17 | 310<<0,
 251        .hs_int_start_stop_x                    = 0x00920358,
 252        .hs_ext_start_stop_x                    = 0x000F035F,
 253        .vs_int_start_x                         = 0x1a7<<16,
 254        .vs_int_stop_x__vs_int_start_y          = 0x000601A7,
 255        .vs_int_stop_y__vs_ext_start_x          = 0x01AF0036,
 256        .vs_ext_stop_x__vs_ext_start_y          = 0x27101af,
 257        .vs_ext_stop_y                          = 0x05,
 258        .avid_start_stop_x                      = 0x03530082,
 259        .avid_start_stop_y                      = 0x0270002E,
 260        .fid_int_start_x__fid_int_start_y       = 0x0005008A,
 261        .fid_int_offset_y__fid_ext_start_x      = 0x002E0138,
 262        .fid_ext_start_y__fid_ext_offset_y      = 0x01380005,
 263};
 264
 265const struct omap_video_timings omap_dss_pal_timings = {
 266        .x_res          = 720,
 267        .y_res          = 574,
 268        .pixelclock     = 13500000,
 269        .hsw            = 64,
 270        .hfp            = 12,
 271        .hbp            = 68,
 272        .vsw            = 5,
 273        .vfp            = 5,
 274        .vbp            = 41,
 275
 276        .interlace      = true,
 277};
 278EXPORT_SYMBOL(omap_dss_pal_timings);
 279
 280const struct omap_video_timings omap_dss_ntsc_timings = {
 281        .x_res          = 720,
 282        .y_res          = 482,
 283        .pixelclock     = 13500000,
 284        .hsw            = 64,
 285        .hfp            = 16,
 286        .hbp            = 58,
 287        .vsw            = 6,
 288        .vfp            = 6,
 289        .vbp            = 31,
 290
 291        .interlace      = true,
 292};
 293EXPORT_SYMBOL(omap_dss_ntsc_timings);
 294
 295static struct {
 296        struct platform_device *pdev;
 297        void __iomem *base;
 298        struct mutex venc_lock;
 299        u32 wss_data;
 300        struct regulator *vdda_dac_reg;
 301
 302        struct clk      *tv_dac_clk;
 303
 304        struct omap_video_timings timings;
 305        enum omap_dss_venc_type type;
 306        bool invert_polarity;
 307
 308        struct omap_dss_device output;
 309} venc;
 310
 311static inline void venc_write_reg(int idx, u32 val)
 312{
 313        __raw_writel(val, venc.base + idx);
 314}
 315
 316static inline u32 venc_read_reg(int idx)
 317{
 318        u32 l = __raw_readl(venc.base + idx);
 319        return l;
 320}
 321
 322static void venc_write_config(const struct venc_config *config)
 323{
 324        DSSDBG("write venc conf\n");
 325
 326        venc_write_reg(VENC_LLEN, config->llen);
 327        venc_write_reg(VENC_FLENS, config->flens);
 328        venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
 329        venc_write_reg(VENC_C_PHASE, config->c_phase);
 330        venc_write_reg(VENC_GAIN_U, config->gain_u);
 331        venc_write_reg(VENC_GAIN_V, config->gain_v);
 332        venc_write_reg(VENC_GAIN_Y, config->gain_y);
 333        venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
 334        venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
 335        venc_write_reg(VENC_M_CONTROL, config->m_control);
 336        venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
 337                        venc.wss_data);
 338        venc_write_reg(VENC_S_CARR, config->s_carr);
 339        venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
 340        venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
 341        venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
 342        venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
 343        venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
 344        venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
 345        venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
 346        venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
 347                       config->vs_int_stop_x__vs_int_start_y);
 348        venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
 349                       config->vs_int_stop_y__vs_ext_start_x);
 350        venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
 351                       config->vs_ext_stop_x__vs_ext_start_y);
 352        venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
 353        venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
 354        venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
 355        venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
 356                       config->fid_int_start_x__fid_int_start_y);
 357        venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
 358                       config->fid_int_offset_y__fid_ext_start_x);
 359        venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
 360                       config->fid_ext_start_y__fid_ext_offset_y);
 361
 362        venc_write_reg(VENC_DAC_B__DAC_C,  venc_read_reg(VENC_DAC_B__DAC_C));
 363        venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
 364        venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
 365        venc_write_reg(VENC_X_COLOR, config->x_color);
 366        venc_write_reg(VENC_LINE21, config->line21);
 367        venc_write_reg(VENC_LN_SEL, config->ln_sel);
 368        venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
 369        venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
 370                       config->tvdetgp_int_start_stop_x);
 371        venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
 372                       config->tvdetgp_int_start_stop_y);
 373        venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
 374        venc_write_reg(VENC_F_CONTROL, config->f_control);
 375        venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
 376}
 377
 378static void venc_reset(void)
 379{
 380        int t = 1000;
 381
 382        venc_write_reg(VENC_F_CONTROL, 1<<8);
 383        while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
 384                if (--t == 0) {
 385                        DSSERR("Failed to reset venc\n");
 386                        return;
 387                }
 388        }
 389
 390#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
 391        /* the magical sleep that makes things work */
 392        /* XXX more info? What bug this circumvents? */
 393        msleep(20);
 394#endif
 395}
 396
 397static int venc_runtime_get(void)
 398{
 399        int r;
 400
 401        DSSDBG("venc_runtime_get\n");
 402
 403        r = pm_runtime_get_sync(&venc.pdev->dev);
 404        WARN_ON(r < 0);
 405        return r < 0 ? r : 0;
 406}
 407
 408static void venc_runtime_put(void)
 409{
 410        int r;
 411
 412        DSSDBG("venc_runtime_put\n");
 413
 414        r = pm_runtime_put_sync(&venc.pdev->dev);
 415        WARN_ON(r < 0 && r != -ENOSYS);
 416}
 417
 418static const struct venc_config *venc_timings_to_config(
 419                struct omap_video_timings *timings)
 420{
 421        if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
 422                return &venc_config_pal_trm;
 423
 424        if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
 425                return &venc_config_ntsc_trm;
 426
 427        BUG();
 428        return NULL;
 429}
 430
 431static int venc_power_on(struct omap_dss_device *dssdev)
 432{
 433        struct omap_overlay_manager *mgr = venc.output.manager;
 434        u32 l;
 435        int r;
 436
 437        r = venc_runtime_get();
 438        if (r)
 439                goto err0;
 440
 441        venc_reset();
 442        venc_write_config(venc_timings_to_config(&venc.timings));
 443
 444        dss_set_venc_output(venc.type);
 445        dss_set_dac_pwrdn_bgz(1);
 446
 447        l = 0;
 448
 449        if (venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 450                l |= 1 << 1;
 451        else /* S-Video */
 452                l |= (1 << 0) | (1 << 2);
 453
 454        if (venc.invert_polarity == false)
 455                l |= 1 << 3;
 456
 457        venc_write_reg(VENC_OUTPUT_CONTROL, l);
 458
 459        dss_mgr_set_timings(mgr, &venc.timings);
 460
 461        r = regulator_enable(venc.vdda_dac_reg);
 462        if (r)
 463                goto err1;
 464
 465        r = dss_mgr_enable(mgr);
 466        if (r)
 467                goto err2;
 468
 469        return 0;
 470
 471err2:
 472        regulator_disable(venc.vdda_dac_reg);
 473err1:
 474        venc_write_reg(VENC_OUTPUT_CONTROL, 0);
 475        dss_set_dac_pwrdn_bgz(0);
 476
 477        venc_runtime_put();
 478err0:
 479        return r;
 480}
 481
 482static void venc_power_off(struct omap_dss_device *dssdev)
 483{
 484        struct omap_overlay_manager *mgr = venc.output.manager;
 485
 486        venc_write_reg(VENC_OUTPUT_CONTROL, 0);
 487        dss_set_dac_pwrdn_bgz(0);
 488
 489        dss_mgr_disable(mgr);
 490
 491        regulator_disable(venc.vdda_dac_reg);
 492
 493        venc_runtime_put();
 494}
 495
 496static int venc_display_enable(struct omap_dss_device *dssdev)
 497{
 498        struct omap_dss_device *out = &venc.output;
 499        int r;
 500
 501        DSSDBG("venc_display_enable\n");
 502
 503        mutex_lock(&venc.venc_lock);
 504
 505        if (out == NULL || out->manager == NULL) {
 506                DSSERR("Failed to enable display: no output/manager\n");
 507                r = -ENODEV;
 508                goto err0;
 509        }
 510
 511        r = venc_power_on(dssdev);
 512        if (r)
 513                goto err0;
 514
 515        venc.wss_data = 0;
 516
 517        mutex_unlock(&venc.venc_lock);
 518
 519        return 0;
 520err0:
 521        mutex_unlock(&venc.venc_lock);
 522        return r;
 523}
 524
 525static void venc_display_disable(struct omap_dss_device *dssdev)
 526{
 527        DSSDBG("venc_display_disable\n");
 528
 529        mutex_lock(&venc.venc_lock);
 530
 531        venc_power_off(dssdev);
 532
 533        mutex_unlock(&venc.venc_lock);
 534}
 535
 536static void venc_set_timings(struct omap_dss_device *dssdev,
 537                struct omap_video_timings *timings)
 538{
 539        DSSDBG("venc_set_timings\n");
 540
 541        mutex_lock(&venc.venc_lock);
 542
 543        /* Reset WSS data when the TV standard changes. */
 544        if (memcmp(&venc.timings, timings, sizeof(*timings)))
 545                venc.wss_data = 0;
 546
 547        venc.timings = *timings;
 548
 549        dispc_set_tv_pclk(13500000);
 550
 551        mutex_unlock(&venc.venc_lock);
 552}
 553
 554static int venc_check_timings(struct omap_dss_device *dssdev,
 555                struct omap_video_timings *timings)
 556{
 557        DSSDBG("venc_check_timings\n");
 558
 559        if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
 560                return 0;
 561
 562        if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
 563                return 0;
 564
 565        return -EINVAL;
 566}
 567
 568static void venc_get_timings(struct omap_dss_device *dssdev,
 569                struct omap_video_timings *timings)
 570{
 571        mutex_lock(&venc.venc_lock);
 572
 573        *timings = venc.timings;
 574
 575        mutex_unlock(&venc.venc_lock);
 576}
 577
 578static u32 venc_get_wss(struct omap_dss_device *dssdev)
 579{
 580        /* Invert due to VENC_L21_WC_CTL:INV=1 */
 581        return (venc.wss_data >> 8) ^ 0xfffff;
 582}
 583
 584static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
 585{
 586        const struct venc_config *config;
 587        int r;
 588
 589        DSSDBG("venc_set_wss\n");
 590
 591        mutex_lock(&venc.venc_lock);
 592
 593        config = venc_timings_to_config(&venc.timings);
 594
 595        /* Invert due to VENC_L21_WC_CTL:INV=1 */
 596        venc.wss_data = (wss ^ 0xfffff) << 8;
 597
 598        r = venc_runtime_get();
 599        if (r)
 600                goto err;
 601
 602        venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
 603                        venc.wss_data);
 604
 605        venc_runtime_put();
 606
 607err:
 608        mutex_unlock(&venc.venc_lock);
 609
 610        return r;
 611}
 612
 613static void venc_set_type(struct omap_dss_device *dssdev,
 614                enum omap_dss_venc_type type)
 615{
 616        mutex_lock(&venc.venc_lock);
 617
 618        venc.type = type;
 619
 620        mutex_unlock(&venc.venc_lock);
 621}
 622
 623static void venc_invert_vid_out_polarity(struct omap_dss_device *dssdev,
 624                bool invert_polarity)
 625{
 626        mutex_lock(&venc.venc_lock);
 627
 628        venc.invert_polarity = invert_polarity;
 629
 630        mutex_unlock(&venc.venc_lock);
 631}
 632
 633static int venc_init_regulator(void)
 634{
 635        struct regulator *vdda_dac;
 636
 637        if (venc.vdda_dac_reg != NULL)
 638                return 0;
 639
 640        if (venc.pdev->dev.of_node)
 641                vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda");
 642        else
 643                vdda_dac = devm_regulator_get(&venc.pdev->dev, "vdda_dac");
 644
 645        if (IS_ERR(vdda_dac)) {
 646                if (PTR_ERR(vdda_dac) != -EPROBE_DEFER)
 647                        DSSERR("can't get VDDA_DAC regulator\n");
 648                return PTR_ERR(vdda_dac);
 649        }
 650
 651        venc.vdda_dac_reg = vdda_dac;
 652
 653        return 0;
 654}
 655
 656static void venc_dump_regs(struct seq_file *s)
 657{
 658#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
 659
 660        if (venc_runtime_get())
 661                return;
 662
 663        DUMPREG(VENC_F_CONTROL);
 664        DUMPREG(VENC_VIDOUT_CTRL);
 665        DUMPREG(VENC_SYNC_CTRL);
 666        DUMPREG(VENC_LLEN);
 667        DUMPREG(VENC_FLENS);
 668        DUMPREG(VENC_HFLTR_CTRL);
 669        DUMPREG(VENC_CC_CARR_WSS_CARR);
 670        DUMPREG(VENC_C_PHASE);
 671        DUMPREG(VENC_GAIN_U);
 672        DUMPREG(VENC_GAIN_V);
 673        DUMPREG(VENC_GAIN_Y);
 674        DUMPREG(VENC_BLACK_LEVEL);
 675        DUMPREG(VENC_BLANK_LEVEL);
 676        DUMPREG(VENC_X_COLOR);
 677        DUMPREG(VENC_M_CONTROL);
 678        DUMPREG(VENC_BSTAMP_WSS_DATA);
 679        DUMPREG(VENC_S_CARR);
 680        DUMPREG(VENC_LINE21);
 681        DUMPREG(VENC_LN_SEL);
 682        DUMPREG(VENC_L21__WC_CTL);
 683        DUMPREG(VENC_HTRIGGER_VTRIGGER);
 684        DUMPREG(VENC_SAVID__EAVID);
 685        DUMPREG(VENC_FLEN__FAL);
 686        DUMPREG(VENC_LAL__PHASE_RESET);
 687        DUMPREG(VENC_HS_INT_START_STOP_X);
 688        DUMPREG(VENC_HS_EXT_START_STOP_X);
 689        DUMPREG(VENC_VS_INT_START_X);
 690        DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
 691        DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
 692        DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
 693        DUMPREG(VENC_VS_EXT_STOP_Y);
 694        DUMPREG(VENC_AVID_START_STOP_X);
 695        DUMPREG(VENC_AVID_START_STOP_Y);
 696        DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
 697        DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
 698        DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
 699        DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
 700        DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
 701        DUMPREG(VENC_GEN_CTRL);
 702        DUMPREG(VENC_OUTPUT_CONTROL);
 703        DUMPREG(VENC_OUTPUT_TEST);
 704
 705        venc_runtime_put();
 706
 707#undef DUMPREG
 708}
 709
 710static int venc_get_clocks(struct platform_device *pdev)
 711{
 712        struct clk *clk;
 713
 714        if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
 715                clk = devm_clk_get(&pdev->dev, "tv_dac_clk");
 716                if (IS_ERR(clk)) {
 717                        DSSERR("can't get tv_dac_clk\n");
 718                        return PTR_ERR(clk);
 719                }
 720        } else {
 721                clk = NULL;
 722        }
 723
 724        venc.tv_dac_clk = clk;
 725
 726        return 0;
 727}
 728
 729static int venc_connect(struct omap_dss_device *dssdev,
 730                struct omap_dss_device *dst)
 731{
 732        struct omap_overlay_manager *mgr;
 733        int r;
 734
 735        r = venc_init_regulator();
 736        if (r)
 737                return r;
 738
 739        mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
 740        if (!mgr)
 741                return -ENODEV;
 742
 743        r = dss_mgr_connect(mgr, dssdev);
 744        if (r)
 745                return r;
 746
 747        r = omapdss_output_set_device(dssdev, dst);
 748        if (r) {
 749                DSSERR("failed to connect output to new device: %s\n",
 750                                dst->name);
 751                dss_mgr_disconnect(mgr, dssdev);
 752                return r;
 753        }
 754
 755        return 0;
 756}
 757
 758static void venc_disconnect(struct omap_dss_device *dssdev,
 759                struct omap_dss_device *dst)
 760{
 761        WARN_ON(dst != dssdev->dst);
 762
 763        if (dst != dssdev->dst)
 764                return;
 765
 766        omapdss_output_unset_device(dssdev);
 767
 768        if (dssdev->manager)
 769                dss_mgr_disconnect(dssdev->manager, dssdev);
 770}
 771
 772static const struct omapdss_atv_ops venc_ops = {
 773        .connect = venc_connect,
 774        .disconnect = venc_disconnect,
 775
 776        .enable = venc_display_enable,
 777        .disable = venc_display_disable,
 778
 779        .check_timings = venc_check_timings,
 780        .set_timings = venc_set_timings,
 781        .get_timings = venc_get_timings,
 782
 783        .set_type = venc_set_type,
 784        .invert_vid_out_polarity = venc_invert_vid_out_polarity,
 785
 786        .set_wss = venc_set_wss,
 787        .get_wss = venc_get_wss,
 788};
 789
 790static void venc_init_output(struct platform_device *pdev)
 791{
 792        struct omap_dss_device *out = &venc.output;
 793
 794        out->dev = &pdev->dev;
 795        out->id = OMAP_DSS_OUTPUT_VENC;
 796        out->output_type = OMAP_DISPLAY_TYPE_VENC;
 797        out->name = "venc.0";
 798        out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
 799        out->ops.atv = &venc_ops;
 800        out->owner = THIS_MODULE;
 801
 802        omapdss_register_output(out);
 803}
 804
 805static void __exit venc_uninit_output(struct platform_device *pdev)
 806{
 807        struct omap_dss_device *out = &venc.output;
 808
 809        omapdss_unregister_output(out);
 810}
 811
 812static int venc_probe_of(struct platform_device *pdev)
 813{
 814        struct device_node *node = pdev->dev.of_node;
 815        struct device_node *ep;
 816        u32 channels;
 817        int r;
 818
 819        ep = omapdss_of_get_first_endpoint(node);
 820        if (!ep)
 821                return 0;
 822
 823        venc.invert_polarity = of_property_read_bool(ep, "ti,invert-polarity");
 824
 825        r = of_property_read_u32(ep, "ti,channels", &channels);
 826        if (r) {
 827                dev_err(&pdev->dev,
 828                        "failed to read property 'ti,channels': %d\n", r);
 829                goto err;
 830        }
 831
 832        switch (channels) {
 833        case 1:
 834                venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE;
 835                break;
 836        case 2:
 837                venc.type = OMAP_DSS_VENC_TYPE_SVIDEO;
 838                break;
 839        default:
 840                dev_err(&pdev->dev, "bad channel propert '%d'\n", channels);
 841                r = -EINVAL;
 842                goto err;
 843        }
 844
 845        of_node_put(ep);
 846
 847        return 0;
 848err:
 849        of_node_put(ep);
 850
 851        return 0;
 852}
 853
 854/* VENC HW IP initialisation */
 855static int omap_venchw_probe(struct platform_device *pdev)
 856{
 857        u8 rev_id;
 858        struct resource *venc_mem;
 859        int r;
 860
 861        venc.pdev = pdev;
 862
 863        mutex_init(&venc.venc_lock);
 864
 865        venc.wss_data = 0;
 866
 867        venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
 868        if (!venc_mem) {
 869                DSSERR("can't get IORESOURCE_MEM VENC\n");
 870                return -EINVAL;
 871        }
 872
 873        venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
 874                                 resource_size(venc_mem));
 875        if (!venc.base) {
 876                DSSERR("can't ioremap VENC\n");
 877                return -ENOMEM;
 878        }
 879
 880        r = venc_get_clocks(pdev);
 881        if (r)
 882                return r;
 883
 884        pm_runtime_enable(&pdev->dev);
 885
 886        r = venc_runtime_get();
 887        if (r)
 888                goto err_runtime_get;
 889
 890        rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
 891        dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
 892
 893        venc_runtime_put();
 894
 895        if (pdev->dev.of_node) {
 896                r = venc_probe_of(pdev);
 897                if (r) {
 898                        DSSERR("Invalid DT data\n");
 899                        goto err_probe_of;
 900                }
 901        }
 902
 903        dss_debugfs_create_file("venc", venc_dump_regs);
 904
 905        venc_init_output(pdev);
 906
 907        return 0;
 908
 909err_probe_of:
 910err_runtime_get:
 911        pm_runtime_disable(&pdev->dev);
 912        return r;
 913}
 914
 915static int __exit omap_venchw_remove(struct platform_device *pdev)
 916{
 917        venc_uninit_output(pdev);
 918
 919        pm_runtime_disable(&pdev->dev);
 920
 921        return 0;
 922}
 923
 924static int venc_runtime_suspend(struct device *dev)
 925{
 926        if (venc.tv_dac_clk)
 927                clk_disable_unprepare(venc.tv_dac_clk);
 928
 929        dispc_runtime_put();
 930
 931        return 0;
 932}
 933
 934static int venc_runtime_resume(struct device *dev)
 935{
 936        int r;
 937
 938        r = dispc_runtime_get();
 939        if (r < 0)
 940                return r;
 941
 942        if (venc.tv_dac_clk)
 943                clk_prepare_enable(venc.tv_dac_clk);
 944
 945        return 0;
 946}
 947
 948static const struct dev_pm_ops venc_pm_ops = {
 949        .runtime_suspend = venc_runtime_suspend,
 950        .runtime_resume = venc_runtime_resume,
 951};
 952
 953
 954static const struct of_device_id venc_of_match[] = {
 955        { .compatible = "ti,omap2-venc", },
 956        { .compatible = "ti,omap3-venc", },
 957        { .compatible = "ti,omap4-venc", },
 958        {},
 959};
 960
 961static struct platform_driver omap_venchw_driver = {
 962        .probe          = omap_venchw_probe,
 963        .remove         = __exit_p(omap_venchw_remove),
 964        .driver         = {
 965                .name   = "omapdss_venc",
 966                .pm     = &venc_pm_ops,
 967                .of_match_table = venc_of_match,
 968                .suppress_bind_attrs = true,
 969        },
 970};
 971
 972int __init venc_init_platform_driver(void)
 973{
 974        return platform_driver_register(&omap_venchw_driver);
 975}
 976
 977void __exit venc_uninit_platform_driver(void)
 978{
 979        platform_driver_unregister(&omap_venchw_driver);
 980}
 981
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