linux/drivers/usb/host/ohci-pxa27x.c
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   1/*
   2 * OHCI HCD (Host Controller Driver) for USB.
   3 *
   4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6 * (C) Copyright 2002 Hewlett-Packard Company
   7 *
   8 * Bus Glue for pxa27x
   9 *
  10 * Written by Christopher Hoover <ch@hpl.hp.com>
  11 * Based on fragments of previous driver by Russell King et al.
  12 *
  13 * Modified for LH7A404 from ohci-sa1111.c
  14 *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
  15 *
  16 * Modified for pxa27x from ohci-lh7a404.c
  17 *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
  18 *
  19 * This file is licenced under the GPL.
  20 */
  21
  22#include <linux/clk.h>
  23#include <linux/device.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/io.h>
  26#include <linux/kernel.h>
  27#include <linux/module.h>
  28#include <linux/of_platform.h>
  29#include <linux/of_gpio.h>
  30#include <linux/platform_data/usb-ohci-pxa27x.h>
  31#include <linux/platform_data/usb-pxa3xx-ulpi.h>
  32#include <linux/platform_device.h>
  33#include <linux/signal.h>
  34#include <linux/usb.h>
  35#include <linux/usb/hcd.h>
  36#include <linux/usb/otg.h>
  37
  38#include <mach/hardware.h>
  39
  40#include "ohci.h"
  41
  42#define DRIVER_DESC "OHCI PXA27x/PXA3x driver"
  43
  44/*
  45 * UHC: USB Host Controller (OHCI-like) register definitions
  46 */
  47#define UHCREV          (0x0000) /* UHC HCI Spec Revision */
  48#define UHCHCON         (0x0004) /* UHC Host Control Register */
  49#define UHCCOMS         (0x0008) /* UHC Command Status Register */
  50#define UHCINTS         (0x000C) /* UHC Interrupt Status Register */
  51#define UHCINTE         (0x0010) /* UHC Interrupt Enable */
  52#define UHCINTD         (0x0014) /* UHC Interrupt Disable */
  53#define UHCHCCA         (0x0018) /* UHC Host Controller Comm. Area */
  54#define UHCPCED         (0x001C) /* UHC Period Current Endpt Descr */
  55#define UHCCHED         (0x0020) /* UHC Control Head Endpt Descr */
  56#define UHCCCED         (0x0024) /* UHC Control Current Endpt Descr */
  57#define UHCBHED         (0x0028) /* UHC Bulk Head Endpt Descr */
  58#define UHCBCED         (0x002C) /* UHC Bulk Current Endpt Descr */
  59#define UHCDHEAD        (0x0030) /* UHC Done Head */
  60#define UHCFMI          (0x0034) /* UHC Frame Interval */
  61#define UHCFMR          (0x0038) /* UHC Frame Remaining */
  62#define UHCFMN          (0x003C) /* UHC Frame Number */
  63#define UHCPERS         (0x0040) /* UHC Periodic Start */
  64#define UHCLS           (0x0044) /* UHC Low Speed Threshold */
  65
  66#define UHCRHDA         (0x0048) /* UHC Root Hub Descriptor A */
  67#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
  68#define UHCRHDA_OCPM    (1 << 11)       /* Over Current Protection Mode */
  69#define UHCRHDA_POTPGT(x) \
  70                        (((x) & 0xff) << 24) /* Power On To Power Good Time */
  71
  72#define UHCRHDB         (0x004C) /* UHC Root Hub Descriptor B */
  73#define UHCRHS          (0x0050) /* UHC Root Hub Status */
  74#define UHCRHPS1        (0x0054) /* UHC Root Hub Port 1 Status */
  75#define UHCRHPS2        (0x0058) /* UHC Root Hub Port 2 Status */
  76#define UHCRHPS3        (0x005C) /* UHC Root Hub Port 3 Status */
  77
  78#define UHCSTAT         (0x0060) /* UHC Status Register */
  79#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
  80#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
  81#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
  82#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
  83#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
  84#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
  85#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
  86#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
  87#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
  88
  89#define UHCHR           (0x0064) /* UHC Reset Register */
  90#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
  91#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
  92#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
  93#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
  94#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
  95#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
  96#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
  97#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
  98#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
  99#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
 100#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
 101
 102#define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
 103#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
 104#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
 105#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
 106#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
 107#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
 108                                           Interrupt Enable*/
 109#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
 110#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
 111
 112#define UHCHIT          (0x006C) /* UHC Interrupt Test register */
 113
 114#define PXA_UHC_MAX_PORTNUM    3
 115
 116static const char hcd_name[] = "ohci-pxa27x";
 117
 118static struct hc_driver __read_mostly ohci_pxa27x_hc_driver;
 119
 120struct pxa27x_ohci {
 121        struct clk      *clk;
 122        void __iomem    *mmio_base;
 123};
 124
 125#define to_pxa27x_ohci(hcd)     (struct pxa27x_ohci *)(hcd_to_ohci(hcd)->priv)
 126
 127/*
 128  PMM_NPS_MODE -- PMM Non-power switching mode
 129      Ports are powered continuously.
 130
 131  PMM_GLOBAL_MODE -- PMM global switching mode
 132      All ports are powered at the same time.
 133
 134  PMM_PERPORT_MODE -- PMM per port switching mode
 135      Ports are powered individually.
 136 */
 137static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *pxa_ohci, int mode)
 138{
 139        uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
 140        uint32_t uhcrhdb = __raw_readl(pxa_ohci->mmio_base + UHCRHDB);
 141
 142        switch (mode) {
 143        case PMM_NPS_MODE:
 144                uhcrhda |= RH_A_NPS;
 145                break;
 146        case PMM_GLOBAL_MODE:
 147                uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
 148                break;
 149        case PMM_PERPORT_MODE:
 150                uhcrhda &= ~(RH_A_NPS);
 151                uhcrhda |= RH_A_PSM;
 152
 153                /* Set port power control mask bits, only 3 ports. */
 154                uhcrhdb |= (0x7<<17);
 155                break;
 156        default:
 157                printk( KERN_ERR
 158                        "Invalid mode %d, set to non-power switch mode.\n",
 159                        mode );
 160
 161                uhcrhda |= RH_A_NPS;
 162        }
 163
 164        __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
 165        __raw_writel(uhcrhdb, pxa_ohci->mmio_base + UHCRHDB);
 166        return 0;
 167}
 168
 169/*-------------------------------------------------------------------------*/
 170
 171static inline void pxa27x_setup_hc(struct pxa27x_ohci *pxa_ohci,
 172                                   struct pxaohci_platform_data *inf)
 173{
 174        uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
 175        uint32_t uhcrhda = __raw_readl(pxa_ohci->mmio_base + UHCRHDA);
 176
 177        if (inf->flags & ENABLE_PORT1)
 178                uhchr &= ~UHCHR_SSEP1;
 179
 180        if (inf->flags & ENABLE_PORT2)
 181                uhchr &= ~UHCHR_SSEP2;
 182
 183        if (inf->flags & ENABLE_PORT3)
 184                uhchr &= ~UHCHR_SSEP3;
 185
 186        if (inf->flags & POWER_CONTROL_LOW)
 187                uhchr |= UHCHR_PCPL;
 188
 189        if (inf->flags & POWER_SENSE_LOW)
 190                uhchr |= UHCHR_PSPL;
 191
 192        if (inf->flags & NO_OC_PROTECTION)
 193                uhcrhda |= UHCRHDA_NOCP;
 194        else
 195                uhcrhda &= ~UHCRHDA_NOCP;
 196
 197        if (inf->flags & OC_MODE_PERPORT)
 198                uhcrhda |= UHCRHDA_OCPM;
 199        else
 200                uhcrhda &= ~UHCRHDA_OCPM;
 201
 202        if (inf->power_on_delay) {
 203                uhcrhda &= ~UHCRHDA_POTPGT(0xff);
 204                uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
 205        }
 206
 207        __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
 208        __raw_writel(uhcrhda, pxa_ohci->mmio_base + UHCRHDA);
 209}
 210
 211static inline void pxa27x_reset_hc(struct pxa27x_ohci *pxa_ohci)
 212{
 213        uint32_t uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR);
 214
 215        __raw_writel(uhchr | UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
 216        udelay(11);
 217        __raw_writel(uhchr & ~UHCHR_FHR, pxa_ohci->mmio_base + UHCHR);
 218}
 219
 220#ifdef CONFIG_PXA27x
 221extern void pxa27x_clear_otgph(void);
 222#else
 223#define pxa27x_clear_otgph()    do {} while (0)
 224#endif
 225
 226static int pxa27x_start_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
 227{
 228        int retval = 0;
 229        struct pxaohci_platform_data *inf;
 230        uint32_t uhchr;
 231        struct usb_hcd *hcd = dev_get_drvdata(dev);
 232
 233        inf = dev_get_platdata(dev);
 234
 235        clk_prepare_enable(pxa_ohci->clk);
 236
 237        pxa27x_reset_hc(pxa_ohci);
 238
 239        uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
 240        __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
 241
 242        while (__raw_readl(pxa_ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
 243                cpu_relax();
 244
 245        pxa27x_setup_hc(pxa_ohci, inf);
 246
 247        if (inf->init)
 248                retval = inf->init(dev);
 249
 250        if (retval < 0)
 251                return retval;
 252
 253        if (cpu_is_pxa3xx())
 254                pxa3xx_u2d_start_hc(&hcd->self);
 255
 256        uhchr = __raw_readl(pxa_ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
 257        __raw_writel(uhchr, pxa_ohci->mmio_base + UHCHR);
 258        __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, pxa_ohci->mmio_base + UHCHIE);
 259
 260        /* Clear any OTG Pin Hold */
 261        pxa27x_clear_otgph();
 262        return 0;
 263}
 264
 265static void pxa27x_stop_hc(struct pxa27x_ohci *pxa_ohci, struct device *dev)
 266{
 267        struct pxaohci_platform_data *inf;
 268        struct usb_hcd *hcd = dev_get_drvdata(dev);
 269        uint32_t uhccoms;
 270
 271        inf = dev_get_platdata(dev);
 272
 273        if (cpu_is_pxa3xx())
 274                pxa3xx_u2d_stop_hc(&hcd->self);
 275
 276        if (inf->exit)
 277                inf->exit(dev);
 278
 279        pxa27x_reset_hc(pxa_ohci);
 280
 281        /* Host Controller Reset */
 282        uhccoms = __raw_readl(pxa_ohci->mmio_base + UHCCOMS) | 0x01;
 283        __raw_writel(uhccoms, pxa_ohci->mmio_base + UHCCOMS);
 284        udelay(10);
 285
 286        clk_disable_unprepare(pxa_ohci->clk);
 287}
 288
 289#ifdef CONFIG_OF
 290static const struct of_device_id pxa_ohci_dt_ids[] = {
 291        { .compatible = "marvell,pxa-ohci" },
 292        { }
 293};
 294
 295MODULE_DEVICE_TABLE(of, pxa_ohci_dt_ids);
 296
 297static int ohci_pxa_of_init(struct platform_device *pdev)
 298{
 299        struct device_node *np = pdev->dev.of_node;
 300        struct pxaohci_platform_data *pdata;
 301        u32 tmp;
 302        int ret;
 303
 304        if (!np)
 305                return 0;
 306
 307        /* Right now device-tree probed devices don't get dma_mask set.
 308         * Since shared usb code relies on it, set it here for now.
 309         * Once we have dma capability bindings this can go away.
 310         */
 311        ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 312        if (ret)
 313                return ret;
 314
 315        pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 316        if (!pdata)
 317                return -ENOMEM;
 318
 319        if (of_get_property(np, "marvell,enable-port1", NULL))
 320                pdata->flags |= ENABLE_PORT1;
 321        if (of_get_property(np, "marvell,enable-port2", NULL))
 322                pdata->flags |= ENABLE_PORT2;
 323        if (of_get_property(np, "marvell,enable-port3", NULL))
 324                pdata->flags |= ENABLE_PORT3;
 325        if (of_get_property(np, "marvell,port-sense-low", NULL))
 326                pdata->flags |= POWER_SENSE_LOW;
 327        if (of_get_property(np, "marvell,power-control-low", NULL))
 328                pdata->flags |= POWER_CONTROL_LOW;
 329        if (of_get_property(np, "marvell,no-oc-protection", NULL))
 330                pdata->flags |= NO_OC_PROTECTION;
 331        if (of_get_property(np, "marvell,oc-mode-perport", NULL))
 332                pdata->flags |= OC_MODE_PERPORT;
 333        if (!of_property_read_u32(np, "marvell,power-on-delay", &tmp))
 334                pdata->power_on_delay = tmp;
 335        if (!of_property_read_u32(np, "marvell,port-mode", &tmp))
 336                pdata->port_mode = tmp;
 337        if (!of_property_read_u32(np, "marvell,power-budget", &tmp))
 338                pdata->power_budget = tmp;
 339
 340        pdev->dev.platform_data = pdata;
 341
 342        return 0;
 343}
 344#else
 345static int ohci_pxa_of_init(struct platform_device *pdev)
 346{
 347        return 0;
 348}
 349#endif
 350
 351/*-------------------------------------------------------------------------*/
 352
 353/* configure so an HC device and id are always provided */
 354/* always called with process context; sleeping is OK */
 355
 356
 357/**
 358 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
 359 * Context: !in_interrupt()
 360 *
 361 * Allocates basic resources for this USB host controller, and
 362 * then invokes the start() method for the HCD associated with it
 363 * through the hotplug entry's driver_data.
 364 *
 365 */
 366int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
 367{
 368        int retval, irq;
 369        struct usb_hcd *hcd;
 370        struct pxaohci_platform_data *inf;
 371        struct pxa27x_ohci *pxa_ohci;
 372        struct ohci_hcd *ohci;
 373        struct resource *r;
 374        struct clk *usb_clk;
 375
 376        retval = ohci_pxa_of_init(pdev);
 377        if (retval)
 378                return retval;
 379
 380        inf = dev_get_platdata(&pdev->dev);
 381
 382        if (!inf)
 383                return -ENODEV;
 384
 385        irq = platform_get_irq(pdev, 0);
 386        if (irq < 0) {
 387                pr_err("no resource of IORESOURCE_IRQ");
 388                return -ENXIO;
 389        }
 390
 391        usb_clk = devm_clk_get(&pdev->dev, NULL);
 392        if (IS_ERR(usb_clk))
 393                return PTR_ERR(usb_clk);
 394
 395        hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
 396        if (!hcd)
 397                return -ENOMEM;
 398
 399        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 400        if (!r) {
 401                pr_err("no resource of IORESOURCE_MEM");
 402                retval = -ENXIO;
 403                goto err;
 404        }
 405
 406        hcd->rsrc_start = r->start;
 407        hcd->rsrc_len = resource_size(r);
 408
 409        hcd->regs = devm_ioremap_resource(&pdev->dev, r);
 410        if (IS_ERR(hcd->regs)) {
 411                retval = PTR_ERR(hcd->regs);
 412                goto err;
 413        }
 414
 415        /* initialize "struct pxa27x_ohci" */
 416        pxa_ohci = to_pxa27x_ohci(hcd);
 417        pxa_ohci->clk = usb_clk;
 418        pxa_ohci->mmio_base = (void __iomem *)hcd->regs;
 419
 420        retval = pxa27x_start_hc(pxa_ohci, &pdev->dev);
 421        if (retval < 0) {
 422                pr_debug("pxa27x_start_hc failed");
 423                goto err;
 424        }
 425
 426        /* Select Power Management Mode */
 427        pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
 428
 429        if (inf->power_budget)
 430                hcd->power_budget = inf->power_budget;
 431
 432        /* The value of NDP in roothub_a is incorrect on this hardware */
 433        ohci = hcd_to_ohci(hcd);
 434        ohci->num_ports = 3;
 435
 436        retval = usb_add_hcd(hcd, irq, 0);
 437        if (retval == 0) {
 438                device_wakeup_enable(hcd->self.controller);
 439                return retval;
 440        }
 441
 442        pxa27x_stop_hc(pxa_ohci, &pdev->dev);
 443 err:
 444        usb_put_hcd(hcd);
 445        return retval;
 446}
 447
 448
 449/* may be called without controller electrically present */
 450/* may be called with controller, bus, and devices active */
 451
 452/**
 453 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
 454 * @dev: USB Host Controller being removed
 455 * Context: !in_interrupt()
 456 *
 457 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
 458 * the HCD's stop() method.  It is always called from a thread
 459 * context, normally "rmmod", "apmd", or something similar.
 460 *
 461 */
 462void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
 463{
 464        struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
 465
 466        usb_remove_hcd(hcd);
 467        pxa27x_stop_hc(pxa_ohci, &pdev->dev);
 468        usb_put_hcd(hcd);
 469}
 470
 471/*-------------------------------------------------------------------------*/
 472
 473static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
 474{
 475        pr_debug ("In ohci_hcd_pxa27x_drv_probe");
 476
 477        if (usb_disabled())
 478                return -ENODEV;
 479
 480        return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
 481}
 482
 483static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
 484{
 485        struct usb_hcd *hcd = platform_get_drvdata(pdev);
 486
 487        usb_hcd_pxa27x_remove(hcd, pdev);
 488        return 0;
 489}
 490
 491#ifdef CONFIG_PM
 492static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
 493{
 494        struct usb_hcd *hcd = dev_get_drvdata(dev);
 495        struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
 496        struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 497        bool do_wakeup = device_may_wakeup(dev);
 498        int ret;
 499
 500
 501        if (time_before(jiffies, ohci->next_statechange))
 502                msleep(5);
 503        ohci->next_statechange = jiffies;
 504
 505        ret = ohci_suspend(hcd, do_wakeup);
 506        if (ret)
 507                return ret;
 508
 509        pxa27x_stop_hc(pxa_ohci, dev);
 510        return ret;
 511}
 512
 513static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
 514{
 515        struct usb_hcd *hcd = dev_get_drvdata(dev);
 516        struct pxa27x_ohci *pxa_ohci = to_pxa27x_ohci(hcd);
 517        struct pxaohci_platform_data *inf = dev_get_platdata(dev);
 518        struct ohci_hcd *ohci = hcd_to_ohci(hcd);
 519        int status;
 520
 521        if (time_before(jiffies, ohci->next_statechange))
 522                msleep(5);
 523        ohci->next_statechange = jiffies;
 524
 525        status = pxa27x_start_hc(pxa_ohci, dev);
 526        if (status < 0)
 527                return status;
 528
 529        /* Select Power Management Mode */
 530        pxa27x_ohci_select_pmm(pxa_ohci, inf->port_mode);
 531
 532        ohci_resume(hcd, false);
 533        return 0;
 534}
 535
 536static const struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
 537        .suspend        = ohci_hcd_pxa27x_drv_suspend,
 538        .resume         = ohci_hcd_pxa27x_drv_resume,
 539};
 540#endif
 541
 542static struct platform_driver ohci_hcd_pxa27x_driver = {
 543        .probe          = ohci_hcd_pxa27x_drv_probe,
 544        .remove         = ohci_hcd_pxa27x_drv_remove,
 545        .shutdown       = usb_hcd_platform_shutdown,
 546        .driver         = {
 547                .name   = "pxa27x-ohci",
 548                .owner  = THIS_MODULE,
 549                .of_match_table = of_match_ptr(pxa_ohci_dt_ids),
 550#ifdef CONFIG_PM
 551                .pm     = &ohci_hcd_pxa27x_pm_ops,
 552#endif
 553        },
 554};
 555
 556static const struct ohci_driver_overrides pxa27x_overrides __initconst = {
 557        .extra_priv_size =      sizeof(struct pxa27x_ohci),
 558};
 559
 560static int __init ohci_pxa27x_init(void)
 561{
 562        if (usb_disabled())
 563                return -ENODEV;
 564
 565        pr_info("%s: " DRIVER_DESC "\n", hcd_name);
 566        ohci_init_driver(&ohci_pxa27x_hc_driver, &pxa27x_overrides);
 567        return platform_driver_register(&ohci_hcd_pxa27x_driver);
 568}
 569module_init(ohci_pxa27x_init);
 570
 571static void __exit ohci_pxa27x_cleanup(void)
 572{
 573        platform_driver_unregister(&ohci_hcd_pxa27x_driver);
 574}
 575module_exit(ohci_pxa27x_cleanup);
 576
 577MODULE_DESCRIPTION(DRIVER_DESC);
 578MODULE_LICENSE("GPL");
 579MODULE_ALIAS("platform:pxa27x-ohci");
 580
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