linux/drivers/usb/host/ohci-pxa27x.c
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. .11/a>1spa= class="comment">/*1/spa="v. .21/a>1spa= class="comment"> * OHCI HCD (Host Controller Driver) for USB.1/spa="v. .31/a>1spa= class="comment"> *1/spa="v. .41/a>1spa= class="comment"> * (C) Copyright 1999 Roma= Weissgaerber <weissg@vienna.at>1/spa="v. .51/a>1spa= class="comment"> * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>1/spa="v. .61/a>1spa= class="comment"> * (C) Copyright 2002 Hewlett-Packard Compa=y1/spa="v. .71/a>1spa= class="comment"> *1/spa="v. .81/a>1spa= class="comment"> * Bus G v3 for pxa27x1/spa="v. .91/a>1spa= class="comment"> *1/spa="v. ion a>1spa= class="comment"> * Written by Christopher Hoover <ch@hpl.hp.com>1/spa="v. 111/a>1spa= class="comment"> * Based on fragments of previous driver by Russell King et al.1/spa="v. 121/a>1spa= class="comment"> *1/spa="v. 131/a>1spa= class="comment"> * Modified for LH7A404 from ohci-sa1111.c1/spa="v. 141/a>1spa= class="comment"> *  by Durgesh Pattamatta <pattamattad@sharpsec.com>1/spa="v. 151/a>1spa= class="comment"> *1/spa="v. 161/a>1spa= class="comment"> * Modified for pxa27x from ohci-lh7a404.c1/spa="v. 171/a>1spa= class="comment"> *  by Nick Bane <nick@cecomputing.co.uk> 26-8-20041/spa="v. 181/a>1spa= class="comment"> *1/spa="v. 191/a>1spa= class="comment"> * This file is licenced under the GPL.1/spa="v. 2on a>1spa= class="comment"> */1/spa="v. 211/a>v. 221/a>#include <linux/clk.h1/a>>v. 231/a>#include <linux/device.h1/a>>v. 241/a>#include <linux/dma-mapping.h1/a>>v. 251/a>#include <linux/io.h1/a>>v. 261/a>#include <linux/kernel.h1/a>>v. 271/a>#include <linux/module.h1/a>>v. 281/a>#include <linux/of_platform.h1/a>>v. 291/a>#include <linux/of_gpio.h1/a>>v. 301/a>#include <linux/platform_data/usb-ohci-pxa27x.h1/a>>v. 311/a>#include <linux/platform_data/usb-pxa3xx-ulpi.h1/a>>v. 321/a>#include <linux/platform_device.h1/a>>v. 331/a>#include <linux/regulator/consumer.h1/a>>v. 341/a>#include <linux/signal.h1/a>>v. 351/a>#include <linux/usb.h1/a>>v. 361/a>#include <linux/usb/hcd.h1/a>>v. 371/a>#include <linux/usb/otg.h1/a>>v. 381/a>v. 391/a>#include <mach/hardware.h1/a>>v. 401/a>v. 411/a>#include "ohci.h1/a>"v. 421/a>v. 431/a>#define.1a href="+code=DRIVER_DESC" class="sref">DRIVER_DESC1/a> 1spa= class="string">"OHCI PXA27x/PXA3x driver". 441/a>v. 451/a>1spa= class="comment">/*1/spa="v. 461/a>1spa= class="comment"> * UHC: USB Host Controller (OHCI-like) register definilue=s1/spa="v. 471/a>1spa= class="comment"> */1/spa="v. 481/a>#define.1a href="+code=UHCREV" class="sref">UHCREV1/a>          (0x0000) 1spa= class="comment">/* UHC HCI Spec Revis	  >*/1/spa="v. 491/a>#define.1a href="+code=UHCHCON" class="sref">UHCHCON1/a>         (0x0004) 1spa= class="comment">/* UHC Host Control Register */1/spa="v. 501/a>#define.1a href="+code=UHCCOMS" class="sref">UHCCOMS1/a>         (0x0008) 1spa= class="comment">/* UHC Command Status Register */1/spa="v. 511/a>#define.1a href="+code=UHCINTS" class="sref">UHCINTS1/a>         (0x000C) 1spa= class="comment">/* UHC Interrupt Status Register */1/spa="v. 521/a>#define.1a href="+code=UHCINTE" class="sref">UHCINTE1/a>         (0x0010) 1spa= class="comment">/* UHC Interrupt Enable */1/spa="v. 531/a>#define.1a href="+code=UHCINTD" class="sref">UHCINTD1/a>         (0x0014) 1spa= class="comment">/* UHC Interrupt Disable */1/spa="v. 541/a>#define.1a href="+code=UHCHCCA" class="sref">UHCHCCA1/a>         (0x0018) 1spa= class="comment">/* UHC Host Controller Comm. Area */1/spa="v. 551/a>#define.1a href="+code=UHCPCED" class="sref">UHCPCED1/a>         (0x001C) 1spa= class="comment">/* UHC Period Current Endpt Descr */1/spa="v. 561/a>#define.1a href="+code=UHCCHED" class="sref">UHCCHED1/a>         (0x0020) 1spa= class="comment">/* UHC Control Head Endpt Descr */1/spa="v. 571/a>#define.1a href="+code=UHCCCED" class="sref">UHCCCED1/a>         (0x0024) 1spa= class="comment">/* UHC Control Current Endpt Descr */1/spa="v. 581/a>#define.1a href="+code=UHCBHED" class="sref">UHCBHED1/a>         (0x0028) 1spa= class="comment">/* UHC Bulk Head Endpt Descr */1/spa="v. 591/a>#define.1a href="+code=UHCBCED" class="sref">UHCBCED1/a>         (0x002C) 1spa= class="comment">/* UHC Bulk Current Endpt Descr */1/spa="v. 601/a>#define.1a href="+code=UHCDHEAD" class="sref">UHCDHEAD1/a>        (0x0030) 1spa= class="comment">/* UHC Done.Head */1/spa="v. 611/a>#define.1a href="+code=UHCFMI" class="sref">UHCFMI1/a>          (0x0034) 1spa= class="comment">/* UHC Fram3 Interval */1/spa="v. 621/a>#define.1a href="+code=UHCFMR" class="sref">UHCFMR1/a>          (0x0038) 1spa= class="comment">/* UHC Fram3 Remaining */1/spa="v. 631/a>#define.1a href="+code=UHCFMN" class="sref">UHCFMN1/a>          (0x003C) 1spa= class="comment">/* UHC Fram3 Number */1/spa="v. 641/a>#define.1a href="+code=UHCPERS" class="sref">UHCPERS1/a>         (0x0040) 1spa= class="comment">/* UHC Periodic Start */1/spa="v. 651/a>#define.1a href="+code=UHCLS" class="sref">UHCLS1/a>           (0x0044) 1spa= class="comment">/* UHC Low Speed Threshold */1/spa="v. 661/a>v. 671/a>#define.1a href="+code=UHCRHDA" class="sref">UHCRHDA1/a>         (0x0048) 1spa= class="comment">/* UHC Root Hub Descriptor A */1/spa="v. 681/a>#define.1a href="+code=UHCRHDA_NOCP" class="sref">UHCRHDA_NOCP1/a>    (1 << 12)       1spa= class="comment">/* No over current proteclue= */1/spa="v. 691/a>#define.1a href="+code=UHCRHDA_OCPM" class="sref">UHCRHDA_OCPM1/a>    (1 << 11)       1spa= class="comment">/* Over Current Proteclue= Mode */1/spa="v. 701/a>#define.1a href="+code=UHCRHDA_POTPGT" class="sref">UHCRHDA_POTPGT1/a>(1a href="+code=x" class="sref">x1/a>) \v. 711/a>                        (((1a href="+code=x" class="sref">x1/a>) & 0xff) << 24) 1spa= class="comment">/* Power On To Power Good Time */1/spa="v. 721/a>v. 731/a>#define.1a href="+code=UHCRHDB" class="sref">UHCRHDB1/a>         (0x004C) 1spa= class="comment">/* UHC Root Hub Descriptor B */1/spa="v. 741/a>#define.1a href="+code=UHCRHS" class="sref">UHCRHS1/a>          (0x0050) 1spa= class="comment">/* UHC Root Hub Status */1/spa="v. 751/a>#define.1a href="+code=UHCRHPS1" class="sref">UHCRHPS11/a>        (0x0054) 1spa= class="comment">/* UHC Root Hub Port 1 Status */1/spa="v. 761/a>#define.1a href="+code=UHCRHPS2" class="sref">UHCRHPS21/a>        (0x0058) 1spa= class="comment">/* UHC Root Hub Port 2 Status */1/spa="v. 771/a>#define.1a href="+code=UHCRHPS3" class="sref">UHCRHPS31/a>        (0x005C) 1spa= class="comment">/* UHC Root Hub Port 3 Status */1/spa="v. 781/a>v. 791/a>#define.1a href="+code=UHCSTAT" class="sref">UHCSTAT1/a>         (0x0060) 1spa= class="comment">/* UHC Status Register */1/spa="v. 801/a>#define.1a href="+code=UHCSTAT_UPS3" class="sref">UHCSTAT_UPS31/a>    (1 << 16)       1spa= class="comment">/* USB Power Sense Port3 */1/spa="v. 811/a>#define.1a href="+code=UHCSTAT_SBMAI" class="sref">UHCSTAT_SBMAI1/a>   (1 << 15)       1spa= class="comment">/* System Bus Master Abort Interrupt*/1/spa="v. 821/a>#define.1a href="+code=UHCSTAT_SBTAI" class="sref">UHCSTAT_SBTAI1/a>   (1 << 14)       1spa= class="comment">/* System Bus Target Abort Interrupt*/1/spa="v. 831/a>#define.1a href="+code=UHCSTAT_UPRI" class="sref">UHCSTAT_UPRI1/a>    (1 << 13)       1spa= class="comment">/* USB Port Resume Interrupt */1/spa="v. 841/a>#define.1a href="+code=UHCSTAT_UPS2" class="sref">UHCSTAT_UPS21/a>    (1 << 12)       1spa= class="comment">/* USB Power Sense Port 2 */1/spa="v. 851/a>#define.1a href="+code=UHCSTAT_UPS1" class="sref">UHCSTAT_UPS11/a>    (1 << 11)       1spa= class="comment">/* USB Power Sense Port 1 */1/spa="v. 861/a>#define.1a href="+code=UHCSTAT_HTA" class="sref">UHCSTAT_HTA1/a>     (1 << 10)       1spa= class="comment">/* HCI Target Abort */1/spa="v. 871/a>#define.1a href="+code=UHCSTAT_HBA" class="sref">UHCSTAT_HBA1/a>     (1 << 8)        1spa= class="comment">/* HCI Buffer Acluve */1/spa="v. 881/a>#define.1a href="+code=UHCSTAT_RWUE" class="sref">UHCSTAT_RWUE1/a>    (1 << 7)        1spa= class="comment">/* HCI Remote Wake Up Event */1/spa="v. 891/a>v. 901/a>#define.1a href="+code=UHCHR" class="sref">UHCHR1/a>           (0x0064) 1spa= class="comment">/* UHC Reset Register */1/spa="v. 911/a>#define.1a href="+code=UHCHR_SSEP3" class="sref">UHCHR_SSEP31/a>     (1 << 11)       1spa= class="comment">/* Sleep Standby Enable for Port3 */1/spa="v. 921/a>#define.1a href="+code=UHCHR_SSEP2" class="sref">UHCHR_SSEP21/a>     (1 << 10)       1spa= class="comment">/* Sleep Standby Enable for Port2 */1/spa="v. 931/a>#define.1a href="+code=UHCHR_SSEP1" class="sref">UHCHR_SSEP11/a>     (1 << 9)        1spa= class="comment">/* Sleep Standby Enable for Port1 */1/spa="v. 941/a>#define.1a href="+code=UHCHR_PCPL" class="sref">UHCHR_PCPL1/a>      (1 << 7)        1spa= class="comment">/* Power control polarity low */1/spa="v. 951/a>#define.1a href="+code=UHCHR_PSPL" class="sref">UHCHR_PSPL1/a>      (1 << 6)        1spa= class="comment">/* Power sense polarity low */1/spa="v. 961/a>#define.1a href="+code=UHCHR_SSE" class="sref">UHCHR_SSE1/a>       (1 << 5)        1spa= class="comment">/* Sleep Standby Enable */1/spa="v. 971/a>#define.1a href="+code=UHCHR_UIT" class="sref">UHCHR_UIT1/a>       (1 << 4)        1spa= class="comment">/* USB Interrupt Test */1/spa="v. 981/a>#define.1a href="+code=UHCHR_SSDC" class="sref">UHCHR_SSDC1/a>      (1 << 3)        1spa= class="comment">/* Simulatue= Scale Down Clock */1/spa="v. 991/a>#define.1a href="+code=UHCHR_CGR" class="sref">UHCHR_CGR1/a>       (1 << 2)        1spa= class="comment">/* Clock Generatue= Reset */1/spa="v.1001/a>#define.1a href="+code=UHCHR_FHR" class="sref">UHCHR_FHR1/a>       (1 << 1)        1spa= class="comment">/* Force Host Controller Reset */1/spa="v.1011/a>#define.1a href="+code=UHCHR_FSBIR" class="sref">UHCHR_FSBIR1/a>     (1 << 0)        1spa= class="comment">/* Force System Bus Iface Reset */1/spa="v.1021/a>v.1031/a>#define.1a href="+code=UHCHIE" class="sref">UHCHIE1/a>          (0x0068) 1spa= class="comment">/* UHC Interrupt Enable Register*/1/spa="v.1041/a>#define.1a href="+code=UHCHIE_UPS3IE" class="sref">UHCHIE_UPS3IE1/a>   (1 << 14)       1spa= class="comment">/* Power Sense Port3 IntE= */1/spa="v.1051/a>#define.1a href="+code=UHCHIE_UPRIE" class="sref">UHCHIE_UPRIE1/a>    (1 << 13)       1spa= class="comment">/* Port Resume IntE= */1/spa="v.1061/a>#define.1a href="+code=UHCHIE_UPS2IE" class="sref">UHCHIE_UPS2IE1/a>   (1 << 12)       1spa= class="comment">/* Power Sense Port2 IntE= */1/spa="v.1071/a>#define.1a href="+code=UHCHIE_UPS1IE" class="sref">UHCHIE_UPS1IE1/a>   (1 << 11)       1spa= class="comment">/* Power Sense Port1 IntE= */1/spa="v.1081/a>#define.1a href="+code=UHCHIE_TAIE" class="sref">UHCHIE_TAIE1/a>     (1 << 10)       1spa= class="comment">/* HCI Interface Transfer Abort1/spa="v.1091/a>1spa= class="comment">                                           Interrupt Enable*/1/spa="v.1101/a>#define.1a href="+code=UHCHIE_HBAIE" class="sref">UHCHIE_HBAIE1/a>    (1 << 8)        1spa= class="comment">/* HCI Buffer Acluve IntE= */1/spa="v.1111/a>#define.1a href="+code=UHCHIE_RWIE" class="sref">UHCHIE_RWIE1/a>     (1 << 7)        1spa= class="comment">/* Remote Wake-up IntE= */1/spa="v.1121/a>v.1131/a>#define.1a href="+code=UHCHIT" class="sref">UHCHIT1/a>          (0x006C) 1spa= class="comment">/* UHC Interrupt Test register */1/spa="v.1141/a>v.1151/a>#define.1a href="+code=PXA_UHC_MAX_PORTNUM" class="sref">PXA_UHC_MAX_PORTNUM1/a>    3v.1161/a>v.1171/a>static const char.1a href="+code=hcd_nam3" class="sref">hcd_nam31/a>[] = 1spa= class="string">"ohci-pxa27x".1181/a>v.1191/a>static struct.1a href="+code=hc_driver" class="sref">hc_driver1/a> 1a href="+code=__read_mostly" class="sref">__read_mostly1/a> 1a href="+code=ohci_pxa27x_hc_driver" class="sref">ohci_pxa27x_hc_driver1/a>;v.1201/a>v.1211/a>struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> {v.1221/a>        struct.1a href="+code=clk" class="sref">clk1/a>      *1a href="+code=clk" class="sref">clk1/a>;v.1231/a>        void 1a href="+code=__iomem" class="sref">__iomem1/a>    *1a href="+code=mmio_bas3" class="sref">mmio_bas31/a>;v.1241/a>        struct.1a href="+code=regulator" class="sref">regulator1/a> *1a href="+code=vbus" class="sref">vbus1/a>[3];v.1251/a>        1a href="+code=bool" class="sref">bool1/a>            1a href="+code=vbus_enabled" class="sref">vbus_enabled1/a>[3];v.1261/a>};v.1271/a>v.1281/a>#define.1a href="+code=to_pxa27x_ohci" class="sref">to_pxa27x_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>)     (struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *)(1a href="+code=hcd_to_ohci" class="sref">hcd_to_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>)->1a href="+code=priv" class="sref">priv1/a>)v.1291/a>v.13on a>1spa= class="comment">/*1/spa="v.1311/a>1spa= class="comment">  PMM_NPS_MODE -- PMM Non-power switching mode1/spa="v.1321/a>1spa= class="comment">      Ports are powered continuously.1/spa="v.1331/a>v.1341/a>1spa= class="comment">  PMM_GLOBAL_MODE -- PMM global switching mode1/spa="v.1351/a>1spa= class="comment">      All ports are powered at the sam3 time.1/spa="v.1361/a>v.1371/a>1spa= class="comment">  PMM_PERPORT_MODE -- PMM per port switching mode1/spa="v.1381/a>1spa= class="comment">      Ports are powered individually.1/spa="v.1391/a>1spa= class="comment"> */1/spa="v.1401/a>static int.1a href="+code=pxa27x_ohci_select_pmm" class="sref">pxa27x_ohci_select_pmm1/a>(struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, int.1a href="+code=mode" class="sref">mode1/a>)v.1411/a>{v.1421/a>        1a href="+code=uint32_t" class="sref">uint32_t1/a> 1a href="+code=uhcrhda" class="sref">uhcrhda1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCRHDA" class="sref">UHCRHDA1/a>);v.1431/a>        1a href="+code=uint32_t" class="sref">uint32_t1/a> 1a href="+code=uhcrhdb" class="sref">uhcrhdb1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCRHDB" class="sref">UHCRHDB1/a>);v.1441/a>v.1451/a>        switch (1a href="+code=mode" class="sref">mode1/a>) {v.1461/a>        cas3.1a href="+code=PMM_NPS_MODE" class="sref">PMM_NPS_MODE1/a>:v.1471/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> |= 1a href="+code=RH_A_NPS" class="sref">RH_A_NPS1/a>;v.1481/a>                break;v.1491/a>        cas3.1a href="+code=PMM_GLOBAL_MODE" class="sref">PMM_GLOBAL_MODE1/a>:v.1501/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> &= ~(1a href="+code=RH_A_NPS" class="sref">RH_A_NPS1/a> & 1a href="+code=RH_A_PSM" class="sref">RH_A_PSM1/a>);v.1511/a>                break;v.1521/a>        cas3.1a href="+code=PMM_PERPORT_MODE" class="sref">PMM_PERPORT_MODE1/a>:v.1531/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> &= ~(1a href="+code=RH_A_NPS" class="sref">RH_A_NPS1/a>);v.1541/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> |= 1a href="+code=RH_A_PSM" class="sref">RH_A_PSM1/a>;v.1551/a>v.1561/a>                1spa= class="comment">/* Set port power control mask bits, only 3 ports. */1/spa="v.1571/a>                1a href="+code=uhcrhdb" class="sref">uhcrhdb1/a> |= (0x7<<17);v.1581/a>                break;v.1591/a>        default:v.1601/a>                1a href="+code=printk" class="sref">printk1/a>( 1a href="+code=KERN_ERR" class="sref">KERN_ERR1/a>v.1611/a>                        1spa= class="string">"Invalid mode %d, set to non-power switch mode.\n".1621/a>                        1a href="+code=mode" class="sref">mode1/a> );v.1631/a>v.1641/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> |= 1a href="+code=RH_A_NPS" class="sref">RH_A_NPS1/a>;v.1651/a>        }v.1661/a>v.1671/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhcrhda" class="sref">uhcrhda1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCRHDA" class="sref">UHCRHDA1/a>);v.1681/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhcrhdb" class="sref">uhcrhdb1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCRHDB" class="sref">UHCRHDB1/a>);v.1691/a>        return 0;v.1701/a>}v.1711/a>v.1721/a>static int.1a href="+code=pxa27x_ohci_set_vbus_power" class="sref">pxa27x_ohci_set_vbus_power1/a>(struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>,v.1731/a>                                      unsigned int.1a href="+code=port" class="sref">port1/a>,.1a href="+code=bool" class="sref">bool1/a> 1a href="+code=enable" class="sref">enable1/a>)v.1741/a>{v.1751/a>        struct.1a href="+code=regulator" class="sref">regulator1/a> *1a href="+code=vbus" class="sref">vbus1/a> = 1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=vbus" class="sref">vbus1/a>[1a href="+code=port" class="sref">port1/a>];v.1761/a>        int.1a href="+code=ret" class="sref">ret1/a> = 0;v.1771/a>v.1781/a>        if (1a href="+code=IS_ERR_OR_NULL" class="sref">IS_ERR_OR_NULL1/a>(1a href="+code=vbus" class="sref">vbus1/a>))v.1791/a>                return 0;v.1801/a>v.1811/a>        if (1a href="+code=enable" class="sref">enable1/a> && !1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=vbus_enabled" class="sref">vbus_enabled1/a>[1a href="+code=port" class="sref">port1/a>])v.1821/a>                1a href="+code=ret" class="sref">ret1/a> = 1a href="+code=regulator_enable" class="sref">regulator_enable1/a>(1a href="+code=vbus" class="sref">vbus1/a>);v.1831/a>        else if (!1a href="+code=enable" class="sref">enable1/a> && 1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=vbus_enabled" class="sref">vbus_enabled1/a>[1a href="+code=port" class="sref">port1/a>])v.1841/a>                1a href="+code=ret" class="sref">ret1/a> = 1a href="+code=regulator_disable" class="sref">regulator_disable1/a>(1a href="+code=vbus" class="sref">vbus1/a>);v.1851/a>v.1861/a>        if (1a href="+code=ret" class="sref">ret1/a> < 0)v.1871/a>                return 1a href="+code=ret" class="sref">ret1/a>;v.1881/a>v.1891/a>        1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=vbus_enabled" class="sref">vbus_enabled1/a>[1a href="+code=port" class="sref">port1/a>] = 1a href="+code=enable" class="sref">enable1/a>;v.1901/a>v.1911/a>        return 0;v.1921/a>}v.1931/a>v.1941/a>static int.1a href="+code=pxa27x_ohci_hub_control" class="sref">pxa27x_ohci_hub_control1/a>(struct.1a href="+code=usb_hcd" class="sref">usb_hcd1/a> *1a href="+code=hcd" class="sref">hcd1/a>,.1a href="+code=u16" class="sref">u161/a>.1a href="+code=typeReq" class="sref">typeReq1/a>,.1a href="+code=u16" class="sref">u161/a>.1a href="+code=wValue" class="sref">wValue1/a>,v.1951/a>                                   1a href="+code=u16" class="sref">u161/a>.1a href="+code=wIndex" class="sref">wIndex1/a>,.char.*1a href="+code=buf" class="sref">buf1/a>,.1a href="+code=u16" class="sref">u161/a>.1a href="+code=wLength" class="sref">wLength1/a>)v.1961/a>{v.1971/a>        struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a> = 1a href="+code=to_pxa27x_ohci" class="sref">to_pxa27x_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.1981/a>        int.1a href="+code=ret" class="sref">ret1/a>;v.1991/a>v.2001/a>        switch (1a href="+code=typeReq" class="sref">typeReq1/a>) {v.2011/a>        cas3.1a href="+code=SetPortFeature" class="sref">SetPortFeature1/a>:v.2021/a>        cas3.1a href="+code=ClearPortFeature" class="sref">ClearPortFeature1/a>:v.2031/a>                if (!1a href="+code=wIndex" class="sref">wIndex1/a> ||.1a href="+code=wIndex" class="sref">wIndex1/a> > 3)v.2041/a>                        return -1a href="+code=EPIPE" class="sref">EPIPE1/a>;v.2051/a>v.2061/a>                if (1a href="+code=wValue" class="sref">wValue1/a> != 1a href="+code=USB_PORT_FEAT_POWER" class="sref">USB_PORT_FEAT_POWER1/a>)v.2071/a>                        break;v.2081/a>v.2091/a>                1a href="+code=ret" class="sref">ret1/a> = 1a href="+code=pxa27x_ohci_set_vbus_power" class="sref">pxa27x_ohci_set_vbus_power1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>,.1a href="+code=wIndex" class="sref">wIndex1/a> - 1,v.2101/a>                                                 1a href="+code=typeReq" class="sref">typeReq1/a> == 1a href="+code=SetPortFeature" class="sref">SetPortFeature1/a>);v.2111/a>                if (1a href="+code=ret" class="sref">ret1/a>)v.2121/a>                        return 1a href="+code=ret" class="sref">ret1/a>;v.2131/a>                break;v.2141/a>        }v.2151/a>v.2161/a>        return 1a href="+code=ohci_hub_control" class="sref">ohci_hub_control1/a>(1a href="+code=hcd" class="sref">hcd1/a>,.1a href="+code=typeReq" class="sref">typeReq1/a>,.1a href="+code=wValue" class="sref">wValue1/a>,.1a href="+code=wIndex" class="sref">wIndex1/a>,.1a href="+code=buf" class="sref">buf1/a>,.1a href="+code=wLength" class="sref">wLength1/a>);v.2171/a>}v.2181/a>1spa= class="comment">/*-------------------------------------------------------------------------*/1/spa="v.2191/a>v.2201/a>static 1a href="+code=inline" class="sref">inline1/a> void 1a href="+code=pxa27x_setup_hc" class="sref">pxa27x_setup_hc1/a>(struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>,v.2211/a>                                   struct.1a href="+code=pxaohci_platform_data" class="sref">pxaohci_platform_data1/a> *1a href="+code=inf" class="sref">inf1/a>)v.2221/a>{v.2231/a>        1a href="+code=uint32_t" class="sref">uint32_t1/a> 1a href="+code=uhchr" class="sref">uhchr1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>);v.2241/a>        1a href="+code=uint32_t" class="sref">uint32_t1/a> 1a href="+code=uhcrhda" class="sref">uhcrhda1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCRHDA" class="sref">UHCRHDA1/a>);v.2251/a>v.2261/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.1a href="+code=ENABLE_PORT1" class="sref">ENABLE_PORT11/a>)v.2271/a>                1a href="+code=uhchr" class="sref">uhchr1/a> &= ~1a href="+code=UHCHR_SSEP1" class="sref">UHCHR_SSEP11/a>;v.2281/a>v.2291/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.1a href="+code=ENABLE_PORT2" class="sref">ENABLE_PORT21/a>)v.2301/a>                1a href="+code=uhchr" class="sref">uhchr1/a> &= ~1a href="+code=UHCHR_SSEP2" class="sref">UHCHR_SSEP21/a>;v.2311/a>v.2321/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.1a href="+code=ENABLE_PORT3" class="sref">ENABLE_PORT31/a>)v.2331/a>                1a href="+code=uhchr" class="sref">uhchr1/a> &= ~1a href="+code=UHCHR_SSEP3" class="sref">UHCHR_SSEP31/a>;v.2341/a>v.2351/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.1a href="+code=POWER_CONTROL_LOW" class="sref">POWER_CONTROL_LOW1/a>)v.2361/a>                1a href="+code=uhchr" class="sref">uhchr1/a> |= 1a href="+code=UHCHR_PCPL" class="sref">UHCHR_PCPL1/a>;v.2371/a>v.2381/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.1a href="+code=POWER_SENSE_LOW" class="sref">POWER_SENSE_LOW1/a>)v.2391/a>                1a href="+code=uhchr" class="sref">uhchr1/a> |= 1a href="+code=UHCHR_PSPL" class="sref">UHCHR_PSPL1/a>;v.2401/a>v.2411/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.1a href="+code=NO_OC_PROTECTION" class="sref">NO_OC_PROTECTION1/a>)v.2421/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> |= 1a href="+code=UHCRHDA_NOCP" class="sref">UHCRHDA_NOCP1/a>;v.2431/a>        elsev.2441/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> &= ~1a href="+code=UHCRHDA_NOCP" class="sref">UHCRHDA_NOCP1/a>;v.2451/a>v.2461/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.1a href="+code=OC_MODE_PERPORT" class="sref">OC_MODE_PERPORT1/a>)v.2471/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> |= 1a href="+code=UHCRHDA_OCPM" class="sref">UHCRHDA_OCPM1/a>;v.2481/a>        elsev.2491/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> &= ~1a href="+code=UHCRHDA_OCPM" class="sref">UHCRHDA_OCPM1/a>;v.2501/a>v.2511/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=power_on_delay" class="sref">power_on_delay1/a>) {v.2521/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> &= ~1a href="+code=UHCRHDA_POTPGT" class="sref">UHCRHDA_POTPGT1/a>(0xff);v.2531/a>                1a href="+code=uhcrhda" class="sref">uhcrhda1/a> |= 1a href="+code=UHCRHDA_POTPGT" class="sref">UHCRHDA_POTPGT1/a>(1a href="+code=inf" class="sref">inf1/a>->1a href="+code=power_on_delay" class="sref">power_on_delay1/a> / 2);v.2541/a>        }v.2551/a>v.2561/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhchr" class="sref">uhchr1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>);v.2571/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhcrhda" class="sref">uhcrhda1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCRHDA" class="sref">UHCRHDA1/a>);v.2581/a>}v.2591/a>v.2601/a>static 1a href="+code=inline" class="sref">inline1/a> void 1a href="+code=pxa27x_reset_hc" class="sref">pxa27x_reset_hc1/a>(struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>)v.2611/a>{v.2621/a>        1a href="+code=uint32_t" class="sref">uint32_t1/a> 1a href="+code=uhchr" class="sref">uhchr1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>);v.2631/a>v.2641/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhchr" class="sref">uhchr1/a> |.1a href="+code=UHCHR_FHR" class="sref">UHCHR_FHR1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>);v.2651/a>        1a href="+code=udelay" class="sref">udelay1/a>(11);v.2661/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhchr" class="sref">uhchr1/a> &.~1a href="+code=UHCHR_FHR" class="sref">UHCHR_FHR1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>);v.2671/a>}v.2681/a>v.2691/a>#ifdef.1a href="+code=CONFIG_PXA27x" class="sref">CONFIG_PXA27x1/a>v.2701/a>extern void 1a href="+code=pxa27x_clear_otgph" class="sref">pxa27x_clear_otgph1/a>(void);v.2711/a>#elsev.2721/a>#define.1a href="+code=pxa27x_clear_otgph" class="sref">pxa27x_clear_otgph1/a>()    do {} while (0)v.2731/a>#endifv.2741/a>v.2751/a>static int.1a href="+code=pxa27x_start_hc" class="sref">pxa27x_start_hc1/a>(struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, struct.1a href="+code=devic3" class="sref">devic31/a> *1a href="+code=dev" class="sref">dev1/a>)v.2761/a>{v.2771/a>        int.1a href="+code=retval" class="sref">retval1/a> = 0;v.2781/a>        struct.1a href="+code=pxaohci_platform_data" class="sref">pxaohci_platform_data1/a> *1a href="+code=inf" class="sref">inf1/a>;v.2791/a>        1a href="+code=uint32_t" class="sref">uint32_t1/a> 1a href="+code=uhchr" class="sref">uhchr1/a>;v.2801/a>        struct.1a href="+code=usb_hcd" class="sref">usb_hcd1/a> *1a href="+code=hcd" class="sref">hcd1/a> = 1a href="+code=dev_get_drvdata" class="sref">dev_get_drvdata1/a>(1a href="+code=dev" class="sref">dev1/a>);v.2811/a>v.2821/a>        1a href="+code=inf" class="sref">inf1/a> = 1a href="+code=dev_get_platdata" class="sref">dev_get_platdata1/a>(1a href="+code=dev" class="sref">dev1/a>);v.2831/a>v.2841/a>        1a href="+code=clk_prepare_enable" class="sref">clk_prepare_enable1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=clk" class="sref">clk1/a>);v.2851/a>v.2861/a>        1a href="+code=pxa27x_reset_hc" class="sref">pxa27x_reset_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>);v.2871/a>v.2881/a>        1a href="+code=uhchr" class="sref">uhchr1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>) |.1a href="+code=UHCHR_FSBIR" class="sref">UHCHR_FSBIR1/a>;v.2891/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhchr" class="sref">uhchr1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>);v.2901/a>v.2911/a>        while (1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>) &.1a href="+code=UHCHR_FSBIR" class="sref">UHCHR_FSBIR1/a>)v.2921/a>                1a href="+code=cpu_relax" class="sref">cpu_relax1/a>();v.2931/a>v.2941/a>        1a href="+code=pxa27x_setup_hc" class="sref">pxa27x_setup_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, 1a href="+code=inf" class="sref">inf1/a>);v.2951/a>v.2961/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=init" class="sref">init1/a>)v.2971/a>                1a href="+code=retval" class="sref">retval1/a> = 1a href="+code=inf" class="sref">inf1/a>->1a href="+code=init" class="sref">init1/a>(1a href="+code=dev" class="sref">dev1/a>);v.2981/a>v.2991/a>        if (1a href="+code=retval" class="sref">retval1/a> < 0)v.3001/a>                return 1a href="+code=retval" class="sref">retval1/a>;v.3011/a>v.3021/a>        if (1a href="+code=cpu_is_pxa3xx" class="sref">cpu_is_pxa3xx1/a>())v.3031/a>                1a href="+code=pxa3xx_u2d_start_hc" class="sref">pxa3xx_u2d_start_hc1/a>(&1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=self" class="sref">self1/a>);v.3041/a>v.3051/a>        1a href="+code=uhchr" class="sref">uhchr1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>) &.~1a href="+code=UHCHR_SSE" class="sref">UHCHR_SSE1/a>;v.3061/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhchr" class="sref">uhchr1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHR" class="sref">UHCHR1/a>);v.3071/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=UHCHIE_UPRIE" class="sref">UHCHIE_UPRIE1/a> |.1a href="+code=UHCHIE_RWIE" class="sref">UHCHIE_RWIE1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCHIE" class="sref">UHCHIE1/a>);v.3081/a>v.3091/a>        1spa= class="comment">/* Clear any OTG Pin Hold */1/spa="v.3101/a>        1a href="+code=pxa27x_clear_otgph" class="sref">pxa27x_clear_otgph1/a>();v.3111/a>        return 0;v.3121/a>}v.3131/a>v.3141/a>static void 1a href="+code=pxa27x_stop_hc" class="sref">pxa27x_stop_hc1/a>(struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, struct.1a href="+code=devic3" class="sref">devic31/a> *1a href="+code=dev" class="sref">dev1/a>)v.3151/a>{v.3161/a>        struct.1a href="+code=pxaohci_platform_data" class="sref">pxaohci_platform_data1/a> *1a href="+code=inf" class="sref">inf1/a>;v.3171/a>        struct.1a href="+code=usb_hcd" class="sref">usb_hcd1/a> *1a href="+code=hcd" class="sref">hcd1/a> = 1a href="+code=dev_get_drvdata" class="sref">dev_get_drvdata1/a>(1a href="+code=dev" class="sref">dev1/a>);v.3181/a>        1a href="+code=uint32_t" class="sref">uint32_t1/a> 1a href="+code=uhccoms" class="sref">uhccoms1/a>;v.3191/a>v.3201/a>        1a href="+code=inf" class="sref">inf1/a> = 1a href="+code=dev_get_platdata" class="sref">dev_get_platdata1/a>(1a href="+code=dev" class="sref">dev1/a>);v.3211/a>v.3221/a>        if (1a href="+code=cpu_is_pxa3xx" class="sref">cpu_is_pxa3xx1/a>())v.3231/a>                1a href="+code=pxa3xx_u2d_stop_hc" class="sref">pxa3xx_u2d_stop_hc1/a>(&1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=self" class="sref">self1/a>);v.3241/a>v.3251/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=exit" class="sref">exit1/a>)v.3261/a>                1a href="+code=inf" class="sref">inf1/a>->1a href="+code=exit" class="sref">exit1/a>(1a href="+code=dev" class="sref">dev1/a>);v.3271/a>v.3281/a>        1a href="+code=pxa27x_reset_hc" class="sref">pxa27x_reset_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>);v.3291/a>v.3301/a>        1spa= class="comment">/* Host Controller Reset */1/spa="v.3311/a>        1a href="+code=uhccoms" class="sref">uhccoms1/a> = 1a href="+code=__raw_readl" class="sref">__raw_readl1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCCOMS" class="sref">UHCCOMS1/a>) |.0x01;v.3321/a>        1a href="+code=__raw_writel" class="sref">__raw_writel1/a>(1a href="+code=uhccoms" class="sref">uhccoms1/a>,.1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> +.1a href="+code=UHCCOMS" class="sref">UHCCOMS1/a>);v.3331/a>        1a href="+code=udelay" class="sref">udelay1/a>(10);v.3341/a>v.3351/a>        1a href="+code=clk_disable_unprepare" class="sref">clk_disable_unprepare1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=clk" class="sref">clk1/a>);v.3361/a>}v.3371/a>v.3381/a>#ifdef.1a href="+code=CONFIG_OF" class="sref">CONFIG_OF1/a>v.3391/a>static const struct.1a href="+code=of_devic3_id" class="sref">of_devic3_id1/a> 1a href="+code=pxa_ohci_dt_ids" class="sref">pxa_ohci_dt_ids1/a>[] = {v.3401/a>        { .1a href="+code=compatible" class="sref">compatible1/a> = 1spa= class="string">"marvell,pxa-ohci"1/spa=" },v.3411/a>        { }v.3421/a>};v.3431/a>v.3441/a>1a href="+code=MODULE_DEVICE_TABLE" class="sref">MODULE_DEVICE_TABLE1/a>(1a href="+code=of" class="sref">of1/a>,.1a href="+code=pxa_ohci_dt_ids" class="sref">pxa_ohci_dt_ids1/a>);v.3451/a>v.3461/a>static int.1a href="+code=ohci_pxa_of_init" class="sref">ohci_pxa_of_init1/a>(struct.1a href="+code=platform_devic3" class="sref">platform_devic31/a> *1a href="+code=pdev" class="sref">pdev1/a>)v.3471/a>{v.3481/a>        struct.1a href="+code=devic3_node" class="sref">devic3_node1/a> *1a href="+code=np" class="sref">np1/a> = 1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>.1a href="+code=of_node" class="sref">of_node1/a>;v.3491/a>        struct.1a href="+code=pxaohci_platform_data" class="sref">pxaohci_platform_data1/a> *1a href="+code=pdata" class="sref">pdata1/a>;v.3501/a>        1a href="+code=u32" class="sref">u321/a> 1a href="+code=tmp" class="sref">tmp1/a>;v.3511/a>        int.1a href="+code=ret" class="sref">ret1/a>;v.3521/a>v.3531/a>        if (!1a href="+code=np" class="sref">np1/a>)v.3541/a>                return 0;v.3551/a>v.3561/a>        1spa= class="comment">/* Right now devic3-tree probed devic3s don't get dma_mask set.1/spa="v.3571/a>1spa= class="comment">         * Since shared usb code reli3s on it, set it here for now.1/spa="v.3581/a>1spa= class="comment">         * Once we have dma capability bindings this can go away.1/spa="v.3591/a>1spa= class="comment">         */1/spa="v.3601/a>        1a href="+code=ret" class="sref">ret1/a> = 1a href="+code=dma_coerc3_mask_and_coherent" class="sref">dma_coerc3_mask_and_coherent1/a>(&1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>,.1a href="+code=DMA_BIT_MASK" class="sref">DMA_BIT_MASK1/a>(32));v.3611/a>        if (1a href="+code=ret" class="sref">ret1/a>)v.3621/a>                return 1a href="+code=ret" class="sref">ret1/a>;v.3631/a>v.3641/a>        1a href="+code=pdata" class="sref">pdata1/a> = 1a href="+code=devm_kzalloc" class="sref">devm_kzalloc1/a>(&1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>,.sizeof(*1a href="+code=pdata" class="sref">pdata1/a>),.1a href="+code=GFP_KERNEL" class="sref">GFP_KERNEL1/a>);v.3651/a>        if (!1a href="+code=pdata" class="sref">pdata1/a>)v.3661/a>                return -1a href="+code=ENOMEM" class="sref">ENOMEM1/a>;v.3671/a>v.3681/a>        if (1a href="+code=of_property_read_bool" class="sref">of_property_read_bool1/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,enable-port1"1/spa="))v.3691/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=flags" class="sref">flags1/a> |= 1a href="+code=ENABLE_PORT1" class="sref">ENABLE_PORT11/a>;v.3701/a>        if (1a href="+code=of_property_read_bool" class="sref">of_property_read_bool1/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,enable-port2"1/spa="))v.3711/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=flags" class="sref">flags1/a> |= 1a href="+code=ENABLE_PORT2" class="sref">ENABLE_PORT21/a>;v.3721/a>        if (1a href="+code=of_property_read_bool" class="sref">of_property_read_bool1/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,enable-port3"1/spa="))v.3731/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=flags" class="sref">flags1/a> |= 1a href="+code=ENABLE_PORT3" class="sref">ENABLE_PORT31/a>;v.3741/a>        if (1a href="+code=of_property_read_bool" class="sref">of_property_read_bool1/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,port-sense-low"1/spa="))v.3751/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=flags" class="sref">flags1/a> |= 1a href="+code=POWER_SENSE_LOW" class="sref">POWER_SENSE_LOW1/a>;v.3761/a>        if (1a href="+code=of_property_read_bool" class="sref">of_property_read_bool1/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,power-control-low"1/spa="))v.3771/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=flags" class="sref">flags1/a> |= 1a href="+code=POWER_CONTROL_LOW" class="sref">POWER_CONTROL_LOW1/a>;v.3781/a>        if (1a href="+code=of_property_read_bool" class="sref">of_property_read_bool1/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,no-oc-protection"1/spa="))v.3791/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=flags" class="sref">flags1/a> |= 1a href="+code=NO_OC_PROTECTION" class="sref">NO_OC_PROTECTION1/a>;v.3801/a>        if (1a href="+code=of_property_read_bool" class="sref">of_property_read_bool1/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,oc-mode-perport"1/spa="))v.3811/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=flags" class="sref">flags1/a> |= 1a href="+code=OC_MODE_PERPORT" class="sref">OC_MODE_PERPORT1/a>;v.3821/a>        if (!1a href="+code=of_property_read_u32" class="sref">of_property_read_u321/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,power-on-delay"1/spa=", &1a href="+code=tmp" class="sref">tmp1/a>))v.3831/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=power_on_delay" class="sref">power_on_delay1/a> = 1a href="+code=tmp" class="sref">tmp1/a>;v.3841/a>        if (!1a href="+code=of_property_read_u32" class="sref">of_property_read_u321/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,port-mode"1/spa=", &1a href="+code=tmp" class="sref">tmp1/a>))v.3851/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=port_mode" class="sref">port_mode1/a> = 1a href="+code=tmp" class="sref">tmp1/a>;v.3861/a>        if (!1a href="+code=of_property_read_u32" class="sref">of_property_read_u321/a>(1a href="+code=np" class="sref">np1/a>, 1spa= class="string">"marvell,power-budget"1/spa=", &1a href="+code=tmp" class="sref">tmp1/a>))v.3871/a>                1a href="+code=pdata" class="sref">pdata1/a>->1a href="+code=power_budget" class="sref">power_budget1/a> = 1a href="+code=tmp" class="sref">tmp1/a>;v.3881/a>v.3891/a>        1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>.1a href="+code=platform_data" class="sref">platform_data1/a> = 1a href="+code=pdata" class="sref">pdata1/a>;v.3901/a>v.3911/a>        return 0;v.3921/a>}v.3931/a>#elsev.3941/a>static int.1a href="+code=ohci_pxa_of_init" class="sref">ohci_pxa_of_init1/a>(struct.1a href="+code=platform_devic3" class="sref">platform_devic31/a> *1a href="+code=pdev" class="sref">pdev1/a>)v.3951/a>{v.3961/a>        return 0;v.3971/a>}v.3981/a>#endifv.3991/a>v.4001/a>1spa= class="comment">/*-------------------------------------------------------------------------*/1/spa="v.4011/a>v.4021/a>1spa= class="comment">/* configure so a= HC devic3 a=d id are always provided */1/spa="v.4031/a>1spa= class="comment">/* always called with process context; sleeping is OK */1/spa="v.4041/a>v.4051/a>v.4061/a>1spa= class="comment">/**1/spa="v.4071/a>1spa= class="comment"> * ohci_hcd_pxa27x_probe - initialize pxa27x-bas3d HCDs1/spa="v.4081/a>1spa= class="comment"> * Context: !in_interrupt()1/spa="v.4091/a>1spa= class="comment"> *1/spa="v.4101/a>1spa= class="comment"> * Allocates basic resourc3s for this USB host controller, a=d1/spa="v.4111/a>1spa= class="comment"> * then invokes the start() method for the HCD associated with it1/spa="v.4121/a>1spa= class="comment"> * through the hotplug entry's driver_data.1/spa="v.4131/a>1spa= class="comment"> *1/spa="v.4141/a>1spa= class="comment"> */1/spa="v.4151/a>static int.1a href="+code=ohci_hcd_pxa27x_probe" class="sref">ohci_hcd_pxa27x_probe1/a>(struct.1a href="+code=platform_devic3" class="sref">platform_devic31/a> *1a href="+code=pdev" class="sref">pdev1/a>)v.4161/a>{v.4171/a>        int.1a href="+code=retval" class="sref">retval1/a>, 1a href="+code=irq" class="sref">irq1/a>;v.4181/a>        struct.1a href="+code=usb_hcd" class="sref">usb_hcd1/a> *1a href="+code=hcd" class="sref">hcd1/a>;v.4191/a>        struct.1a href="+code=pxaohci_platform_data" class="sref">pxaohci_platform_data1/a> *1a href="+code=inf" class="sref">inf1/a>;v.4201/a>        struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>;v.4211/a>        struct.1a href="+code=ohci_hcd" class="sref">ohci_hcd1/a> *1a href="+code=ohci" class="sref">ohci1/a>;v.4221/a>        struct.1a href="+code=resourc3" class="sref">resourc31/a> *1a href="+code=r" class="sref">r1/a>;v.4231/a>        struct.1a href="+code=clk" class="sref">clk1/a> *1a href="+code=usb_clk" class="sref">usb_clk1/a>;v.4241/a>        unsigned int.1a href="+code=i" class="sref">i1/a>;v.4251/a>v.4261/a>        1a href="+code=retval" class="sref">retval1/a> = 1a href="+code=ohci_pxa_of_init" class="sref">ohci_pxa_of_init1/a>(1a href="+code=pdev" class="sref">pdev1/a>);v.4271/a>        if (1a href="+code=retval" class="sref">retval1/a>)v.4281/a>                return 1a href="+code=retval" class="sref">retval1/a>;v.4291/a>v.4301/a>        1a href="+code=inf" class="sref">inf1/a> = 1a href="+code=dev_get_platdata" class="sref">dev_get_platdata1/a>(&1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>);v.4311/a>v.4321/a>        if (!1a href="+code=inf" class="sref">inf1/a>)v.4331/a>                return -1a href="+code=ENODEV" class="sref">ENODEV1/a>;v.4341/a>v.4351/a>        1a href="+code=irq" class="sref">irq1/a> = 1a href="+code=platform_get_irq" class="sref">platform_get_irq1/a>(1a href="+code=pdev" class="sref">pdev1/a>, 0);v.4361/a>        if (1a href="+code=irq" class="sref">irq1/a> < 0) {v.4371/a>                1a href="+code=pr_err" class="sref">pr_err1/a>(1spa= class="string">"no resourc3 of IORESOURCE_IRQ"1/spa=");v.4381/a>                return 1a href="+code=irq" class="sref">irq1/a>;v.4391/a>        }v.4401/a>v.4411/a>        1a href="+code=usb_clk" class="sref">usb_clk1/a> = 1a href="+code=devm_clk_get" class="sref">devm_clk_get1/a>(&1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>, 1a href="+code=NULL" class="sref">NULL1/a>);v.4421/a>        if (1a href="+code=IS_ERR" class="sref">IS_ERR1/a>(1a href="+code=usb_clk" class="sref">usb_clk1/a>))v.4431/a>                return 1a href="+code=PTR_ERR" class="sref">PTR_ERR1/a>(1a href="+code=usb_clk" class="sref">usb_clk1/a>);v.4441/a>v.4451/a>        1a href="+code=hcd" class="sref">hcd1/a> = 1a href="+code=usb_create_hcd" class="sref">usb_create_hcd1/a>(&1a href="+code=ohci_pxa27x_hc_driver" class="sref">ohci_pxa27x_hc_driver1/a>, &1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>, 1spa= class="string">"pxa27x"1/spa=");v.4461/a>        if (!1a href="+code=hcd" class="sref">hcd1/a>)v.4471/a>                return -1a href="+code=ENOMEM" class="sref">ENOMEM1/a>;v.4481/a>v.4491/a>        1a href="+code=r" class="sref">r1/a> = 1a href="+code=platform_get_resourc3" class="sref">platform_get_resourc31/a>(1a href="+code=pdev" class="sref">pdev1/a>, 1a href="+code=IORESOURCE_MEM" class="sref">IORESOURCE_MEM1/a>, 0);v.4501/a>        1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=regs" class="sref">regs1/a> = 1a href="+code=devm_ioremap_resourc3" class="sref">devm_ioremap_resourc31/a>(&1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>, 1a href="+code=r" class="sref">r1/a>);v.4511/a>        if (1a href="+code=IS_ERR" class="sref">IS_ERR1/a>(1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=regs" class="sref">regs1/a>)) {v.4521/a>                1a href="+code=retval" class="sref">retval1/a> = 1a href="+code=PTR_ERR" class="sref">PTR_ERR1/a>(1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=regs" class="sref">regs1/a>);v.4531/a>                goto 1a href="+code=err" class="sref">err1/a>;v.4541/a>        }v.4551/a>        1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=rsrc_start" class="sref">rsrc_start1/a> = 1a href="+code=r" class="sref">r1/a>->1a href="+code=start" class="sref">start1/a>;v.4561/a>        1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=rsrc_len" class="sref">rsrc_len1/a> = 1a href="+code=resourc3_size" class="sref">resourc3_size1/a>(1a href="+code=r" class="sref">r1/a>);v.4571/a>v.4581/a>        1spa= class="comment">/* initialize "struct.pxa27x_ohci" */1/spa="v.4591/a>        1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a> = 1a href="+code=to_pxa27x_ohci" class="sref">to_pxa27x_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.4601/a>        1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=clk" class="sref">clk1/a> = 1a href="+code=usb_clk" class="sref">usb_clk1/a>;v.4611/a>        1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=mmio_bas3" class="sref">mmio_bas31/a> = (void 1a href="+code=__iomem" class="sref">__iomem1/a> *)1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=regs" class="sref">regs1/a>;v.4621/a>v.4631/a>        for (1a href="+code=i" class="sref">i1/a> = 0;.1a href="+code=i" class="sref">i1/a> < 3; ++1a href="+code=i" class="sref">i1/a>) {v.4641/a>                char.1a href="+code=nam3" class="sref">nam31/a>[6];v.4651/a>v.4661/a>                if (!(1a href="+code=inf" class="sref">inf1/a>->1a href="+code=flags" class="sref">flags1/a> &.(1a href="+code=ENABLE_PORT1" class="sref">ENABLE_PORT11/a> << 1a href="+code=i" class="sref">i1/a>)))v.4671/a>                        continue;v.4681/a>v.4691/a>                1a href="+code=sprintf" class="sref">sprintf1/a>(1a href="+code=nam3" class="sref">nam31/a>, 1spa= class="string">"vbus%u"1/spa=", 1a href="+code=i" class="sref">i1/a> + 1);v.4701/a>                1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>->1a href="+code=vbus" class="sref">vbus1/a>[1a href="+code=i" class="sref">i1/a>] = 1a href="+code=devm_regulator_get" class="sref">devm_regulator_get1/a>(&1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>, 1a href="+code=nam3" class="sref">nam31/a>);v.4711/a>        }v.4721/a>v.4731/a>        1a href="+code=retval" class="sref">retval1/a> = 1a href="+code=pxa27x_start_hc" class="sref">pxa27x_start_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, &1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>);v.4741/a>        if (1a href="+code=retval" class="sref">retval1/a> < 0) {v.4751/a>                1a href="+code=pr_debug" class="sref">pr_debug1/a>(1spa= class="string">"pxa27x_start_hc failed"1/spa=");v.4761/a>                goto 1a href="+code=err" class="sref">err1/a>;v.4771/a>        }v.4781/a>v.4791/a>        1spa= class="comment">/* Select Power Management Mode */1/spa="v.4801/a>        1a href="+code=pxa27x_ohci_select_pmm" class="sref">pxa27x_ohci_select_pmm1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, 1a href="+code=inf" class="sref">inf1/a>->1a href="+code=port_mode" class="sref">port_mode1/a>);v.4811/a>v.4821/a>        if (1a href="+code=inf" class="sref">inf1/a>->1a href="+code=power_budget" class="sref">power_budget1/a>)v.4831/a>                1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=power_budget" class="sref">power_budget1/a> = 1a href="+code=inf" class="sref">inf1/a>->1a href="+code=power_budget" class="sref">power_budget1/a>;v.4841/a>v.4851/a>        1spa= class="comment">/* The valu3 of NDP in roothub_a is incorrect on this hardware */1/spa="v.4861/a>        1a href="+code=ohci" class="sref">ohci1/a> = 1a href="+code=hcd_to_ohci" class="sref">hcd_to_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.4871/a>        1a href="+code=ohci" class="sref">ohci1/a>->1a href="+code=num_ports" class="sref">num_ports1/a> = 3;v.4881/a>v.4891/a>        1a href="+code=retval" class="sref">retval1/a> = 1a href="+code=usb_add_hcd" class="sref">usb_add_hcd1/a>(1a href="+code=hcd" class="sref">hcd1/a>, 1a href="+code=irq" class="sref">irq1/a>, 0);v.4901/a>        if (1a href="+code=retval" class="sref">retval1/a> == 0) {v.4911/a>                1a href="+code=devic3_wakeup_enable" class="sref">devic3_wakeup_enable1/a>(1a href="+code=hcd" class="sref">hcd1/a>->1a href="+code=self" class="sref">self1/a>.1a href="+code=controller" class="sref">controller1/a>);v.4921/a>                return 1a href="+code=retval" class="sref">retval1/a>;v.4931/a>        }v.4941/a>v.4951/a>        1a href="+code=pxa27x_stop_hc" class="sref">pxa27x_stop_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, &1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>);v.4961/a> 1a href="+code=err" class="sref">err1/a>:v.4971/a>        1a href="+code=usb_put_hcd" class="sref">usb_put_hcd1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.4981/a>        return 1a href="+code=retval" class="sref">retval1/a>;v.4991/a>}v.5001/a>v.5011/a>v.5021/a>1spa= class="comment">/* may be called without controller electrically present */1/spa="v.5031/a>1spa= class="comment">/* may be called with controller, bus, a=d devic3s active */1/spa="v.5041/a>v.5051/a>1spa= class="comment">/**1/spa="v.5061/a>1spa= class="comment"> * ohci_hcd_pxa27x_remove - shutdown processing for pxa27x-bas3d HCDs1/spa="v.5071/a>1spa= class="comment"> * @dev: USB Host Controller being removed1/spa="v.5081/a>1spa= class="comment"> * Context: !in_interrupt()1/spa="v.5091/a>1spa= class="comment"> *1/spa="v.5101/a>1spa= class="comment"> * Reverses the effect of ohci_hcd_pxa27x_probe(), first invoking1/spa="v.5111/a>1spa= class="comment"> * the HCD's stop() method.  It is always called from a thread1/spa="v.5121/a>1spa= class="comment"> * context, normally "rmmod", "apmd", or something similar.1/spa="v.5131/a>1spa= class="comment"> *1/spa="v.5141/a>1spa= class="comment"> */1/spa="v.5151/a>static int.1a href="+code=ohci_hcd_pxa27x_remove" class="sref">ohci_hcd_pxa27x_remove1/a>(struct.1a href="+code=platform_devic3" class="sref">platform_devic31/a> *1a href="+code=pdev" class="sref">pdev1/a>)v.5161/a>{v.5171/a>        struct.1a href="+code=usb_hcd" class="sref">usb_hcd1/a> *1a href="+code=hcd" class="sref">hcd1/a> = 1a href="+code=platform_get_drvdata" class="sref">platform_get_drvdata1/a>(1a href="+code=pdev" class="sref">pdev1/a>);v.5181/a>        struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a> = 1a href="+code=to_pxa27x_ohci" class="sref">to_pxa27x_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.5191/a>        unsigned int.1a href="+code=i" class="sref">i1/a>;v.5201/a>v.5211/a>        1a href="+code=usb_remove_hcd" class="sref">usb_remove_hcd1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.5221/a>        1a href="+code=pxa27x_stop_hc" class="sref">pxa27x_stop_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, &1a href="+code=pdev" class="sref">pdev1/a>->1a href="+code=dev" class="sref">dev1/a>);v.5231/a>v.5241/a>        for (1a href="+code=i" class="sref">i1/a> = 0;.1a href="+code=i" class="sref">i1/a> < 3; ++1a href="+code=i" class="sref">i1/a>)v.5251/a>                1a href="+code=pxa27x_ohci_set_vbus_power" class="sref">pxa27x_ohci_set_vbus_power1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, 1a href="+code=i" class="sref">i1/a>, 1a href="+code=fals3" class="sref">fals31/a>);v.5261/a>v.5271/a>        1a href="+code=usb_put_hcd" class="sref">usb_put_hcd1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.5281/a>        return 0;v.5291/a>}v.5301/a>v.5311/a>1spa= class="comment">/*-------------------------------------------------------------------------*/1/spa="v.5321/a>v.5331/a>#ifdef 1a href="+code=CONFIG_PM" class="sref">CONFIG_PM1/a>v.5341/a>static int.1a href="+code=ohci_hcd_pxa27x_drv_suspend" class="sref">ohci_hcd_pxa27x_drv_suspend1/a>(struct.1a href="+code=devic3" class="sref">devic31/a> *1a href="+code=dev" class="sref">dev1/a>)v.5351/a>{v.5361/a>        struct.1a href="+code=usb_hcd" class="sref">usb_hcd1/a> *1a href="+code=hcd" class="sref">hcd1/a> = 1a href="+code=dev_get_drvdata" class="sref">dev_get_drvdata1/a>(1a href="+code=dev" class="sref">dev1/a>);v.5371/a>        struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a> = 1a href="+code=to_pxa27x_ohci" class="sref">to_pxa27x_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.5381/a>        struct.1a href="+code=ohci_hcd" class="sref">ohci_hcd1/a> *1a href="+code=ohci" class="sref">ohci1/a> = 1a href="+code=hcd_to_ohci" class="sref">hcd_to_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.5391/a>        1a href="+code=bool" class="sref">bool1/a> 1a href="+code=do_wakeup" class="sref">do_wakeup1/a> = 1a href="+code=devic3_may_wakeup" class="sref">devic3_may_wakeup1/a>(1a href="+code=dev" class="sref">dev1/a>);v.5401/a>        int.1a href="+code=ret" class="sref">ret1/a>;v.5411/a>v.5421/a>v.5431/a>        if (1a href="+code=time_befor3" class="sref">time_befor31/a>(1a href="+code=jiffies" class="sref">jiffies1/a>, 1a href="+code=ohci" class="sref">ohci1/a>->1a href="+code=next_statechang3" class="sref">next_statechang31/a>))v.5441/a>                1a href="+code=msleep" class="sref">msleep1/a>(5);v.5451/a>        1a href="+code=ohci" class="sref">ohci1/a>->1a href="+code=next_statechang3" class="sref">next_statechang31/a> = 1a href="+code=jiffies" class="sref">jiffies1/a>;v.5461/a>v.5471/a>        1a href="+code=ret" class="sref">ret1/a> = 1a href="+code=ohci_suspend" class="sref">ohci_suspend1/a>(1a href="+code=hcd" class="sref">hcd1/a>, 1a href="+code=do_wakeup" class="sref">do_wakeup1/a>);v.5481/a>        if (1a href="+code=ret" class="sref">ret1/a>)v.5491/a>                return 1a href="+code=ret" class="sref">ret1/a>;v.5501/a>v.5511/a>        1a href="+code=pxa27x_stop_hc" class="sref">pxa27x_stop_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, 1a href="+code=dev" class="sref">dev1/a>);v.5521/a>        return 1a href="+code=ret" class="sref">ret1/a>;v.5531/a>}v.5541/a>v.5551/a>static int.1a href="+code=ohci_hcd_pxa27x_drv_resum3" class="sref">ohci_hcd_pxa27x_drv_resum31/a>(struct.1a href="+code=devic3" class="sref">devic31/a> *1a href="+code=dev" class="sref">dev1/a>)v.5561/a>{v.5571/a>        struct.1a href="+code=usb_hcd" class="sref">usb_hcd1/a> *1a href="+code=hcd" class="sref">hcd1/a> = 1a href="+code=dev_get_drvdata" class="sref">dev_get_drvdata1/a>(1a href="+code=dev" class="sref">dev1/a>);v.5581/a>        struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a> *1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a> = 1a href="+code=to_pxa27x_ohci" class="sref">to_pxa27x_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.5591/a>        struct.1a href="+code=pxaohci_platform_data" class="sref">pxaohci_platform_data1/a> *1a href="+code=inf" class="sref">inf1/a> = 1a href="+code=dev_get_platdata" class="sref">dev_get_platdata1/a>(1a href="+code=dev" class="sref">dev1/a>);v.5601/a>        struct.1a href="+code=ohci_hcd" class="sref">ohci_hcd1/a> *1a href="+code=ohci" class="sref">ohci1/a> = 1a href="+code=hcd_to_ohci" class="sref">hcd_to_ohci1/a>(1a href="+code=hcd" class="sref">hcd1/a>);v.5611/a>        int.1a href="+code=status" class="sref">status1/a>;v.5621/a>v.5631/a>        if (1a href="+code=time_befor3" class="sref">time_befor31/a>(1a href="+code=jiffies" class="sref">jiffies1/a>, 1a href="+code=ohci" class="sref">ohci1/a>->1a href="+code=next_statechang3" class="sref">next_statechang31/a>))v.5641/a>                1a href="+code=msleep" class="sref">msleep1/a>(5);v.5651/a>        1a href="+code=ohci" class="sref">ohci1/a>->1a href="+code=next_statechang3" class="sref">next_statechang31/a> = 1a href="+code=jiffies" class="sref">jiffies1/a>;v.5661/a>v.5671/a>        1a href="+code=status" class="sref">status1/a> = 1a href="+code=pxa27x_start_hc" class="sref">pxa27x_start_hc1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, 1a href="+code=dev" class="sref">dev1/a>);v.5681/a>        if (1a href="+code=status" class="sref">status1/a> < 0)v.5691/a>                return 1a href="+code=status" class="sref">status1/a>;v.5701/a>v.5711/a>        1spa= class="comment">/* Select Power Management Mode */1/spa="v.5721/a>        1a href="+code=pxa27x_ohci_select_pmm" class="sref">pxa27x_ohci_select_pmm1/a>(1a href="+code=pxa_ohci" class="sref">pxa_ohci1/a>, 1a href="+code=inf" class="sref">inf1/a>->1a href="+code=port_mode" class="sref">port_mode1/a>);v.5731/a>v.5741/a>        1a href="+code=ohci_resum3" class="sref">ohci_resum31/a>(1a href="+code=hcd" class="sref">hcd1/a>, 1a href="+code=fals3" class="sref">fals31/a>);v.5751/a>        return 0;v.5761/a>}v.5771/a>v.5781/a>static const struct.1a href="+code=dev_pm_ops" class="sref">dev_pm_ops1/a> 1a href="+code=ohci_hcd_pxa27x_pm_ops" class="sref">ohci_hcd_pxa27x_pm_ops1/a> = {v.5791/a>        .1a href="+code=suspend" class="sref">suspend1/a>        = 1a href="+code=ohci_hcd_pxa27x_drv_suspend" class="sref">ohci_hcd_pxa27x_drv_suspend1/a>,v.5801/a>        .1a href="+code=resum3" class="sref">resum31/a>         = 1a href="+code=ohci_hcd_pxa27x_drv_resum3" class="sref">ohci_hcd_pxa27x_drv_resum31/a>,v.5811/a>};v.5821/a>#endifv.5831/a>v.5841/a>static struct.1a href="+code=platform_driver" class="sref">platform_driver1/a> 1a href="+code=ohci_hcd_pxa27x_driver" class="sref">ohci_hcd_pxa27x_driver1/a> = {v.5851/a>        .1a href="+code=probe" class="sref">probe1/a>          = 1a href="+code=ohci_hcd_pxa27x_probe" class="sref">ohci_hcd_pxa27x_probe1/a>,v.5861/a>        .1a href="+code=remove" class="sref">remove1/a>         = 1a href="+code=ohci_hcd_pxa27x_remove" class="sref">ohci_hcd_pxa27x_remove1/a>,v.5871/a>        .1a href="+code=shutdown" class="sref">shutdown1/a>       = 1a href="+code=usb_hcd_platform_shutdown" class="sref">usb_hcd_platform_shutdown1/a>,v.5881/a>        .1a href="+code=driver" class="sref">driver1/a>         = {v.5891/a>                .1a href="+code=nam3" class="sref">nam31/a>   = 1spa= class="string">"pxa27x-ohci"1/spa=",v.5901/a>                .1a href="+code=of_match_table" class="sref">of_match_table1/a> = 1a href="+code=of_match_ptr" class="sref">of_match_ptr1/a>(1a href="+code=pxa_ohci_dt_ids" class="sref">pxa_ohci_dt_ids1/a>),v.5911/a>#ifdef 1a href="+code=CONFIG_PM" class="sref">CONFIG_PM1/a>v.5921/a>                .1a href="+code=pm" class="sref">pm1/a>     = &1a href="+code=ohci_hcd_pxa27x_pm_ops" class="sref">ohci_hcd_pxa27x_pm_ops1/a>,v.5931/a>#endifv.5941/a>        },v.5951/a>};v.5961/a>v.5971/a>static const struct.1a href="+code=ohci_driver_overrides" class="sref">ohci_driver_overrides1/a> 1a href="+code=pxa27x_overrides" class="sref">pxa27x_overrides1/a> 1a href="+code=__initconst" class="sref">__initconst1/a> = {v.5981/a>        .1a href="+code=extra_priv_size" class="sref">extra_priv_size1/a> =      sizeof(struct.1a href="+code=pxa27x_ohci" class="sref">pxa27x_ohci1/a>),v.5991/a>};v.6001/a>v.6011/a>static int.1a href="+code=__init" class="sref">__init1/a> 1a href="+code=ohci_pxa27x_init" class="sref">ohci_pxa27x_init1/a>(void)v.6021/a>{v.6031/a>        if (1a href="+code=usb_disabled" class="sref">usb_disabled1/a>())v.6041/a>                return -1a href="+code=ENODEV" class="sref">ENODEV1/a>;v.6051/a>v.6061/a>        1a href="+code=pr_info" class="sref">pr_info1/a>(1spa= class="string">"%s: "1/spa=" 1a href="+code=DRIVER_DESC" class="sref">DRIVER_DESC1/a> 1spa= class="string">"\n"1/spa=", 1a href="+code=hcd_nam3" class="sref">hcd_nam31/a>);v.6071/a>v.6081/a>        1a href="+code=ohci_init_driver" class="sref">ohci_init_driver1/a>(&1a href="+code=ohci_pxa27x_hc_driver" class="sref">ohci_pxa27x_hc_driver1/a>, &1a href="+code=pxa27x_overrides" class="sref">pxa27x_overrides1/a>);v.6091/a>        1a href="+code=ohci_pxa27x_hc_driver" class="sref">ohci_pxa27x_hc_driver1/a>.1a href="+code=hub_control" class="sref">hub_control1/a> = 1a href="+code=pxa27x_ohci_hub_control" class="sref">pxa27x_ohci_hub_control1/a>;v.6101/a>v.6111/a>        return 1a href="+code=platform_driver_register" class="sref">platform_driver_register1/a>(&1a href="+code=ohci_hcd_pxa27x_driver" class="sref">ohci_hcd_pxa27x_driver1/a>);v.6121/a>}v.6131/a>1a href="+code=module_init" class="sref">module_init1/a>(1a href="+code=ohci_pxa27x_init" class="sref">ohci_pxa27x_init1/a>);v.6141/a>v.6151/a>static void 1a href="+code=__exit" class="sref">__exit1/a> 1a href="+code=ohci_pxa27x_cleanup" class="sref">ohci_pxa27x_cleanup1/a>(void)v.6161/a>{v.6171/a>        1a href="+code=platform_driver_unregister" class="sref">platform_driver_unregister1/a>(&1a href="+code=ohci_hcd_pxa27x_driver" class="sref">ohci_hcd_pxa27x_driver1/a>);v.6181/a>}v.6191/a>1a href="+code=module_exit" class="sref">module_exit1/a>(1a href="+code=ohci_pxa27x_cleanup" class="sref">ohci_pxa27x_cleanup1/a>);v.6201/a>v.6211/a>1a href="+code=MODULE_DESCRIPTION" class="sref">MODULE_DESCRIPTION1/a>(1a href="+code=DRIVER_DESC" class="sref">DRIVER_DESC1/a>);v.6221/a>1a href="+code=MODULE_LICENSE" class="sref">MODULE_LICENSE1/a>(1spa= class="string">"GPL"1/spa=");v.6231/a>1a href="+code=MODULE_ALIAS" class="sref">MODULE_ALIAS1/a>(1spa= class="string">"platform:pxa27x-ohci"1/spa=");v.6241/a>
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