linux/drivers/tty/serial/pch_uart.c
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   1/*
   2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3 *
   4 *This program is free software; you can redistribute it and/or modify
   5 *it under the terms of the GNU General Public License as published by
   6 *the Free Software Foundation; version 2 of the License.
   7 *
   8 *This program is distributed in the hope that it will be useful,
   9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 *GNU General Public License for more details.
  12 *
  13 *You should have received a copy of the GNU General Public License
  14 *along with this program; if not, write to the Free Software
  15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16 */
  17#if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18#define SUPPORT_SYSRQ
  19#endif
  20#include <linux/kernel.h>
  21#include <linux/serial_reg.h>
  22#include <linux/slab.h>
  23#include <linux/module.h>
  24#include <linux/pci.h>
  25#include <linux/console.h>
  26#include <linux/serial_core.h>
  27#include <linux/tty.h>
  28#include <linux/tty_flip.h>
  29#include <linux/interrupt.h>
  30#include <linux/io.h>
  31#include <linux/dmi.h>
  32#include <linux/nmi.h>
  33#include <linux/delay.h>
  34#include <linux/of.h>
  35
  36#include <linux/debugfs.h>
  37#include <linux/dmaengine.h>
  38#include <linux/pch_dma.h>
  39
  40enum {
  41        PCH_UART_HANDLED_RX_INT_SHIFT,
  42        PCH_UART_HANDLED_TX_INT_SHIFT,
  43        PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  44        PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  45        PCH_UART_HANDLED_MS_INT_SHIFT,
  46        PCH_UART_HANDLED_LS_INT_SHIFT,
  47};
  48
  49enum {
  50        PCH_UART_8LINE,
  51        PCH_UART_2LINE,
  52};
  53
  54#define PCH_UART_DRIVER_DEVICE "ttyPCH"
  55
  56/* Set the max number of UART port
  57 * Intel EG20T PCH: 4 port
  58 * LAPIS Semiconductor ML7213 IOH: 3 port
  59 * LAPIS Semiconductor ML7223 IOH: 2 port
  60*/
  61#define PCH_UART_NR     4
  62
  63#define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  64#define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  65#define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  66                                        PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  67#define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  68                                        PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  69#define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  70
  71#define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  72
  73#define PCH_UART_RBR            0x00
  74#define PCH_UART_THR            0x00
  75
  76#define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  77                                PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  78#define PCH_UART_IER_ERBFI      0x00000001
  79#define PCH_UART_IER_ETBEI      0x00000002
  80#define PCH_UART_IER_ELSI       0x00000004
  81#define PCH_UART_IER_EDSSI      0x00000008
  82
  83#define PCH_UART_IIR_IP                 0x00000001
  84#define PCH_UART_IIR_IID                0x00000006
  85#define PCH_UART_IIR_MSI                0x00000000
  86#define PCH_UART_IIR_TRI                0x00000002
  87#define PCH_UART_IIR_RRI                0x00000004
  88#define PCH_UART_IIR_REI                0x00000006
  89#define PCH_UART_IIR_TOI                0x00000008
  90#define PCH_UART_IIR_FIFO256            0x00000020
  91#define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  92#define PCH_UART_IIR_FE                 0x000000C0
  93
  94#define PCH_UART_FCR_FIFOE              0x00000001
  95#define PCH_UART_FCR_RFR                0x00000002
  96#define PCH_UART_FCR_TFR                0x00000004
  97#define PCH_UART_FCR_DMS                0x00000008
  98#define PCH_UART_FCR_FIFO256            0x00000020
  99#define PCH_UART_FCR_RFTL               0x000000C0
 100
 101#define PCH_UART_FCR_RFTL1              0x00000000
 102#define PCH_UART_FCR_RFTL64             0x00000040
 103#define PCH_UART_FCR_RFTL128            0x00000080
 104#define PCH_UART_FCR_RFTL224            0x000000C0
 105#define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 106#define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 107#define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 108#define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 109#define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 110#define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 111#define PCH_UART_FCR_RFTL_SHIFT         6
 112
 113#define PCH_UART_LCR_WLS        0x00000003
 114#define PCH_UART_LCR_STB        0x00000004
 115#define PCH_UART_LCR_PEN        0x00000008
 116#define PCH_UART_LCR_EPS        0x00000010
 117#define PCH_UART_LCR_SP         0x00000020
 118#define PCH_UART_LCR_SB         0x00000040
 119#define PCH_UART_LCR_DLAB       0x00000080
 120#define PCH_UART_LCR_NP         0x00000000
 121#define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 122#define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 123#define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 124#define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 125                                PCH_UART_LCR_SP)
 126
 127#define PCH_UART_LCR_5BIT       0x00000000
 128#define PCH_UART_LCR_6BIT       0x00000001
 129#define PCH_UART_LCR_7BIT       0x00000002
 130#define PCH_UART_LCR_8BIT       0x00000003
 131
 132#define PCH_UART_MCR_DTR        0x00000001
 133#define PCH_UART_MCR_RTS        0x00000002
 134#define PCH_UART_MCR_OUT        0x0000000C
 135#define PCH_UART_MCR_LOOP       0x00000010
 136#define PCH_UART_MCR_AFE        0x00000020
 137
 138#define PCH_UART_LSR_DR         0x00000001
 139#define PCH_UART_LSR_ERR        (1<<7)
 140
 141#define PCH_UART_MSR_DCTS       0x00000001
 142#define PCH_UART_MSR_DDSR       0x00000002
 143#define PCH_UART_MSR_TERI       0x00000004
 144#define PCH_UART_MSR_DDCD       0x00000008
 145#define PCH_UART_MSR_CTS        0x00000010
 146#define PCH_UART_MSR_DSR        0x00000020
 147#define PCH_UART_MSR_RI         0x00000040
 148#define PCH_UART_MSR_DCD        0x00000080
 149#define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 150                                PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 151
 152#define PCH_UART_DLL            0x00
 153#define PCH_UART_DLM            0x01
 154
 155#define PCH_UART_BRCSR          0x0E
 156
 157#define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 158#define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 159#define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 160#define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 161#define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 162
 163#define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 164#define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 165#define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 166#define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 167#define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 168#define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 169#define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 170#define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 171#define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 172#define PCH_UART_HAL_STB1               0
 173#define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 174
 175#define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 176#define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 177#define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 178                                        PCH_UART_HAL_CLR_RX_FIFO)
 179
 180#define PCH_UART_HAL_DMA_MODE0          0
 181#define PCH_UART_HAL_FIFO_DIS           0
 182#define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 183#define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 184                                        PCH_UART_FCR_FIFO256)
 185#define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 186#define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 187#define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 188#define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 189#define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 190#define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 191#define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 192#define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 193#define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 194#define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 195#define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 196#define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 197#define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 198#define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 199
 200#define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 201#define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 202#define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 203#define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 204#define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 205
 206#define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 207#define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 208#define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 209#define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 210#define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 211
 212#define PCI_VENDOR_ID_ROHM              0x10DB
 213
 214#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 215
 216#define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 217#define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 218#define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 219#define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 220#define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 221#define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 222
 223struct pch_uart_buffer {
 224        unsigned char *buf;
 225        int size;
 226};
 227
 228struct eg20t_port {
 229        struct uart_port port;
 230        int port_type;
 231        void __iomem *membase;
 232        resource_size_t mapbase;
 233        unsigned int iobase;
 234        struct pci_dev *pdev;
 235        int fifo_size;
 236        unsigned int uartclk;
 237        int start_tx;
 238        int start_rx;
 239        int tx_empty;
 240        int trigger;
 241        int trigger_level;
 242        struct pch_uart_buffer rxbuf;
 243        unsigned int dmsr;
 244        unsigned int fcr;
 245        unsigned int mcr;
 246        unsigned int use_dma;
 247        struct dma_async_tx_descriptor  *desc_tx;
 248        struct dma_async_tx_descriptor  *desc_rx;
 249        struct pch_dma_slave            param_tx;
 250        struct pch_dma_slave            param_rx;
 251        struct dma_chan                 *chan_tx;
 252        struct dma_chan                 *chan_rx;
 253        struct scatterlist              *sg_tx_p;
 254        int                             nent;
 255        struct scatterlist              sg_rx;
 256        int                             tx_dma_use;
 257        void                            *rx_buf_virt;
 258        dma_addr_t                      rx_buf_dma;
 259
 260        struct dentry   *debugfs;
 261#define IRQ_NAME_SIZE 17
 262        char                            irq_name[IRQ_NAME_SIZE];
 263
 264        /* protect the eg20t_port private structure and io access to membase */
 265        spinlock_t lock;
 266};
 267
 268/**
 269 * struct pch_uart_driver_data - private data structure for UART-DMA
 270 * @port_type:                  The number of DMA channel
 271 * @line_no:                    UART port line number (0, 1, 2...)
 272 */
 273struct pch_uart_driver_data {
 274        int port_type;
 275        int line_no;
 276};
 277
 278enum pch_uart_num_t {
 279        pch_et20t_uart0 = 0,
 280        pch_et20t_uart1,
 281        pch_et20t_uart2,
 282        pch_et20t_uart3,
 283        pch_ml7213_uart0,
 284        pch_ml7213_uart1,
 285        pch_ml7213_uart2,
 286        pch_ml7223_uart0,
 287        pch_ml7223_uart1,
 288        pch_ml7831_uart0,
 289        pch_ml7831_uart1,
 290};
 291
 292static struct pch_uart_driver_data drv_dat[] = {
 293        [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 294        [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 295        [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 296        [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 297        [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 298        [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 299        [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 300        [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 301        [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 302        [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 303        [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 304};
 305
 306#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 307static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 308#endif
 309static unsigned int default_baud = 9600;
 310static unsigned int user_uartclk = 0;
 311static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 312static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 313static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 314static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 315
 316#ifdef CONFIG_DEBUG_FS
 317
 318#define PCH_REGS_BUFSIZE        1024
 319
 320
 321static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 322                                size_t count, loff_t *ppos)
 323{
 324        struct eg20t_port *priv = file->private_data;
 325        char *buf;
 326        u32 len = 0;
 327        ssize_t ret;
 328        unsigned char lcr;
 329
 330        buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 331        if (!buf)
 332                return 0;
 333
 334        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 335                        "PCH EG20T port[%d] regs:\n", priv->port.line);
 336
 337        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 338                        "=================================\n");
 339        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                        "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 341        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 342                        "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 343        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 344                        "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 345        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 346                        "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 347        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 348                        "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 349        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 350                        "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 351        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 352                        "BRCSR: \t0x%02x\n",
 353                        ioread8(priv->membase + PCH_UART_BRCSR));
 354
 355        lcr = ioread8(priv->membase + UART_LCR);
 356        iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 357        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 358                        "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 359        len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 360                        "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 361        iowrite8(lcr, priv->membase + UART_LCR);
 362
 363        if (len > PCH_REGS_BUFSIZE)
 364                len = PCH_REGS_BUFSIZE;
 365
 366        ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 367        kfree(buf);
 368        return ret;
 369}
 370
 371static const struct file_operations port_regs_ops = {
 372        .owner          = THIS_MODULE,
 373        .open           = simple_open,
 374        .read           = port_show_regs,
 375        .llseek         = default_llseek,
 376};
 377#endif  /* CONFIG_DEBUG_FS */
 378
 379static struct dmi_system_id pch_uart_dmi_table[] = {
 380        {
 381                .ident = "CM-iTC",
 382                {
 383                        DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 384                },
 385                (void *)CMITC_UARTCLK,
 386        },
 387        {
 388                .ident = "FRI2",
 389                {
 390                        DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 391                },
 392                (void *)FRI2_64_UARTCLK,
 393        },
 394        {
 395                .ident = "Fish River Island II",
 396                {
 397                        DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 398                },
 399                (void *)FRI2_48_UARTCLK,
 400        },
 401        {
 402                .ident = "COMe-mTT",
 403                {
 404                        DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 405                },
 406                (void *)NTC1_UARTCLK,
 407        },
 408        {
 409                .ident = "nanoETXexpress-TT",
 410                {
 411                        DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 412                },
 413                (void *)NTC1_UARTCLK,
 414        },
 415        {
 416                .ident = "MinnowBoard",
 417                {
 418                        DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 419                },
 420                (void *)MINNOW_UARTCLK,
 421        },
 422        { }
 423};
 424
 425/* Return UART clock, checking for board specific clocks. */
 426static unsigned int pch_uart_get_uartclk(void)
 427{
 428        const struct dmi_system_id *d;
 429
 430        if (user_uartclk)
 431                return user_uartclk;
 432
 433        d = dmi_first_match(pch_uart_dmi_table);
 434        if (d)
 435                return (unsigned long)d->driver_data;
 436
 437        return DEFAULT_UARTCLK;
 438}
 439
 440static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 441                                          unsigned int flag)
 442{
 443        u8 ier = ioread8(priv->membase + UART_IER);
 444        ier |= flag & PCH_UART_IER_MASK;
 445        iowrite8(ier, priv->membase + UART_IER);
 446}
 447
 448static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 449                                           unsigned int flag)
 450{
 451        u8 ier = ioread8(priv->membase + UART_IER);
 452        ier &= ~(flag & PCH_UART_IER_MASK);
 453        iowrite8(ier, priv->membase + UART_IER);
 454}
 455
 456static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 457                                 unsigned int parity, unsigned int bits,
 458                                 unsigned int stb)
 459{
 460        unsigned int dll, dlm, lcr;
 461        int div;
 462
 463        div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 464        if (div < 0 || USHRT_MAX <= div) {
 465                dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 466                return -EINVAL;
 467        }
 468
 469        dll = (unsigned int)div & 0x00FFU;
 470        dlm = ((unsigned int)div >> 8) & 0x00FFU;
 471
 472        if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 473                dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 474                return -EINVAL;
 475        }
 476
 477        if (bits & ~PCH_UART_LCR_WLS) {
 478                dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 479                return -EINVAL;
 480        }
 481
 482        if (stb & ~PCH_UART_LCR_STB) {
 483                dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 484                return -EINVAL;
 485        }
 486
 487        lcr = parity;
 488        lcr |= bits;
 489        lcr |= stb;
 490
 491        dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 492                 __func__, baud, div, lcr, jiffies);
 493        iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 494        iowrite8(dll, priv->membase + PCH_UART_DLL);
 495        iowrite8(dlm, priv->membase + PCH_UART_DLM);
 496        iowrite8(lcr, priv->membase + UART_LCR);
 497
 498        return 0;
 499}
 500
 501static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 502                                    unsigned int flag)
 503{
 504        if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 505                dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 506                        __func__, flag);
 507                return -EINVAL;
 508        }
 509
 510        iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 511        iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 512                 priv->membase + UART_FCR);
 513        iowrite8(priv->fcr, priv->membase + UART_FCR);
 514
 515        return 0;
 516}
 517
 518static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 519                                 unsigned int dmamode,
 520                                 unsigned int fifo_size, unsigned int trigger)
 521{
 522        u8 fcr;
 523
 524        if (dmamode & ~PCH_UART_FCR_DMS) {
 525                dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 526                        __func__, dmamode);
 527                return -EINVAL;
 528        }
 529
 530        if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 531                dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 532                        __func__, fifo_size);
 533                return -EINVAL;
 534        }
 535
 536        if (trigger & ~PCH_UART_FCR_RFTL) {
 537                dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 538                        __func__, trigger);
 539                return -EINVAL;
 540        }
 541
 542        switch (priv->fifo_size) {
 543        case 256:
 544                priv->trigger_level =
 545                    trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 546                break;
 547        case 64:
 548                priv->trigger_level =
 549                    trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 550                break;
 551        case 16:
 552                priv->trigger_level =
 553                    trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 554                break;
 555        default:
 556                priv->trigger_level =
 557                    trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 558                break;
 559        }
 560        fcr =
 561            dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 562        iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 563        iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 564                 priv->membase + UART_FCR);
 565        iowrite8(fcr, priv->membase + UART_FCR);
 566        priv->fcr = fcr;
 567
 568        return 0;
 569}
 570
 571static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 572{
 573        unsigned int msr = ioread8(priv->membase + UART_MSR);
 574        priv->dmsr = msr & PCH_UART_MSR_DELTA;
 575        return (u8)msr;
 576}
 577
 578static void pch_uart_hal_write(struct eg20t_port *priv,
 579                              const unsigned char *buf, int tx_size)
 580{
 581        int i;
 582        unsigned int thr;
 583
 584        for (i = 0; i < tx_size;) {
 585                thr = buf[i++];
 586                iowrite8(thr, priv->membase + PCH_UART_THR);
 587        }
 588}
 589
 590static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 591                             int rx_size)
 592{
 593        int i;
 594        u8 rbr, lsr;
 595        struct uart_port *port = &priv->port;
 596
 597        lsr = ioread8(priv->membase + UART_LSR);
 598        for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 599             i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 600             lsr = ioread8(priv->membase + UART_LSR)) {
 601                rbr = ioread8(priv->membase + PCH_UART_RBR);
 602
 603                if (lsr & UART_LSR_BI) {
 604                        port->icount.brk++;
 605                        if (uart_handle_break(port))
 606                                continue;
 607                }
 608#ifdef SUPPORT_SYSRQ
 609                if (port->sysrq) {
 610                        if (uart_handle_sysrq_char(port, rbr))
 611                                continue;
 612                }
 613#endif
 614
 615                buf[i++] = rbr;
 616        }
 617        return i;
 618}
 619
 620static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 621{
 622        return ioread8(priv->membase + UART_IIR) &\
 623                      (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 624}
 625
 626static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 627{
 628        return ioread8(priv->membase + UART_LSR);
 629}
 630
 631static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 632{
 633        unsigned int lcr;
 634
 635        lcr = ioread8(priv->membase + UART_LCR);
 636        if (on)
 637                lcr |= PCH_UART_LCR_SB;
 638        else
 639                lcr &= ~PCH_UART_LCR_SB;
 640
 641        iowrite8(lcr, priv->membase + UART_LCR);
 642}
 643
 644static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 645                   int size)
 646{
 647        struct uart_port *port = &priv->port;
 648        struct tty_port *tport = &port->state->port;
 649
 650        tty_insert_flip_string(tport, buf, size);
 651        tty_flip_buffer_push(tport);
 652
 653        return 0;
 654}
 655
 656static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 657{
 658        int ret = 0;
 659        struct uart_port *port = &priv->port;
 660
 661        if (port->x_char) {
 662                dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 663                        __func__, port->x_char, jiffies);
 664                buf[0] = port->x_char;
 665                port->x_char = 0;
 666                ret = 1;
 667        }
 668
 669        return ret;
 670}
 671
 672static int dma_push_rx(struct eg20t_port *priv, int size)
 673{
 674        int room;
 675        struct uart_port *port = &priv->port;
 676        struct tty_port *tport = &port->state->port;
 677
 678        room = tty_buffer_request_room(tport, size);
 679
 680        if (room < size)
 681                dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 682                         size - room);
 683        if (!room)
 684                return 0;
 685
 686        tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 687
 688        port->icount.rx += room;
 689
 690        return room;
 691}
 692
 693static void pch_free_dma(struct uart_port *port)
 694{
 695        struct eg20t_port *priv;
 696        priv = container_of(port, struct eg20t_port, port);
 697
 698        if (priv->chan_tx) {
 699                dma_release_channel(priv->chan_tx);
 700                priv->chan_tx = NULL;
 701        }
 702        if (priv->chan_rx) {
 703                dma_release_channel(priv->chan_rx);
 704                priv->chan_rx = NULL;
 705        }
 706
 707        if (priv->rx_buf_dma) {
 708                dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 709                                  priv->rx_buf_dma);
 710                priv->rx_buf_virt = NULL;
 711                priv->rx_buf_dma = 0;
 712        }
 713
 714        return;
 715}
 716
 717static bool filter(struct dma_chan *chan, void *slave)
 718{
 719        struct pch_dma_slave *param = slave;
 720
 721        if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 722                                                  chan->device->dev)) {
 723                chan->private = param;
 724                return true;
 725        } else {
 726                return false;
 727        }
 728}
 729
 730static void pch_request_dma(struct uart_port *port)
 731{
 732        dma_cap_mask_t mask;
 733        struct dma_chan *chan;
 734        struct pci_dev *dma_dev;
 735        struct pch_dma_slave *param;
 736        struct eg20t_port *priv =
 737                                container_of(port, struct eg20t_port, port);
 738        dma_cap_zero(mask);
 739        dma_cap_set(DMA_SLAVE, mask);
 740
 741        /* Get DMA's dev information */
 742        dma_dev = pci_get_slot(priv->pdev->bus,
 743                        PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 744
 745        /* Set Tx DMA */
 746        param = &priv->param_tx;
 747        param->dma_dev = &dma_dev->dev;
 748        param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 749
 750        param->tx_reg = port->mapbase + UART_TX;
 751        chan = dma_request_channel(mask, filter, param);
 752        if (!chan) {
 753                dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 754                        __func__);
 755                return;
 756        }
 757        priv->chan_tx = chan;
 758
 759        /* Set Rx DMA */
 760        param = &priv->param_rx;
 761        param->dma_dev = &dma_dev->dev;
 762        param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 763
 764        param->rx_reg = port->mapbase + UART_RX;
 765        chan = dma_request_channel(mask, filter, param);
 766        if (!chan) {
 767                dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 768                        __func__);
 769                dma_release_channel(priv->chan_tx);
 770                priv->chan_tx = NULL;
 771                return;
 772        }
 773
 774        /* Get Consistent memory for DMA */
 775        priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 776                                    &priv->rx_buf_dma, GFP_KERNEL);
 777        priv->chan_rx = chan;
 778}
 779
 780static void pch_dma_rx_complete(void *arg)
 781{
 782        struct eg20t_port *priv = arg;
 783        struct uart_port *port = &priv->port;
 784        int count;
 785
 786        dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 787        count = dma_push_rx(priv, priv->trigger_level);
 788        if (count)
 789                tty_flip_buffer_push(&port->state->port);
 790        async_tx_ack(priv->desc_rx);
 791        pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 792                                            PCH_UART_HAL_RX_ERR_INT);
 793}
 794
 795static void pch_dma_tx_complete(void *arg)
 796{
 797        struct eg20t_port *priv = arg;
 798        struct uart_port *port = &priv->port;
 799        struct circ_buf *xmit = &port->state->xmit;
 800        struct scatterlist *sg = priv->sg_tx_p;
 801        int i;
 802
 803        for (i = 0; i < priv->nent; i++, sg++) {
 804                xmit->tail += sg_dma_len(sg);
 805                port->icount.tx += sg_dma_len(sg);
 806        }
 807        xmit->tail &= UART_XMIT_SIZE - 1;
 808        async_tx_ack(priv->desc_tx);
 809        dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
 810        priv->tx_dma_use = 0;
 811        priv->nent = 0;
 812        kfree(priv->sg_tx_p);
 813        pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 814}
 815
 816static int pop_tx(struct eg20t_port *priv, int size)
 817{
 818        int count = 0;
 819        struct uart_port *port = &priv->port;
 820        struct circ_buf *xmit = &port->state->xmit;
 821
 822        if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 823                goto pop_tx_end;
 824
 825        do {
 826                int cnt_to_end =
 827                    CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 828                int sz = min(size - count, cnt_to_end);
 829                pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 830                xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 831                count += sz;
 832        } while (!uart_circ_empty(xmit) && count < size);
 833
 834pop_tx_end:
 835        dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 836                 count, size - count, jiffies);
 837
 838        return count;
 839}
 840
 841static int handle_rx_to(struct eg20t_port *priv)
 842{
 843        struct pch_uart_buffer *buf;
 844        int rx_size;
 845        int ret;
 846        if (!priv->start_rx) {
 847                pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 848                                                     PCH_UART_HAL_RX_ERR_INT);
 849                return 0;
 850        }
 851        buf = &priv->rxbuf;
 852        do {
 853                rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 854                ret = push_rx(priv, buf->buf, rx_size);
 855                if (ret)
 856                        return 0;
 857        } while (rx_size == buf->size);
 858
 859        return PCH_UART_HANDLED_RX_INT;
 860}
 861
 862static int handle_rx(struct eg20t_port *priv)
 863{
 864        return handle_rx_to(priv);
 865}
 866
 867static int dma_handle_rx(struct eg20t_port *priv)
 868{
 869        struct uart_port *port = &priv->port;
 870        struct dma_async_tx_descriptor *desc;
 871        struct scatterlist *sg;
 872
 873        priv = container_of(port, struct eg20t_port, port);
 874        sg = &priv->sg_rx;
 875
 876        sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 877
 878        sg_dma_len(sg) = priv->trigger_level;
 879
 880        sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 881                     sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 882                     ~PAGE_MASK);
 883
 884        sg_dma_address(sg) = priv->rx_buf_dma;
 885
 886        desc = dmaengine_prep_slave_sg(priv->chan_rx,
 887                        sg, 1, DMA_DEV_TO_MEM,
 888                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 889
 890        if (!desc)
 891                return 0;
 892
 893        priv->desc_rx = desc;
 894        desc->callback = pch_dma_rx_complete;
 895        desc->callback_param = priv;
 896        desc->tx_submit(desc);
 897        dma_async_issue_pending(priv->chan_rx);
 898
 899        return PCH_UART_HANDLED_RX_INT;
 900}
 901
 902static unsigned int handle_tx(struct eg20t_port *priv)
 903{
 904        struct uart_port *port = &priv->port;
 905        struct circ_buf *xmit = &port->state->xmit;
 906        int fifo_size;
 907        int tx_size;
 908        int size;
 909        int tx_empty;
 910
 911        if (!priv->start_tx) {
 912                dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 913                        __func__, jiffies);
 914                pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 915                priv->tx_empty = 1;
 916                return 0;
 917        }
 918
 919        fifo_size = max(priv->fifo_size, 1);
 920        tx_empty = 1;
 921        if (pop_tx_x(priv, xmit->buf)) {
 922                pch_uart_hal_write(priv, xmit->buf, 1);
 923                port->icount.tx++;
 924                tx_empty = 0;
 925                fifo_size--;
 926        }
 927        size = min(xmit->head - xmit->tail, fifo_size);
 928        if (size < 0)
 929                size = fifo_size;
 930
 931        tx_size = pop_tx(priv, size);
 932        if (tx_size > 0) {
 933                port->icount.tx += tx_size;
 934                tx_empty = 0;
 935        }
 936
 937        priv->tx_empty = tx_empty;
 938
 939        if (tx_empty) {
 940                pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 941                uart_write_wakeup(port);
 942        }
 943
 944        return PCH_UART_HANDLED_TX_INT;
 945}
 946
 947static unsigned int dma_handle_tx(struct eg20t_port *priv)
 948{
 949        struct uart_port *port = &priv->port;
 950        struct circ_buf *xmit = &port->state->xmit;
 951        struct scatterlist *sg;
 952        int nent;
 953        int fifo_size;
 954        int tx_empty;
 955        struct dma_async_tx_descriptor *desc;
 956        int num;
 957        int i;
 958        int bytes;
 959        int size;
 960        int rem;
 961
 962        if (!priv->start_tx) {
 963                dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 964                        __func__, jiffies);
 965                pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 966                priv->tx_empty = 1;
 967                return 0;
 968        }
 969
 970        if (priv->tx_dma_use) {
 971                dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 972                        __func__, jiffies);
 973                pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 974                priv->tx_empty = 1;
 975                return 0;
 976        }
 977
 978        fifo_size = max(priv->fifo_size, 1);
 979        tx_empty = 1;
 980        if (pop_tx_x(priv, xmit->buf)) {
 981                pch_uart_hal_write(priv, xmit->buf, 1);
 982                port->icount.tx++;
 983                tx_empty = 0;
 984                fifo_size--;
 985        }
 986
 987        bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 988                             UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 989                             xmit->tail, UART_XMIT_SIZE));
 990        if (!bytes) {
 991                dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 992                pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 993                uart_write_wakeup(port);
 994                return 0;
 995        }
 996
 997        if (bytes > fifo_size) {
 998                num = bytes / fifo_size + 1;
 999                size = fifo_size;
1000                rem = bytes % fifo_size;
1001        } else {
1002                num = 1;
1003                size = bytes;
1004                rem = bytes;
1005        }
1006
1007        dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1008                __func__, num, size, rem);
1009
1010        priv->tx_dma_use = 1;
1011
1012        priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1013        if (!priv->sg_tx_p) {
1014                dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1015                return 0;
1016        }
1017
1018        sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1019        sg = priv->sg_tx_p;
1020
1021        for (i = 0; i < num; i++, sg++) {
1022                if (i == (num - 1))
1023                        sg_set_page(sg, virt_to_page(xmit->buf),
1024                                    rem, fifo_size * i);
1025                else
1026                        sg_set_page(sg, virt_to_page(xmit->buf),
1027                                    size, fifo_size * i);
1028        }
1029
1030        sg = priv->sg_tx_p;
1031        nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1032        if (!nent) {
1033                dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1034                return 0;
1035        }
1036        priv->nent = nent;
1037
1038        for (i = 0; i < nent; i++, sg++) {
1039                sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1040                              fifo_size * i;
1041                sg_dma_address(sg) = (sg_dma_address(sg) &
1042                                    ~(UART_XMIT_SIZE - 1)) + sg->offset;
1043                if (i == (nent - 1))
1044                        sg_dma_len(sg) = rem;
1045                else
1046                        sg_dma_len(sg) = size;
1047        }
1048
1049        desc = dmaengine_prep_slave_sg(priv->chan_tx,
1050                                        priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1051                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1052        if (!desc) {
1053                dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1054                        __func__);
1055                return 0;
1056        }
1057        dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1058        priv->desc_tx = desc;
1059        desc->callback = pch_dma_tx_complete;
1060        desc->callback_param = priv;
1061
1062        desc->tx_submit(desc);
1063
1064        dma_async_issue_pending(priv->chan_tx);
1065
1066        return PCH_UART_HANDLED_TX_INT;
1067}
1068
1069static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1070{
1071        struct uart_port *port = &priv->port;
1072        struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1073        char   *error_msg[5] = {};
1074        int    i = 0;
1075
1076        if (lsr & PCH_UART_LSR_ERR)
1077                error_msg[i++] = "Error data in FIFO\n";
1078
1079        if (lsr & UART_LSR_FE) {
1080                port->icount.frame++;
1081                error_msg[i++] = "  Framing Error\n";
1082        }
1083
1084        if (lsr & UART_LSR_PE) {
1085                port->icount.parity++;
1086                error_msg[i++] = "  Parity Error\n";
1087        }
1088
1089        if (lsr & UART_LSR_OE) {
1090                port->icount.overrun++;
1091                error_msg[i++] = "  Overrun Error\n";
1092        }
1093
1094        if (tty == NULL) {
1095                for (i = 0; error_msg[i] != NULL; i++)
1096                        dev_err(&priv->pdev->dev, error_msg[i]);
1097        } else {
1098                tty_kref_put(tty);
1099        }
1100}
1101
1102static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1103{
1104        struct eg20t_port *priv = dev_id;
1105        unsigned int handled;
1106        u8 lsr;
1107        int ret = 0;
1108        unsigned char iid;
1109        unsigned long flags;
1110        int next = 1;
1111        u8 msr;
1112
1113        spin_lock_irqsave(&priv->lock, flags);
1114        handled = 0;
1115        while (next) {
1116                iid = pch_uart_hal_get_iid(priv);
1117                if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1118                        break;
1119                switch (iid) {
1120                case PCH_UART_IID_RLS:  /* Receiver Line Status */
1121                        lsr = pch_uart_hal_get_line_status(priv);
1122                        if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1123                                                UART_LSR_PE | UART_LSR_OE)) {
1124                                pch_uart_err_ir(priv, lsr);
1125                                ret = PCH_UART_HANDLED_RX_ERR_INT;
1126                        } else {
1127                                ret = PCH_UART_HANDLED_LS_INT;
1128                        }
1129                        break;
1130                case PCH_UART_IID_RDR:  /* Received Data Ready */
1131                        if (priv->use_dma) {
1132                                pch_uart_hal_disable_interrupt(priv,
1133                                                PCH_UART_HAL_RX_INT |
1134                                                PCH_UART_HAL_RX_ERR_INT);
1135                                ret = dma_handle_rx(priv);
1136                                if (!ret)
1137                                        pch_uart_hal_enable_interrupt(priv,
1138                                                PCH_UART_HAL_RX_INT |
1139                                                PCH_UART_HAL_RX_ERR_INT);
1140                        } else {
1141                                ret = handle_rx(priv);
1142                        }
1143                        break;
1144                case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1145                                                   (FIFO Timeout) */
1146                        ret = handle_rx_to(priv);
1147                        break;
1148                case PCH_UART_IID_THRE: /* Transmitter Holding Register
1149                                                   Empty */
1150                        if (priv->use_dma)
1151                                ret = dma_handle_tx(priv);
1152                        else
1153                                ret = handle_tx(priv);
1154                        break;
1155                case PCH_UART_IID_MS:   /* Modem Status */
1156                        msr = pch_uart_hal_get_modem(priv);
1157                        next = 0; /* MS ir prioirty is the lowest. So, MS ir
1158                                     means final interrupt */
1159                        if ((msr & UART_MSR_ANY_DELTA) == 0)
1160                                break;
1161                        ret |= PCH_UART_HANDLED_MS_INT;
1162                        break;
1163                default:        /* Never junp to this label */
1164                        dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1165                                iid, jiffies);
1166                        ret = -1;
1167                        next = 0;
1168                        break;
1169                }
1170                handled |= (unsigned int)ret;
1171        }
1172
1173        spin_unlock_irqrestore(&priv->lock, flags);
1174        return IRQ_RETVAL(handled);
1175}
1176
1177/* This function tests whether the transmitter fifo and shifter for the port
1178                                                described by 'port' is empty. */
1179static unsigned int pch_uart_tx_empty(struct uart_port *port)
1180{
1181        struct eg20t_port *priv;
1182
1183        priv = container_of(port, struct eg20t_port, port);
1184        if (priv->tx_empty)
1185                return TIOCSER_TEMT;
1186        else
1187                return 0;
1188}
1189
1190/* Returns the current state of modem control inputs. */
1191static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1192{
1193        struct eg20t_port *priv;
1194        u8 modem;
1195        unsigned int ret = 0;
1196
1197        priv = container_of(port, struct eg20t_port, port);
1198        modem = pch_uart_hal_get_modem(priv);
1199
1200        if (modem & UART_MSR_DCD)
1201                ret |= TIOCM_CAR;
1202
1203        if (modem & UART_MSR_RI)
1204                ret |= TIOCM_RNG;
1205
1206        if (modem & UART_MSR_DSR)
1207                ret |= TIOCM_DSR;
1208
1209        if (modem & UART_MSR_CTS)
1210                ret |= TIOCM_CTS;
1211
1212        return ret;
1213}
1214
1215static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1216{
1217        u32 mcr = 0;
1218        struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1219
1220        if (mctrl & TIOCM_DTR)
1221                mcr |= UART_MCR_DTR;
1222        if (mctrl & TIOCM_RTS)
1223                mcr |= UART_MCR_RTS;
1224        if (mctrl & TIOCM_LOOP)
1225                mcr |= UART_MCR_LOOP;
1226
1227        if (priv->mcr & UART_MCR_AFE)
1228                mcr |= UART_MCR_AFE;
1229
1230        if (mctrl)
1231                iowrite8(mcr, priv->membase + UART_MCR);
1232}
1233
1234static void pch_uart_stop_tx(struct uart_port *port)
1235{
1236        struct eg20t_port *priv;
1237        priv = container_of(port, struct eg20t_port, port);
1238        priv->start_tx = 0;
1239        priv->tx_dma_use = 0;
1240}
1241
1242static void pch_uart_start_tx(struct uart_port *port)
1243{
1244        struct eg20t_port *priv;
1245
1246        priv = container_of(port, struct eg20t_port, port);
1247
1248        if (priv->use_dma) {
1249                if (priv->tx_dma_use) {
1250                        dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1251                                __func__);
1252                        return;
1253                }
1254        }
1255
1256        priv->start_tx = 1;
1257        pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1258}
1259
1260static void pch_uart_stop_rx(struct uart_port *port)
1261{
1262        struct eg20t_port *priv;
1263        priv = container_of(port, struct eg20t_port, port);
1264        priv->start_rx = 0;
1265        pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1266                                             PCH_UART_HAL_RX_ERR_INT);
1267}
1268
1269/* Enable the modem status interrupts. */
1270static void pch_uart_enable_ms(struct uart_port *port)
1271{
1272        struct eg20t_port *priv;
1273        priv = container_of(port, struct eg20t_port, port);
1274        pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1275}
1276
1277/* Control the transmission of a break signal. */
1278static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1279{
1280        struct eg20t_port *priv;
1281        unsigned long flags;
1282
1283        priv = container_of(port, struct eg20t_port, port);
1284        spin_lock_irqsave(&priv->lock, flags);
1285        pch_uart_hal_set_break(priv, ctl);
1286        spin_unlock_irqrestore(&priv->lock, flags);
1287}
1288
1289/* Grab any interrupt resources and initialise any low level driver state. */
1290static int pch_uart_startup(struct uart_port *port)
1291{
1292        struct eg20t_port *priv;
1293        int ret;
1294        int fifo_size;
1295        int trigger_level;
1296
1297        priv = container_of(port, struct eg20t_port, port);
1298        priv->tx_empty = 1;
1299
1300        if (port->uartclk)
1301                priv->uartclk = port->uartclk;
1302        else
1303                port->uartclk = priv->uartclk;
1304
1305        pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1306        ret = pch_uart_hal_set_line(priv, default_baud,
1307                              PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1308                              PCH_UART_HAL_STB1);
1309        if (ret)
1310                return ret;
1311
1312        switch (priv->fifo_size) {
1313        case 256:
1314                fifo_size = PCH_UART_HAL_FIFO256;
1315                break;
1316        case 64:
1317                fifo_size = PCH_UART_HAL_FIFO64;
1318                break;
1319        case 16:
1320                fifo_size = PCH_UART_HAL_FIFO16;
1321                break;
1322        case 1:
1323        default:
1324                fifo_size = PCH_UART_HAL_FIFO_DIS;
1325                break;
1326        }
1327
1328        switch (priv->trigger) {
1329        case PCH_UART_HAL_TRIGGER1:
1330                trigger_level = 1;
1331                break;
1332        case PCH_UART_HAL_TRIGGER_L:
1333                trigger_level = priv->fifo_size / 4;
1334                break;
1335        case PCH_UART_HAL_TRIGGER_M:
1336                trigger_level = priv->fifo_size / 2;
1337                break;
1338        case PCH_UART_HAL_TRIGGER_H:
1339        default:
1340                trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1341                break;
1342        }
1343
1344        priv->trigger_level = trigger_level;
1345        ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1346                                    fifo_size, priv->trigger);
1347        if (ret < 0)
1348                return ret;
1349
1350        ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1351                        priv->irq_name, priv);
1352        if (ret < 0)
1353                return ret;
1354
1355        if (priv->use_dma)
1356                pch_request_dma(port);
1357
1358        priv->start_rx = 1;
1359        pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1360                                            PCH_UART_HAL_RX_ERR_INT);
1361        uart_update_timeout(port, CS8, default_baud);
1362
1363        return 0;
1364}
1365
1366static void pch_uart_shutdown(struct uart_port *port)
1367{
1368        struct eg20t_port *priv;
1369        int ret;
1370
1371        priv = container_of(port, struct eg20t_port, port);
1372        pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1373        pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1374        ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1375                              PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1376        if (ret)
1377                dev_err(priv->port.dev,
1378                        "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1379
1380        pch_free_dma(port);
1381
1382        free_irq(priv->port.irq, priv);
1383}
1384
1385/* Change the port parameters, including word length, parity, stop
1386 *bits.  Update read_status_mask and ignore_status_mask to indicate
1387 *the types of events we are interested in receiving.  */
1388static void pch_uart_set_termios(struct uart_port *port,
1389                                 struct ktermios *termios, struct ktermios *old)
1390{
1391        int rtn;
1392        unsigned int baud, parity, bits, stb;
1393        struct eg20t_port *priv;
1394        unsigned long flags;
1395
1396        priv = container_of(port, struct eg20t_port, port);
1397        switch (termios->c_cflag & CSIZE) {
1398        case CS5:
1399                bits = PCH_UART_HAL_5BIT;
1400                break;
1401        case CS6:
1402                bits = PCH_UART_HAL_6BIT;
1403                break;
1404        case CS7:
1405                bits = PCH_UART_HAL_7BIT;
1406                break;
1407        default:                /* CS8 */
1408                bits = PCH_UART_HAL_8BIT;
1409                break;
1410        }
1411        if (termios->c_cflag & CSTOPB)
1412                stb = PCH_UART_HAL_STB2;
1413        else
1414                stb = PCH_UART_HAL_STB1;
1415
1416        if (termios->c_cflag & PARENB) {
1417                if (termios->c_cflag & PARODD)
1418                        parity = PCH_UART_HAL_PARITY_ODD;
1419                else
1420                        parity = PCH_UART_HAL_PARITY_EVEN;
1421
1422        } else
1423                parity = PCH_UART_HAL_PARITY_NONE;
1424
1425        /* Only UART0 has auto hardware flow function */
1426        if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1427                priv->mcr |= UART_MCR_AFE;
1428        else
1429                priv->mcr &= ~UART_MCR_AFE;
1430
1431        termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1432
1433        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1434
1435        spin_lock_irqsave(&priv->lock, flags);
1436        spin_lock(&port->lock);
1437
1438        uart_update_timeout(port, termios->c_cflag, baud);
1439        rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1440        if (rtn)
1441                goto out;
1442
1443        pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1444        /* Don't rewrite B0 */
1445        if (tty_termios_baud_rate(termios))
1446                tty_termios_encode_baud_rate(termios, baud, baud);
1447
1448out:
1449        spin_unlock(&port->lock);
1450        spin_unlock_irqrestore(&priv->lock, flags);
1451}
1452
1453static const char *pch_uart_type(struct uart_port *port)
1454{
1455        return KBUILD_MODNAME;
1456}
1457
1458static void pch_uart_release_port(struct uart_port *port)
1459{
1460        struct eg20t_port *priv;
1461
1462        priv = container_of(port, struct eg20t_port, port);
1463        pci_iounmap(priv->pdev, priv->membase);
1464        pci_release_regions(priv->pdev);
1465}
1466
1467static int pch_uart_request_port(struct uart_port *port)
1468{
1469        struct eg20t_port *priv;
1470        int ret;
1471        void __iomem *membase;
1472
1473        priv = container_of(port, struct eg20t_port, port);
1474        ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1475        if (ret < 0)
1476                return -EBUSY;
1477
1478        membase = pci_iomap(priv->pdev, 1, 0);
1479        if (!membase) {
1480                pci_release_regions(priv->pdev);
1481                return -EBUSY;
1482        }
1483        priv->membase = port->membase = membase;
1484
1485        return 0;
1486}
1487
1488static void pch_uart_config_port(struct uart_port *port, int type)
1489{
1490        struct eg20t_port *priv;
1491
1492        priv = container_of(port, struct eg20t_port, port);
1493        if (type & UART_CONFIG_TYPE) {
1494                port->type = priv->port_type;
1495                pch_uart_request_port(port);
1496        }
1497}
1498
1499static int pch_uart_verify_port(struct uart_port *port,
1500                                struct serial_struct *serinfo)
1501{
1502        struct eg20t_port *priv;
1503
1504        priv = container_of(port, struct eg20t_port, port);
1505        if (serinfo->flags & UPF_LOW_LATENCY) {
1506                dev_info(priv->port.dev,
1507                        "PCH UART : Use PIO Mode (without DMA)\n");
1508                priv->use_dma = 0;
1509                serinfo->flags &= ~UPF_LOW_LATENCY;
1510        } else {
1511#ifndef CONFIG_PCH_DMA
1512                dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1513                        __func__);
1514                return -EOPNOTSUPP;
1515#endif
1516                if (!priv->use_dma) {
1517                        pch_request_dma(port);
1518                        if (priv->chan_rx)
1519                                priv->use_dma = 1;
1520                }
1521                dev_info(priv->port.dev, "PCH UART: %s\n",
1522                                priv->use_dma ?
1523                                "Use DMA Mode" : "No DMA");
1524        }
1525
1526        return 0;
1527}
1528
1529#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1530/*
1531 *      Wait for transmitter & holding register to empty
1532 */
1533static void wait_for_xmitr(struct eg20t_port *up, int bits)
1534{
1535        unsigned int status, tmout = 10000;
1536
1537        /* Wait up to 10ms for the character(s) to be sent. */
1538        for (;;) {
1539                status = ioread8(up->membase + UART_LSR);
1540
1541                if ((status & bits) == bits)
1542                        break;
1543                if (--tmout == 0)
1544                        break;
1545                udelay(1);
1546        }
1547
1548        /* Wait up to 1s for flow control if necessary */
1549        if (up->port.flags & UPF_CONS_FLOW) {
1550                unsigned int tmout;
1551                for (tmout = 1000000; tmout; tmout--) {
1552                        unsigned int msr = ioread8(up->membase + UART_MSR);
1553                        if (msr & UART_MSR_CTS)
1554                                break;
1555                        udelay(1);
1556                        touch_nmi_watchdog();
1557                }
1558        }
1559}
1560#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1561
1562#ifdef CONFIG_CONSOLE_POLL
1563/*
1564 * Console polling routines for communicate via uart while
1565 * in an interrupt or debug context.
1566 */
1567static int pch_uart_get_poll_char(struct uart_port *port)
1568{
1569        struct eg20t_port *priv =
1570                container_of(port, struct eg20t_port, port);
1571        u8 lsr = ioread8(priv->membase + UART_LSR);
1572
1573        if (!(lsr & UART_LSR_DR))
1574                return NO_POLL_CHAR;
1575
1576        return ioread8(priv->membase + PCH_UART_RBR);
1577}
1578
1579
1580static void pch_uart_put_poll_char(struct uart_port *port,
1581                         unsigned char c)
1582{
1583        unsigned int ier;
1584        struct eg20t_port *priv =
1585                container_of(port, struct eg20t_port, port);
1586
1587        /*
1588         * First save the IER then disable the interrupts
1589         */
1590        ier = ioread8(priv->membase + UART_IER);
1591        pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1592
1593        wait_for_xmitr(priv, UART_LSR_THRE);
1594        /*
1595         * Send the character out.
1596         */
1597        iowrite8(c, priv->membase + PCH_UART_THR);
1598
1599        /*
1600         * Finally, wait for transmitter to become empty
1601         * and restore the IER
1602         */
1603        wait_for_xmitr(priv, BOTH_EMPTY);
1604        iowrite8(ier, priv->membase + UART_IER);
1605}
1606#endif /* CONFIG_CONSOLE_POLL */
1607
1608static const struct uart_ops pch_uart_ops = {
1609        .tx_empty = pch_uart_tx_empty,
1610        .set_mctrl = pch_uart_set_mctrl,
1611        .get_mctrl = pch_uart_get_mctrl,
1612        .stop_tx = pch_uart_stop_tx,
1613        .start_tx = pch_uart_start_tx,
1614        .stop_rx = pch_uart_stop_rx,
1615        .enable_ms = pch_uart_enable_ms,
1616        .break_ctl = pch_uart_break_ctl,
1617        .startup = pch_uart_startup,
1618        .shutdown = pch_uart_shutdown,
1619        .set_termios = pch_uart_set_termios,
1620/*      .pm             = pch_uart_pm,          Not supported yet */
1621        .type = pch_uart_type,
1622        .release_port = pch_uart_release_port,
1623        .request_port = pch_uart_request_port,
1624        .config_port = pch_uart_config_port,
1625        .verify_port = pch_uart_verify_port,
1626#ifdef CONFIG_CONSOLE_POLL
1627        .poll_get_char = pch_uart_get_poll_char,
1628        .poll_put_char = pch_uart_put_poll_char,
1629#endif
1630};
1631
1632#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1633
1634static void pch_console_putchar(struct uart_port *port, int ch)
1635{
1636        struct eg20t_port *priv =
1637                container_of(port, struct eg20t_port, port);
1638
1639        wait_for_xmitr(priv, UART_LSR_THRE);
1640        iowrite8(ch, priv->membase + PCH_UART_THR);
1641}
1642
1643/*
1644 *      Print a string to the serial port trying not to disturb
1645 *      any possible real use of the port...
1646 *
1647 *      The console_lock must be held when we get here.
1648 */
1649static void
1650pch_console_write(struct console *co, const char *s, unsigned int count)
1651{
1652        struct eg20t_port *priv;
1653        unsigned long flags;
1654        int priv_locked = 1;
1655        int port_locked = 1;
1656        u8 ier;
1657
1658        priv = pch_uart_ports[co->index];
1659
1660        touch_nmi_watchdog();
1661
1662        local_irq_save(flags);
1663        if (priv->port.sysrq) {
1664                /* call to uart_handle_sysrq_char already took the priv lock */
1665                priv_locked = 0;
1666                /* serial8250_handle_port() already took the port lock */
1667                port_locked = 0;
1668        } else if (oops_in_progress) {
1669                priv_locked = spin_trylock(&priv->lock);
1670                port_locked = spin_trylock(&priv->port.lock);
1671        } else {
1672                spin_lock(&priv->lock);
1673                spin_lock(&priv->port.lock);
1674        }
1675
1676        /*
1677         *      First save the IER then disable the interrupts
1678         */
1679        ier = ioread8(priv->membase + UART_IER);
1680
1681        pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1682
1683        uart_console_write(&priv->port, s, count, pch_console_putchar);
1684
1685        /*
1686         *      Finally, wait for transmitter to become empty
1687         *      and restore the IER
1688         */
1689        wait_for_xmitr(priv, BOTH_EMPTY);
1690        iowrite8(ier, priv->membase + UART_IER);
1691
1692        if (port_locked)
1693                spin_unlock(&priv->port.lock);
1694        if (priv_locked)
1695                spin_unlock(&priv->lock);
1696        local_irq_restore(flags);
1697}
1698
1699static int __init pch_console_setup(struct console *co, char *options)
1700{
1701        struct uart_port *port;
1702        int baud = default_baud;
1703        int bits = 8;
1704        int parity = 'n';
1705        int flow = 'n';
1706
1707        /*
1708         * Check whether an invalid uart number has been specified, and
1709         * if so, search for the first available port that does have
1710         * console support.
1711         */
1712        if (co->index >= PCH_UART_NR)
1713                co->index = 0;
1714        port = &pch_uart_ports[co->index]->port;
1715
1716        if (!port || (!port->iobase && !port->membase))
1717                return -ENODEV;
1718
1719        port->uartclk = pch_uart_get_uartclk();
1720
1721        if (options)
1722                uart_parse_options(options, &baud, &parity, &bits, &flow);
1723
1724        return uart_set_options(port, co, baud, parity, bits, flow);
1725}
1726
1727static struct uart_driver pch_uart_driver;
1728
1729static struct console pch_console = {
1730        .name           = PCH_UART_DRIVER_DEVICE,
1731        .write          = pch_console_write,
1732        .device         = uart_console_device,
1733        .setup          = pch_console_setup,
1734        .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1735        .index          = -1,
1736        .data           = &pch_uart_driver,
1737};
1738
1739#define PCH_CONSOLE     (&pch_console)
1740#else
1741#define PCH_CONSOLE     NULL
1742#endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1743
1744static struct uart_driver pch_uart_driver = {
1745        .owner = THIS_MODULE,
1746        .driver_name = KBUILD_MODNAME,
1747        .dev_name = PCH_UART_DRIVER_DEVICE,
1748        .major = 0,
1749        .minor = 0,
1750        .nr = PCH_UART_NR,
1751        .cons = PCH_CONSOLE,
1752};
1753
1754static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1755                                             const struct pci_device_id *id)
1756{
1757        struct eg20t_port *priv;
1758        int ret;
1759        unsigned int iobase;
1760        unsigned int mapbase;
1761        unsigned char *rxbuf;
1762        int fifosize;
1763        int port_type;
1764        struct pch_uart_driver_data *board;
1765#ifdef CONFIG_DEBUG_FS
1766        char name[32];  /* for debugfs file name */
1767#endif
1768
1769        board = &drv_dat[id->driver_data];
1770        port_type = board->port_type;
1771
1772        priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1773        if (priv == NULL)
1774                goto init_port_alloc_err;
1775
1776        rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1777        if (!rxbuf)
1778                goto init_port_free_txbuf;
1779
1780        switch (port_type) {
1781        case PORT_UNKNOWN:
1782                fifosize = 256; /* EG20T/ML7213: UART0 */
1783                break;
1784        case PORT_8250:
1785                fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1786                break;
1787        default:
1788                dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1789                goto init_port_hal_free;
1790        }
1791
1792        pci_enable_msi(pdev);
1793        pci_set_master(pdev);
1794
1795        spin_lock_init(&priv->lock);
1796
1797        iobase = pci_resource_start(pdev, 0);
1798        mapbase = pci_resource_start(pdev, 1);
1799        priv->mapbase = mapbase;
1800        priv->iobase = iobase;
1801        priv->pdev = pdev;
1802        priv->tx_empty = 1;
1803        priv->rxbuf.buf = rxbuf;
1804        priv->rxbuf.size = PAGE_SIZE;
1805
1806        priv->fifo_size = fifosize;
1807        priv->uartclk = pch_uart_get_uartclk();
1808        priv->port_type = PORT_MAX_8250 + port_type + 1;
1809        priv->port.dev = &pdev->dev;
1810        priv->port.iobase = iobase;
1811        priv->port.membase = NULL;
1812        priv->port.mapbase = mapbase;
1813        priv->port.irq = pdev->irq;
1814        priv->port.iotype = UPIO_PORT;
1815        priv->port.ops = &pch_uart_ops;
1816        priv->port.flags = UPF_BOOT_AUTOCONF;
1817        priv->port.fifosize = fifosize;
1818        priv->port.line = board->line_no;
1819        priv->trigger = PCH_UART_HAL_TRIGGER_M;
1820
1821        snprintf(priv->irq_name, IRQ_NAME_SIZE,
1822                 KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1823                 priv->port.line);
1824
1825        spin_lock_init(&priv->port.lock);
1826
1827        pci_set_drvdata(pdev, priv);
1828        priv->trigger_level = 1;
1829        priv->fcr = 0;
1830
1831        if (pdev->dev.of_node)
1832                of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1833                                         , &user_uartclk);
1834
1835#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1836        pch_uart_ports[board->line_no] = priv;
1837#endif
1838        ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1839        if (ret < 0)
1840                goto init_port_hal_free;
1841
1842#ifdef CONFIG_DEBUG_FS
1843        snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1844        priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1845                                NULL, priv, &port_regs_ops);
1846#endif
1847
1848        return priv;
1849
1850init_port_hal_free:
1851#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1852        pch_uart_ports[board->line_no] = NULL;
1853#endif
1854        free_page((unsigned long)rxbuf);
1855init_port_free_txbuf:
1856        kfree(priv);
1857init_port_alloc_err:
1858
1859        return NULL;
1860}
1861
1862static void pch_uart_exit_port(struct eg20t_port *priv)
1863{
1864
1865#ifdef CONFIG_DEBUG_FS
1866        if (priv->debugfs)
1867                debugfs_remove(priv->debugfs);
1868#endif
1869        uart_remove_one_port(&pch_uart_driver, &priv->port);
1870        free_page((unsigned long)priv->rxbuf.buf);
1871}
1872
1873static void pch_uart_pci_remove(struct pci_dev *pdev)
1874{
1875        struct eg20t_port *priv = pci_get_drvdata(pdev);
1876
1877        pci_disable_msi(pdev);
1878
1879#ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1880        pch_uart_ports[priv->port.line] = NULL;
1881#endif
1882        pch_uart_exit_port(priv);
1883        pci_disable_device(pdev);
1884        kfree(priv);
1885        return;
1886}
1887#ifdef CONFIG_PM
1888static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1889{
1890        struct eg20t_port *priv = pci_get_drvdata(pdev);
1891
1892        uart_suspend_port(&pch_uart_driver, &priv->port);
1893
1894        pci_save_state(pdev);
1895        pci_set_power_state(pdev, pci_choose_state(pdev, state));
1896        return 0;
1897}
1898
1899static int pch_uart_pci_resume(struct pci_dev *pdev)
1900{
1901        struct eg20t_port *priv = pci_get_drvdata(pdev);
1902        int ret;
1903
1904        pci_set_power_state(pdev, PCI_D0);
1905        pci_restore_state(pdev);
1906
1907        ret = pci_enable_device(pdev);
1908        if (ret) {
1909                dev_err(&pdev->dev,
1910                "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1911                return ret;
1912        }
1913
1914        uart_resume_port(&pch_uart_driver, &priv->port);
1915
1916        return 0;
1917}
1918#else
1919#define pch_uart_pci_suspend NULL
1920#define pch_uart_pci_resume NULL
1921#endif
1922
1923static const struct pci_device_id pch_uart_pci_id[] = {
1924        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1925         .driver_data = pch_et20t_uart0},
1926        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1927         .driver_data = pch_et20t_uart1},
1928        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1929         .driver_data = pch_et20t_uart2},
1930        {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1931         .driver_data = pch_et20t_uart3},
1932        {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1933         .driver_data = pch_ml7213_uart0},
1934        {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1935         .driver_data = pch_ml7213_uart1},
1936        {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1937         .driver_data = pch_ml7213_uart2},
1938        {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1939         .driver_data = pch_ml7223_uart0},
1940        {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1941         .driver_data = pch_ml7223_uart1},
1942        {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1943         .driver_data = pch_ml7831_uart0},
1944        {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1945         .driver_data = pch_ml7831_uart1},
1946        {0,},
1947};
1948
1949static int pch_uart_pci_probe(struct pci_dev *pdev,
1950                                        const struct pci_device_id *id)
1951{
1952        int ret;
1953        struct eg20t_port *priv;
1954
1955        ret = pci_enable_device(pdev);
1956        if (ret < 0)
1957                goto probe_error;
1958
1959        priv = pch_uart_init_port(pdev, id);
1960        if (!priv) {
1961                ret = -EBUSY;
1962                goto probe_disable_device;
1963        }
1964        pci_set_drvdata(pdev, priv);
1965
1966        return ret;
1967
1968probe_disable_device:
1969        pci_disable_msi(pdev);
1970        pci_disable_device(pdev);
1971probe_error:
1972        return ret;
1973}
1974
1975static struct pci_driver pch_uart_pci_driver = {
1976        .name = "pch_uart",
1977        .id_table = pch_uart_pci_id,
1978        .probe = pch_uart_pci_probe,
1979        .remove = pch_uart_pci_remove,
1980        .suspend = pch_uart_pci_suspend,
1981        .resume = pch_uart_pci_resume,
1982};
1983
1984static int __init pch_uart_module_init(void)
1985{
1986        int ret;
1987
1988        /* register as UART driver */
1989        ret = uart_register_driver(&pch_uart_driver);
1990        if (ret < 0)
1991                return ret;
1992
1993        /* register as PCI driver */
1994        ret = pci_register_driver(&pch_uart_pci_driver);
1995        if (ret < 0)
1996                uart_unregister_driver(&pch_uart_driver);
1997
1998        return ret;
1999}
2000module_init(pch_uart_module_init);
2001
2002static void __exit pch_uart_module_exit(void)
2003{
2004        pci_unregister_driver(&pch_uart_pci_driver);
2005        uart_unregister_driver(&pch_uart_driver);
2006}
2007module_exit(pch_uart_module_exit);
2008
2009MODULE_LICENSE("GPL v2");
2010MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2011MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2012
2013module_param(default_baud, uint, S_IRUGO);
2014MODULE_PARM_DESC(default_baud,
2015                 "Default BAUD for initial driver state and console (default 9600)");
2016module_param(user_uartclk, uint, S_IRUGO);
2017MODULE_PARM_DESC(user_uartclk,
2018                 "Override UART default or board specific UART clock");
2019
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