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17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/init.h>
20#include <linux/console.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/slab.h>
24#include <linux/wait.h>
25#include <linux/tty.h>
26#include <linux/tty_driver.h>
27#include <linux/tty_flip.h>
28#include <linux/serial.h>
29#include <linux/serial_core.h>
30#include <linux/platform_device.h>
31#include <linux/device.h>
32#include <linux/clk.h>
33#include <linux/delay.h>
34#include <linux/io.h>
35#include <linux/pinctrl/consumer.h>
36#include <linux/of_device.h>
37#include <linux/dma-mapping.h>
38#include <linux/fsl/mxs-dma.h>
39
40#include <asm/cacheflush.h>
41
42#define MXS_AUART_PORTS 5
43
44#define AUART_CTRL0 0x00000000
45#define AUART_CTRL0_SET 0x00000004
46#define AUART_CTRL0_CLR 0x00000008
47#define AUART_CTRL0_TOG 0x0000000c
48#define AUART_CTRL1 0x00000010
49#define AUART_CTRL1_SET 0x00000014
50#define AUART_CTRL1_CLR 0x00000018
51#define AUART_CTRL1_TOG 0x0000001c
52#define AUART_CTRL2 0x00000020
53#define AUART_CTRL2_SET 0x00000024
54#define AUART_CTRL2_CLR 0x00000028
55#define AUART_CTRL2_TOG 0x0000002c
56#define AUART_LINECTRL 0x00000030
57#define AUART_LINECTRL_SET 0x00000034
58#define AUART_LINECTRL_CLR 0x00000038
59#define AUART_LINECTRL_TOG 0x0000003c
60#define AUART_LINECTRL2 0x00000040
61#define AUART_LINECTRL2_SET 0x00000044
62#define AUART_LINECTRL2_CLR 0x00000048
63#define AUART_LINECTRL2_TOG 0x0000004c
64#define AUART_INTR 0x00000050
65#define AUART_INTR_SET 0x00000054
66#define AUART_INTR_CLR 0x00000058
67#define AUART_INTR_TOG 0x0000005c
68#define AUART_DATA 0x00000060
69#define AUART_STAT 0x00000070
70#define AUART_DEBUG 0x00000080
71#define AUART_VERSION 0x00000090
72#define AUART_AUTOBAUD 0x000000a0
73
74#define AUART_CTRL0_SFTRST (1 << 31)
75#define AUART_CTRL0_CLKGATE (1 << 30)
76#define AUART_CTRL0_RXTO_ENABLE (1 << 27)
77#define AUART_CTRL0_RXTIMEOUT(v) (((v) & 0x7ff) << 16)
78#define AUART_CTRL0_XFER_COUNT(v) ((v) & 0xffff)
79
80#define AUART_CTRL1_XFER_COUNT(v) ((v) & 0xffff)
81
82#define AUART_CTRL2_DMAONERR (1 << 26)
83#define AUART_CTRL2_TXDMAE (1 << 25)
84#define AUART_CTRL2_RXDMAE (1 << 24)
85
86#define AUART_CTRL2_CTSEN (1 << 15)
87#define AUART_CTRL2_RTSEN (1 << 14)
88#define AUART_CTRL2_RTS (1 << 11)
89#define AUART_CTRL2_RXE (1 << 9)
90#define AUART_CTRL2_TXE (1 << 8)
91#define AUART_CTRL2_UARTEN (1 << 0)
92
93#define AUART_LINECTRL_BAUD_DIVINT_SHIFT 16
94#define AUART_LINECTRL_BAUD_DIVINT_MASK 0xffff0000
95#define AUART_LINECTRL_BAUD_DIVINT(v) (((v) & 0xffff) << 16)
96#define AUART_LINECTRL_BAUD_DIVFRAC_SHIFT 8
97#define AUART_LINECTRL_BAUD_DIVFRAC_MASK 0x00003f00
98#define AUART_LINECTRL_BAUD_DIVFRAC(v) (((v) & 0x3f) << 8)
99#define AUART_LINECTRL_WLEN_MASK 0x00000060
100#define AUART_LINECTRL_WLEN(v) (((v) & 0x3) << 5)
101#define AUART_LINECTRL_FEN (1 << 4)
102#define AUART_LINECTRL_STP2 (1 << 3)
103#define AUART_LINECTRL_EPS (1 << 2)
104#define AUART_LINECTRL_PEN (1 << 1)
105#define AUART_LINECTRL_BRK (1 << 0)
106
107#define AUART_INTR_RTIEN (1 << 22)
108#define AUART_INTR_TXIEN (1 << 21)
109#define AUART_INTR_RXIEN (1 << 20)
110#define AUART_INTR_CTSMIEN (1 << 17)
111#define AUART_INTR_RTIS (1 << 6)
112#define AUART_INTR_TXIS (1 << 5)
113#define AUART_INTR_RXIS (1 << 4)
114#define AUART_INTR_CTSMIS (1 << 1)
115
116#define AUART_STAT_BUSY (1 << 29)
117#define AUART_STAT_CTS (1 << 28)
118#define AUART_STAT_TXFE (1 << 27)
119#define AUART_STAT_TXFF (1 << 25)
120#define AUART_STAT_RXFE (1 << 24)
121#define AUART_STAT_OERR (1 << 19)
122#define AUART_STAT_BERR (1 << 18)
123#define AUART_STAT_PERR (1 << 17)
124#define AUART_STAT_FERR (1 << 16)
125#define AUART_STAT_RXCOUNT_MASK 0xffff
126
127static struct uart_driver auart_driver;
128
129enum mxs_auart_type {
130 IMX23_AUART,
131 IMX28_AUART,
132};
133
134struct mxs_auart_port {
135 struct uart_port port;
136
137#define MXS_AUART_DMA_CONFIG 0x1
138#define MXS_AUART_DMA_ENABLED 0x2
139#define MXS_AUART_DMA_TX_SYNC 2
140#define MXS_AUART_DMA_RX_READY 3
141 unsigned long flags;
142 unsigned int ctrl;
143 enum mxs_auart_type devtype;
144
145 unsigned int irq;
146
147 struct clk *clk;
148 struct device *dev;
149
150
151 struct mxs_dma_data dma_data;
152 int dma_channel_rx, dma_channel_tx;
153 int dma_irq_rx, dma_irq_tx;
154 int dma_channel;
155
156 struct scatterlist tx_sgl;
157 struct dma_chan *tx_dma_chan;
158 void *tx_dma_buf;
159
160 struct scatterlist rx_sgl;
161 struct dma_chan *rx_dma_chan;
162 void *rx_dma_buf;
163};
164
165static struct platform_device_id mxs_auart_devtype[] = {
166 { .name = "mxs-auart-imx23", .driver_data = IMX23_AUART },
167 { .name = "mxs-auart-imx28", .driver_data = IMX28_AUART },
168 { }
169};
170MODULE_DEVICE_TABLE(platform, mxs_auart_devtype);
171
172static struct of_device_id mxs_auart_dt_ids[] = {
173 {
174 .compatible = "fsl,imx28-auart",
175 .data = &mxs_auart_devtype[IMX28_AUART]
176 }, {
177 .compatible = "fsl,imx23-auart",
178 .data = &mxs_auart_devtype[IMX23_AUART]
179 }, { }
180};
181MODULE_DEVICE_TABLE(of, mxs_auart_dt_ids);
182
183static inline int is_imx28_auart(struct mxs_auart_port *s)
184{
185 return s->devtype == IMX28_AUART;
186}
187
188static inline bool auart_dma_enabled(struct mxs_auart_port *s)
189{
190 return s->flags & MXS_AUART_DMA_ENABLED;
191}
192
193static void mxs_auart_stop_tx(struct uart_port *u);
194
195#define to_auart_port(u) container_of(u, struct mxs_auart_port, port)
196
197static void mxs_auart_tx_chars(struct mxs_auart_port *s);
198
199static void dma_tx_callback(void *param)
200{
201 struct mxs_auart_port *s = param;
202 struct circ_buf *xmit = &s->port.state->xmit;
203
204 dma_unmap_sg(s->dev, &s->tx_sgl, 1, DMA_TO_DEVICE);
205
206
207 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
208 smp_mb__after_clear_bit();
209
210
211 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
212 uart_write_wakeup(&s->port);
213
214 mxs_auart_tx_chars(s);
215}
216
217static int mxs_auart_dma_tx(struct mxs_auart_port *s, int size)
218{
219 struct dma_async_tx_descriptor *desc;
220 struct scatterlist *sgl = &s->tx_sgl;
221 struct dma_chan *channel = s->tx_dma_chan;
222 u32 pio;
223
224
225 pio = AUART_CTRL1_XFER_COUNT(size);
226 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)&pio,
227 1, DMA_TRANS_NONE, 0);
228 if (!desc) {
229 dev_err(s->dev, "step 1 error\n");
230 return -EINVAL;
231 }
232
233
234 sg_init_one(sgl, s->tx_dma_buf, size);
235 dma_map_sg(s->dev, sgl, 1, DMA_TO_DEVICE);
236 desc = dmaengine_prep_slave_sg(channel, sgl,
237 1, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
238 if (!desc) {
239 dev_err(s->dev, "step 2 error\n");
240 return -EINVAL;
241 }
242
243
244 desc->callback = dma_tx_callback;
245 desc->callback_param = s;
246 dmaengine_submit(desc);
247 dma_async_issue_pending(channel);
248 return 0;
249}
250
251static void mxs_auart_tx_chars(struct mxs_auart_port *s)
252{
253 struct circ_buf *xmit = &s->port.state->xmit;
254
255 if (auart_dma_enabled(s)) {
256 u32 i = 0;
257 int size;
258 void *buffer = s->tx_dma_buf;
259
260 if (test_and_set_bit(MXS_AUART_DMA_TX_SYNC, &s->flags))
261 return;
262
263 while (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
264 size = min_t(u32, UART_XMIT_SIZE - i,
265 CIRC_CNT_TO_END(xmit->head,
266 xmit->tail,
267 UART_XMIT_SIZE));
268 memcpy(buffer + i, xmit->buf + xmit->tail, size);
269 xmit->tail = (xmit->tail + size) & (UART_XMIT_SIZE - 1);
270
271 i += size;
272 if (i >= UART_XMIT_SIZE)
273 break;
274 }
275
276 if (uart_tx_stopped(&s->port))
277 mxs_auart_stop_tx(&s->port);
278
279 if (i) {
280 mxs_auart_dma_tx(s, i);
281 } else {
282 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
283 smp_mb__after_clear_bit();
284 }
285 return;
286 }
287
288
289 while (!(readl(s->port.membase + AUART_STAT) &
290 AUART_STAT_TXFF)) {
291 if (s->port.x_char) {
292 s->port.icount.tx++;
293 writel(s->port.x_char,
294 s->port.membase + AUART_DATA);
295 s->port.x_char = 0;
296 continue;
297 }
298 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&s->port)) {
299 s->port.icount.tx++;
300 writel(xmit->buf[xmit->tail],
301 s->port.membase + AUART_DATA);
302 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
303 } else
304 break;
305 }
306 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
307 uart_write_wakeup(&s->port);
308
309 if (uart_circ_empty(&(s->port.state->xmit)))
310 writel(AUART_INTR_TXIEN,
311 s->port.membase + AUART_INTR_CLR);
312 else
313 writel(AUART_INTR_TXIEN,
314 s->port.membase + AUART_INTR_SET);
315
316 if (uart_tx_stopped(&s->port))
317 mxs_auart_stop_tx(&s->port);
318}
319
320static void mxs_auart_rx_char(struct mxs_auart_port *s)
321{
322 int flag;
323 u32 stat;
324 u8 c;
325
326 c = readl(s->port.membase + AUART_DATA);
327 stat = readl(s->port.membase + AUART_STAT);
328
329 flag = TTY_NORMAL;
330 s->port.icount.rx++;
331
332 if (stat & AUART_STAT_BERR) {
333 s->port.icount.brk++;
334 if (uart_handle_break(&s->port))
335 goto out;
336 } else if (stat & AUART_STAT_PERR) {
337 s->port.icount.parity++;
338 } else if (stat & AUART_STAT_FERR) {
339 s->port.icount.frame++;
340 }
341
342
343
344
345 stat &= s->port.read_status_mask;
346
347 if (stat & AUART_STAT_BERR) {
348 flag = TTY_BREAK;
349 } else if (stat & AUART_STAT_PERR)
350 flag = TTY_PARITY;
351 else if (stat & AUART_STAT_FERR)
352 flag = TTY_FRAME;
353
354 if (stat & AUART_STAT_OERR)
355 s->port.icount.overrun++;
356
357 if (uart_handle_sysrq_char(&s->port, c))
358 goto out;
359
360 uart_insert_char(&s->port, stat, AUART_STAT_OERR, c, flag);
361out:
362 writel(stat, s->port.membase + AUART_STAT);
363}
364
365static void mxs_auart_rx_chars(struct mxs_auart_port *s)
366{
367 u32 stat = 0;
368
369 for (;;) {
370 stat = readl(s->port.membase + AUART_STAT);
371 if (stat & AUART_STAT_RXFE)
372 break;
373 mxs_auart_rx_char(s);
374 }
375
376 writel(stat, s->port.membase + AUART_STAT);
377 tty_flip_buffer_push(&s->port.state->port);
378}
379
380static int mxs_auart_request_port(struct uart_port *u)
381{
382 return 0;
383}
384
385static int mxs_auart_verify_port(struct uart_port *u,
386 struct serial_struct *ser)
387{
388 if (u->type != PORT_UNKNOWN && u->type != PORT_IMX)
389 return -EINVAL;
390 return 0;
391}
392
393static void mxs_auart_config_port(struct uart_port *u, int flags)
394{
395}
396
397static const char *mxs_auart_type(struct uart_port *u)
398{
399 struct mxs_auart_port *s = to_auart_port(u);
400
401 return dev_name(s->dev);
402}
403
404static void mxs_auart_release_port(struct uart_port *u)
405{
406}
407
408static void mxs_auart_set_mctrl(struct uart_port *u, unsigned mctrl)
409{
410 struct mxs_auart_port *s = to_auart_port(u);
411
412 u32 ctrl = readl(u->membase + AUART_CTRL2);
413
414 ctrl &= ~(AUART_CTRL2_RTSEN | AUART_CTRL2_RTS);
415 if (mctrl & TIOCM_RTS) {
416 if (tty_port_cts_enabled(&u->state->port))
417 ctrl |= AUART_CTRL2_RTSEN;
418 else
419 ctrl |= AUART_CTRL2_RTS;
420 }
421
422 s->ctrl = mctrl;
423 writel(ctrl, u->membase + AUART_CTRL2);
424}
425
426static u32 mxs_auart_get_mctrl(struct uart_port *u)
427{
428 struct mxs_auart_port *s = to_auart_port(u);
429 u32 stat = readl(u->membase + AUART_STAT);
430 int ctrl2 = readl(u->membase + AUART_CTRL2);
431 u32 mctrl = s->ctrl;
432
433 mctrl &= ~TIOCM_CTS;
434 if (stat & AUART_STAT_CTS)
435 mctrl |= TIOCM_CTS;
436
437 if (ctrl2 & AUART_CTRL2_RTS)
438 mctrl |= TIOCM_RTS;
439
440 return mctrl;
441}
442
443static bool mxs_auart_dma_filter(struct dma_chan *chan, void *param)
444{
445 struct mxs_auart_port *s = param;
446
447 if (!mxs_dma_is_apbx(chan))
448 return false;
449
450 if (s->dma_channel == chan->chan_id) {
451 chan->private = &s->dma_data;
452 return true;
453 }
454 return false;
455}
456
457static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s);
458static void dma_rx_callback(void *arg)
459{
460 struct mxs_auart_port *s = (struct mxs_auart_port *) arg;
461 struct tty_port *port = &s->port.state->port;
462 int count;
463 u32 stat;
464
465 dma_unmap_sg(s->dev, &s->rx_sgl, 1, DMA_FROM_DEVICE);
466
467 stat = readl(s->port.membase + AUART_STAT);
468 stat &= ~(AUART_STAT_OERR | AUART_STAT_BERR |
469 AUART_STAT_PERR | AUART_STAT_FERR);
470
471 count = stat & AUART_STAT_RXCOUNT_MASK;
472 tty_insert_flip_string(port, s->rx_dma_buf, count);
473
474 writel(stat, s->port.membase + AUART_STAT);
475 tty_flip_buffer_push(port);
476
477
478 mxs_auart_dma_prep_rx(s);
479}
480
481static int mxs_auart_dma_prep_rx(struct mxs_auart_port *s)
482{
483 struct dma_async_tx_descriptor *desc;
484 struct scatterlist *sgl = &s->rx_sgl;
485 struct dma_chan *channel = s->rx_dma_chan;
486 u32 pio[1];
487
488
489 pio[0] = AUART_CTRL0_RXTO_ENABLE
490 | AUART_CTRL0_RXTIMEOUT(0x80)
491 | AUART_CTRL0_XFER_COUNT(UART_XMIT_SIZE);
492 desc = dmaengine_prep_slave_sg(channel, (struct scatterlist *)pio,
493 1, DMA_TRANS_NONE, 0);
494 if (!desc) {
495 dev_err(s->dev, "step 1 error\n");
496 return -EINVAL;
497 }
498
499
500 sg_init_one(sgl, s->rx_dma_buf, UART_XMIT_SIZE);
501 dma_map_sg(s->dev, sgl, 1, DMA_FROM_DEVICE);
502 desc = dmaengine_prep_slave_sg(channel, sgl, 1, DMA_DEV_TO_MEM,
503 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
504 if (!desc) {
505 dev_err(s->dev, "step 2 error\n");
506 return -1;
507 }
508
509
510 desc->callback = dma_rx_callback;
511 desc->callback_param = s;
512 dmaengine_submit(desc);
513 dma_async_issue_pending(channel);
514 return 0;
515}
516
517static void mxs_auart_dma_exit_channel(struct mxs_auart_port *s)
518{
519 if (s->tx_dma_chan) {
520 dma_release_channel(s->tx_dma_chan);
521 s->tx_dma_chan = NULL;
522 }
523 if (s->rx_dma_chan) {
524 dma_release_channel(s->rx_dma_chan);
525 s->rx_dma_chan = NULL;
526 }
527
528 kfree(s->tx_dma_buf);
529 kfree(s->rx_dma_buf);
530 s->tx_dma_buf = NULL;
531 s->rx_dma_buf = NULL;
532}
533
534static void mxs_auart_dma_exit(struct mxs_auart_port *s)
535{
536
537 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,
538 s->port.membase + AUART_CTRL2_CLR);
539
540 mxs_auart_dma_exit_channel(s);
541 s->flags &= ~MXS_AUART_DMA_ENABLED;
542 clear_bit(MXS_AUART_DMA_TX_SYNC, &s->flags);
543 clear_bit(MXS_AUART_DMA_RX_READY, &s->flags);
544}
545
546static int mxs_auart_dma_init(struct mxs_auart_port *s)
547{
548 dma_cap_mask_t mask;
549
550 if (auart_dma_enabled(s))
551 return 0;
552
553
554 if (s->dma_channel_rx == -1 || s->dma_channel_tx == -1)
555 return -EINVAL;
556
557
558 dma_cap_zero(mask);
559 dma_cap_set(DMA_SLAVE, mask);
560 s->dma_channel = s->dma_channel_rx;
561 s->dma_data.chan_irq = s->dma_irq_rx;
562 s->rx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
563 if (!s->rx_dma_chan)
564 goto err_out;
565 s->rx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
566 if (!s->rx_dma_buf)
567 goto err_out;
568
569
570 s->dma_channel = s->dma_channel_tx;
571 s->dma_data.chan_irq = s->dma_irq_tx;
572 s->tx_dma_chan = dma_request_channel(mask, mxs_auart_dma_filter, s);
573 if (!s->tx_dma_chan)
574 goto err_out;
575 s->tx_dma_buf = kzalloc(UART_XMIT_SIZE, GFP_KERNEL | GFP_DMA);
576 if (!s->tx_dma_buf)
577 goto err_out;
578
579
580 s->flags |= MXS_AUART_DMA_ENABLED;
581 dev_dbg(s->dev, "enabled the DMA support.");
582
583 return 0;
584
585err_out:
586 mxs_auart_dma_exit_channel(s);
587 return -EINVAL;
588
589}
590
591static void mxs_auart_settermios(struct uart_port *u,
592 struct ktermios *termios,
593 struct ktermios *old)
594{
595 struct mxs_auart_port *s = to_auart_port(u);
596 u32 bm, ctrl, ctrl2, div;
597 unsigned int cflag, baud;
598
599 cflag = termios->c_cflag;
600
601 ctrl = AUART_LINECTRL_FEN;
602 ctrl2 = readl(u->membase + AUART_CTRL2);
603
604
605 switch (cflag & CSIZE) {
606 case CS5:
607 bm = 0;
608 break;
609 case CS6:
610 bm = 1;
611 break;
612 case CS7:
613 bm = 2;
614 break;
615 case CS8:
616 bm = 3;
617 break;
618 default:
619 return;
620 }
621
622 ctrl |= AUART_LINECTRL_WLEN(bm);
623
624
625 if (cflag & PARENB) {
626 ctrl |= AUART_LINECTRL_PEN;
627 if ((cflag & PARODD) == 0)
628 ctrl |= AUART_LINECTRL_EPS;
629 }
630
631 u->read_status_mask = 0;
632
633 if (termios->c_iflag & INPCK)
634 u->read_status_mask |= AUART_STAT_PERR;
635 if (termios->c_iflag & (BRKINT | PARMRK))
636 u->read_status_mask |= AUART_STAT_BERR;
637
638
639
640
641 u->ignore_status_mask = 0;
642 if (termios->c_iflag & IGNPAR)
643 u->ignore_status_mask |= AUART_STAT_PERR;
644 if (termios->c_iflag & IGNBRK) {
645 u->ignore_status_mask |= AUART_STAT_BERR;
646
647
648
649
650 if (termios->c_iflag & IGNPAR)
651 u->ignore_status_mask |= AUART_STAT_OERR;
652 }
653
654
655
656
657 if (cflag & CREAD)
658 ctrl2 |= AUART_CTRL2_RXE;
659 else
660 ctrl2 &= ~AUART_CTRL2_RXE;
661
662
663 if (cflag & CSTOPB)
664 ctrl |= AUART_LINECTRL_STP2;
665
666
667 if (cflag & CRTSCTS) {
668
669
670
671
672
673
674 if (is_imx28_auart(s) && (s->flags & MXS_AUART_DMA_CONFIG)) {
675 if (!mxs_auart_dma_init(s))
676
677 ctrl2 |= AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE
678 | AUART_CTRL2_DMAONERR;
679 }
680 ctrl2 |= AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN;
681 } else {
682 ctrl2 &= ~(AUART_CTRL2_CTSEN | AUART_CTRL2_RTSEN);
683 }
684
685
686 baud = uart_get_baud_rate(u, termios, old, 0, u->uartclk);
687 div = u->uartclk * 32 / baud;
688 ctrl |= AUART_LINECTRL_BAUD_DIVFRAC(div & 0x3F);
689 ctrl |= AUART_LINECTRL_BAUD_DIVINT(div >> 6);
690
691 writel(ctrl, u->membase + AUART_LINECTRL);
692 writel(ctrl2, u->membase + AUART_CTRL2);
693
694 uart_update_timeout(u, termios->c_cflag, baud);
695
696
697 if (auart_dma_enabled(s) &&
698 !test_and_set_bit(MXS_AUART_DMA_RX_READY, &s->flags)) {
699 if (!mxs_auart_dma_prep_rx(s)) {
700
701 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,
702 u->membase + AUART_INTR_CLR);
703 } else {
704 mxs_auart_dma_exit(s);
705 dev_err(s->dev, "We can not start up the DMA.\n");
706 }
707 }
708}
709
710static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
711{
712 u32 istatus, istat;
713 struct mxs_auart_port *s = context;
714 u32 stat = readl(s->port.membase + AUART_STAT);
715
716 istatus = istat = readl(s->port.membase + AUART_INTR);
717
718 if (istat & AUART_INTR_CTSMIS) {
719 uart_handle_cts_change(&s->port, stat & AUART_STAT_CTS);
720 writel(AUART_INTR_CTSMIS,
721 s->port.membase + AUART_INTR_CLR);
722 istat &= ~AUART_INTR_CTSMIS;
723 }
724
725 if (istat & (AUART_INTR_RTIS | AUART_INTR_RXIS)) {
726 if (!auart_dma_enabled(s))
727 mxs_auart_rx_chars(s);
728 istat &= ~(AUART_INTR_RTIS | AUART_INTR_RXIS);
729 }
730
731 if (istat & AUART_INTR_TXIS) {
732 mxs_auart_tx_chars(s);
733 istat &= ~AUART_INTR_TXIS;
734 }
735
736 writel(istatus & (AUART_INTR_RTIS
737 | AUART_INTR_TXIS
738 | AUART_INTR_RXIS
739 | AUART_INTR_CTSMIS),
740 s->port.membase + AUART_INTR_CLR);
741
742 return IRQ_HANDLED;
743}
744
745static void mxs_auart_reset(struct uart_port *u)
746{
747 int i;
748 unsigned int reg;
749
750 writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);
751
752 for (i = 0; i < 10000; i++) {
753 reg = readl(u->membase + AUART_CTRL0);
754 if (!(reg & AUART_CTRL0_SFTRST))
755 break;
756 udelay(3);
757 }
758 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
759}
760
761static int mxs_auart_startup(struct uart_port *u)
762{
763 struct mxs_auart_port *s = to_auart_port(u);
764
765 clk_prepare_enable(s->clk);
766
767 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);
768
769 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);
770
771 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
772 u->membase + AUART_INTR);
773
774
775
776
777
778 writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);
779
780 return 0;
781}
782
783static void mxs_auart_shutdown(struct uart_port *u)
784{
785 struct mxs_auart_port *s = to_auart_port(u);
786
787 if (auart_dma_enabled(s))
788 mxs_auart_dma_exit(s);
789
790 writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);
791
792 writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,
793 u->membase + AUART_INTR_CLR);
794
795 writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);
796
797 clk_disable_unprepare(s->clk);
798}
799
800static unsigned int mxs_auart_tx_empty(struct uart_port *u)
801{
802 if (readl(u->membase + AUART_STAT) & AUART_STAT_TXFE)
803 return TIOCSER_TEMT;
804 else
805 return 0;
806}
807
808static void mxs_auart_start_tx(struct uart_port *u)
809{
810 struct mxs_auart_port *s = to_auart_port(u);
811
812
813 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);
814
815 mxs_auart_tx_chars(s);
816}
817
818static void mxs_auart_stop_tx(struct uart_port *u)
819{
820 writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);
821}
822
823static void mxs_auart_stop_rx(struct uart_port *u)
824{
825 writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);
826}
827
828static void mxs_auart_break_ctl(struct uart_port *u, int ctl)
829{
830 if (ctl)
831 writel(AUART_LINECTRL_BRK,
832 u->membase + AUART_LINECTRL_SET);
833 else
834 writel(AUART_LINECTRL_BRK,
835 u->membase + AUART_LINECTRL_CLR);
836}
837
838static void mxs_auart_enable_ms(struct uart_port *port)
839{
840
841}
842
843static struct uart_ops mxs_auart_ops = {
844 .tx_empty = mxs_auart_tx_empty,
845 .start_tx = mxs_auart_start_tx,
846 .stop_tx = mxs_auart_stop_tx,
847 .stop_rx = mxs_auart_stop_rx,
848 .enable_ms = mxs_auart_enable_ms,
849 .break_ctl = mxs_auart_break_ctl,
850 .set_mctrl = mxs_auart_set_mctrl,
851 .get_mctrl = mxs_auart_get_mctrl,
852 .startup = mxs_auart_startup,
853 .shutdown = mxs_auart_shutdown,
854 .set_termios = mxs_auart_settermios,
855 .type = mxs_auart_type,
856 .release_port = mxs_auart_release_port,
857 .request_port = mxs_auart_request_port,
858 .config_port = mxs_auart_config_port,
859 .verify_port = mxs_auart_verify_port,
860};
861
862static struct mxs_auart_port *auart_port[MXS_AUART_PORTS];
863
864#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
865static void mxs_auart_console_putchar(struct uart_port *port, int ch)
866{
867 unsigned int to = 1000;
868
869 while (readl(port->membase + AUART_STAT) & AUART_STAT_TXFF) {
870 if (!to--)
871 break;
872 udelay(1);
873 }
874
875 writel(ch, port->membase + AUART_DATA);
876}
877
878static void
879auart_console_write(struct console *co, const char *str, unsigned int count)
880{
881 struct mxs_auart_port *s;
882 struct uart_port *port;
883 unsigned int old_ctrl0, old_ctrl2;
884 unsigned int to = 1000;
885
886 if (co->index > MXS_AUART_PORTS || co->index < 0)
887 return;
888
889 s = auart_port[co->index];
890 port = &s->port;
891
892 clk_enable(s->clk);
893
894
895 old_ctrl2 = readl(port->membase + AUART_CTRL2);
896 old_ctrl0 = readl(port->membase + AUART_CTRL0);
897
898 writel(AUART_CTRL0_CLKGATE,
899 port->membase + AUART_CTRL0_CLR);
900 writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,
901 port->membase + AUART_CTRL2_SET);
902
903 uart_console_write(port, str, count, mxs_auart_console_putchar);
904
905
906
907
908
909 while (readl(port->membase + AUART_STAT) & AUART_STAT_BUSY) {
910 if (!to--)
911 break;
912 udelay(1);
913 }
914
915 writel(old_ctrl0, port->membase + AUART_CTRL0);
916 writel(old_ctrl2, port->membase + AUART_CTRL2);
917
918 clk_disable(s->clk);
919}
920
921static void __init
922auart_console_get_options(struct uart_port *port, int *baud,
923 int *parity, int *bits)
924{
925 unsigned int lcr_h, quot;
926
927 if (!(readl(port->membase + AUART_CTRL2) & AUART_CTRL2_UARTEN))
928 return;
929
930 lcr_h = readl(port->membase + AUART_LINECTRL);
931
932 *parity = 'n';
933 if (lcr_h & AUART_LINECTRL_PEN) {
934 if (lcr_h & AUART_LINECTRL_EPS)
935 *parity = 'e';
936 else
937 *parity = 'o';
938 }
939
940 if ((lcr_h & AUART_LINECTRL_WLEN_MASK) == AUART_LINECTRL_WLEN(2))
941 *bits = 7;
942 else
943 *bits = 8;
944
945 quot = ((readl(port->membase + AUART_LINECTRL)
946 & AUART_LINECTRL_BAUD_DIVINT_MASK))
947 >> (AUART_LINECTRL_BAUD_DIVINT_SHIFT - 6);
948 quot |= ((readl(port->membase + AUART_LINECTRL)
949 & AUART_LINECTRL_BAUD_DIVFRAC_MASK))
950 >> AUART_LINECTRL_BAUD_DIVFRAC_SHIFT;
951 if (quot == 0)
952 quot = 1;
953
954 *baud = (port->uartclk << 2) / quot;
955}
956
957static int __init
958auart_console_setup(struct console *co, char *options)
959{
960 struct mxs_auart_port *s;
961 int baud = 9600;
962 int bits = 8;
963 int parity = 'n';
964 int flow = 'n';
965 int ret;
966
967
968
969
970
971
972 if (co->index == -1 || co->index >= ARRAY_SIZE(auart_port))
973 co->index = 0;
974 s = auart_port[co->index];
975 if (!s)
976 return -ENODEV;
977
978 clk_prepare_enable(s->clk);
979
980 if (options)
981 uart_parse_options(options, &baud, &parity, &bits, &flow);
982 else
983 auart_console_get_options(&s->port, &baud, &parity, &bits);
984
985 ret = uart_set_options(&s->port, co, baud, parity, bits, flow);
986
987 clk_disable_unprepare(s->clk);
988
989 return ret;
990}
991
992static struct console auart_console = {
993 .name = "ttyAPP",
994 .write = auart_console_write,
995 .device = uart_console_device,
996 .setup = auart_console_setup,
997 .flags = CON_PRINTBUFFER,
998 .index = -1,
999 .data = &auart_driver,
1000};
1001#endif
1002
1003static struct uart_driver auart_driver = {
1004 .owner = THIS_MODULE,
1005 .driver_name = "ttyAPP",
1006 .dev_name = "ttyAPP",
1007 .major = 0,
1008 .minor = 0,
1009 .nr = MXS_AUART_PORTS,
1010#ifdef CONFIG_SERIAL_MXS_AUART_CONSOLE
1011 .cons = &auart_console,
1012#endif
1013};
1014
1015
1016
1017
1018
1019static int serial_mxs_probe_dt(struct mxs_auart_port *s,
1020 struct platform_device *pdev)
1021{
1022 struct device_node *np = pdev->dev.of_node;
1023 u32 dma_channel[2];
1024 int ret;
1025
1026 if (!np)
1027
1028 return 1;
1029
1030 ret = of_alias_get_id(np, "serial");
1031 if (ret < 0) {
1032 dev_err(&pdev->dev, "failed to get alias id: %d\n", ret);
1033 return ret;
1034 }
1035 s->port.line = ret;
1036
1037 s->dma_irq_rx = platform_get_irq(pdev, 1);
1038 s->dma_irq_tx = platform_get_irq(pdev, 2);
1039
1040 ret = of_property_read_u32_array(np, "fsl,auart-dma-channel",
1041 dma_channel, 2);
1042 if (ret == 0) {
1043 s->dma_channel_rx = dma_channel[0];
1044 s->dma_channel_tx = dma_channel[1];
1045
1046 s->flags |= MXS_AUART_DMA_CONFIG;
1047 } else {
1048 s->dma_channel_rx = -1;
1049 s->dma_channel_tx = -1;
1050 }
1051 return 0;
1052}
1053
1054static int mxs_auart_probe(struct platform_device *pdev)
1055{
1056 const struct of_device_id *of_id =
1057 of_match_device(mxs_auart_dt_ids, &pdev->dev);
1058 struct mxs_auart_port *s;
1059 u32 version;
1060 int ret = 0;
1061 struct resource *r;
1062 struct pinctrl *pinctrl;
1063
1064 s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL);
1065 if (!s) {
1066 ret = -ENOMEM;
1067 goto out;
1068 }
1069
1070 ret = serial_mxs_probe_dt(s, pdev);
1071 if (ret > 0)
1072 s->port.line = pdev->id < 0 ? 0 : pdev->id;
1073 else if (ret < 0)
1074 goto out_free;
1075
1076 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1077 if (IS_ERR(pinctrl)) {
1078 ret = PTR_ERR(pinctrl);
1079 goto out_free;
1080 }
1081
1082 if (of_id) {
1083 pdev->id_entry = of_id->data;
1084 s->devtype = pdev->id_entry->driver_data;
1085 }
1086
1087 s->clk = clk_get(&pdev->dev, NULL);
1088 if (IS_ERR(s->clk)) {
1089 ret = PTR_ERR(s->clk);
1090 goto out_free;
1091 }
1092
1093 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1094 if (!r) {
1095 ret = -ENXIO;
1096 goto out_free_clk;
1097 }
1098
1099 s->port.mapbase = r->start;
1100 s->port.membase = ioremap(r->start, resource_size(r));
1101 s->port.ops = &mxs_auart_ops;
1102 s->port.iotype = UPIO_MEM;
1103 s->port.fifosize = 16;
1104 s->port.uartclk = clk_get_rate(s->clk);
1105 s->port.type = PORT_IMX;
1106 s->port.dev = s->dev = get_device(&pdev->dev);
1107
1108 s->ctrl = 0;
1109
1110 s->irq = platform_get_irq(pdev, 0);
1111 s->port.irq = s->irq;
1112 ret = request_irq(s->irq, mxs_auart_irq_handle, 0, dev_name(&pdev->dev), s);
1113 if (ret)
1114 goto out_free_clk;
1115
1116 platform_set_drvdata(pdev, s);
1117
1118 auart_port[s->port.line] = s;
1119
1120 mxs_auart_reset(&s->port);
1121
1122 ret = uart_add_one_port(&auart_driver, &s->port);
1123 if (ret)
1124 goto out_free_irq;
1125
1126 version = readl(s->port.membase + AUART_VERSION);
1127 dev_info(&pdev->dev, "Found APPUART %d.%d.%d\n",
1128 (version >> 24) & 0xff,
1129 (version >> 16) & 0xff, version & 0xffff);
1130
1131 return 0;
1132
1133out_free_irq:
1134 auart_port[pdev->id] = NULL;
1135 free_irq(s->irq, s);
1136out_free_clk:
1137 put_device(s->dev);
1138 clk_put(s->clk);
1139out_free:
1140 kfree(s);
1141out:
1142 return ret;
1143}
1144
1145static int mxs_auart_remove(struct platform_device *pdev)
1146{
1147 struct mxs_auart_port *s = platform_get_drvdata(pdev);
1148
1149 uart_remove_one_port(&auart_driver, &s->port);
1150
1151 auart_port[pdev->id] = NULL;
1152
1153 put_device(s->dev);
1154 clk_put(s->clk);
1155 free_irq(s->irq, s);
1156 kfree(s);
1157
1158 return 0;
1159}
1160
1161static struct platform_driver mxs_auart_driver = {
1162 .probe = mxs_auart_probe,
1163 .remove = mxs_auart_remove,
1164 .driver = {
1165 .name = "mxs-auart",
1166 .owner = THIS_MODULE,
1167 .of_match_table = mxs_auart_dt_ids,
1168 },
1169};
1170
1171static int __init mxs_auart_init(void)
1172{
1173 int r;
1174
1175 r = uart_register_driver(&auart_driver);
1176 if (r)
1177 goto out;
1178
1179 r = platform_driver_register(&mxs_auart_driver);
1180 if (r)
1181 goto out_err;
1182
1183 return 0;
1184out_err:
1185 uart_unregister_driver(&auart_driver);
1186out:
1187 return r;
1188}
1189
1190static void __exit mxs_auart_exit(void)
1191{
1192 platform_driver_unregister(&mxs_auart_driver);
1193 uart_unregister_driver(&auart_driver);
1194}
1195
1196module_init(mxs_auart_init);
1197module_exit(mxs_auart_exit);
1198MODULE_LICENSE("GPL");
1199MODULE_DESCRIPTION("Freescale MXS application uart driver");
1200MODULE_ALIAS("platform:mxs-auart");
1201
