linux/drivers/staging/comedi/drivers/s626.c
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   1/*
   2 * comedi/drivers/s626.c
   3 * Sensoray s626 Comedi driver
   4 *
   5 * COMEDI - Linux Control and Measurement Device Interface
   6 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
   7 *
   8 * Based on Sensoray Model 626 Linux driver Version 0.2
   9 * Copyright (C) 2002-2004 Sensoray Co., Inc.
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 */
  21
  22/*
  23 * Driver: s626
  24 * Description: Sensoray 626 driver
  25 * Devices: [Sensoray] 626 (s626)
  26 * Authors: Gianluca Palli <gpalli@deis.unibo.it>,
  27 * Updated: Fri, 15 Feb 2008 10:28:42 +0000
  28 * Status: experimental
  29
  30 * Configuration options: not applicable, uses PCI auto config
  31
  32 * INSN_CONFIG instructions:
  33 *   analog input:
  34 *    none
  35 *
  36 *   analog output:
  37 *    none
  38 *
  39 *   digital channel:
  40 *    s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
  41 *    supported configuration options:
  42 *    INSN_CONFIG_DIO_QUERY
  43 *    COMEDI_INPUT
  44 *    COMEDI_OUTPUT
  45 *
  46 *   encoder:
  47 *    Every channel must be configured before reading.
  48 *
  49 *   Example code
  50 *
  51 *    insn.insn=INSN_CONFIG;   //configuration instruction
  52 *    insn.n=1;                //number of operation (must be 1)
  53 *    insn.data=&initialvalue; //initial value loaded into encoder
  54 *                             //during configuration
  55 *    insn.subdev=5;           //encoder subdevice
  56 *    insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
  57 *                                                         //to configure
  58 *
  59 *    comedi_do_insn(cf,&insn); //executing configuration
  60 */
  61
  62#include <linux/module.h>
  63#include <linux/delay.h>
  64#include <linux/interrupt.h>
  65#include <linux/kernel.h>
  66#include <linux/types.h>
  67
  68#include "../comedi_pci.h"
  69
  70#include "s626.h"
  71
  72struct s626_buffer_dma {
  73        dma_addr_t physical_base;
  74        void *logical_base;
  75};
  76
  77struct s626_private {
  78        uint8_t ai_cmd_running;         /* ai_cmd is running */
  79        unsigned int ai_sample_timer;   /* time between samples in
  80                                         * units of the timer */
  81        int ai_convert_count;           /* conversion counter */
  82        unsigned int ai_convert_timer;  /* time between conversion in
  83                                         * units of the timer */
  84        uint16_t counter_int_enabs;     /* counter interrupt enable mask
  85                                         * for MISC2 register */
  86        uint8_t adc_items;              /* number of items in ADC poll list */
  87        struct s626_buffer_dma rps_buf; /* DMA buffer used to hold ADC (RPS1)
  88                                         * program */
  89        struct s626_buffer_dma ana_buf; /* DMA buffer used to receive ADC data
  90                                         * and hold DAC data */
  91        uint32_t *dac_wbuf;             /* pointer to logical adrs of DMA buffer
  92                                         * used to hold DAC data */
  93        uint16_t dacpol;                /* image of DAC polarity register */
  94        uint8_t trim_setpoint[12];      /* images of TrimDAC setpoints */
  95        uint32_t i2c_adrs;              /* I2C device address for onboard EEPROM
  96                                         * (board rev dependent) */
  97};
  98
  99/* Counter overflow/index event flag masks for RDMISC2. */
 100#define S626_INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 +  4)))
 101#define S626_OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
 102
 103/*
 104 * Enable/disable a function or test status bit(s) that are accessed
 105 * through Main Control Registers 1 or 2.
 106 */
 107static void s626_mc_enable(struct comedi_device *dev,
 108                           unsigned int cmd, unsigned int reg)
 109{
 110        unsigned int val = (cmd << 16) | cmd;
 111
 112        mmiowb();
 113        writel(val, dev->mmio + reg);
 114}
 115
 116static void s626_mc_disable(struct comedi_device *dev,
 117                            unsigned int cmd, unsigned int reg)
 118{
 119        writel(cmd << 16, dev->mmio + reg);
 120        mmiowb();
 121}
 122
 123static bool s626_mc_test(struct comedi_device *dev,
 124                         unsigned int cmd, unsigned int reg)
 125{
 126        unsigned int val;
 127
 128        val = readl(dev->mmio + reg);
 129
 130        return (val & cmd) ? true : false;
 131}
 132
 133#define S626_BUGFIX_STREG(REGADRS)   ((REGADRS) - 4)
 134
 135/* Write a time slot control record to TSL2. */
 136#define S626_VECTPORT(VECTNUM)          (S626_P_TSL2 + ((VECTNUM) << 2))
 137
 138static const struct comedi_lrange s626_range_table = {
 139        2, {
 140                BIP_RANGE(5),
 141                BIP_RANGE(10)
 142        }
 143};
 144
 145/*
 146 * Execute a DEBI transfer.  This must be called from within a critical section.
 147 */
 148static void s626_debi_transfer(struct comedi_device *dev)
 149{
 150        static const int timeout = 10000;
 151        int i;
 152
 153        /* Initiate upload of shadow RAM to DEBI control register */
 154        s626_mc_enable(dev, S626_MC2_UPLD_DEBI, S626_P_MC2);
 155
 156        /*
 157         * Wait for completion of upload from shadow RAM to
 158         * DEBI control register.
 159         */
 160        for (i = 0; i < timeout; i++) {
 161                if (s626_mc_test(dev, S626_MC2_UPLD_DEBI, S626_P_MC2))
 162                        break;
 163                udelay(1);
 164        }
 165        if (i == timeout)
 166                dev_err(dev->class_dev,
 167                        "Timeout while uploading to DEBI control register\n");
 168
 169        /* Wait until DEBI transfer is done */
 170        for (i = 0; i < timeout; i++) {
 171                if (!(readl(dev->mmio + S626_P_PSR) & S626_PSR_DEBI_S))
 172                        break;
 173                udelay(1);
 174        }
 175        if (i == timeout)
 176                dev_err(dev->class_dev, "DEBI transfer timeout\n");
 177}
 178
 179/*
 180 * Read a value from a gate array register.
 181 */
 182static uint16_t s626_debi_read(struct comedi_device *dev, uint16_t addr)
 183{
 184        /* Set up DEBI control register value in shadow RAM */
 185        writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
 186
 187        /*  Execute the DEBI transfer. */
 188        s626_debi_transfer(dev);
 189
 190        return readl(dev->mmio + S626_P_DEBIAD);
 191}
 192
 193/*
 194 * Write a value to a gate array register.
 195 */
 196static void s626_debi_write(struct comedi_device *dev, uint16_t addr,
 197                            uint16_t wdata)
 198{
 199        /* Set up DEBI control register value in shadow RAM */
 200        writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
 201        writel(wdata, dev->mmio + S626_P_DEBIAD);
 202
 203        /*  Execute the DEBI transfer. */
 204        s626_debi_transfer(dev);
 205}
 206
 207/*
 208 * Replace the specified bits in a gate array register.  Imports: mask
 209 * specifies bits that are to be preserved, wdata is new value to be
 210 * or'd with the masked original.
 211 */
 212static void s626_debi_replace(struct comedi_device *dev, unsigned int addr,
 213                              unsigned int mask, unsigned int wdata)
 214{
 215        unsigned int val;
 216
 217        addr &= 0xffff;
 218        writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD);
 219        s626_debi_transfer(dev);
 220
 221        writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD);
 222        val = readl(dev->mmio + S626_P_DEBIAD);
 223        val &= mask;
 224        val |= wdata;
 225        writel(val & 0xffff, dev->mmio + S626_P_DEBIAD);
 226        s626_debi_transfer(dev);
 227}
 228
 229/* **************  EEPROM ACCESS FUNCTIONS  ************** */
 230
 231static int s626_i2c_handshake_eoc(struct comedi_device *dev,
 232                                  struct comedi_subdevice *s,
 233                                  struct comedi_insn *insn,
 234                                  unsigned long context)
 235{
 236        bool status;
 237
 238        status = s626_mc_test(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
 239        if (status)
 240                return 0;
 241        return -EBUSY;
 242}
 243
 244static int s626_i2c_handshake(struct comedi_device *dev, uint32_t val)
 245{
 246        unsigned int ctrl;
 247        int ret;
 248
 249        /* Write I2C command to I2C Transfer Control shadow register */
 250        writel(val, dev->mmio + S626_P_I2CCTRL);
 251
 252        /*
 253         * Upload I2C shadow registers into working registers and
 254         * wait for upload confirmation.
 255         */
 256        s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
 257        ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
 258        if (ret)
 259                return ret;
 260
 261        /* Wait until I2C bus transfer is finished or an error occurs */
 262        do {
 263                ctrl = readl(dev->mmio + S626_P_I2CCTRL);
 264        } while ((ctrl & (S626_I2C_BUSY | S626_I2C_ERR)) == S626_I2C_BUSY);
 265
 266        /* Return non-zero if I2C error occurred */
 267        return ctrl & S626_I2C_ERR;
 268}
 269
 270/* Read uint8_t from EEPROM. */
 271static uint8_t s626_i2c_read(struct comedi_device *dev, uint8_t addr)
 272{
 273        struct s626_private *devpriv = dev->private;
 274
 275        /*
 276         * Send EEPROM target address:
 277         *  Byte2 = I2C command: write to I2C EEPROM device.
 278         *  Byte1 = EEPROM internal target address.
 279         *  Byte0 = Not sent.
 280         */
 281        if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
 282                                                devpriv->i2c_adrs) |
 283                                    S626_I2C_B1(S626_I2C_ATTRSTOP, addr) |
 284                                    S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
 285                /* Abort function and declare error if handshake failed. */
 286                return 0;
 287
 288        /*
 289         * Execute EEPROM read:
 290         *  Byte2 = I2C command: read from I2C EEPROM device.
 291         *  Byte1 receives uint8_t from EEPROM.
 292         *  Byte0 = Not sent.
 293         */
 294        if (s626_i2c_handshake(dev, S626_I2C_B2(S626_I2C_ATTRSTART,
 295                                                (devpriv->i2c_adrs | 1)) |
 296                                    S626_I2C_B1(S626_I2C_ATTRSTOP, 0) |
 297                                    S626_I2C_B0(S626_I2C_ATTRNOP, 0)))
 298                /* Abort function and declare error if handshake failed. */
 299                return 0;
 300
 301        return (readl(dev->mmio + S626_P_I2CCTRL) >> 16) & 0xff;
 302}
 303
 304/* ***********  DAC FUNCTIONS *********** */
 305
 306/* TrimDac LogicalChan-to-PhysicalChan mapping table. */
 307static const uint8_t s626_trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
 308
 309/* TrimDac LogicalChan-to-EepromAdrs mapping table. */
 310static const uint8_t s626_trimadrs[] = {
 311        0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63
 312};
 313
 314enum {
 315        s626_send_dac_wait_not_mc1_a2out,
 316        s626_send_dac_wait_ssr_af2_out,
 317        s626_send_dac_wait_fb_buffer2_msb_00,
 318        s626_send_dac_wait_fb_buffer2_msb_ff
 319};
 320
 321static int s626_send_dac_eoc(struct comedi_device *dev,
 322                             struct comedi_subdevice *s,
 323                             struct comedi_insn *insn,
 324                             unsigned long context)
 325{
 326        unsigned int status;
 327
 328        switch (context) {
 329        case s626_send_dac_wait_not_mc1_a2out:
 330                status = readl(dev->mmio + S626_P_MC1);
 331                if (!(status & S626_MC1_A2OUT))
 332                        return 0;
 333                break;
 334        case s626_send_dac_wait_ssr_af2_out:
 335                status = readl(dev->mmio + S626_P_SSR);
 336                if (status & S626_SSR_AF2_OUT)
 337                        return 0;
 338                break;
 339        case s626_send_dac_wait_fb_buffer2_msb_00:
 340                status = readl(dev->mmio + S626_P_FB_BUFFER2);
 341                if (!(status & 0xff000000))
 342                        return 0;
 343                break;
 344        case s626_send_dac_wait_fb_buffer2_msb_ff:
 345                status = readl(dev->mmio + S626_P_FB_BUFFER2);
 346                if (status & 0xff000000)
 347                        return 0;
 348                break;
 349        default:
 350                return -EINVAL;
 351        }
 352        return -EBUSY;
 353}
 354
 355/*
 356 * Private helper function: Transmit serial data to DAC via Audio
 357 * channel 2.  Assumes: (1) TSL2 slot records initialized, and (2)
 358 * dacpol contains valid target image.
 359 */
 360static int s626_send_dac(struct comedi_device *dev, uint32_t val)
 361{
 362        struct s626_private *devpriv = dev->private;
 363        int ret;
 364
 365        /* START THE SERIAL CLOCK RUNNING ------------- */
 366
 367        /*
 368         * Assert DAC polarity control and enable gating of DAC serial clock
 369         * and audio bit stream signals.  At this point in time we must be
 370         * assured of being in time slot 0.  If we are not in slot 0, the
 371         * serial clock and audio stream signals will be disabled; this is
 372         * because the following s626_debi_write statement (which enables
 373         * signals to be passed through the gate array) would execute before
 374         * the trailing edge of WS1/WS3 (which turns off the signals), thus
 375         * causing the signals to be inactive during the DAC write.
 376         */
 377        s626_debi_write(dev, S626_LP_DACPOL, devpriv->dacpol);
 378
 379        /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
 380
 381        /* Copy DAC setpoint value to DAC's output DMA buffer. */
 382        /* writel(val, dev->mmio + (uint32_t)devpriv->dac_wbuf); */
 383        *devpriv->dac_wbuf = val;
 384
 385        /*
 386         * Enable the output DMA transfer. This will cause the DMAC to copy
 387         * the DAC's data value to A2's output FIFO. The DMA transfer will
 388         * then immediately terminate because the protection address is
 389         * reached upon transfer of the first DWORD value.
 390         */
 391        s626_mc_enable(dev, S626_MC1_A2OUT, S626_P_MC1);
 392
 393        /* While the DMA transfer is executing ... */
 394
 395        /*
 396         * Reset Audio2 output FIFO's underflow flag (along with any
 397         * other FIFO underflow/overflow flags). When set, this flag
 398         * will indicate that we have emerged from slot 0.
 399         */
 400        writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR);
 401
 402        /*
 403         * Wait for the DMA transfer to finish so that there will be data
 404         * available in the FIFO when time slot 1 tries to transfer a DWORD
 405         * from the FIFO to the output buffer register.  We test for DMA
 406         * Done by polling the DMAC enable flag; this flag is automatically
 407         * cleared when the transfer has finished.
 408         */
 409        ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
 410                             s626_send_dac_wait_not_mc1_a2out);
 411        if (ret) {
 412                dev_err(dev->class_dev, "DMA transfer timeout\n");
 413                return ret;
 414        }
 415
 416        /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
 417
 418        /*
 419         * FIFO data is now available, so we enable execution of time slots
 420         * 1 and higher by clearing the EOS flag in slot 0.  Note that SD3
 421         * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
 422         * detection.
 423         */
 424        writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2,
 425               dev->mmio + S626_VECTPORT(0));
 426
 427        /*
 428         * Wait for slot 1 to execute to ensure that the Packet will be
 429         * transmitted.  This is detected by polling the Audio2 output FIFO
 430         * underflow flag, which will be set when slot 1 execution has
 431         * finished transferring the DAC's data DWORD from the output FIFO
 432         * to the output buffer register.
 433         */
 434        ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
 435                             s626_send_dac_wait_ssr_af2_out);
 436        if (ret) {
 437                dev_err(dev->class_dev,
 438                        "TSL timeout waiting for slot 1 to execute\n");
 439                return ret;
 440        }
 441
 442        /*
 443         * Set up to trap execution at slot 0 when the TSL sequencer cycles
 444         * back to slot 0 after executing the EOS in slot 5.  Also,
 445         * simultaneously shift out and in the 0x00 that is ALWAYS the value
 446         * stored in the last byte to be shifted out of the FIFO's DWORD
 447         * buffer register.
 448         */
 449        writel(S626_XSD2 | S626_XFIFO_2 | S626_RSD2 | S626_SIB_A2 | S626_EOS,
 450               dev->mmio + S626_VECTPORT(0));
 451
 452        /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
 453
 454        /*
 455         * Wait for the TSL to finish executing all time slots before
 456         * exiting this function.  We must do this so that the next DAC
 457         * write doesn't start, thereby enabling clock/chip select signals:
 458         *
 459         * 1. Before the TSL sequence cycles back to slot 0, which disables
 460         *    the clock/cs signal gating and traps slot // list execution.
 461         *    we have not yet finished slot 5 then the clock/cs signals are
 462         *    still gated and we have not finished transmitting the stream.
 463         *
 464         * 2. While slots 2-5 are executing due to a late slot 0 trap.  In
 465         *    this case, the slot sequence is currently repeating, but with
 466         *    clock/cs signals disabled.  We must wait for slot 0 to trap
 467         *    execution before setting up the next DAC setpoint DMA transfer
 468         *    and enabling the clock/cs signals.  To detect the end of slot 5,
 469         *    we test for the FB_BUFFER2 MSB contents to be equal to 0xFF.  If
 470         *    the TSL has not yet finished executing slot 5 ...
 471         */
 472        if (readl(dev->mmio + S626_P_FB_BUFFER2) & 0xff000000) {
 473                /*
 474                 * The trap was set on time and we are still executing somewhere
 475                 * in slots 2-5, so we now wait for slot 0 to execute and trap
 476                 * TSL execution.  This is detected when FB_BUFFER2 MSB changes
 477                 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
 478                 * out/in on SD2 the 0x00 that is always referenced by slot 5.
 479                 */
 480                ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
 481                                     s626_send_dac_wait_fb_buffer2_msb_00);
 482                if (ret) {
 483                        dev_err(dev->class_dev,
 484                                "TSL timeout waiting for slot 0 to execute\n");
 485                        return ret;
 486                }
 487        }
 488        /*
 489         * Either (1) we were too late setting the slot 0 trap; the TSL
 490         * sequencer restarted slot 0 before we could set the EOS trap flag,
 491         * or (2) we were not late and execution is now trapped at slot 0.
 492         * In either case, we must now change slot 0 so that it will store
 493         * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
 494         * In order to do this, we reprogram slot 0 so that it will shift in
 495         * SD3, which is driven only by a pull-up resistor.
 496         */
 497        writel(S626_RSD3 | S626_SIB_A2 | S626_EOS,
 498               dev->mmio + S626_VECTPORT(0));
 499
 500        /*
 501         * Wait for slot 0 to execute, at which time the TSL is setup for
 502         * the next DAC write.  This is detected when FB_BUFFER2 MSB changes
 503         * from 0x00 to 0xFF.
 504         */
 505        ret = comedi_timeout(dev, NULL, NULL, s626_send_dac_eoc,
 506                             s626_send_dac_wait_fb_buffer2_msb_ff);
 507        if (ret) {
 508                dev_err(dev->class_dev,
 509                        "TSL timeout waiting for slot 0 to execute\n");
 510                return ret;
 511        }
 512        return 0;
 513}
 514
 515/*
 516 * Private helper function: Write setpoint to an application DAC channel.
 517 */
 518static int s626_set_dac(struct comedi_device *dev,
 519                        uint16_t chan, int16_t dacdata)
 520{
 521        struct s626_private *devpriv = dev->private;
 522        uint16_t signmask;
 523        uint32_t ws_image;
 524        uint32_t val;
 525
 526        /*
 527         * Adjust DAC data polarity and set up Polarity Control Register image.
 528         */
 529        signmask = 1 << chan;
 530        if (dacdata < 0) {
 531                dacdata = -dacdata;
 532                devpriv->dacpol |= signmask;
 533        } else {
 534                devpriv->dacpol &= ~signmask;
 535        }
 536
 537        /* Limit DAC setpoint value to valid range. */
 538        if ((uint16_t)dacdata > 0x1FFF)
 539                dacdata = 0x1FFF;
 540
 541        /*
 542         * Set up TSL2 records (aka "vectors") for DAC update.  Vectors V2
 543         * and V3 transmit the setpoint to the target DAC.  V4 and V5 send
 544         * data to a non-existent TrimDac channel just to keep the clock
 545         * running after sending data to the target DAC.  This is necessary
 546         * to eliminate the clock glitch that would otherwise occur at the
 547         * end of the target DAC's serial data stream.  When the sequence
 548         * restarts at V0 (after executing V5), the gate array automatically
 549         * disables gating for the DAC clock and all DAC chip selects.
 550         */
 551
 552        /* Choose DAC chip select to be asserted */
 553        ws_image = (chan & 2) ? S626_WS1 : S626_WS2;
 554        /* Slot 2: Transmit high data byte to target DAC */
 555        writel(S626_XSD2 | S626_XFIFO_1 | ws_image,
 556               dev->mmio + S626_VECTPORT(2));
 557        /* Slot 3: Transmit low data byte to target DAC */
 558        writel(S626_XSD2 | S626_XFIFO_0 | ws_image,
 559               dev->mmio + S626_VECTPORT(3));
 560        /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
 561        writel(S626_XSD2 | S626_XFIFO_3 | S626_WS3,
 562               dev->mmio + S626_VECTPORT(4));
 563        /* Slot 5: running after writing target DAC's low data byte */
 564        writel(S626_XSD2 | S626_XFIFO_2 | S626_WS3 | S626_EOS,
 565               dev->mmio + S626_VECTPORT(5));
 566
 567        /*
 568         * Construct and transmit target DAC's serial packet:
 569         * (A10D DDDD), (DDDD DDDD), (0x0F), (0x00) where A is chan<0>,
 570         * and D<12:0> is the DAC setpoint.  Append a WORD value (that writes
 571         * to a  non-existent TrimDac channel) that serves to keep the clock
 572         * running after the packet has been sent to the target DAC.
 573         */
 574        val = 0x0F000000;       /* Continue clock after target DAC data
 575                                 * (write to non-existent trimdac). */
 576        val |= 0x00004000;      /* Address the two main dual-DAC devices
 577                                 * (TSL's chip select enables target device). */
 578        val |= ((uint32_t)(chan & 1) << 15);    /* Address the DAC channel
 579                                                 * within the device. */
 580        val |= (uint32_t)dacdata;       /* Include DAC setpoint data. */
 581        return s626_send_dac(dev, val);
 582}
 583
 584static int s626_write_trim_dac(struct comedi_device *dev,
 585                               uint8_t logical_chan, uint8_t dac_data)
 586{
 587        struct s626_private *devpriv = dev->private;
 588        uint32_t chan;
 589
 590        /*
 591         * Save the new setpoint in case the application needs to read it back
 592         * later.
 593         */
 594        devpriv->trim_setpoint[logical_chan] = (uint8_t)dac_data;
 595
 596        /* Map logical channel number to physical channel number. */
 597        chan = s626_trimchan[logical_chan];
 598
 599        /*
 600         * Set up TSL2 records for TrimDac write operation.  All slots shift
 601         * 0xFF in from pulled-up SD3 so that the end of the slot sequence
 602         * can be detected.
 603         */
 604
 605        /* Slot 2: Send high uint8_t to target TrimDac */
 606        writel(S626_XSD2 | S626_XFIFO_1 | S626_WS3,
 607               dev->mmio + S626_VECTPORT(2));
 608        /* Slot 3: Send low uint8_t to target TrimDac */
 609        writel(S626_XSD2 | S626_XFIFO_0 | S626_WS3,
 610               dev->mmio + S626_VECTPORT(3));
 611        /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
 612        writel(S626_XSD2 | S626_XFIFO_3 | S626_WS1,
 613               dev->mmio + S626_VECTPORT(4));
 614        /* Slot 5: Send NOP low  uint8_t to DAC0 */
 615        writel(S626_XSD2 | S626_XFIFO_2 | S626_WS1 | S626_EOS,
 616               dev->mmio + S626_VECTPORT(5));
 617
 618        /*
 619         * Construct and transmit target DAC's serial packet:
 620         * (0000 AAAA), (DDDD DDDD), (0x00), (0x00) where A<3:0> is the
 621         * DAC channel's address, and D<7:0> is the DAC setpoint.  Append a
 622         * WORD value (that writes a channel 0 NOP command to a non-existent
 623         * main DAC channel) that serves to keep the clock running after the
 624         * packet has been sent to the target DAC.
 625         */
 626
 627        /*
 628         * Address the DAC channel within the trimdac device.
 629         * Include DAC setpoint data.
 630         */
 631        return s626_send_dac(dev, (chan << 8) | dac_data);
 632}
 633
 634static int s626_load_trim_dacs(struct comedi_device *dev)
 635{
 636        uint8_t i;
 637        int ret;
 638
 639        /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
 640        for (i = 0; i < ARRAY_SIZE(s626_trimchan); i++) {
 641                ret = s626_write_trim_dac(dev, i,
 642                                          s626_i2c_read(dev, s626_trimadrs[i]));
 643                if (ret)
 644                        return ret;
 645        }
 646        return 0;
 647}
 648
 649/* ******  COUNTER FUNCTIONS  ******* */
 650
 651/*
 652 * All counter functions address a specific counter by means of the
 653 * "Counter" argument, which is a logical counter number.  The Counter
 654 * argument may have any of the following legal values: 0=0A, 1=1A,
 655 * 2=2A, 3=0B, 4=1B, 5=2B.
 656 */
 657
 658/*
 659 * Return/set a counter pair's latch trigger source.  0: On read
 660 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
 661 * latches B.
 662 */
 663static void s626_set_latch_source(struct comedi_device *dev,
 664                                  unsigned int chan, uint16_t value)
 665{
 666        s626_debi_replace(dev, S626_LP_CRB(chan),
 667                          ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_LATCHSRC),
 668                          S626_SET_CRB_LATCHSRC(value));
 669}
 670
 671/*
 672 * Write value into counter preload register.
 673 */
 674static void s626_preload(struct comedi_device *dev,
 675                         unsigned int chan, uint32_t value)
 676{
 677        s626_debi_write(dev, S626_LP_CNTR(chan), value);
 678        s626_debi_write(dev, S626_LP_CNTR(chan) + 2, value >> 16);
 679}
 680
 681/* ******  PRIVATE COUNTER FUNCTIONS ****** */
 682
 683/*
 684 * Reset a counter's index and overflow event capture flags.
 685 */
 686static void s626_reset_cap_flags(struct comedi_device *dev,
 687                                 unsigned int chan)
 688{
 689        uint16_t set;
 690
 691        set = S626_SET_CRB_INTRESETCMD(1);
 692        if (chan < 3)
 693                set |= S626_SET_CRB_INTRESET_A(1);
 694        else
 695                set |= S626_SET_CRB_INTRESET_B(1);
 696
 697        s626_debi_replace(dev, S626_LP_CRB(chan), ~S626_CRBMSK_INTCTRL, set);
 698}
 699
 700#ifdef unused
 701/*
 702 * Return counter setup in a format (COUNTER_SETUP) that is consistent
 703 * for both A and B counters.
 704 */
 705static uint16_t s626_get_mode_a(struct comedi_device *dev,
 706                                unsigned int chan)
 707{
 708        uint16_t cra;
 709        uint16_t crb;
 710        uint16_t setup;
 711        unsigned cntsrc, clkmult, clkpol, encmode;
 712
 713        /* Fetch CRA and CRB register images. */
 714        cra = s626_debi_read(dev, S626_LP_CRA(chan));
 715        crb = s626_debi_read(dev, S626_LP_CRB(chan));
 716
 717        /*
 718         * Populate the standardized counter setup bit fields.
 719         */
 720        setup =
 721                /* LoadSrc  = LoadSrcA. */
 722                S626_SET_STD_LOADSRC(S626_GET_CRA_LOADSRC_A(cra)) |
 723                /* LatchSrc = LatchSrcA. */
 724                S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
 725                /* IntSrc   = IntSrcA. */
 726                S626_SET_STD_INTSRC(S626_GET_CRA_INTSRC_A(cra)) |
 727                /* IndxSrc  = IndxSrcA. */
 728                S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_A(cra)) |
 729                /* IndxPol  = IndxPolA. */
 730                S626_SET_STD_INDXPOL(S626_GET_CRA_INDXPOL_A(cra)) |
 731                /* ClkEnab  = ClkEnabA. */
 732                S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_A(crb));
 733
 734        /* Adjust mode-dependent parameters. */
 735        cntsrc = S626_GET_CRA_CNTSRC_A(cra);
 736        if (cntsrc & S626_CNTSRC_SYSCLK) {
 737                /* Timer mode (CntSrcA<1> == 1): */
 738                encmode = S626_ENCMODE_TIMER;
 739                /* Set ClkPol to indicate count direction (CntSrcA<0>). */
 740                clkpol = cntsrc & 1;
 741                /* ClkMult must be 1x in Timer mode. */
 742                clkmult = S626_CLKMULT_1X;
 743        } else {
 744                /* Counter mode (CntSrcA<1> == 0): */
 745                encmode = S626_ENCMODE_COUNTER;
 746                /* Pass through ClkPol. */
 747                clkpol = S626_GET_CRA_CLKPOL_A(cra);
 748                /* Force ClkMult to 1x if not legal, else pass through. */
 749                clkmult = S626_GET_CRA_CLKMULT_A(cra);
 750                if (clkmult == S626_CLKMULT_SPECIAL)
 751                        clkmult = S626_CLKMULT_1X;
 752        }
 753        setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
 754                 S626_SET_STD_CLKPOL(clkpol);
 755
 756        /* Return adjusted counter setup. */
 757        return setup;
 758}
 759
 760static uint16_t s626_get_mode_b(struct comedi_device *dev,
 761                                unsigned int chan)
 762{
 763        uint16_t cra;
 764        uint16_t crb;
 765        uint16_t setup;
 766        unsigned cntsrc, clkmult, clkpol, encmode;
 767
 768        /* Fetch CRA and CRB register images. */
 769        cra = s626_debi_read(dev, S626_LP_CRA(chan));
 770        crb = s626_debi_read(dev, S626_LP_CRB(chan));
 771
 772        /*
 773         * Populate the standardized counter setup bit fields.
 774         */
 775        setup =
 776                /* IntSrc   = IntSrcB. */
 777                S626_SET_STD_INTSRC(S626_GET_CRB_INTSRC_B(crb)) |
 778                /* LatchSrc = LatchSrcB. */
 779                S626_SET_STD_LATCHSRC(S626_GET_CRB_LATCHSRC(crb)) |
 780                /* LoadSrc  = LoadSrcB. */
 781                S626_SET_STD_LOADSRC(S626_GET_CRB_LOADSRC_B(crb)) |
 782                /* IndxPol  = IndxPolB. */
 783                S626_SET_STD_INDXPOL(S626_GET_CRB_INDXPOL_B(crb)) |
 784                /* ClkEnab  = ClkEnabB. */
 785                S626_SET_STD_CLKENAB(S626_GET_CRB_CLKENAB_B(crb)) |
 786                /* IndxSrc  = IndxSrcB. */
 787                S626_SET_STD_INDXSRC(S626_GET_CRA_INDXSRC_B(cra));
 788
 789        /* Adjust mode-dependent parameters. */
 790        cntsrc = S626_GET_CRA_CNTSRC_B(cra);
 791        clkmult = S626_GET_CRB_CLKMULT_B(crb);
 792        if (clkmult == S626_CLKMULT_SPECIAL) {
 793                /* Extender mode (ClkMultB == S626_CLKMULT_SPECIAL): */
 794                encmode = S626_ENCMODE_EXTENDER;
 795                /* Indicate multiplier is 1x. */
 796                clkmult = S626_CLKMULT_1X;
 797                /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
 798                clkpol = cntsrc & 1;
 799        } else if (cntsrc & S626_CNTSRC_SYSCLK) {
 800                /* Timer mode (CntSrcB<1> == 1): */
 801                encmode = S626_ENCMODE_TIMER;
 802                /* Indicate multiplier is 1x. */
 803                clkmult = S626_CLKMULT_1X;
 804                /* Set ClkPol equal to Timer count direction (CntSrcB<0>). */
 805                clkpol = cntsrc & 1;
 806        } else {
 807                /* If Counter mode (CntSrcB<1> == 0): */
 808                encmode = S626_ENCMODE_COUNTER;
 809                /* Clock multiplier is passed through. */
 810                /* Clock polarity is passed through. */
 811                clkpol = S626_GET_CRB_CLKPOL_B(crb);
 812        }
 813        setup |= S626_SET_STD_ENCMODE(encmode) | S626_SET_STD_CLKMULT(clkmult) |
 814                 S626_SET_STD_CLKPOL(clkpol);
 815
 816        /* Return adjusted counter setup. */
 817        return setup;
 818}
 819
 820static uint16_t s626_get_mode(struct comedi_device *dev,
 821                              unsigned int chan)
 822{
 823        return (chan < 3) ? s626_get_mode_a(dev, chan)
 824                          : s626_get_mode_b(dev, chan);
 825}
 826#endif
 827
 828/*
 829 * Set the operating mode for the specified counter.  The setup
 830 * parameter is treated as a COUNTER_SETUP data type.  The following
 831 * parameters are programmable (all other parms are ignored): ClkMult,
 832 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
 833 */
 834static void s626_set_mode_a(struct comedi_device *dev,
 835                            unsigned int chan, uint16_t setup,
 836                            uint16_t disable_int_src)
 837{
 838        struct s626_private *devpriv = dev->private;
 839        uint16_t cra;
 840        uint16_t crb;
 841        unsigned cntsrc, clkmult, clkpol;
 842
 843        /* Initialize CRA and CRB images. */
 844        /* Preload trigger is passed through. */
 845        cra = S626_SET_CRA_LOADSRC_A(S626_GET_STD_LOADSRC(setup));
 846        /* IndexSrc is passed through. */
 847        cra |= S626_SET_CRA_INDXSRC_A(S626_GET_STD_INDXSRC(setup));
 848
 849        /* Reset any pending CounterA event captures. */
 850        crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_A(1);
 851        /* Clock enable is passed through. */
 852        crb |= S626_SET_CRB_CLKENAB_A(S626_GET_STD_CLKENAB(setup));
 853
 854        /* Force IntSrc to Disabled if disable_int_src is asserted. */
 855        if (!disable_int_src)
 856                cra |= S626_SET_CRA_INTSRC_A(S626_GET_STD_INTSRC(setup));
 857
 858        /* Populate all mode-dependent attributes of CRA & CRB images. */
 859        clkpol = S626_GET_STD_CLKPOL(setup);
 860        switch (S626_GET_STD_ENCMODE(setup)) {
 861        case S626_ENCMODE_EXTENDER: /* Extender Mode: */
 862                /* Force to Timer mode (Extender valid only for B counters). */
 863                /* Fall through to case S626_ENCMODE_TIMER: */
 864        case S626_ENCMODE_TIMER:        /* Timer Mode: */
 865                /* CntSrcA<1> selects system clock */
 866                cntsrc = S626_CNTSRC_SYSCLK;
 867                /* Count direction (CntSrcA<0>) obtained from ClkPol. */
 868                cntsrc |= clkpol;
 869                /* ClkPolA behaves as always-on clock enable. */
 870                clkpol = 1;
 871                /* ClkMult must be 1x. */
 872                clkmult = S626_CLKMULT_1X;
 873                break;
 874        default:                /* Counter Mode: */
 875                /* Select ENC_C and ENC_D as clock/direction inputs. */
 876                cntsrc = S626_CNTSRC_ENCODER;
 877                /* Clock polarity is passed through. */
 878                /* Force multiplier to x1 if not legal, else pass through. */
 879                clkmult = S626_GET_STD_CLKMULT(setup);
 880                if (clkmult == S626_CLKMULT_SPECIAL)
 881                        clkmult = S626_CLKMULT_1X;
 882                break;
 883        }
 884        cra |= S626_SET_CRA_CNTSRC_A(cntsrc) | S626_SET_CRA_CLKPOL_A(clkpol) |
 885               S626_SET_CRA_CLKMULT_A(clkmult);
 886
 887        /*
 888         * Force positive index polarity if IndxSrc is software-driven only,
 889         * otherwise pass it through.
 890         */
 891        if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
 892                cra |= S626_SET_CRA_INDXPOL_A(S626_GET_STD_INDXPOL(setup));
 893
 894        /*
 895         * If IntSrc has been forced to Disabled, update the MISC2 interrupt
 896         * enable mask to indicate the counter interrupt is disabled.
 897         */
 898        if (disable_int_src)
 899                devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
 900                                                S626_INDXMASK(chan));
 901
 902        /*
 903         * While retaining CounterB and LatchSrc configurations, program the
 904         * new counter operating mode.
 905         */
 906        s626_debi_replace(dev, S626_LP_CRA(chan),
 907                          S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B, cra);
 908        s626_debi_replace(dev, S626_LP_CRB(chan),
 909                          ~(S626_CRBMSK_INTCTRL | S626_CRBMSK_CLKENAB_A), crb);
 910}
 911
 912static void s626_set_mode_b(struct comedi_device *dev,
 913                            unsigned int chan, uint16_t setup,
 914                            uint16_t disable_int_src)
 915{
 916        struct s626_private *devpriv = dev->private;
 917        uint16_t cra;
 918        uint16_t crb;
 919        unsigned cntsrc, clkmult, clkpol;
 920
 921        /* Initialize CRA and CRB images. */
 922        /* IndexSrc is passed through. */
 923        cra = S626_SET_CRA_INDXSRC_B(S626_GET_STD_INDXSRC(setup));
 924
 925        /* Reset event captures and disable interrupts. */
 926        crb = S626_SET_CRB_INTRESETCMD(1) | S626_SET_CRB_INTRESET_B(1);
 927        /* Clock enable is passed through. */
 928        crb |= S626_SET_CRB_CLKENAB_B(S626_GET_STD_CLKENAB(setup));
 929        /* Preload trigger source is passed through. */
 930        crb |= S626_SET_CRB_LOADSRC_B(S626_GET_STD_LOADSRC(setup));
 931
 932        /* Force IntSrc to Disabled if disable_int_src is asserted. */
 933        if (!disable_int_src)
 934                crb |= S626_SET_CRB_INTSRC_B(S626_GET_STD_INTSRC(setup));
 935
 936        /* Populate all mode-dependent attributes of CRA & CRB images. */
 937        clkpol = S626_GET_STD_CLKPOL(setup);
 938        switch (S626_GET_STD_ENCMODE(setup)) {
 939        case S626_ENCMODE_TIMER:        /* Timer Mode: */
 940                /* CntSrcB<1> selects system clock */
 941                cntsrc = S626_CNTSRC_SYSCLK;
 942                /* with direction (CntSrcB<0>) obtained from ClkPol. */
 943                cntsrc |= clkpol;
 944                /* ClkPolB behaves as always-on clock enable. */
 945                clkpol = 1;
 946                /* ClkMultB must be 1x. */
 947                clkmult = S626_CLKMULT_1X;
 948                break;
 949        case S626_ENCMODE_EXTENDER:     /* Extender Mode: */
 950                /* CntSrcB source is OverflowA (same as "timer") */
 951                cntsrc = S626_CNTSRC_SYSCLK;
 952                /* with direction obtained from ClkPol. */
 953                cntsrc |= clkpol;
 954                /* ClkPolB controls IndexB -- always set to active. */
 955                clkpol = 1;
 956                /* ClkMultB selects OverflowA as the clock source. */
 957                clkmult = S626_CLKMULT_SPECIAL;
 958                break;
 959        default:                /* Counter Mode: */
 960                /* Select ENC_C and ENC_D as clock/direction inputs. */
 961                cntsrc = S626_CNTSRC_ENCODER;
 962                /* ClkPol is passed through. */
 963                /* Force ClkMult to x1 if not legal, otherwise pass through. */
 964                clkmult = S626_GET_STD_CLKMULT(setup);
 965                if (clkmult == S626_CLKMULT_SPECIAL)
 966                        clkmult = S626_CLKMULT_1X;
 967                break;
 968        }
 969        cra |= S626_SET_CRA_CNTSRC_B(cntsrc);
 970        crb |= S626_SET_CRB_CLKPOL_B(clkpol) | S626_SET_CRB_CLKMULT_B(clkmult);
 971
 972        /*
 973         * Force positive index polarity if IndxSrc is software-driven only,
 974         * otherwise pass it through.
 975         */
 976        if (S626_GET_STD_INDXSRC(setup) != S626_INDXSRC_SOFT)
 977                crb |= S626_SET_CRB_INDXPOL_B(S626_GET_STD_INDXPOL(setup));
 978
 979        /*
 980         * If IntSrc has been forced to Disabled, update the MISC2 interrupt
 981         * enable mask to indicate the counter interrupt is disabled.
 982         */
 983        if (disable_int_src)
 984                devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
 985                                                S626_INDXMASK(chan));
 986
 987        /*
 988         * While retaining CounterA and LatchSrc configurations, program the
 989         * new counter operating mode.
 990         */
 991        s626_debi_replace(dev, S626_LP_CRA(chan),
 992                          ~(S626_CRAMSK_INDXSRC_B | S626_CRAMSK_CNTSRC_B), cra);
 993        s626_debi_replace(dev, S626_LP_CRB(chan),
 994                          S626_CRBMSK_CLKENAB_A | S626_CRBMSK_LATCHSRC, crb);
 995}
 996
 997static void s626_set_mode(struct comedi_device *dev,
 998                          unsigned int chan,
 999                          uint16_t setup, uint16_t disable_int_src)
1000{
1001        if (chan < 3)
1002                s626_set_mode_a(dev, chan, setup, disable_int_src);
1003        else
1004                s626_set_mode_b(dev, chan, setup, disable_int_src);
1005}
1006
1007/*
1008 * Return/set a counter's enable.  enab: 0=always enabled, 1=enabled by index.
1009 */
1010static void s626_set_enable(struct comedi_device *dev,
1011                            unsigned int chan, uint16_t enab)
1012{
1013        unsigned int mask = S626_CRBMSK_INTCTRL;
1014        unsigned int set;
1015
1016        if (chan < 3) {
1017                mask |= S626_CRBMSK_CLKENAB_A;
1018                set = S626_SET_CRB_CLKENAB_A(enab);
1019        } else {
1020                mask |= S626_CRBMSK_CLKENAB_B;
1021                set = S626_SET_CRB_CLKENAB_B(enab);
1022        }
1023        s626_debi_replace(dev, S626_LP_CRB(chan), ~mask, set);
1024}
1025
1026#ifdef unused
1027static uint16_t s626_get_enable(struct comedi_device *dev,
1028                                unsigned int chan)
1029{
1030        uint16_t crb = s626_debi_read(dev, S626_LP_CRB(chan));
1031
1032        return (chan < 3) ? S626_GET_CRB_CLKENAB_A(crb)
1033                          : S626_GET_CRB_CLKENAB_B(crb);
1034}
1035#endif
1036
1037#ifdef unused
1038static uint16_t s626_get_latch_source(struct comedi_device *dev,
1039                                      unsigned int chan)
1040{
1041        return S626_GET_CRB_LATCHSRC(s626_debi_read(dev, S626_LP_CRB(chan)));
1042}
1043#endif
1044
1045/*
1046 * Return/set the event that will trigger transfer of the preload
1047 * register into the counter.  0=ThisCntr_Index, 1=ThisCntr_Overflow,
1048 * 2=OverflowA (B counters only), 3=disabled.
1049 */
1050static void s626_set_load_trig(struct comedi_device *dev,
1051                               unsigned int chan, uint16_t trig)
1052{
1053        uint16_t reg;
1054        uint16_t mask;
1055        uint16_t set;
1056
1057        if (chan < 3) {
1058                reg = S626_LP_CRA(chan);
1059                mask = S626_CRAMSK_LOADSRC_A;
1060                set = S626_SET_CRA_LOADSRC_A(trig);
1061        } else {
1062                reg = S626_LP_CRB(chan);
1063                mask = S626_CRBMSK_LOADSRC_B | S626_CRBMSK_INTCTRL;
1064                set = S626_SET_CRB_LOADSRC_B(trig);
1065        }
1066        s626_debi_replace(dev, reg, ~mask, set);
1067}
1068
1069#ifdef unused
1070static uint16_t s626_get_load_trig(struct comedi_device *dev,
1071                                   unsigned int chan)
1072{
1073        if (chan < 3)
1074                return S626_GET_CRA_LOADSRC_A(s626_debi_read(dev,
1075                                                        S626_LP_CRA(chan)));
1076        else
1077                return S626_GET_CRB_LOADSRC_B(s626_debi_read(dev,
1078                                                        S626_LP_CRB(chan)));
1079}
1080#endif
1081
1082/*
1083 * Return/set counter interrupt source and clear any captured
1084 * index/overflow events.  int_source: 0=Disabled, 1=OverflowOnly,
1085 * 2=IndexOnly, 3=IndexAndOverflow.
1086 */
1087static void s626_set_int_src(struct comedi_device *dev,
1088                             unsigned int chan, uint16_t int_source)
1089{
1090        struct s626_private *devpriv = dev->private;
1091        uint16_t cra_reg = S626_LP_CRA(chan);
1092        uint16_t crb_reg = S626_LP_CRB(chan);
1093
1094        if (chan < 3) {
1095                /* Reset any pending counter overflow or index captures */
1096                s626_debi_replace(dev, crb_reg, ~S626_CRBMSK_INTCTRL,
1097                                  S626_SET_CRB_INTRESETCMD(1) |
1098                                  S626_SET_CRB_INTRESET_A(1));
1099
1100                /* Program counter interrupt source */
1101                s626_debi_replace(dev, cra_reg, ~S626_CRAMSK_INTSRC_A,
1102                                  S626_SET_CRA_INTSRC_A(int_source));
1103        } else {
1104                uint16_t crb;
1105
1106                /* Cache writeable CRB register image */
1107                crb = s626_debi_read(dev, crb_reg);
1108                crb &= ~S626_CRBMSK_INTCTRL;
1109
1110                /* Reset any pending counter overflow or index captures */
1111                s626_debi_write(dev, crb_reg,
1112                                crb | S626_SET_CRB_INTRESETCMD(1) |
1113                                S626_SET_CRB_INTRESET_B(1));
1114
1115                /* Program counter interrupt source */
1116                s626_debi_write(dev, crb_reg,
1117                                (crb & ~S626_CRBMSK_INTSRC_B) |
1118                                S626_SET_CRB_INTSRC_B(int_source));
1119        }
1120
1121        /* Update MISC2 interrupt enable mask. */
1122        devpriv->counter_int_enabs &= ~(S626_OVERMASK(chan) |
1123                                        S626_INDXMASK(chan));
1124        switch (int_source) {
1125        case 0:
1126        default:
1127                break;
1128        case 1:
1129                devpriv->counter_int_enabs |= S626_OVERMASK(chan);
1130                break;
1131        case 2:
1132                devpriv->counter_int_enabs |= S626_INDXMASK(chan);
1133                break;
1134        case 3:
1135                devpriv->counter_int_enabs |= (S626_OVERMASK(chan) |
1136                                               S626_INDXMASK(chan));
1137                break;
1138        }
1139}
1140
1141#ifdef unused
1142static uint16_t s626_get_int_src(struct comedi_device *dev,
1143                                 unsigned int chan)
1144{
1145        if (chan < 3)
1146                return S626_GET_CRA_INTSRC_A(s626_debi_read(dev,
1147                                                        S626_LP_CRA(chan)));
1148        else
1149                return S626_GET_CRB_INTSRC_B(s626_debi_read(dev,
1150                                                        S626_LP_CRB(chan)));
1151}
1152#endif
1153
1154#ifdef unused
1155/*
1156 * Return/set the clock multiplier.
1157 */
1158static void s626_set_clk_mult(struct comedi_device *dev,
1159                              unsigned int chan, uint16_t value)
1160{
1161        uint16_t mode;
1162
1163        mode = s626_get_mode(dev, chan);
1164        mode &= ~S626_STDMSK_CLKMULT;
1165        mode |= S626_SET_STD_CLKMULT(value);
1166
1167        s626_set_mode(dev, chan, mode, false);
1168}
1169
1170/*
1171 * Return/set the clock polarity.
1172 */
1173static void s626_set_clk_pol(struct comedi_device *dev,
1174                             unsigned int chan, uint16_t value)
1175{
1176        uint16_t mode;
1177
1178        mode = s626_get_mode(dev, chan);
1179        mode &= ~S626_STDMSK_CLKPOL;
1180        mode |= S626_SET_STD_CLKPOL(value);
1181
1182        s626_set_mode(dev, chan, mode, false);
1183}
1184
1185/*
1186 * Return/set the encoder mode.
1187 */
1188static void s626_set_enc_mode(struct comedi_device *dev,
1189                              unsigned int chan, uint16_t value)
1190{
1191        uint16_t mode;
1192
1193        mode = s626_get_mode(dev, chan);
1194        mode &= ~S626_STDMSK_ENCMODE;
1195        mode |= S626_SET_STD_ENCMODE(value);
1196
1197        s626_set_mode(dev, chan, mode, false);
1198}
1199
1200static uint16_t s626_get_index_pol(struct comedi_device *dev,
1201                                   unsigned int chan)
1202{
1203        return S626_GET_STD_INDXPOL(s626_get_mode(dev, chan));
1204}
1205
1206/*
1207 * Return/set the index source.
1208 */
1209static void s626_set_index_src(struct comedi_device *dev,
1210                               unsigned int chan, uint16_t value)
1211{
1212        uint16_t mode;
1213
1214        mode = s626_get_mode(dev, chan);
1215        mode &= ~S626_STDMSK_INDXSRC;
1216        mode |= S626_SET_STD_INDXSRC(value != 0);
1217
1218        s626_set_mode(dev, chan, mode, false);
1219}
1220
1221static uint16_t s626_get_index_src(struct comedi_device *dev,
1222                                   unsigned int chan)
1223{
1224        return S626_GET_STD_INDXSRC(s626_get_mode(dev, chan));
1225}
1226#endif
1227
1228/*
1229 * Generate an index pulse.
1230 */
1231static void s626_pulse_index(struct comedi_device *dev,
1232                             unsigned int chan)
1233{
1234        if (chan < 3) {
1235                uint16_t cra;
1236
1237                cra = s626_debi_read(dev, S626_LP_CRA(chan));
1238
1239                /* Pulse index */
1240                s626_debi_write(dev, S626_LP_CRA(chan),
1241                                (cra ^ S626_CRAMSK_INDXPOL_A));
1242                s626_debi_write(dev, S626_LP_CRA(chan), cra);
1243        } else {
1244                uint16_t crb;
1245
1246                crb = s626_debi_read(dev, S626_LP_CRB(chan));
1247                crb &= ~S626_CRBMSK_INTCTRL;
1248
1249                /* Pulse index */
1250                s626_debi_write(dev, S626_LP_CRB(chan),
1251                                (crb ^ S626_CRBMSK_INDXPOL_B));
1252                s626_debi_write(dev, S626_LP_CRB(chan), crb);
1253        }
1254}
1255
1256static unsigned int s626_ai_reg_to_uint(unsigned int data)
1257{
1258        return ((data >> 18) & 0x3fff) ^ 0x2000;
1259}
1260
1261static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
1262{
1263        unsigned int group = chan / 16;
1264        unsigned int mask = 1 << (chan - (16 * group));
1265        unsigned int status;
1266
1267        /* set channel to capture positive edge */
1268        status = s626_debi_read(dev, S626_LP_RDEDGSEL(group));
1269        s626_debi_write(dev, S626_LP_WREDGSEL(group), mask | status);
1270
1271        /* enable interrupt on selected channel */
1272        status = s626_debi_read(dev, S626_LP_RDINTSEL(group));
1273        s626_debi_write(dev, S626_LP_WRINTSEL(group), mask | status);
1274
1275        /* enable edge capture write command */
1276        s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_EDCAP);
1277
1278        /* enable edge capture on selected channel */
1279        status = s626_debi_read(dev, S626_LP_RDCAPSEL(group));
1280        s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask | status);
1281
1282        return 0;
1283}
1284
1285static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
1286                              unsigned int mask)
1287{
1288        /* disable edge capture write command */
1289        s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1290
1291        /* enable edge capture on selected channel */
1292        s626_debi_write(dev, S626_LP_WRCAPSEL(group), mask);
1293
1294        return 0;
1295}
1296
1297static int s626_dio_clear_irq(struct comedi_device *dev)
1298{
1299        unsigned int group;
1300
1301        /* disable edge capture write command */
1302        s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
1303
1304        /* clear all dio pending events and interrupt */
1305        for (group = 0; group < S626_DIO_BANKS; group++)
1306                s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
1307
1308        return 0;
1309}
1310
1311static void s626_handle_dio_interrupt(struct comedi_device *dev,
1312                                      uint16_t irqbit, uint8_t group)
1313{
1314        struct s626_private *devpriv = dev->private;
1315        struct comedi_subdevice *s = dev->read_subdev;
1316        struct comedi_cmd *cmd = &s->async->cmd;
1317
1318        s626_dio_reset_irq(dev, group, irqbit);
1319
1320        if (devpriv->ai_cmd_running) {
1321                /* check if interrupt is an ai acquisition start trigger */
1322                if ((irqbit >> (cmd->start_arg - (16 * group))) == 1 &&
1323                    cmd->start_src == TRIG_EXT) {
1324                        /* Start executing the RPS program */
1325                        s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1326
1327                        if (cmd->scan_begin_src == TRIG_EXT)
1328                                s626_dio_set_irq(dev, cmd->scan_begin_arg);
1329                }
1330                if ((irqbit >> (cmd->scan_begin_arg - (16 * group))) == 1 &&
1331                    cmd->scan_begin_src == TRIG_EXT) {
1332                        /* Trigger ADC scan loop start */
1333                        s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1334
1335                        if (cmd->convert_src == TRIG_EXT) {
1336                                devpriv->ai_convert_count = cmd->chanlist_len;
1337
1338                                s626_dio_set_irq(dev, cmd->convert_arg);
1339                        }
1340
1341                        if (cmd->convert_src == TRIG_TIMER) {
1342                                devpriv->ai_convert_count = cmd->chanlist_len;
1343                                s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
1344                        }
1345                }
1346                if ((irqbit >> (cmd->convert_arg - (16 * group))) == 1 &&
1347                    cmd->convert_src == TRIG_EXT) {
1348                        /* Trigger ADC scan loop start */
1349                        s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1350
1351                        devpriv->ai_convert_count--;
1352                        if (devpriv->ai_convert_count > 0)
1353                                s626_dio_set_irq(dev, cmd->convert_arg);
1354                }
1355        }
1356}
1357
1358static void s626_check_dio_interrupts(struct comedi_device *dev)
1359{
1360        uint16_t irqbit;
1361        uint8_t group;
1362
1363        for (group = 0; group < S626_DIO_BANKS; group++) {
1364                /* read interrupt type */
1365                irqbit = s626_debi_read(dev, S626_LP_RDCAPFLG(group));
1366
1367                /* check if interrupt is generated from dio channels */
1368                if (irqbit) {
1369                        s626_handle_dio_interrupt(dev, irqbit, group);
1370                        return;
1371                }
1372        }
1373}
1374
1375static void s626_check_counter_interrupts(struct comedi_device *dev)
1376{
1377        struct s626_private *devpriv = dev->private;
1378        struct comedi_subdevice *s = dev->read_subdev;
1379        struct comedi_async *async = s->async;
1380        struct comedi_cmd *cmd = &async->cmd;
1381        uint16_t irqbit;
1382
1383        /* read interrupt type */
1384        irqbit = s626_debi_read(dev, S626_LP_RDMISC2);
1385
1386        /* check interrupt on counters */
1387        if (irqbit & S626_IRQ_COINT1A) {
1388                /* clear interrupt capture flag */
1389                s626_reset_cap_flags(dev, 0);
1390        }
1391        if (irqbit & S626_IRQ_COINT2A) {
1392                /* clear interrupt capture flag */
1393                s626_reset_cap_flags(dev, 1);
1394        }
1395        if (irqbit & S626_IRQ_COINT3A) {
1396                /* clear interrupt capture flag */
1397                s626_reset_cap_flags(dev, 2);
1398        }
1399        if (irqbit & S626_IRQ_COINT1B) {
1400                /* clear interrupt capture flag */
1401                s626_reset_cap_flags(dev, 3);
1402        }
1403        if (irqbit & S626_IRQ_COINT2B) {
1404                /* clear interrupt capture flag */
1405                s626_reset_cap_flags(dev, 4);
1406
1407                if (devpriv->ai_convert_count > 0) {
1408                        devpriv->ai_convert_count--;
1409                        if (devpriv->ai_convert_count == 0)
1410                                s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
1411
1412                        if (cmd->convert_src == TRIG_TIMER) {
1413                                /* Trigger ADC scan loop start */
1414                                s626_mc_enable(dev, S626_MC2_ADC_RPS,
1415                                               S626_P_MC2);
1416                        }
1417                }
1418        }
1419        if (irqbit & S626_IRQ_COINT3B) {
1420                /* clear interrupt capture flag */
1421                s626_reset_cap_flags(dev, 5);
1422
1423                if (cmd->scan_begin_src == TRIG_TIMER) {
1424                        /* Trigger ADC scan loop start */
1425                        s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1426                }
1427
1428                if (cmd->convert_src == TRIG_TIMER) {
1429                        devpriv->ai_convert_count = cmd->chanlist_len;
1430                        s626_set_enable(dev, 4, S626_CLKENAB_ALWAYS);
1431                }
1432        }
1433}
1434
1435static bool s626_handle_eos_interrupt(struct comedi_device *dev)
1436{
1437        struct s626_private *devpriv = dev->private;
1438        struct comedi_subdevice *s = dev->read_subdev;
1439        struct comedi_async *async = s->async;
1440        struct comedi_cmd *cmd = &async->cmd;
1441        /*
1442         * Init ptr to DMA buffer that holds new ADC data.  We skip the
1443         * first uint16_t in the buffer because it contains junk data
1444         * from the final ADC of the previous poll list scan.
1445         */
1446        uint32_t *readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1447        int i;
1448
1449        /* get the data and hand it over to comedi */
1450        for (i = 0; i < cmd->chanlist_len; i++) {
1451                unsigned short tempdata;
1452
1453                /*
1454                 * Convert ADC data to 16-bit integer values and copy
1455                 * to application buffer.
1456                 */
1457                tempdata = s626_ai_reg_to_uint(*readaddr);
1458                readaddr++;
1459
1460                comedi_buf_write_samples(s, &tempdata, 1);
1461        }
1462
1463        if (cmd->stop_src == TRIG_COUNT && async->scans_done >= cmd->stop_arg)
1464                async->events |= COMEDI_CB_EOA;
1465
1466        if (async->events & COMEDI_CB_CANCEL_MASK)
1467                devpriv->ai_cmd_running = 0;
1468
1469        if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT)
1470                s626_dio_set_irq(dev, cmd->scan_begin_arg);
1471
1472        comedi_handle_events(dev, s);
1473
1474        return !devpriv->ai_cmd_running;
1475}
1476
1477static irqreturn_t s626_irq_handler(int irq, void *d)
1478{
1479        struct comedi_device *dev = d;
1480        unsigned long flags;
1481        uint32_t irqtype, irqstatus;
1482
1483        if (!dev->attached)
1484                return IRQ_NONE;
1485        /* lock to avoid race with comedi_poll */
1486        spin_lock_irqsave(&dev->spinlock, flags);
1487
1488        /* save interrupt enable register state */
1489        irqstatus = readl(dev->mmio + S626_P_IER);
1490
1491        /* read interrupt type */
1492        irqtype = readl(dev->mmio + S626_P_ISR);
1493
1494        /* disable master interrupt */
1495        writel(0, dev->mmio + S626_P_IER);
1496
1497        /* clear interrupt */
1498        writel(irqtype, dev->mmio + S626_P_ISR);
1499
1500        switch (irqtype) {
1501        case S626_IRQ_RPS1:     /* end_of_scan occurs */
1502                if (s626_handle_eos_interrupt(dev))
1503                        irqstatus = 0;
1504                break;
1505        case S626_IRQ_GPIO3:    /* check dio and counter interrupt */
1506                /* s626_dio_clear_irq(dev); */
1507                s626_check_dio_interrupts(dev);
1508                s626_check_counter_interrupts(dev);
1509                break;
1510        }
1511
1512        /* enable interrupt */
1513        writel(irqstatus, dev->mmio + S626_P_IER);
1514
1515        spin_unlock_irqrestore(&dev->spinlock, flags);
1516        return IRQ_HANDLED;
1517}
1518
1519/*
1520 * This function builds the RPS program for hardware driven acquisition.
1521 */
1522static void s626_reset_adc(struct comedi_device *dev, uint8_t *ppl)
1523{
1524        struct s626_private *devpriv = dev->private;
1525        struct comedi_subdevice *s = dev->read_subdev;
1526        struct comedi_cmd *cmd = &s->async->cmd;
1527        uint32_t *rps;
1528        uint32_t jmp_adrs;
1529        uint16_t i;
1530        uint16_t n;
1531        uint32_t local_ppl;
1532
1533        /* Stop RPS program in case it is currently running */
1534        s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
1535
1536        /* Set starting logical address to write RPS commands. */
1537        rps = (uint32_t *)devpriv->rps_buf.logical_base;
1538
1539        /* Initialize RPS instruction pointer */
1540        writel((uint32_t)devpriv->rps_buf.physical_base,
1541               dev->mmio + S626_P_RPSADDR1);
1542
1543        /* Construct RPS program in rps_buf DMA buffer */
1544        if (cmd->scan_begin_src != TRIG_FOLLOW) {
1545                /* Wait for Start trigger. */
1546                *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1547                *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1548        }
1549
1550        /*
1551         * SAA7146 BUG WORKAROUND Do a dummy DEBI Write.  This is necessary
1552         * because the first RPS DEBI Write following a non-RPS DEBI write
1553         * seems to always fail.  If we don't do this dummy write, the ADC
1554         * gain might not be set to the value required for the first slot in
1555         * the poll list; the ADC gain would instead remain unchanged from
1556         * the previously programmed value.
1557         */
1558        /* Write DEBI Write command and address to shadow RAM. */
1559        *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1560        *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1561        *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1562        /* Write DEBI immediate data  to shadow RAM: */
1563        *rps++ = S626_GSEL_BIPOLAR5V;   /* arbitrary immediate data  value. */
1564        *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1565        /* Reset "shadow RAM  uploaded" flag. */
1566        /* Invoke shadow RAM upload. */
1567        *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1568        /* Wait for shadow upload to finish. */
1569        *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1570
1571        /*
1572         * Digitize all slots in the poll list. This is implemented as a
1573         * for loop to limit the slot count to 16 in case the application
1574         * forgot to set the S626_EOPL flag in the final slot.
1575         */
1576        for (devpriv->adc_items = 0; devpriv->adc_items < 16;
1577             devpriv->adc_items++) {
1578                /*
1579                 * Convert application's poll list item to private board class
1580                 * format.  Each app poll list item is an uint8_t with form
1581                 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1582                 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1583                 */
1584                local_ppl = (*ppl << 8) | (*ppl & 0x10 ? S626_GSEL_BIPOLAR5V :
1585                                           S626_GSEL_BIPOLAR10V);
1586
1587                /* Switch ADC analog gain. */
1588                /* Write DEBI command and address to shadow RAM. */
1589                *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1590                *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_GSEL;
1591                /* Write DEBI immediate data to shadow RAM. */
1592                *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1593                *rps++ = local_ppl;
1594                /* Reset "shadow RAM uploaded" flag. */
1595                *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1596                /* Invoke shadow RAM upload. */
1597                *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1598                /* Wait for shadow upload to finish. */
1599                *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1600                /* Select ADC analog input channel. */
1601                *rps++ = S626_RPS_LDREG | (S626_P_DEBICMD >> 2);
1602                /* Write DEBI command and address to shadow RAM. */
1603                *rps++ = S626_DEBI_CMD_WRWORD | S626_LP_ISEL;
1604                *rps++ = S626_RPS_LDREG | (S626_P_DEBIAD >> 2);
1605                /* Write DEBI immediate data to shadow RAM. */
1606                *rps++ = local_ppl;
1607                /* Reset "shadow RAM uploaded" flag. */
1608                *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_DEBI;
1609                /* Invoke shadow RAM upload. */
1610                *rps++ = S626_RPS_UPLOAD | S626_RPS_DEBI;
1611                /* Wait for shadow upload to finish. */
1612                *rps++ = S626_RPS_PAUSE | S626_RPS_DEBI;
1613
1614                /*
1615                 * Delay at least 10 microseconds for analog input settling.
1616                 * Instead of padding with NOPs, we use S626_RPS_JUMP
1617                 * instructions here; this allows us to produce a longer delay
1618                 * than is possible with NOPs because each S626_RPS_JUMP
1619                 * flushes the RPS' instruction prefetch pipeline.
1620                 */
1621                jmp_adrs =
1622                        (uint32_t)devpriv->rps_buf.physical_base +
1623                        (uint32_t)((unsigned long)rps -
1624                                   (unsigned long)devpriv->
1625                                                  rps_buf.logical_base);
1626                for (i = 0; i < (10 * S626_RPSCLK_PER_US / 2); i++) {
1627                        jmp_adrs += 8;  /* Repeat to implement time delay: */
1628                        /* Jump to next RPS instruction. */
1629                        *rps++ = S626_RPS_JUMP;
1630                        *rps++ = jmp_adrs;
1631                }
1632
1633                if (cmd->convert_src != TRIG_NOW) {
1634                        /* Wait for Start trigger. */
1635                        *rps++ = S626_RPS_PAUSE | S626_RPS_SIGADC;
1636                        *rps++ = S626_RPS_CLRSIGNAL | S626_RPS_SIGADC;
1637                }
1638                /* Start ADC by pulsing GPIO1. */
1639                /* Begin ADC Start pulse. */
1640                *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1641                *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1642                *rps++ = S626_RPS_NOP;
1643                /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1644                /* End ADC Start pulse. */
1645                *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1646                *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1647                /*
1648                 * Wait for ADC to complete (GPIO2 is asserted high when ADC not
1649                 * busy) and for data from previous conversion to shift into FB
1650                 * BUFFER 1 register.
1651                 */
1652                /* Wait for ADC done. */
1653                *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;
1654
1655                /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
1656                *rps++ = S626_RPS_STREG |
1657                         (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1658                *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1659                         (devpriv->adc_items << 2);
1660
1661                /*
1662                 * If this slot's EndOfPollList flag is set, all channels have
1663                 * now been processed.
1664                 */
1665                if (*ppl++ & S626_EOPL) {
1666                        devpriv->adc_items++; /* Adjust poll list item count. */
1667                        break;  /* Exit poll list processing loop. */
1668                }
1669        }
1670
1671        /*
1672         * VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US.  Allow the
1673         * ADC to stabilize for 2 microseconds before starting the final
1674         * (dummy) conversion.  This delay is necessary to allow sufficient
1675         * time between last conversion finished and the start of the dummy
1676         * conversion.  Without this delay, the last conversion's data value
1677         * is sometimes set to the previous conversion's data value.
1678         */
1679        for (n = 0; n < (2 * S626_RPSCLK_PER_US); n++)
1680                *rps++ = S626_RPS_NOP;
1681
1682        /*
1683         * Start a dummy conversion to cause the data from the last
1684         * conversion of interest to be shifted in.
1685         */
1686        /* Begin ADC Start pulse. */
1687        *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2);
1688        *rps++ = S626_GPIO_BASE | S626_GPIO1_LO;
1689        *rps++ = S626_RPS_NOP;
1690        /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1691        *rps++ = S626_RPS_LDREG | (S626_P_GPIO >> 2); /* End ADC Start pulse. */
1692        *rps++ = S626_GPIO_BASE | S626_GPIO1_HI;
1693
1694        /*
1695         * Wait for the data from the last conversion of interest to arrive
1696         * in FB BUFFER 1 register.
1697         */
1698        *rps++ = S626_RPS_PAUSE | S626_RPS_GPIO2;       /* Wait for ADC done. */
1699
1700        /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1701        *rps++ = S626_RPS_STREG | (S626_BUGFIX_STREG(S626_P_FB_BUFFER1) >> 2);
1702        *rps++ = (uint32_t)devpriv->ana_buf.physical_base +
1703                 (devpriv->adc_items << 2);
1704
1705        /* Indicate ADC scan loop is finished. */
1706        /* Signal ReadADC() that scan is done. */
1707        /* *rps++= S626_RPS_CLRSIGNAL | S626_RPS_SIGADC; */
1708
1709        /* invoke interrupt */
1710        if (devpriv->ai_cmd_running == 1)
1711                *rps++ = S626_RPS_IRQ;
1712
1713        /* Restart RPS program at its beginning. */
1714        *rps++ = S626_RPS_JUMP; /* Branch to start of RPS program. */
1715        *rps++ = (uint32_t)devpriv->rps_buf.physical_base;
1716
1717        /* End of RPS program build */
1718}
1719
1720#ifdef unused_code
1721static int s626_ai_rinsn(struct comedi_device *dev,
1722                         struct comedi_subdevice *s,
1723                         struct comedi_insn *insn,
1724                         unsigned int *data)
1725{
1726        struct s626_private *devpriv = dev->private;
1727        uint8_t i;
1728        int32_t *readaddr;
1729
1730        /* Trigger ADC scan loop start */
1731        s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2);
1732
1733        /* Wait until ADC scan loop is finished (RPS Signal 0 reset) */
1734        while (s626_mc_test(dev, S626_MC2_ADC_RPS, S626_P_MC2))
1735                ;
1736
1737        /*
1738         * Init ptr to DMA buffer that holds new ADC data.  We skip the
1739         * first uint16_t in the buffer because it contains junk data from
1740         * the final ADC of the previous poll list scan.
1741         */
1742        readaddr = (uint32_t *)devpriv->ana_buf.logical_base + 1;
1743
1744        /*
1745         * Convert ADC data to 16-bit integer values and
1746         * copy to application buffer.
1747         */
1748        for (i = 0; i < devpriv->adc_items; i++) {
1749                *data = s626_ai_reg_to_uint(*readaddr++);
1750                data++;
1751        }
1752
1753        return i;
1754}
1755#endif
1756
1757static int s626_ai_eoc(struct comedi_device *dev,
1758                       struct comedi_subdevice *s,
1759                       struct comedi_insn *insn,
1760                       unsigned long context)
1761{
1762        unsigned int status;
1763
1764        status = readl(dev->mmio + S626_P_PSR);
1765        if (status & S626_PSR_GPIO2)
1766                return 0;
1767        return -EBUSY;
1768}
1769
1770static int s626_ai_insn_read(struct comedi_device *dev,
1771                             struct comedi_subdevice *s,
1772                             struct comedi_insn *insn,
1773                             unsigned int *data)
1774{
1775        uint16_t chan = CR_CHAN(insn->chanspec);
1776        uint16_t range = CR_RANGE(insn->chanspec);
1777        uint16_t adc_spec = 0;
1778        uint32_t gpio_image;
1779        uint32_t tmp;
1780        int ret;
1781        int n;
1782
1783        /*
1784         * Convert application's ADC specification into form
1785         *  appropriate for register programming.
1786         */
1787        if (range == 0)
1788                adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR5V);
1789        else
1790                adc_spec = (chan << 8) | (S626_GSEL_BIPOLAR10V);
1791
1792        /* Switch ADC analog gain. */
1793        s626_debi_write(dev, S626_LP_GSEL, adc_spec);   /* Set gain. */
1794
1795        /* Select ADC analog input channel. */
1796        s626_debi_write(dev, S626_LP_ISEL, adc_spec);   /* Select channel. */
1797
1798        for (n = 0; n < insn->n; n++) {
1799                /* Delay 10 microseconds for analog input settling. */
1800                udelay(10);
1801
1802                /* Start ADC by pulsing GPIO1 low */
1803                gpio_image = readl(dev->mmio + S626_P_GPIO);
1804                /* Assert ADC Start command */
1805                writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1806                /* and stretch it out */
1807                writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1808                writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1809                /* Negate ADC Start command */
1810                writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1811
1812                /*
1813                 * Wait for ADC to complete (GPIO2 is asserted high when
1814                 * ADC not busy) and for data from previous conversion to
1815                 * shift into FB BUFFER 1 register.
1816                 */
1817
1818                /* Wait for ADC done */
1819                ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1820                if (ret)
1821                        return ret;
1822
1823                /* Fetch ADC data */
1824                if (n != 0) {
1825                        tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1826                        data[n - 1] = s626_ai_reg_to_uint(tmp);
1827                }
1828
1829                /*
1830                 * Allow the ADC to stabilize for 4 microseconds before
1831                 * starting the next (final) conversion.  This delay is
1832                 * necessary to allow sufficient time between last
1833                 * conversion finished and the start of the next
1834                 * conversion.  Without this delay, the last conversion's
1835                 * data value is sometimes set to the previous
1836                 * conversion's data value.
1837                 */
1838                udelay(4);
1839        }
1840
1841        /*
1842         * Start a dummy conversion to cause the data from the
1843         * previous conversion to be shifted in.
1844         */
1845        gpio_image = readl(dev->mmio + S626_P_GPIO);
1846        /* Assert ADC Start command */
1847        writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1848        /* and stretch it out */
1849        writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1850        writel(gpio_image & ~S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1851        /* Negate ADC Start command */
1852        writel(gpio_image | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
1853
1854        /* Wait for the data to arrive in FB BUFFER 1 register. */
1855
1856        /* Wait for ADC done */
1857        ret = comedi_timeout(dev, s, insn, s626_ai_eoc, 0);
1858        if (ret)
1859                return ret;
1860
1861        /* Fetch ADC data from audio interface's input shift register. */
1862
1863        /* Fetch ADC data */
1864        if (n != 0) {
1865                tmp = readl(dev->mmio + S626_P_FB_BUFFER1);
1866                data[n - 1] = s626_ai_reg_to_uint(tmp);
1867        }
1868
1869        return n;
1870}
1871
1872static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
1873{
1874        int n;
1875
1876        for (n = 0; n < cmd->chanlist_len; n++) {
1877                if (CR_RANGE(cmd->chanlist[n]) == 0)
1878                        ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_5V;
1879                else
1880                        ppl[n] = CR_CHAN(cmd->chanlist[n]) | S626_RANGE_10V;
1881        }
1882        if (n != 0)
1883                ppl[n - 1] |= S626_EOPL;
1884
1885        return n;
1886}
1887
1888static int s626_ai_inttrig(struct comedi_device *dev,
1889                           struct comedi_subdevice *s,
1890                           unsigned int trig_num)
1891{
1892        struct comedi_cmd *cmd = &s->async->cmd;
1893
1894        if (trig_num != cmd->start_arg)
1895                return -EINVAL;
1896
1897        /* Start executing the RPS program */
1898        s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
1899
1900        s->async->inttrig = NULL;
1901
1902        return 1;
1903}
1904
1905/*
1906 * This function doesn't require a particular form, this is just what
1907 * happens to be used in some of the drivers.  It should convert ns
1908 * nanoseconds to a counter value suitable for programming the device.
1909 * Also, it should adjust ns so that it cooresponds to the actual time
1910 * that the device will use.
1911 */
1912static int s626_ns_to_timer(unsigned int *nanosec, unsigned int flags)
1913{
1914        int divider, base;
1915
1916        base = 500;             /* 2MHz internal clock */
1917
1918        switch (flags & CMDF_ROUND_MASK) {
1919        case CMDF_ROUND_NEAREST:
1920        default:
1921                divider = DIV_ROUND_CLOSEST(*nanosec, base);
1922                break;
1923        case CMDF_ROUND_DOWN:
1924                divider = (*nanosec) / base;
1925                break;
1926        case CMDF_ROUND_UP:
1927                divider = DIV_ROUND_UP(*nanosec, base);
1928                break;
1929        }
1930
1931        *nanosec = base * divider;
1932        return divider - 1;
1933}
1934
1935static void s626_timer_load(struct comedi_device *dev,
1936                            unsigned int chan, int tick)
1937{
1938        uint16_t setup =
1939                /* Preload upon index. */
1940                S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
1941                /* Disable hardware index. */
1942                S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
1943                /* Operating mode is Timer. */
1944                S626_SET_STD_ENCMODE(S626_ENCMODE_TIMER) |
1945                /* Count direction is Down. */
1946                S626_SET_STD_CLKPOL(S626_CNTDIR_DOWN) |
1947                /* Clock multiplier is 1x. */
1948                S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
1949                /* Enabled by index */
1950                S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
1951        uint16_t value_latchsrc = S626_LATCHSRC_A_INDXA;
1952        /* uint16_t enab = S626_CLKENAB_ALWAYS; */
1953
1954        s626_set_mode(dev, chan, setup, false);
1955
1956        /* Set the preload register */
1957        s626_preload(dev, chan, tick);
1958
1959        /*
1960         * Software index pulse forces the preload register to load
1961         * into the counter
1962         */
1963        s626_set_load_trig(dev, chan, 0);
1964        s626_pulse_index(dev, chan);
1965
1966        /* set reload on counter overflow */
1967        s626_set_load_trig(dev, chan, 1);
1968
1969        /* set interrupt on overflow */
1970        s626_set_int_src(dev, chan, S626_INTSRC_OVER);
1971
1972        s626_set_latch_source(dev, chan, value_latchsrc);
1973        /* s626_set_enable(dev, chan, (uint16_t)(enab != 0)); */
1974}
1975
1976/* TO COMPLETE  */
1977static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
1978{
1979        struct s626_private *devpriv = dev->private;
1980        uint8_t ppl[16];
1981        struct comedi_cmd *cmd = &s->async->cmd;
1982        int tick;
1983
1984        if (devpriv->ai_cmd_running) {
1985                dev_err(dev->class_dev,
1986                        "s626_ai_cmd: Another ai_cmd is running\n");
1987                return -EBUSY;
1988        }
1989        /* disable interrupt */
1990        writel(0, dev->mmio + S626_P_IER);
1991
1992        /* clear interrupt request */
1993        writel(S626_IRQ_RPS1 | S626_IRQ_GPIO3, dev->mmio + S626_P_ISR);
1994
1995        /* clear any pending interrupt */
1996        s626_dio_clear_irq(dev);
1997        /* s626_enc_clear_irq(dev); */
1998
1999        /* reset ai_cmd_running flag */
2000        devpriv->ai_cmd_running = 0;
2001
2002        s626_ai_load_polllist(ppl, cmd);
2003        devpriv->ai_cmd_running = 1;
2004        devpriv->ai_convert_count = 0;
2005
2006        switch (cmd->scan_begin_src) {
2007        case TRIG_FOLLOW:
2008                break;
2009        case TRIG_TIMER:
2010                /*
2011                 * set a counter to generate adc trigger at scan_begin_arg
2012                 * interval
2013                 */
2014                tick = s626_ns_to_timer(&cmd->scan_begin_arg, cmd->flags);
2015
2016                /* load timer value and enable interrupt */
2017                s626_timer_load(dev, 5, tick);
2018                s626_set_enable(dev, 5, S626_CLKENAB_ALWAYS);
2019                break;
2020        case TRIG_EXT:
2021                /* set the digital line and interrupt for scan trigger */
2022                if (cmd->start_src != TRIG_EXT)
2023                        s626_dio_set_irq(dev, cmd->scan_begin_arg);
2024                break;
2025        }
2026
2027        switch (cmd->convert_src) {
2028        case TRIG_NOW:
2029                break;
2030        case TRIG_TIMER:
2031                /*
2032                 * set a counter to generate adc trigger at convert_arg
2033                 * interval
2034                 */
2035                tick = s626_ns_to_timer(&cmd->convert_arg, cmd->flags);
2036
2037                /* load timer value and enable interrupt */
2038                s626_timer_load(dev, 4, tick);
2039                s626_set_enable(dev, 4, S626_CLKENAB_INDEX);
2040                break;
2041        case TRIG_EXT:
2042                /* set the digital line and interrupt for convert trigger */
2043                if (cmd->scan_begin_src != TRIG_EXT &&
2044                    cmd->start_src == TRIG_EXT)
2045                        s626_dio_set_irq(dev, cmd->convert_arg);
2046                break;
2047        }
2048
2049        s626_reset_adc(dev, ppl);
2050
2051        switch (cmd->start_src) {
2052        case TRIG_NOW:
2053                /* Trigger ADC scan loop start */
2054                /* s626_mc_enable(dev, S626_MC2_ADC_RPS, S626_P_MC2); */
2055
2056                /* Start executing the RPS program */
2057                s626_mc_enable(dev, S626_MC1_ERPS1, S626_P_MC1);
2058                s->async->inttrig = NULL;
2059                break;
2060        case TRIG_EXT:
2061                /* configure DIO channel for acquisition trigger */
2062                s626_dio_set_irq(dev, cmd->start_arg);
2063                s->async->inttrig = NULL;
2064                break;
2065        case TRIG_INT:
2066                s->async->inttrig = s626_ai_inttrig;
2067                break;
2068        }
2069
2070        /* enable interrupt */
2071        writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1, dev->mmio + S626_P_IER);
2072
2073        return 0;
2074}
2075
2076static int s626_ai_cmdtest(struct comedi_device *dev,
2077                           struct comedi_subdevice *s, struct comedi_cmd *cmd)
2078{
2079        int err = 0;
2080        unsigned int arg;
2081
2082        /* Step 1 : check if triggers are trivially valid */
2083
2084        err |= comedi_check_trigger_src(&cmd->start_src,
2085                                        TRIG_NOW | TRIG_INT | TRIG_EXT);
2086        err |= comedi_check_trigger_src(&cmd->scan_begin_src,
2087                                        TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW);
2088        err |= comedi_check_trigger_src(&cmd->convert_src,
2089                                        TRIG_TIMER | TRIG_EXT | TRIG_NOW);
2090        err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2091        err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
2092
2093        if (err)
2094                return 1;
2095
2096        /* Step 2a : make sure trigger sources are unique */
2097
2098        err |= comedi_check_trigger_is_unique(cmd->start_src);
2099        err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2100        err |= comedi_check_trigger_is_unique(cmd->convert_src);
2101        err |= comedi_check_trigger_is_unique(cmd->stop_src);
2102
2103        /* Step 2b : and mutually compatible */
2104
2105        if (err)
2106                return 2;
2107
2108        /* Step 3: check if arguments are trivially valid */
2109
2110        switch (cmd->start_src) {
2111        case TRIG_NOW:
2112        case TRIG_INT:
2113                err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2114                break;
2115        case TRIG_EXT:
2116                err |= comedi_check_trigger_arg_max(&cmd->start_arg, 39);
2117                break;
2118        }
2119
2120        if (cmd->scan_begin_src == TRIG_EXT)
2121                err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 39);
2122        if (cmd->convert_src == TRIG_EXT)
2123                err |= comedi_check_trigger_arg_max(&cmd->convert_arg, 39);
2124
2125#define S626_MAX_SPEED  200000  /* in nanoseconds */
2126#define S626_MIN_SPEED  2000000000      /* in nanoseconds */
2127
2128        if (cmd->scan_begin_src == TRIG_TIMER) {
2129                err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
2130                                                    S626_MAX_SPEED);
2131                err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg,
2132                                                    S626_MIN_SPEED);
2133        } else {
2134                /*
2135                 * external trigger
2136                 * should be level/edge, hi/lo specification here
2137                 * should specify multiple external triggers
2138                 * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
2139                 */
2140        }
2141        if (cmd->convert_src == TRIG_TIMER) {
2142                err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2143                                                    S626_MAX_SPEED);
2144                err |= comedi_check_trigger_arg_max(&cmd->convert_arg,
2145                                                    S626_MIN_SPEED);
2146        } else {
2147                /*
2148                 * external trigger - see above
2149                 * err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, 9);
2150                 */
2151        }
2152
2153        err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2154                                           cmd->chanlist_len);
2155
2156        if (cmd->stop_src == TRIG_COUNT)
2157                err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2158        else    /* TRIG_NONE */
2159                err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2160
2161        if (err)
2162                return 3;
2163
2164        /* step 4: fix up any arguments */
2165
2166        if (cmd->scan_begin_src == TRIG_TIMER) {
2167                arg = cmd->scan_begin_arg;
2168                s626_ns_to_timer(&arg, cmd->flags);
2169                err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
2170        }
2171
2172        if (cmd->convert_src == TRIG_TIMER) {
2173                arg = cmd->convert_arg;
2174                s626_ns_to_timer(&arg, cmd->flags);
2175                err |= comedi_check_trigger_arg_is(&cmd->convert_arg, arg);
2176
2177                if (cmd->scan_begin_src == TRIG_TIMER) {
2178                        arg = cmd->convert_arg * cmd->scan_end_arg;
2179                        err |= comedi_check_trigger_arg_min(&cmd->
2180                                                            scan_begin_arg,
2181                                                            arg);
2182                }
2183        }
2184
2185        if (err)
2186                return 4;
2187
2188        return 0;
2189}
2190
2191static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
2192{
2193        struct s626_private *devpriv = dev->private;
2194
2195        /* Stop RPS program in case it is currently running */
2196        s626_mc_disable(dev, S626_MC1_ERPS1, S626_P_MC1);
2197
2198        /* disable master interrupt */
2199        writel(0, dev->mmio + S626_P_IER);
2200
2201        devpriv->ai_cmd_running = 0;
2202
2203        return 0;
2204}
2205
2206static int s626_ao_insn_write(struct comedi_device *dev,
2207                              struct comedi_subdevice *s,
2208                              struct comedi_insn *insn,
2209                              unsigned int *data)
2210{
2211        unsigned int chan = CR_CHAN(insn->chanspec);
2212        int i;
2213
2214        for (i = 0; i < insn->n; i++) {
2215                int16_t dacdata = (int16_t)data[i];
2216                int ret;
2217
2218                dacdata -= (0x1fff);
2219
2220                ret = s626_set_dac(dev, chan, dacdata);
2221                if (ret)
2222                        return ret;
2223
2224                s->readback[chan] = data[i];
2225        }
2226
2227        return insn->n;
2228}
2229
2230/* *************** DIGITAL I/O FUNCTIONS *************** */
2231
2232/*
2233 * All DIO functions address a group of DIO channels by means of
2234 * "group" argument.  group may be 0, 1 or 2, which correspond to DIO
2235 * ports A, B and C, respectively.
2236 */
2237
2238static void s626_dio_init(struct comedi_device *dev)
2239{
2240        uint16_t group;
2241
2242        /* Prepare to treat writes to WRCapSel as capture disables. */
2243        s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_NOEDCAP);
2244
2245        /* For each group of sixteen channels ... */
2246        for (group = 0; group < S626_DIO_BANKS; group++) {
2247                /* Disable all interrupts */
2248                s626_debi_write(dev, S626_LP_WRINTSEL(group), 0);
2249                /* Disable all event captures */
2250                s626_debi_write(dev, S626_LP_WRCAPSEL(group), 0xffff);
2251                /* Init all DIOs to default edge polarity */
2252                s626_debi_write(dev, S626_LP_WREDGSEL(group), 0);
2253                /* Program all outputs to inactive state */
2254                s626_debi_write(dev, S626_LP_WRDOUT(group), 0);
2255        }
2256}
2257
2258static int s626_dio_insn_bits(struct comedi_device *dev,
2259                              struct comedi_subdevice *s,
2260                              struct comedi_insn *insn,
2261                              unsigned int *data)
2262{
2263        unsigned long group = (unsigned long)s->private;
2264
2265        if (comedi_dio_update_state(s, data))
2266                s626_debi_write(dev, S626_LP_WRDOUT(group), s->state);
2267
2268        data[1] = s626_debi_read(dev, S626_LP_RDDIN(group));
2269
2270        return insn->n;
2271}
2272
2273static int s626_dio_insn_config(struct comedi_device *dev,
2274                                struct comedi_subdevice *s,
2275                                struct comedi_insn *insn,
2276                                unsigned int *data)
2277{
2278        unsigned long group = (unsigned long)s->private;
2279        int ret;
2280
2281        ret = comedi_dio_insn_config(dev, s, insn, data, 0);
2282        if (ret)
2283                return ret;
2284
2285        s626_debi_write(dev, S626_LP_WRDOUT(group), s->io_bits);
2286
2287        return insn->n;
2288}
2289
2290/*
2291 * Now this function initializes the value of the counter (data[0])
2292 * and set the subdevice. To complete with trigger and interrupt
2293 * configuration.
2294 *
2295 * FIXME: data[0] is supposed to be an INSN_CONFIG_xxx constant indicating
2296 * what is being configured, but this function appears to be using data[0]
2297 * as a variable.
2298 */
2299static int s626_enc_insn_config(struct comedi_device *dev,
2300                                struct comedi_subdevice *s,
2301                                struct comedi_insn *insn, unsigned int *data)
2302{
2303        unsigned int chan = CR_CHAN(insn->chanspec);
2304        uint16_t setup =
2305                /* Preload upon index. */
2306                S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2307                /* Disable hardware index. */
2308                S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2309                /* Operating mode is Counter. */
2310                S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2311                /* Active high clock. */
2312                S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2313                /* Clock multiplier is 1x. */
2314                S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2315                /* Enabled by index */
2316                S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2317        /* uint16_t disable_int_src = true; */
2318        /* uint32_t Preloadvalue;              //Counter initial value */
2319        uint16_t value_latchsrc = S626_LATCHSRC_AB_READ;
2320        uint16_t enab = S626_CLKENAB_ALWAYS;
2321
2322        /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
2323
2324        s626_set_mode(dev, chan, setup, true);
2325        s626_preload(dev, chan, data[0]);
2326        s626_pulse_index(dev, chan);
2327        s626_set_latch_source(dev, chan, value_latchsrc);
2328        s626_set_enable(dev, chan, (enab != 0));
2329
2330        return insn->n;
2331}
2332
2333static int s626_enc_insn_read(struct comedi_device *dev,
2334                              struct comedi_subdevice *s,
2335                              struct comedi_insn *insn,
2336                              unsigned int *data)
2337{
2338        unsigned int chan = CR_CHAN(insn->chanspec);
2339        uint16_t cntr_latch_reg = S626_LP_CNTR(chan);
2340        int i;
2341
2342        for (i = 0; i < insn->n; i++) {
2343                unsigned int val;
2344
2345                /*
2346                 * Read the counter's output latch LSW/MSW.
2347                 * Latches on LSW read.
2348                 */
2349                val = s626_debi_read(dev, cntr_latch_reg);
2350                val |= (s626_debi_read(dev, cntr_latch_reg + 2) << 16);
2351                data[i] = val;
2352        }
2353
2354        return insn->n;
2355}
2356
2357static int s626_enc_insn_write(struct comedi_device *dev,
2358                               struct comedi_subdevice *s,
2359                               struct comedi_insn *insn, unsigned int *data)
2360{
2361        unsigned int chan = CR_CHAN(insn->chanspec);
2362
2363        /* Set the preload register */
2364        s626_preload(dev, chan, data[0]);
2365
2366        /*
2367         * Software index pulse forces the preload register to load
2368         * into the counter
2369         */
2370        s626_set_load_trig(dev, chan, 0);
2371        s626_pulse_index(dev, chan);
2372        s626_set_load_trig(dev, chan, 2);
2373
2374        return 1;
2375}
2376
2377static void s626_write_misc2(struct comedi_device *dev, uint16_t new_image)
2378{
2379        s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WENABLE);
2380        s626_debi_write(dev, S626_LP_WRMISC2, new_image);
2381        s626_debi_write(dev, S626_LP_MISC1, S626_MISC1_WDISABLE);
2382}
2383
2384static void s626_counters_init(struct comedi_device *dev)
2385{
2386        int chan;
2387        uint16_t setup =
2388                /* Preload upon index. */
2389                S626_SET_STD_LOADSRC(S626_LOADSRC_INDX) |
2390                /* Disable hardware index. */
2391                S626_SET_STD_INDXSRC(S626_INDXSRC_SOFT) |
2392                /* Operating mode is counter. */
2393                S626_SET_STD_ENCMODE(S626_ENCMODE_COUNTER) |
2394                /* Active high clock. */
2395                S626_SET_STD_CLKPOL(S626_CLKPOL_POS) |
2396                /* Clock multiplier is 1x. */
2397                S626_SET_STD_CLKMULT(S626_CLKMULT_1X) |
2398                /* Enabled by index */
2399                S626_SET_STD_CLKENAB(S626_CLKENAB_INDEX);
2400
2401        /*
2402         * Disable all counter interrupts and clear any captured counter events.
2403         */
2404        for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
2405                s626_set_mode(dev, chan, setup, true);
2406                s626_set_int_src(dev, chan, 0);
2407                s626_reset_cap_flags(dev, chan);
2408                s626_set_enable(dev, chan, S626_CLKENAB_ALWAYS);
2409        }
2410}
2411
2412static int s626_allocate_dma_buffers(struct comedi_device *dev)
2413{
2414        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2415        struct s626_private *devpriv = dev->private;
2416        void *addr;
2417        dma_addr_t appdma;
2418
2419        addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2420        if (!addr)
2421                return -ENOMEM;
2422        devpriv->ana_buf.logical_base = addr;
2423        devpriv->ana_buf.physical_base = appdma;
2424
2425        addr = pci_alloc_consistent(pcidev, S626_DMABUF_SIZE, &appdma);
2426        if (!addr)
2427                return -ENOMEM;
2428        devpriv->rps_buf.logical_base = addr;
2429        devpriv->rps_buf.physical_base = appdma;
2430
2431        return 0;
2432}
2433
2434static void s626_free_dma_buffers(struct comedi_device *dev)
2435{
2436        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2437        struct s626_private *devpriv = dev->private;
2438
2439        if (!devpriv)
2440                return;
2441
2442        if (devpriv->rps_buf.logical_base)
2443                pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2444                                    devpriv->rps_buf.logical_base,
2445                                    devpriv->rps_buf.physical_base);
2446        if (devpriv->ana_buf.logical_base)
2447                pci_free_consistent(pcidev, S626_DMABUF_SIZE,
2448                                    devpriv->ana_buf.logical_base,
2449                                    devpriv->ana_buf.physical_base);
2450}
2451
2452static int s626_initialize(struct comedi_device *dev)
2453{
2454        struct s626_private *devpriv = dev->private;
2455        dma_addr_t phys_buf;
2456        uint16_t chan;
2457        int i;
2458        int ret;
2459
2460        /* Enable DEBI and audio pins, enable I2C interface */
2461        s626_mc_enable(dev, S626_MC1_DEBI | S626_MC1_AUDIO | S626_MC1_I2C,
2462                       S626_P_MC1);
2463
2464        /*
2465         * Configure DEBI operating mode
2466         *
2467         *  Local bus is 16 bits wide
2468         *  Declare DEBI transfer timeout interval
2469         *  Set up byte lane steering
2470         *  Intel-compatible local bus (DEBI never times out)
2471         */
2472        writel(S626_DEBI_CFG_SLAVE16 |
2473               (S626_DEBI_TOUT << S626_DEBI_CFG_TOUT_BIT) | S626_DEBI_SWAP |
2474               S626_DEBI_CFG_INTEL, dev->mmio + S626_P_DEBICFG);
2475
2476        /* Disable MMU paging */
2477        writel(S626_DEBI_PAGE_DISABLE, dev->mmio + S626_P_DEBIPAGE);
2478
2479        /* Init GPIO so that ADC Start* is negated */
2480        writel(S626_GPIO_BASE | S626_GPIO1_HI, dev->mmio + S626_P_GPIO);
2481
2482        /* I2C device address for onboard eeprom (revb) */
2483        devpriv->i2c_adrs = 0xA0;
2484
2485        /*
2486         * Issue an I2C ABORT command to halt any I2C
2487         * operation in progress and reset BUSY flag.
2488         */
2489        writel(S626_I2C_CLKSEL | S626_I2C_ABORT,
2490               dev->mmio + S626_P_I2CSTAT);
2491        s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2492        ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2493        if (ret)
2494                return ret;
2495
2496        /*
2497         * Per SAA7146 data sheet, write to STATUS
2498         * reg twice to reset all  I2C error flags.
2499         */
2500        for (i = 0; i < 2; i++) {
2501                writel(S626_I2C_CLKSEL, dev->mmio + S626_P_I2CSTAT);
2502                s626_mc_enable(dev, S626_MC2_UPLD_IIC, S626_P_MC2);
2503                ret = comedi_timeout(dev, NULL, NULL, s626_i2c_handshake_eoc, 0);
2504                if (ret)
2505                        return ret;
2506        }
2507
2508        /*
2509         * Init audio interface functional attributes: set DAC/ADC
2510         * serial clock rates, invert DAC serial clock so that
2511         * DAC data setup times are satisfied, enable DAC serial
2512         * clock out.
2513         */
2514        writel(S626_ACON2_INIT, dev->mmio + S626_P_ACON2);
2515
2516        /*
2517         * Set up TSL1 slot list, which is used to control the
2518         * accumulation of ADC data: S626_RSD1 = shift data in on SD1.
2519         * S626_SIB_A1  = store data uint8_t at next available location
2520         * in FB BUFFER1 register.
2521         */
2522        writel(S626_RSD1 | S626_SIB_A1, dev->mmio + S626_P_TSL1);
2523        writel(S626_RSD1 | S626_SIB_A1 | S626_EOS,
2524               dev->mmio + S626_P_TSL1 + 4);
2525
2526        /* Enable TSL1 slot list so that it executes all the time */
2527        writel(S626_ACON1_ADCSTART, dev->mmio + S626_P_ACON1);
2528
2529        /*
2530         * Initialize RPS registers used for ADC
2531         */
2532
2533        /* Physical start of RPS program */
2534        writel((uint32_t)devpriv->rps_buf.physical_base,
2535               dev->mmio + S626_P_RPSADDR1);
2536        /* RPS program performs no explicit mem writes */
2537        writel(0, dev->mmio + S626_P_RPSPAGE1);
2538        /* Disable RPS timeouts */
2539        writel(0, dev->mmio + S626_P_RPS1_TOUT);
2540
2541#if 0
2542        /*
2543         * SAA7146 BUG WORKAROUND
2544         *
2545         * Initialize SAA7146 ADC interface to a known state by
2546         * invoking ADCs until FB BUFFER 1 register shows that it
2547         * is correctly receiving ADC data. This is necessary
2548         * because the SAA7146 ADC interface does not start up in
2549         * a defined state after a PCI reset.
2550         */
2551        {
2552                struct comedi_subdevice *s = dev->read_subdev;
2553                uint8_t poll_list;
2554                uint16_t adc_data;
2555                uint16_t start_val;
2556                uint16_t index;
2557                unsigned int data[16];
2558
2559                /* Create a simple polling list for analog input channel 0 */
2560                poll_list = S626_EOPL;
2561                s626_reset_adc(dev, &poll_list);
2562
2563                /* Get initial ADC value */
2564                s626_ai_rinsn(dev, s, NULL, data);
2565                start_val = data[0];
2566
2567                /*
2568                 * VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED
2569                 * EXECUTION.
2570                 *
2571                 * Invoke ADCs until the new ADC value differs from the initial
2572                 * value or a timeout occurs.  The timeout protects against the
2573                 * possibility that the driver is restarting and the ADC data is
2574                 * a fixed value resulting from the applied ADC analog input
2575                 * being unusually quiet or at the rail.
2576                 */
2577                for (index = 0; index < 500; index++) {
2578                        s626_ai_rinsn(dev, s, NULL, data);
2579                        adc_data = data[0];
2580                        if (adc_data != start_val)
2581                                break;
2582                }
2583        }
2584#endif  /* SAA7146 BUG WORKAROUND */
2585
2586        /*
2587         * Initialize the DAC interface
2588         */
2589
2590        /*
2591         * Init Audio2's output DMAC attributes:
2592         *   burst length = 1 DWORD
2593         *   threshold = 1 DWORD.
2594         */
2595        writel(0, dev->mmio + S626_P_PCI_BT_A);
2596
2597        /*
2598         * Init Audio2's output DMA physical addresses.  The protection
2599         * address is set to 1 DWORD past the base address so that a
2600         * single DWORD will be transferred each time a DMA transfer is
2601         * enabled.
2602         */
2603        phys_buf = devpriv->ana_buf.physical_base +
2604                   (S626_DAC_WDMABUF_OS * sizeof(uint32_t));
2605        writel((uint32_t)phys_buf, dev->mmio + S626_P_BASEA2_OUT);
2606        writel((uint32_t)(phys_buf + sizeof(uint32_t)),
2607               dev->mmio + S626_P_PROTA2_OUT);
2608
2609        /*
2610         * Cache Audio2's output DMA buffer logical address.  This is
2611         * where DAC data is buffered for A2 output DMA transfers.
2612         */
2613        devpriv->dac_wbuf = (uint32_t *)devpriv->ana_buf.logical_base +
2614                            S626_DAC_WDMABUF_OS;
2615
2616        /*
2617         * Audio2's output channels does not use paging.  The
2618         * protection violation handling bit is set so that the
2619         * DMAC will automatically halt and its PCI address pointer
2620         * will be reset when the protection address is reached.
2621         */
2622        writel(8, dev->mmio + S626_P_PAGEA2_OUT);
2623
2624        /*
2625         * Initialize time slot list 2 (TSL2), which is used to control
2626         * the clock generation for and serialization of data to be sent
2627         * to the DAC devices.  Slot 0 is a NOP that is used to trap TSL
2628         * execution; this permits other slots to be safely modified
2629         * without first turning off the TSL sequencer (which is
2630         * apparently impossible to do).  Also, SD3 (which is driven by a
2631         * pull-up resistor) is shifted in and stored to the MSB of
2632         * FB_BUFFER2 to be used as evidence that the slot sequence has
2633         * not yet finished executing.
2634         */
2635
2636        /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
2637        writel(S626_XSD2 | S626_RSD3 | S626_SIB_A2 | S626_EOS,
2638               dev->mmio + S626_VECTPORT(0));
2639
2640        /*
2641         * Initialize slot 1, which is constant.  Slot 1 causes a
2642         * DWORD to be transferred from audio channel 2's output FIFO
2643         * to the FIFO's output buffer so that it can be serialized
2644         * and sent to the DAC during subsequent slots.  All remaining
2645         * slots are dynamically populated as required by the target
2646         * DAC device.
2647         */
2648
2649        /* Slot 1: Fetch DWORD from Audio2's output FIFO */
2650        writel(S626_LF_A2, dev->mmio + S626_VECTPORT(1));
2651
2652        /* Start DAC's audio interface (TSL2) running */
2653        writel(S626_ACON1_DACSTART, dev->mmio + S626_P_ACON1);
2654
2655        /*
2656         * Init Trim DACs to calibrated values.  Do it twice because the
2657         * SAA7146 audio channel does not always reset properly and
2658         * sometimes causes the first few TrimDAC writes to malfunction.
2659         */
2660        s626_load_trim_dacs(dev);
2661        ret = s626_load_trim_dacs(dev);
2662        if (ret)
2663                return ret;
2664
2665        /*
2666         * Manually init all gate array hardware in case this is a soft
2667         * reset (we have no way of determining whether this is a warm
2668         * or cold start).  This is necessary because the gate array will
2669         * reset only in response to a PCI hard reset; there is no soft
2670         * reset function.
2671         */
2672
2673        /*
2674         * Init all DAC outputs to 0V and init all DAC setpoint and
2675         * polarity images.
2676         */
2677        for (chan = 0; chan < S626_DAC_CHANNELS; chan++) {
2678                ret = s626_set_dac(dev, chan, 0);
2679                if (ret)
2680                        return ret;
2681        }
2682
2683        /* Init counters */
2684        s626_counters_init(dev);
2685
2686        /*
2687         * Without modifying the state of the Battery Backup enab, disable
2688         * the watchdog timer, set DIO channels 0-5 to operate in the
2689         * standard DIO (vs. counter overflow) mode, disable the battery
2690         * charger, and reset the watchdog interval selector to zero.
2691         */
2692        s626_write_misc2(dev, (s626_debi_read(dev, S626_LP_RDMISC2) &
2693                               S626_MISC2_BATT_ENABLE));
2694
2695        /* Initialize the digital I/O subsystem */
2696        s626_dio_init(dev);
2697
2698        return 0;
2699}
2700
2701static int s626_auto_attach(struct comedi_device *dev,
2702                            unsigned long context_unused)
2703{
2704        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
2705        struct s626_private *devpriv;
2706        struct comedi_subdevice *s;
2707        int ret;
2708
2709        devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
2710        if (!devpriv)
2711                return -ENOMEM;
2712
2713        ret = comedi_pci_enable(dev);
2714        if (ret)
2715                return ret;
2716
2717        dev->mmio = pci_ioremap_bar(pcidev, 0);
2718        if (!dev->mmio)
2719                return -ENOMEM;
2720
2721        /* disable master interrupt */
2722        writel(0, dev->mmio + S626_P_IER);
2723
2724        /* soft reset */
2725        writel(S626_MC1_SOFT_RESET, dev->mmio + S626_P_MC1);
2726
2727        /* DMA FIXME DMA// */
2728
2729        ret = s626_allocate_dma_buffers(dev);
2730        if (ret)
2731                return ret;
2732
2733        if (pcidev->irq) {
2734                ret = request_irq(pcidev->irq, s626_irq_handler, IRQF_SHARED,
2735                                  dev->board_name, dev);
2736
2737                if (ret == 0)
2738                        dev->irq = pcidev->irq;
2739        }
2740
2741        ret = comedi_alloc_subdevices(dev, 6);
2742        if (ret)
2743                return ret;
2744
2745        s = &dev->subdevices[0];
2746        /* analog input subdevice */
2747        s->type         = COMEDI_SUBD_AI;
2748        s->subdev_flags = SDF_READABLE | SDF_DIFF;
2749        s->n_chan       = S626_ADC_CHANNELS;
2750        s->maxdata      = 0x3fff;
2751        s->range_table  = &s626_range_table;
2752        s->len_chanlist = S626_ADC_CHANNELS;
2753        s->insn_read    = s626_ai_insn_read;
2754        if (dev->irq) {
2755                dev->read_subdev = s;
2756                s->subdev_flags |= SDF_CMD_READ;
2757                s->do_cmd       = s626_ai_cmd;
2758                s->do_cmdtest   = s626_ai_cmdtest;
2759                s->cancel       = s626_ai_cancel;
2760        }
2761
2762        s = &dev->subdevices[1];
2763        /* analog output subdevice */
2764        s->type         = COMEDI_SUBD_AO;
2765        s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2766        s->n_chan       = S626_DAC_CHANNELS;
2767        s->maxdata      = 0x3fff;
2768        s->range_table  = &range_bipolar10;
2769        s->insn_write   = s626_ao_insn_write;
2770
2771        ret = comedi_alloc_subdev_readback(s);
2772        if (ret)
2773                return ret;
2774
2775        s = &dev->subdevices[2];
2776        /* digital I/O subdevice */
2777        s->type         = COMEDI_SUBD_DIO;
2778        s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2779        s->n_chan       = 16;
2780        s->maxdata      = 1;
2781        s->io_bits      = 0xffff;
2782        s->private      = (void *)0;    /* DIO group 0 */
2783        s->range_table  = &range_digital;
2784        s->insn_config  = s626_dio_insn_config;
2785        s->insn_bits    = s626_dio_insn_bits;
2786
2787        s = &dev->subdevices[3];
2788        /* digital I/O subdevice */
2789        s->type         = COMEDI_SUBD_DIO;
2790        s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2791        s->n_chan       = 16;
2792        s->maxdata      = 1;
2793        s->io_bits      = 0xffff;
2794        s->private      = (void *)1;    /* DIO group 1 */
2795        s->range_table  = &range_digital;
2796        s->insn_config  = s626_dio_insn_config;
2797        s->insn_bits    = s626_dio_insn_bits;
2798
2799        s = &dev->subdevices[4];
2800        /* digital I/O subdevice */
2801        s->type         = COMEDI_SUBD_DIO;
2802        s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
2803        s->n_chan       = 16;
2804        s->maxdata      = 1;
2805        s->io_bits      = 0xffff;
2806        s->private      = (void *)2;    /* DIO group 2 */
2807        s->range_table  = &range_digital;
2808        s->insn_config  = s626_dio_insn_config;
2809        s->insn_bits    = s626_dio_insn_bits;
2810
2811        s = &dev->subdevices[5];
2812        /* encoder (counter) subdevice */
2813        s->type         = COMEDI_SUBD_COUNTER;
2814        s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
2815        s->n_chan       = S626_ENCODER_CHANNELS;
2816        s->maxdata      = 0xffffff;
2817        s->range_table  = &range_unknown;
2818        s->insn_config  = s626_enc_insn_config;
2819        s->insn_read    = s626_enc_insn_read;
2820        s->insn_write   = s626_enc_insn_write;
2821
2822        return s626_initialize(dev);
2823}
2824
2825static void s626_detach(struct comedi_device *dev)
2826{
2827        struct s626_private *devpriv = dev->private;
2828
2829        if (devpriv) {
2830                /* stop ai_command */
2831                devpriv->ai_cmd_running = 0;
2832
2833                if (dev->mmio) {
2834                        /* interrupt mask */
2835                        /* Disable master interrupt */
2836                        writel(0, dev->mmio + S626_P_IER);
2837                        /* Clear board's IRQ status flag */
2838                        writel(S626_IRQ_GPIO3 | S626_IRQ_RPS1,
2839                               dev->mmio + S626_P_ISR);
2840
2841                        /* Disable the watchdog timer and battery charger. */
2842                        s626_write_misc2(dev, 0);
2843
2844                        /* Close all interfaces on 7146 device */
2845                        writel(S626_MC1_SHUTDOWN, dev->mmio + S626_P_MC1);
2846                        writel(S626_ACON1_BASE, dev->mmio + S626_P_ACON1);
2847                }
2848        }
2849        comedi_pci_detach(dev);
2850        s626_free_dma_buffers(dev);
2851}
2852
2853static struct comedi_driver s626_driver = {
2854        .driver_name    = "s626",
2855        .module         = THIS_MODULE,
2856        .auto_attach    = s626_auto_attach,
2857        .detach         = s626_detach,
2858};
2859
2860static int s626_pci_probe(struct pci_dev *dev,
2861                          const struct pci_device_id *id)
2862{
2863        return comedi_pci_auto_config(dev, &s626_driver, id->driver_data);
2864}
2865
2866/*
2867 * For devices with vendor:device id == 0x1131:0x7146 you must specify
2868 * also subvendor:subdevice ids, because otherwise it will conflict with
2869 * Philips SAA7146 media/dvb based cards.
2870 */
2871static const struct pci_device_id s626_pci_table[] = {
2872        { PCI_DEVICE_SUB(PCI_VENDOR_ID_PHILIPS, PCI_DEVICE_ID_PHILIPS_SAA7146,
2873                         0x6000, 0x0272) },
2874        { 0 }
2875};
2876MODULE_DEVICE_TABLE(pci, s626_pci_table);
2877
2878static struct pci_driver s626_pci_driver = {
2879        .name           = "s626",
2880        .id_table       = s626_pci_table,
2881        .probe          = s626_pci_probe,
2882        .remove         = comedi_pci_auto_unconfig,
2883};
2884module_comedi_pci_driver(s626_driver, s626_pci_driver);
2885
2886MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
2887MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
2888MODULE_LICENSE("GPL");
2889
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