linux/drivers/staging/comedi/drivers/me_daq.c
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   1/*
   2 * comedi/drivers/me_daq.c
   3 * Hardware driver for Meilhaus data acquisition cards:
   4 *   ME-2000i, ME-2600i, ME-3000vm1
   5 *
   6 * Copyright (C) 2002 Michael Hillmann <hillmann@syscongroup.de>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 */
  18
  19/*
  20 * Driver: me_daq
  21 * Description: Meilhaus PCI data acquisition cards
  22 * Devices: (Meilhaus) ME-2600i [me-2600i]
  23 *          (Meilhaus) ME-2000i [me-2000i]
  24 * Author: Michael Hillmann <hillmann@syscongroup.de>
  25 * Status: experimental
  26 *
  27 * Configuration options: not applicable, uses PCI auto config
  28 *
  29 * Supports:
  30 *    Analog Input, Analog Output, Digital I/O
  31 */
  32
  33#include <linux/module.h>
  34#include <linux/pci.h>
  35#include <linux/interrupt.h>
  36#include <linux/sched.h>
  37
  38#include "../comedidev.h"
  39
  40#include "plx9052.h"
  41
  42#define ME2600_FIRMWARE         "me2600_firmware.bin"
  43
  44#define XILINX_DOWNLOAD_RESET   0x42    /* Xilinx registers */
  45
  46#define ME_CONTROL_1                    0x0000  /* - | W */
  47#define   INTERRUPT_ENABLE              (1<<15)
  48#define   COUNTER_B_IRQ                 (1<<12)
  49#define   COUNTER_A_IRQ                 (1<<11)
  50#define   CHANLIST_READY_IRQ            (1<<10)
  51#define   EXT_IRQ                       (1<<9)
  52#define   ADFIFO_HALFFULL_IRQ           (1<<8)
  53#define   SCAN_COUNT_ENABLE             (1<<5)
  54#define   SIMULTANEOUS_ENABLE           (1<<4)
  55#define   TRIGGER_FALLING_EDGE          (1<<3)
  56#define   CONTINUOUS_MODE               (1<<2)
  57#define   DISABLE_ADC                   (0<<0)
  58#define   SOFTWARE_TRIGGERED_ADC        (1<<0)
  59#define   SCAN_TRIGGERED_ADC            (2<<0)
  60#define   EXT_TRIGGERED_ADC             (3<<0)
  61#define ME_ADC_START                    0x0000  /* R | - */
  62#define ME_CONTROL_2                    0x0002  /* - | W */
  63#define   ENABLE_ADFIFO                 (1<<10)
  64#define   ENABLE_CHANLIST               (1<<9)
  65#define   ENABLE_PORT_B                 (1<<7)
  66#define   ENABLE_PORT_A                 (1<<6)
  67#define   ENABLE_COUNTER_B              (1<<4)
  68#define   ENABLE_COUNTER_A              (1<<3)
  69#define   ENABLE_DAC                    (1<<1)
  70#define   BUFFERED_DAC                  (1<<0)
  71#define ME_DAC_UPDATE                   0x0002  /* R | - */
  72#define ME_STATUS                       0x0004  /* R | - */
  73#define   COUNTER_B_IRQ_PENDING         (1<<12)
  74#define   COUNTER_A_IRQ_PENDING         (1<<11)
  75#define   CHANLIST_READY_IRQ_PENDING    (1<<10)
  76#define   EXT_IRQ_PENDING               (1<<9)
  77#define   ADFIFO_HALFFULL_IRQ_PENDING   (1<<8)
  78#define   ADFIFO_FULL                   (1<<4)
  79#define   ADFIFO_HALFFULL               (1<<3)
  80#define   ADFIFO_EMPTY                  (1<<2)
  81#define   CHANLIST_FULL                 (1<<1)
  82#define   FST_ACTIVE                    (1<<0)
  83#define ME_RESET_INTERRUPT              0x0004  /* - | W */
  84#define ME_DIO_PORT_A                   0x0006  /* R | W */
  85#define ME_DIO_PORT_B                   0x0008  /* R | W */
  86#define ME_TIMER_DATA_0                 0x000A  /* - | W */
  87#define ME_TIMER_DATA_1                 0x000C  /* - | W */
  88#define ME_TIMER_DATA_2                 0x000E  /* - | W */
  89#define ME_CHANNEL_LIST                 0x0010  /* - | W */
  90#define   ADC_UNIPOLAR                  (1<<6)
  91#define   ADC_GAIN_0                    (0<<4)
  92#define   ADC_GAIN_1                    (1<<4)
  93#define   ADC_GAIN_2                    (2<<4)
  94#define   ADC_GAIN_3                    (3<<4)
  95#define ME_READ_AD_FIFO                 0x0010  /* R | - */
  96#define ME_DAC_CONTROL                  0x0012  /* - | W */
  97#define   DAC_UNIPOLAR_D                (0<<4)
  98#define   DAC_BIPOLAR_D                 (1<<4)
  99#define   DAC_UNIPOLAR_C                (0<<5)
 100#define   DAC_BIPOLAR_C                 (1<<5)
 101#define   DAC_UNIPOLAR_B                (0<<6)
 102#define   DAC_BIPOLAR_B                 (1<<6)
 103#define   DAC_UNIPOLAR_A                (0<<7)
 104#define   DAC_BIPOLAR_A                 (1<<7)
 105#define   DAC_GAIN_0_D                  (0<<8)
 106#define   DAC_GAIN_1_D                  (1<<8)
 107#define   DAC_GAIN_0_C                  (0<<9)
 108#define   DAC_GAIN_1_C                  (1<<9)
 109#define   DAC_GAIN_0_B                  (0<<10)
 110#define   DAC_GAIN_1_B                  (1<<10)
 111#define   DAC_GAIN_0_A                  (0<<11)
 112#define   DAC_GAIN_1_A                  (1<<11)
 113#define ME_DAC_CONTROL_UPDATE           0x0012  /* R | - */
 114#define ME_DAC_DATA_A                   0x0014  /* - | W */
 115#define ME_DAC_DATA_B                   0x0016  /* - | W */
 116#define ME_DAC_DATA_C                   0x0018  /* - | W */
 117#define ME_DAC_DATA_D                   0x001A  /* - | W */
 118#define ME_COUNTER_ENDDATA_A            0x001C  /* - | W */
 119#define ME_COUNTER_ENDDATA_B            0x001E  /* - | W */
 120#define ME_COUNTER_STARTDATA_A          0x0020  /* - | W */
 121#define ME_COUNTER_VALUE_A              0x0020  /* R | - */
 122#define ME_COUNTER_STARTDATA_B          0x0022  /* - | W */
 123#define ME_COUNTER_VALUE_B              0x0022  /* R | - */
 124
 125static const struct comedi_lrange me_ai_range = {
 126        8, {
 127                BIP_RANGE(10),
 128                BIP_RANGE(5),
 129                BIP_RANGE(2.5),
 130                BIP_RANGE(1.25),
 131                UNI_RANGE(10),
 132                UNI_RANGE(5),
 133                UNI_RANGE(2.5),
 134                UNI_RANGE(1.25)
 135        }
 136};
 137
 138static const struct comedi_lrange me_ao_range = {
 139        3, {
 140                BIP_RANGE(10),
 141                BIP_RANGE(5),
 142                UNI_RANGE(10)
 143        }
 144};
 145
 146enum me_boardid {
 147        BOARD_ME2600,
 148        BOARD_ME2000,
 149};
 150
 151struct me_board {
 152        const char *name;
 153        int needs_firmware;
 154        int has_ao;
 155};
 156
 157static const struct me_board me_boards[] = {
 158        [BOARD_ME2600] = {
 159                .name           = "me-2600i",
 160                .needs_firmware = 1,
 161                .has_ao         = 1,
 162        },
 163        [BOARD_ME2000] = {
 164                .name           = "me-2000i",
 165        },
 166};
 167
 168struct me_private_data {
 169        void __iomem *plx_regbase;      /* PLX configuration base address */
 170        void __iomem *me_regbase;       /* Base address of the Meilhaus card */
 171
 172        unsigned short control_1;       /* Mirror of CONTROL_1 register */
 173        unsigned short control_2;       /* Mirror of CONTROL_2 register */
 174        unsigned short dac_control;     /* Mirror of the DAC_CONTROL register */
 175        int ao_readback[4];     /* Mirror of analog output data */
 176};
 177
 178static inline void sleep(unsigned sec)
 179{
 180        current->state = TASK_INTERRUPTIBLE;
 181        schedule_timeout(sec * HZ);
 182}
 183
 184static int me_dio_insn_config(struct comedi_device *dev,
 185                              struct comedi_subdevice *s,
 186                              struct comedi_insn *insn,
 187                              unsigned int *data)
 188{
 189        struct me_private_data *devpriv = dev->private;
 190        unsigned int chan = CR_CHAN(insn->chanspec);
 191        unsigned int mask;
 192        int ret;
 193
 194        if (chan < 16)
 195                mask = 0x0000ffff;
 196        else
 197                mask = 0xffff0000;
 198
 199        ret = comedi_dio_insn_config(dev, s, insn, data, mask);
 200        if (ret)
 201                return ret;
 202
 203        if (s->io_bits & 0x0000ffff)
 204                devpriv->control_2 |= ENABLE_PORT_A;
 205        else
 206                devpriv->control_2 &= ~ENABLE_PORT_A;
 207        if (s->io_bits & 0xffff0000)
 208                devpriv->control_2 |= ENABLE_PORT_B;
 209        else
 210                devpriv->control_2 &= ~ENABLE_PORT_B;
 211
 212        writew(devpriv->control_2, devpriv->me_regbase + ME_CONTROL_2);
 213
 214        return insn->n;
 215}
 216
 217static int me_dio_insn_bits(struct comedi_device *dev,
 218                            struct comedi_subdevice *s,
 219                            struct comedi_insn *insn,
 220                            unsigned int *data)
 221{
 222        struct me_private_data *dev_private = dev->private;
 223        void __iomem *mmio_porta = dev_private->me_regbase + ME_DIO_PORT_A;
 224        void __iomem *mmio_portb = dev_private->me_regbase + ME_DIO_PORT_B;
 225        unsigned int mask;
 226        unsigned int val;
 227
 228        mask = comedi_dio_update_state(s, data);
 229        if (mask) {
 230                if (mask & 0x0000ffff)
 231                        writew((s->state & 0xffff), mmio_porta);
 232                if (mask & 0xffff0000)
 233                        writew(((s->state >> 16) & 0xffff), mmio_portb);
 234        }
 235
 236        if (s->io_bits & 0x0000ffff)
 237                val = s->state & 0xffff;
 238        else
 239                val = readw(mmio_porta);
 240
 241        if (s->io_bits & 0xffff0000)
 242                val |= (s->state & 0xffff0000);
 243        else
 244                val |= (readw(mmio_portb) << 16);
 245
 246        data[1] = val;
 247
 248        return insn->n;
 249}
 250
 251static int me_ai_eoc(struct comedi_device *dev,
 252                     struct comedi_subdevice *s,
 253                     struct comedi_insn *insn,
 254                     unsigned long context)
 255{
 256        struct me_private_data *dev_private = dev->private;
 257        unsigned int status;
 258
 259        status = readw(dev_private->me_regbase + ME_STATUS);
 260        if ((status & 0x0004) == 0)
 261                return 0;
 262        return -EBUSY;
 263}
 264
 265static int me_ai_insn_read(struct comedi_device *dev,
 266                           struct comedi_subdevice *s,
 267                           struct comedi_insn *insn,
 268                           unsigned int *data)
 269{
 270        struct me_private_data *dev_private = dev->private;
 271        unsigned int chan = CR_CHAN(insn->chanspec);
 272        unsigned int rang = CR_RANGE(insn->chanspec);
 273        unsigned int aref = CR_AREF(insn->chanspec);
 274        unsigned short val;
 275        int ret;
 276
 277        /* stop any running conversion */
 278        dev_private->control_1 &= 0xFFFC;
 279        writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
 280
 281        /* clear chanlist and ad fifo */
 282        dev_private->control_2 &= ~(ENABLE_ADFIFO | ENABLE_CHANLIST);
 283        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 284
 285        /* reset any pending interrupt */
 286        writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
 287
 288        /* enable the chanlist and ADC fifo */
 289        dev_private->control_2 |= (ENABLE_ADFIFO | ENABLE_CHANLIST);
 290        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 291
 292        /* write to channel list fifo */
 293        val = chan & 0x0f;                      /* b3:b0 channel */
 294        val |= (rang & 0x03) << 4;              /* b5:b4 gain */
 295        val |= (rang & 0x04) << 4;              /* b6 polarity */
 296        val |= ((aref & AREF_DIFF) ? 0x80 : 0); /* b7 differential */
 297        writew(val & 0xff, dev_private->me_regbase + ME_CHANNEL_LIST);
 298
 299        /* set ADC mode to software trigger */
 300        dev_private->control_1 |= SOFTWARE_TRIGGERED_ADC;
 301        writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
 302
 303        /* start conversion by reading from ADC_START */
 304        readw(dev_private->me_regbase + ME_ADC_START);
 305
 306        /* wait for ADC fifo not empty flag */
 307        ret = comedi_timeout(dev, s, insn, me_ai_eoc, 0);
 308        if (ret)
 309                return ret;
 310
 311        /* get value from ADC fifo */
 312        val = readw(dev_private->me_regbase + ME_READ_AD_FIFO);
 313        val = (val ^ 0x800) & 0x0fff;
 314        data[0] = val;
 315
 316        /* stop any running conversion */
 317        dev_private->control_1 &= 0xFFFC;
 318        writew(dev_private->control_1, dev_private->me_regbase + ME_CONTROL_1);
 319
 320        return 1;
 321}
 322
 323static int me_ao_insn_write(struct comedi_device *dev,
 324                            struct comedi_subdevice *s,
 325                            struct comedi_insn *insn,
 326                            unsigned int *data)
 327{
 328        struct me_private_data *dev_private = dev->private;
 329        unsigned int chan = CR_CHAN(insn->chanspec);
 330        unsigned int rang = CR_RANGE(insn->chanspec);
 331        int i;
 332
 333        /* Enable all DAC */
 334        dev_private->control_2 |= ENABLE_DAC;
 335        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 336
 337        /* and set DAC to "buffered" mode */
 338        dev_private->control_2 |= BUFFERED_DAC;
 339        writew(dev_private->control_2, dev_private->me_regbase + ME_CONTROL_2);
 340
 341        /* Set dac-control register */
 342        for (i = 0; i < insn->n; i++) {
 343                /* clear bits for this channel */
 344                dev_private->dac_control &= ~(0x0880 >> chan);
 345                if (rang == 0)
 346                        dev_private->dac_control |=
 347                            ((DAC_BIPOLAR_A | DAC_GAIN_1_A) >> chan);
 348                else if (rang == 1)
 349                        dev_private->dac_control |=
 350                            ((DAC_BIPOLAR_A | DAC_GAIN_0_A) >> chan);
 351        }
 352        writew(dev_private->dac_control,
 353               dev_private->me_regbase + ME_DAC_CONTROL);
 354
 355        /* Update dac-control register */
 356        readw(dev_private->me_regbase + ME_DAC_CONTROL_UPDATE);
 357
 358        /* Set data register */
 359        for (i = 0; i < insn->n; i++) {
 360                writew((data[0] & s->maxdata),
 361                       dev_private->me_regbase + ME_DAC_DATA_A + (chan << 1));
 362                dev_private->ao_readback[chan] = (data[0] & s->maxdata);
 363        }
 364
 365        /* Update dac with data registers */
 366        readw(dev_private->me_regbase + ME_DAC_UPDATE);
 367
 368        return insn->n;
 369}
 370
 371static int me_ao_insn_read(struct comedi_device *dev,
 372                           struct comedi_subdevice *s,
 373                           struct comedi_insn *insn,
 374                           unsigned int *data)
 375{
 376        struct me_private_data *dev_private = dev->private;
 377        unsigned int chan = CR_CHAN(insn->chanspec);
 378        int i;
 379
 380        for (i = 0; i < insn->n; i++)
 381                data[i] = dev_private->ao_readback[chan];
 382
 383        return insn->n;
 384}
 385
 386static int me2600_xilinx_download(struct comedi_device *dev,
 387                                  const u8 *data, size_t size,
 388                                  unsigned long context)
 389{
 390        struct me_private_data *dev_private = dev->private;
 391        unsigned int value;
 392        unsigned int file_length;
 393        unsigned int i;
 394
 395        /* disable irq's on PLX */
 396        writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
 397
 398        /* First, make a dummy read to reset xilinx */
 399        value = readw(dev_private->me_regbase + XILINX_DOWNLOAD_RESET);
 400
 401        /* Wait until reset is over */
 402        sleep(1);
 403
 404        /* Write a dummy value to Xilinx */
 405        writeb(0x00, dev_private->me_regbase + 0x0);
 406        sleep(1);
 407
 408        /*
 409         * Format of the firmware
 410         * Build longs from the byte-wise coded header
 411         * Byte 1-3:   length of the array
 412         * Byte 4-7:   version
 413         * Byte 8-11:  date
 414         * Byte 12-15: reserved
 415         */
 416        if (size < 16)
 417                return -EINVAL;
 418
 419        file_length = (((unsigned int)data[0] & 0xff) << 24) +
 420            (((unsigned int)data[1] & 0xff) << 16) +
 421            (((unsigned int)data[2] & 0xff) << 8) +
 422            ((unsigned int)data[3] & 0xff);
 423
 424        /*
 425         * Loop for writing firmware byte by byte to xilinx
 426         * Firmware data start at offset 16
 427         */
 428        for (i = 0; i < file_length; i++)
 429                writeb((data[16 + i] & 0xff),
 430                       dev_private->me_regbase + 0x0);
 431
 432        /* Write 5 dummy values to xilinx */
 433        for (i = 0; i < 5; i++)
 434                writeb(0x00, dev_private->me_regbase + 0x0);
 435
 436        /* Test if there was an error during download -> INTB was thrown */
 437        value = readl(dev_private->plx_regbase + PLX9052_INTCSR);
 438        if (value & PLX9052_INTCSR_LI2STAT) {
 439                /* Disable interrupt */
 440                writel(0x00, dev_private->plx_regbase + PLX9052_INTCSR);
 441                dev_err(dev->class_dev, "Xilinx download failed\n");
 442                return -EIO;
 443        }
 444
 445        /* Wait until the Xilinx is ready for real work */
 446        sleep(1);
 447
 448        /* Enable PLX-Interrupts */
 449        writel(PLX9052_INTCSR_LI1ENAB |
 450               PLX9052_INTCSR_LI1POL |
 451               PLX9052_INTCSR_PCIENAB,
 452               dev_private->plx_regbase + PLX9052_INTCSR);
 453
 454        return 0;
 455}
 456
 457static int me_reset(struct comedi_device *dev)
 458{
 459        struct me_private_data *dev_private = dev->private;
 460
 461        /* Reset board */
 462        writew(0x00, dev_private->me_regbase + ME_CONTROL_1);
 463        writew(0x00, dev_private->me_regbase + ME_CONTROL_2);
 464        writew(0x00, dev_private->me_regbase + ME_RESET_INTERRUPT);
 465        writew(0x00, dev_private->me_regbase + ME_DAC_CONTROL);
 466
 467        /* Save values in the board context */
 468        dev_private->dac_control = 0;
 469        dev_private->control_1 = 0;
 470        dev_private->control_2 = 0;
 471
 472        return 0;
 473}
 474
 475static int me_auto_attach(struct comedi_device *dev,
 476                          unsigned long context)
 477{
 478        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 479        const struct me_board *board = NULL;
 480        struct me_private_data *dev_private;
 481        struct comedi_subdevice *s;
 482        int ret;
 483
 484        if (context < ARRAY_SIZE(me_boards))
 485                board = &me_boards[context];
 486        if (!board)
 487                return -ENODEV;
 488        dev->board_ptr = board;
 489        dev->board_name = board->name;
 490
 491        dev_private = comedi_alloc_devpriv(dev, sizeof(*dev_private));
 492        if (!dev_private)
 493                return -ENOMEM;
 494
 495        ret = comedi_pci_enable(dev);
 496        if (ret)
 497                return ret;
 498
 499        dev_private->plx_regbase = pci_ioremap_bar(pcidev, 0);
 500        if (!dev_private->plx_regbase)
 501                return -ENOMEM;
 502
 503        dev_private->me_regbase = pci_ioremap_bar(pcidev, 2);
 504        if (!dev_private->me_regbase)
 505                return -ENOMEM;
 506
 507        /* Download firmware and reset card */
 508        if (board->needs_firmware) {
 509                ret = comedi_load_firmware(dev, &comedi_to_pci_dev(dev)->dev,
 510                                           ME2600_FIRMWARE,
 511                                           me2600_xilinx_download, 0);
 512                if (ret < 0)
 513                        return ret;
 514        }
 515        me_reset(dev);
 516
 517        ret = comedi_alloc_subdevices(dev, 3);
 518        if (ret)
 519                return ret;
 520
 521        s = &dev->subdevices[0];
 522        s->type         = COMEDI_SUBD_AI;
 523        s->subdev_flags = SDF_READABLE | SDF_COMMON;
 524        s->n_chan       = 16;
 525        s->maxdata      = 0x0fff;
 526        s->len_chanlist = 16;
 527        s->range_table  = &me_ai_range;
 528        s->insn_read    = me_ai_insn_read;
 529
 530        s = &dev->subdevices[1];
 531        if (board->has_ao) {
 532                s->type         = COMEDI_SUBD_AO;
 533                s->subdev_flags = SDF_WRITEABLE | SDF_COMMON;
 534                s->n_chan       = 4;
 535                s->maxdata      = 0x0fff;
 536                s->len_chanlist = 4;
 537                s->range_table  = &me_ao_range;
 538                s->insn_read    = me_ao_insn_read;
 539                s->insn_write   = me_ao_insn_write;
 540        } else {
 541                s->type = COMEDI_SUBD_UNUSED;
 542        }
 543
 544        s = &dev->subdevices[2];
 545        s->type         = COMEDI_SUBD_DIO;
 546        s->subdev_flags = SDF_READABLE | SDF_WRITEABLE;
 547        s->n_chan       = 32;
 548        s->maxdata      = 1;
 549        s->len_chanlist = 32;
 550        s->range_table  = &range_digital;
 551        s->insn_bits    = me_dio_insn_bits;
 552        s->insn_config  = me_dio_insn_config;
 553
 554        return 0;
 555}
 556
 557static void me_detach(struct comedi_device *dev)
 558{
 559        struct me_private_data *dev_private = dev->private;
 560
 561        if (dev_private) {
 562                if (dev_private->me_regbase) {
 563                        me_reset(dev);
 564                        iounmap(dev_private->me_regbase);
 565                }
 566                if (dev_private->plx_regbase)
 567                        iounmap(dev_private->plx_regbase);
 568        }
 569        comedi_pci_disable(dev);
 570}
 571
 572static struct comedi_driver me_daq_driver = {
 573        .driver_name    = "me_daq",
 574        .module         = THIS_MODULE,
 575        .auto_attach    = me_auto_attach,
 576        .detach         = me_detach,
 577};
 578
 579static int me_daq_pci_probe(struct pci_dev *dev,
 580                            const struct pci_device_id *id)
 581{
 582        return comedi_pci_auto_config(dev, &me_daq_driver, id->driver_data);
 583}
 584
 585static const struct pci_device_id me_daq_pci_table[] = {
 586        { PCI_VDEVICE(MEILHAUS, 0x2600), BOARD_ME2600 },
 587        { PCI_VDEVICE(MEILHAUS, 0x2000), BOARD_ME2000 },
 588        { 0 }
 589};
 590MODULE_DEVICE_TABLE(pci, me_daq_pci_table);
 591
 592static struct pci_driver me_daq_pci_driver = {
 593        .name           = "me_daq",
 594        .id_table       = me_daq_pci_table,
 595        .probe          = me_daq_pci_probe,
 596        .remove         = comedi_pci_auto_unconfig,
 597};
 598module_comedi_pci_driver(me_daq_driver, me_daq_pci_driver);
 599
 600MODULE_AUTHOR("Comedi http://www.comedi.org");
 601MODULE_DESCRIPTION("Comedi low-level driver");
 602MODULE_LICENSE("GPL");
 603MODULE_FIRMWARE(ME2600_FIRMWARE);
 604
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