linux/drivers/staging/comedi/drivers/cb_pcidas64.c
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   1/*
   2    comedi/drivers/cb_pcidas64.c
   3    This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4    64xx, 60xx, and 4020 cards.
   5
   6    Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7    Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9    Thanks also go to the following people:
  10
  11    Steve Rosenbluth, for providing the source code for
  12    his pci-das6402 driver, and source code for working QNX pci-6402
  13    drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14    used directly here, but it was useful as an additional source of
  15    documentation on how to program the boards.
  16
  17    John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19    COMEDI - Linux Control and Measurement Device Interface
  20    Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22    This program is free software; you can redistribute it and/or modify
  23    it under the terms of the GNU General Public License as published by
  24    the Free Software Foundation; either version 2 of the License, or
  25    (at your option) any later version.
  26
  27    This program is distributed in the hope that it will be useful,
  28    but WITHOUT ANY WARRANTY; without even the implied warranty of
  29    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30    GNU General Public License for more details.
  31*/
  32
  33/*
  34 * Driver: cb_pcidas64
  35 * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36 *   with the PLX 9080 PCI controller
  37 * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38 * Status: works
  39 * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40 * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41 *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42 *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43 *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44 *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45 *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46 *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47 *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48 *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49 *
  50 * Configuration options:
  51 *   None.
  52 *
  53 * Manual attachment of PCI cards with the comedi_config utility is not
  54 * supported by this driver; they are attached automatically.
  55 *
  56 * These boards may be autocalibrated with the comedi_calibrate utility.
  57 *
  58 * To select the bnc trigger input on the 4020 (instead of the dio input),
  59 * specify a nonzero channel in the chanspec.  If you wish to use an external
  60 * master clock on the 4020, you may do so by setting the scan_begin_src
  61 * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62 * to configure the divisor to use for the external clock.
  63 *
  64 * Some devices are not identified because the PCI device IDs are not yet
  65 * known. If you have such a board, please let the maintainers know.
  66 */
  67
  68/*
  69
  70TODO:
  71        make it return error if user attempts an ai command that uses the
  72        external queue, and an ao command simultaneously user counter subdevice
  73        there are a number of boards this driver will support when they are
  74        fully released, but does not yet since the pci device id numbers
  75        are not yet available.
  76
  77        support prescaled 100khz clock for slow pacing (not available on 6000
  78        series?)
  79
  80        make ao fifo size adjustable like ai fifo
  81*/
  82
  83#include <linux/module.h>
  84#include <linux/pci.h>
  85#include <linux/delay.h>
  86#include <linux/interrupt.h>
  87
  88#include "../comedidev.h"
  89
  90#include "8253.h"
  91#include "8255.h"
  92#include "plx9080.h"
  93#include "comedi_fc.h"
  94
  95#define TIMER_BASE 25           /*  40MHz master clock */
  96/* 100kHz 'prescaled' clock for slow acquisition,
  97 * maybe I'll support this someday */
  98#define PRESCALED_TIMER_BASE    10000
  99#define DMA_BUFFER_SIZE 0x1000
 100
 101/* maximum value that can be loaded into board's 24-bit counters*/
 102static const int max_counter_value = 0xffffff;
 103
 104/* PCI-DAS64xxx base addresses */
 105
 106/* devpriv->main_iobase registers */
 107enum write_only_registers {
 108        INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 109        HW_CONFIG_REG = 0x2,    /*  hardware config register */
 110        DAQ_SYNC_REG = 0xc,
 111        DAQ_ATRIG_LOW_4020_REG = 0xc,
 112        ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 113        ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 114        CALIBRATION_REG = 0x14,
 115        /*  lower 16 bits of adc sample interval counter */
 116        ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 117        /*  upper 8 bits of adc sample interval counter */
 118        ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 119        /*  lower 16 bits of delay interval counter */
 120        ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 121        /*  upper 8 bits of delay interval counter */
 122        ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 123        /*  lower 16 bits of hardware conversion/scan counter */
 124        ADC_COUNT_LOWER_REG = 0x1e,
 125        /*  upper 8 bits of hardware conversion/scan counter */
 126        ADC_COUNT_UPPER_REG = 0x20,
 127        ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 128        ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 129        ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 130        ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 131        ADC_BUFFER_CLEAR_REG = 0x2a,
 132        /*  high channel for internal queue, use adc_chan_bits() inline above */
 133        ADC_QUEUE_HIGH_REG = 0x2c,
 134        DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 135        DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 136        /*  lower 16 bits of dac sample interval counter */
 137        DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 138        /*  upper 8 bits of dac sample interval counter */
 139        DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 140        DAC_SELECT_REG = 0x60,
 141        DAC_START_REG = 0x64,
 142        DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 143};
 144
 145static inline unsigned int dac_convert_reg(unsigned int channel)
 146{
 147        return 0x70 + (2 * (channel & 0x1));
 148}
 149
 150static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 151{
 152        return 0x70 + (4 * (channel & 0x1));
 153}
 154
 155static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 156{
 157        return 0x72 + (4 * (channel & 0x1));
 158}
 159
 160enum read_only_registers {
 161        /*  hardware status register,
 162         *  reading this apparently clears pending interrupts as well */
 163        HW_STATUS_REG = 0x0,
 164        PIPE1_READ_REG = 0x4,
 165        ADC_READ_PNTR_REG = 0x8,
 166        LOWER_XFER_REG = 0x10,
 167        ADC_WRITE_PNTR_REG = 0xc,
 168        PREPOST_REG = 0x14,
 169};
 170
 171enum read_write_registers {
 172        I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 173        /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 174        ADC_QUEUE_FIFO_REG = 0x100,
 175        ADC_FIFO_REG = 0x200,   /* adc data fifo */
 176        /* dac data fifo, has weird interactions with external channel queue */
 177        DAC_FIFO_REG = 0x300,
 178};
 179
 180/* dev->mmio registers */
 181enum dio_counter_registers {
 182        DIO_8255_OFFSET = 0x0,
 183        DO_REG = 0x20,
 184        DI_REG = 0x28,
 185        DIO_DIRECTION_60XX_REG = 0x40,
 186        DIO_DATA_60XX_REG = 0x48,
 187};
 188
 189/* bit definitions for write-only registers */
 190
 191enum intr_enable_contents {
 192        ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 193        ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 194        ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 195        ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 196        ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 197        EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 198        EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 199        DAC_INTR_SRC_MASK = 0x30,
 200        DAC_INTR_QEMPTY_BITS = 0x0,
 201        DAC_INTR_HIGH_CHAN_BITS = 0x10,
 202        EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 203        EN_DAC_DONE_INTR_BIT = 0x80,
 204        EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 205        EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 206        EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 207        EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 208        EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 209};
 210
 211enum hw_config_contents {
 212        MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 213        INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 214        BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 215        EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 216        EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 217        /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 218        SLOW_DAC_BIT = 0x400,
 219        /*  bit with unknown function yet given as default value in pci-das64
 220         *  manual */
 221        HW_CONFIG_DUMMY_BITS = 0x2000,
 222        /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 223        DMA_CH_SELECT_BIT = 0x8000,
 224        FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 225        DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 226        DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 227};
 228#define DAC_FIFO_SIZE 0x2000
 229
 230enum daq_atrig_low_4020_contents {
 231        /*  use trig/ext clk bnc input for analog gate signal */
 232        EXT_AGATE_BNC_BIT = 0x8000,
 233        /*  use trig/ext clk bnc input for external stop trigger signal */
 234        EXT_STOP_TRIG_BNC_BIT = 0x4000,
 235        /*  use trig/ext clk bnc input for external start trigger signal */
 236        EXT_START_TRIG_BNC_BIT = 0x2000,
 237};
 238
 239static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 240{
 241        return threshold & 0xfff;
 242}
 243
 244enum adc_control0_contents {
 245        ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 246        ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 247        ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 248        ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 249        ADC_GATE_LEVEL_BIT = 0x4,       /*  level-sensitive gate (for digital) */
 250        ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 251        ADC_START_TRIG_SOFT_BITS = 0x10,
 252        ADC_START_TRIG_EXT_BITS = 0x20,
 253        ADC_START_TRIG_ANALOG_BITS = 0x30,
 254        ADC_START_TRIG_MASK = 0x30,
 255        ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 256        /*  external pacing uses falling edge */
 257        ADC_EXT_CONV_FALLING_BIT = 0x800,
 258        /*  enable hardware scan counter */
 259        ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 260        ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 261        ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 262};
 263
 264enum adc_control1_contents {
 265        /*  should be set for boards with > 16 channels */
 266        ADC_QUEUE_CONFIG_BIT = 0x1,
 267        CONVERT_POLARITY_BIT = 0x10,
 268        EOC_POLARITY_BIT = 0x20,
 269        ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 270        ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 271        RETRIGGER_BIT = 0x800,
 272        ADC_LO_CHANNEL_4020_MASK = 0x300,
 273        ADC_HI_CHANNEL_4020_MASK = 0xc00,
 274        TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 275        FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 276        CHANNEL_MODE_4020_MASK = 0x3000,
 277        ADC_MODE_MASK = 0xf000,
 278};
 279
 280static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 281{
 282        return (channel & 0x3) << 8;
 283};
 284
 285static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 286{
 287        return (channel & 0x3) << 10;
 288};
 289
 290static inline uint16_t adc_mode_bits(unsigned int mode)
 291{
 292        return (mode & 0xf) << 12;
 293};
 294
 295enum calibration_contents {
 296        SELECT_8800_BIT = 0x1,
 297        SELECT_8402_64XX_BIT = 0x2,
 298        SELECT_1590_60XX_BIT = 0x2,
 299        CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 300        SERIAL_DATA_IN_BIT = 0x80,
 301        SERIAL_CLOCK_BIT = 0x100,
 302        CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 303        CAL_GAIN_BIT = 0x800,
 304};
 305
 306/* calibration sources for 6025 are:
 307 *  0 : ground
 308 *  1 : 10V
 309 *  2 : 5V
 310 *  3 : 0.5V
 311 *  4 : 0.05V
 312 *  5 : ground
 313 *  6 : dac channel 0
 314 *  7 : dac channel 1
 315 */
 316
 317static inline uint16_t adc_src_bits(unsigned int source)
 318{
 319        return (source & 0xf) << 3;
 320};
 321
 322static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 323{
 324        return (channel & 0x3) << 8;
 325};
 326
 327enum adc_queue_load_contents {
 328        UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 329        ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 330        /*  non-referenced single-ended (common-mode input) */
 331        ADC_COMMON_BIT = 0x2000,
 332        QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 333        QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 334};
 335
 336static inline uint16_t adc_chan_bits(unsigned int channel)
 337{
 338        return channel & 0x3f;
 339};
 340
 341enum dac_control0_contents {
 342        DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 343        DAC_CYCLIC_STOP_BIT = 0x4000,
 344        DAC_WAVEFORM_MODE_BIT = 0x100,
 345        DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 346        DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 347        WAVEFORM_TRIG_MASK = 0x30,
 348        WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 349        WAVEFORM_TRIG_SOFT_BITS = 0x10,
 350        WAVEFORM_TRIG_EXT_BITS = 0x20,
 351        WAVEFORM_TRIG_ADC1_BITS = 0x30,
 352        WAVEFORM_TRIG_FALLING_BIT = 0x8,
 353        WAVEFORM_GATE_LEVEL_BIT = 0x4,
 354        WAVEFORM_GATE_ENABLE_BIT = 0x2,
 355        WAVEFORM_GATE_SELECT_BIT = 0x1,
 356};
 357
 358enum dac_control1_contents {
 359        DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 360        DAC1_EXT_REF_BIT = 0x200,
 361        DAC0_EXT_REF_BIT = 0x100,
 362        DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 363        DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 364        DAC_SW_GATE_BIT = 0x20,
 365        DAC1_UNIPOLAR_BIT = 0x8,
 366        DAC0_UNIPOLAR_BIT = 0x2,
 367};
 368
 369/* bit definitions for read-only registers */
 370enum hw_status_contents {
 371        DAC_UNDERRUN_BIT = 0x1,
 372        ADC_OVERRUN_BIT = 0x2,
 373        DAC_ACTIVE_BIT = 0x4,
 374        ADC_ACTIVE_BIT = 0x8,
 375        DAC_INTR_PENDING_BIT = 0x10,
 376        ADC_INTR_PENDING_BIT = 0x20,
 377        DAC_DONE_BIT = 0x40,
 378        ADC_DONE_BIT = 0x80,
 379        EXT_INTR_PENDING_BIT = 0x100,
 380        ADC_STOP_BIT = 0x200,
 381};
 382
 383static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 384{
 385        return (hw_status_bits >> 10) & 0x3;
 386};
 387
 388static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 389{
 390        return (prepost_bits >> 6) & 0x3;
 391}
 392
 393static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 394{
 395        return (prepost_bits >> 12) & 0x3;
 396}
 397
 398static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 399{
 400        return (prepost_bits >> 14) & 0x3;
 401}
 402
 403/* I2C addresses for 4020 */
 404enum i2c_addresses {
 405        RANGE_CAL_I2C_ADDR = 0x20,
 406        CALDAC0_I2C_ADDR = 0xc,
 407        CALDAC1_I2C_ADDR = 0xd,
 408};
 409
 410enum range_cal_i2c_contents {
 411        /*  bits that set what source the adc converter measures */
 412        ADC_SRC_4020_MASK = 0x70,
 413        /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 414        BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 415};
 416
 417static inline uint8_t adc_src_4020_bits(unsigned int source)
 418{
 419        return (source << 4) & ADC_SRC_4020_MASK;
 420};
 421
 422static inline uint8_t attenuate_bit(unsigned int channel)
 423{
 424        /*  attenuate channel (+-5V input range) */
 425        return 1 << (channel & 0x3);
 426};
 427
 428/* analog input ranges for 64xx boards */
 429static const struct comedi_lrange ai_ranges_64xx = {
 430        8, {
 431                BIP_RANGE(10),
 432                BIP_RANGE(5),
 433                BIP_RANGE(2.5),
 434                BIP_RANGE(1.25),
 435                UNI_RANGE(10),
 436                UNI_RANGE(5),
 437                UNI_RANGE(2.5),
 438                UNI_RANGE(1.25)
 439        }
 440};
 441
 442/* analog input ranges for 60xx boards */
 443static const struct comedi_lrange ai_ranges_60xx = {
 444        4, {
 445                BIP_RANGE(10),
 446                BIP_RANGE(5),
 447                BIP_RANGE(0.5),
 448                BIP_RANGE(0.05)
 449        }
 450};
 451
 452/* analog input ranges for 6030, etc boards */
 453static const struct comedi_lrange ai_ranges_6030 = {
 454        14, {
 455                BIP_RANGE(10),
 456                BIP_RANGE(5),
 457                BIP_RANGE(2),
 458                BIP_RANGE(1),
 459                BIP_RANGE(0.5),
 460                BIP_RANGE(0.2),
 461                BIP_RANGE(0.1),
 462                UNI_RANGE(10),
 463                UNI_RANGE(5),
 464                UNI_RANGE(2),
 465                UNI_RANGE(1),
 466                UNI_RANGE(0.5),
 467                UNI_RANGE(0.2),
 468                UNI_RANGE(0.1)
 469        }
 470};
 471
 472/* analog input ranges for 6052, etc boards */
 473static const struct comedi_lrange ai_ranges_6052 = {
 474        15, {
 475                BIP_RANGE(10),
 476                BIP_RANGE(5),
 477                BIP_RANGE(2.5),
 478                BIP_RANGE(1),
 479                BIP_RANGE(0.5),
 480                BIP_RANGE(0.25),
 481                BIP_RANGE(0.1),
 482                BIP_RANGE(0.05),
 483                UNI_RANGE(10),
 484                UNI_RANGE(5),
 485                UNI_RANGE(2),
 486                UNI_RANGE(1),
 487                UNI_RANGE(0.5),
 488                UNI_RANGE(0.2),
 489                UNI_RANGE(0.1)
 490        }
 491};
 492
 493/* analog input ranges for 4020 board */
 494static const struct comedi_lrange ai_ranges_4020 = {
 495        2, {
 496                BIP_RANGE(5),
 497                BIP_RANGE(1)
 498        }
 499};
 500
 501/* analog output ranges */
 502static const struct comedi_lrange ao_ranges_64xx = {
 503        4, {
 504                BIP_RANGE(5),
 505                BIP_RANGE(10),
 506                UNI_RANGE(5),
 507                UNI_RANGE(10)
 508        }
 509};
 510
 511static const int ao_range_code_64xx[] = {
 512        0x0,
 513        0x1,
 514        0x2,
 515        0x3,
 516};
 517
 518static const int ao_range_code_60xx[] = {
 519        0x0,
 520};
 521
 522static const struct comedi_lrange ao_ranges_6030 = {
 523        2, {
 524                BIP_RANGE(10),
 525                UNI_RANGE(10)
 526        }
 527};
 528
 529static const int ao_range_code_6030[] = {
 530        0x0,
 531        0x2,
 532};
 533
 534static const struct comedi_lrange ao_ranges_4020 = {
 535        2, {
 536                BIP_RANGE(5),
 537                BIP_RANGE(10)
 538        }
 539};
 540
 541static const int ao_range_code_4020[] = {
 542        0x1,
 543        0x0,
 544};
 545
 546enum register_layout {
 547        LAYOUT_60XX,
 548        LAYOUT_64XX,
 549        LAYOUT_4020,
 550};
 551
 552struct hw_fifo_info {
 553        unsigned int num_segments;
 554        unsigned int max_segment_length;
 555        unsigned int sample_packing_ratio;
 556        uint16_t fifo_size_reg_mask;
 557};
 558
 559enum pcidas64_boardid {
 560        BOARD_PCIDAS6402_16,
 561        BOARD_PCIDAS6402_12,
 562        BOARD_PCIDAS64_M1_16,
 563        BOARD_PCIDAS64_M2_16,
 564        BOARD_PCIDAS64_M3_16,
 565        BOARD_PCIDAS6013,
 566        BOARD_PCIDAS6014,
 567        BOARD_PCIDAS6023,
 568        BOARD_PCIDAS6025,
 569        BOARD_PCIDAS6030,
 570        BOARD_PCIDAS6031,
 571        BOARD_PCIDAS6032,
 572        BOARD_PCIDAS6033,
 573        BOARD_PCIDAS6034,
 574        BOARD_PCIDAS6035,
 575        BOARD_PCIDAS6036,
 576        BOARD_PCIDAS6040,
 577        BOARD_PCIDAS6052,
 578        BOARD_PCIDAS6070,
 579        BOARD_PCIDAS6071,
 580        BOARD_PCIDAS4020_12,
 581        BOARD_PCIDAS6402_16_JR,
 582        BOARD_PCIDAS64_M1_16_JR,
 583        BOARD_PCIDAS64_M2_16_JR,
 584        BOARD_PCIDAS64_M3_16_JR,
 585        BOARD_PCIDAS64_M1_14,
 586        BOARD_PCIDAS64_M2_14,
 587        BOARD_PCIDAS64_M3_14,
 588};
 589
 590struct pcidas64_board {
 591        const char *name;
 592        int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 593        int ai_bits;            /*  analog input resolution */
 594        int ai_speed;           /*  fastest conversion period in ns */
 595        const struct comedi_lrange *ai_range_table;
 596        int ao_nchan;           /*  number of analog out channels */
 597        int ao_bits;            /*  analog output resolution */
 598        int ao_scan_speed;      /*  analog output scan speed */
 599        const struct comedi_lrange *ao_range_table;
 600        const int *ao_range_code;
 601        const struct hw_fifo_info *const ai_fifo;
 602        /*  different board families have slightly different registers */
 603        enum register_layout layout;
 604        unsigned has_8255:1;
 605};
 606
 607static const struct hw_fifo_info ai_fifo_4020 = {
 608        .num_segments = 2,
 609        .max_segment_length = 0x8000,
 610        .sample_packing_ratio = 2,
 611        .fifo_size_reg_mask = 0x7f,
 612};
 613
 614static const struct hw_fifo_info ai_fifo_64xx = {
 615        .num_segments = 4,
 616        .max_segment_length = 0x800,
 617        .sample_packing_ratio = 1,
 618        .fifo_size_reg_mask = 0x3f,
 619};
 620
 621static const struct hw_fifo_info ai_fifo_60xx = {
 622        .num_segments = 4,
 623        .max_segment_length = 0x800,
 624        .sample_packing_ratio = 1,
 625        .fifo_size_reg_mask = 0x7f,
 626};
 627
 628/* maximum number of dma transfers we will chain together into a ring
 629 * (and the maximum number of dma buffers we maintain) */
 630#define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 631#define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 632#define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 633static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 634{
 635        if (board->layout == LAYOUT_4020)
 636                return MAX_AI_DMA_RING_COUNT;
 637
 638        return MIN_AI_DMA_RING_COUNT;
 639}
 640
 641static const int bytes_in_sample = 2;
 642
 643static const struct pcidas64_board pcidas64_boards[] = {
 644        [BOARD_PCIDAS6402_16] = {
 645                .name           = "pci-das6402/16",
 646                .ai_se_chans    = 64,
 647                .ai_bits        = 16,
 648                .ai_speed       = 5000,
 649                .ao_nchan       = 2,
 650                .ao_bits        = 16,
 651                .ao_scan_speed  = 10000,
 652                .layout         = LAYOUT_64XX,
 653                .ai_range_table = &ai_ranges_64xx,
 654                .ao_range_table = &ao_ranges_64xx,
 655                .ao_range_code  = ao_range_code_64xx,
 656                .ai_fifo        = &ai_fifo_64xx,
 657                .has_8255       = 1,
 658        },
 659        [BOARD_PCIDAS6402_12] = {
 660                .name           = "pci-das6402/12",     /*  XXX check */
 661                .ai_se_chans    = 64,
 662                .ai_bits        = 12,
 663                .ai_speed       = 5000,
 664                .ao_nchan       = 2,
 665                .ao_bits        = 12,
 666                .ao_scan_speed  = 10000,
 667                .layout         = LAYOUT_64XX,
 668                .ai_range_table = &ai_ranges_64xx,
 669                .ao_range_table = &ao_ranges_64xx,
 670                .ao_range_code  = ao_range_code_64xx,
 671                .ai_fifo        = &ai_fifo_64xx,
 672                .has_8255       = 1,
 673        },
 674        [BOARD_PCIDAS64_M1_16] = {
 675                .name           = "pci-das64/m1/16",
 676                .ai_se_chans    = 64,
 677                .ai_bits        = 16,
 678                .ai_speed       = 1000,
 679                .ao_nchan       = 2,
 680                .ao_bits        = 16,
 681                .ao_scan_speed  = 10000,
 682                .layout         = LAYOUT_64XX,
 683                .ai_range_table = &ai_ranges_64xx,
 684                .ao_range_table = &ao_ranges_64xx,
 685                .ao_range_code  = ao_range_code_64xx,
 686                .ai_fifo        = &ai_fifo_64xx,
 687                .has_8255       = 1,
 688        },
 689        [BOARD_PCIDAS64_M2_16] = {
 690                .name = "pci-das64/m2/16",
 691                .ai_se_chans    = 64,
 692                .ai_bits        = 16,
 693                .ai_speed       = 500,
 694                .ao_nchan       = 2,
 695                .ao_bits        = 16,
 696                .ao_scan_speed  = 10000,
 697                .layout         = LAYOUT_64XX,
 698                .ai_range_table = &ai_ranges_64xx,
 699                .ao_range_table = &ao_ranges_64xx,
 700                .ao_range_code  = ao_range_code_64xx,
 701                .ai_fifo        = &ai_fifo_64xx,
 702                .has_8255       = 1,
 703        },
 704        [BOARD_PCIDAS64_M3_16] = {
 705                .name           = "pci-das64/m3/16",
 706                .ai_se_chans    = 64,
 707                .ai_bits        = 16,
 708                .ai_speed       = 333,
 709                .ao_nchan       = 2,
 710                .ao_bits        = 16,
 711                .ao_scan_speed  = 10000,
 712                .layout         = LAYOUT_64XX,
 713                .ai_range_table = &ai_ranges_64xx,
 714                .ao_range_table = &ao_ranges_64xx,
 715                .ao_range_code  = ao_range_code_64xx,
 716                .ai_fifo        = &ai_fifo_64xx,
 717                .has_8255       = 1,
 718        },
 719        [BOARD_PCIDAS6013] = {
 720                .name           = "pci-das6013",
 721                .ai_se_chans    = 16,
 722                .ai_bits        = 16,
 723                .ai_speed       = 5000,
 724                .ao_nchan       = 0,
 725                .ao_bits        = 16,
 726                .layout         = LAYOUT_60XX,
 727                .ai_range_table = &ai_ranges_60xx,
 728                .ao_range_table = &range_bipolar10,
 729                .ao_range_code  = ao_range_code_60xx,
 730                .ai_fifo        = &ai_fifo_60xx,
 731                .has_8255       = 0,
 732        },
 733        [BOARD_PCIDAS6014] = {
 734                .name           = "pci-das6014",
 735                .ai_se_chans    = 16,
 736                .ai_bits        = 16,
 737                .ai_speed       = 5000,
 738                .ao_nchan       = 2,
 739                .ao_bits        = 16,
 740                .ao_scan_speed  = 100000,
 741                .layout         = LAYOUT_60XX,
 742                .ai_range_table = &ai_ranges_60xx,
 743                .ao_range_table = &range_bipolar10,
 744                .ao_range_code  = ao_range_code_60xx,
 745                .ai_fifo        = &ai_fifo_60xx,
 746                .has_8255       = 0,
 747        },
 748        [BOARD_PCIDAS6023] = {
 749                .name           = "pci-das6023",
 750                .ai_se_chans    = 16,
 751                .ai_bits        = 12,
 752                .ai_speed       = 5000,
 753                .ao_nchan       = 0,
 754                .ao_scan_speed  = 100000,
 755                .layout         = LAYOUT_60XX,
 756                .ai_range_table = &ai_ranges_60xx,
 757                .ao_range_table = &range_bipolar10,
 758                .ao_range_code  = ao_range_code_60xx,
 759                .ai_fifo        = &ai_fifo_60xx,
 760                .has_8255       = 1,
 761        },
 762        [BOARD_PCIDAS6025] = {
 763                .name           = "pci-das6025",
 764                .ai_se_chans    = 16,
 765                .ai_bits        = 12,
 766                .ai_speed       = 5000,
 767                .ao_nchan       = 2,
 768                .ao_bits        = 12,
 769                .ao_scan_speed  = 100000,
 770                .layout         = LAYOUT_60XX,
 771                .ai_range_table = &ai_ranges_60xx,
 772                .ao_range_table = &range_bipolar10,
 773                .ao_range_code  = ao_range_code_60xx,
 774                .ai_fifo        = &ai_fifo_60xx,
 775                .has_8255       = 1,
 776        },
 777        [BOARD_PCIDAS6030] = {
 778                .name           = "pci-das6030",
 779                .ai_se_chans    = 16,
 780                .ai_bits        = 16,
 781                .ai_speed       = 10000,
 782                .ao_nchan       = 2,
 783                .ao_bits        = 16,
 784                .ao_scan_speed  = 10000,
 785                .layout         = LAYOUT_60XX,
 786                .ai_range_table = &ai_ranges_6030,
 787                .ao_range_table = &ao_ranges_6030,
 788                .ao_range_code  = ao_range_code_6030,
 789                .ai_fifo        = &ai_fifo_60xx,
 790                .has_8255       = 0,
 791        },
 792        [BOARD_PCIDAS6031] = {
 793                .name           = "pci-das6031",
 794                .ai_se_chans    = 64,
 795                .ai_bits        = 16,
 796                .ai_speed       = 10000,
 797                .ao_nchan       = 2,
 798                .ao_bits        = 16,
 799                .ao_scan_speed  = 10000,
 800                .layout         = LAYOUT_60XX,
 801                .ai_range_table = &ai_ranges_6030,
 802                .ao_range_table = &ao_ranges_6030,
 803                .ao_range_code  = ao_range_code_6030,
 804                .ai_fifo        = &ai_fifo_60xx,
 805                .has_8255       = 0,
 806        },
 807        [BOARD_PCIDAS6032] = {
 808                .name           = "pci-das6032",
 809                .ai_se_chans    = 16,
 810                .ai_bits        = 16,
 811                .ai_speed       = 10000,
 812                .ao_nchan       = 0,
 813                .layout         = LAYOUT_60XX,
 814                .ai_range_table = &ai_ranges_6030,
 815                .ai_fifo        = &ai_fifo_60xx,
 816                .has_8255       = 0,
 817        },
 818        [BOARD_PCIDAS6033] = {
 819                .name           = "pci-das6033",
 820                .ai_se_chans    = 64,
 821                .ai_bits        = 16,
 822                .ai_speed       = 10000,
 823                .ao_nchan       = 0,
 824                .layout         = LAYOUT_60XX,
 825                .ai_range_table = &ai_ranges_6030,
 826                .ai_fifo        = &ai_fifo_60xx,
 827                .has_8255       = 0,
 828        },
 829        [BOARD_PCIDAS6034] = {
 830                .name           = "pci-das6034",
 831                .ai_se_chans    = 16,
 832                .ai_bits        = 16,
 833                .ai_speed       = 5000,
 834                .ao_nchan       = 0,
 835                .ao_scan_speed  = 0,
 836                .layout         = LAYOUT_60XX,
 837                .ai_range_table = &ai_ranges_60xx,
 838                .ai_fifo        = &ai_fifo_60xx,
 839                .has_8255       = 0,
 840        },
 841        [BOARD_PCIDAS6035] = {
 842                .name           = "pci-das6035",
 843                .ai_se_chans    = 16,
 844                .ai_bits        = 16,
 845                .ai_speed       = 5000,
 846                .ao_nchan       = 2,
 847                .ao_bits        = 12,
 848                .ao_scan_speed  = 100000,
 849                .layout         = LAYOUT_60XX,
 850                .ai_range_table = &ai_ranges_60xx,
 851                .ao_range_table = &range_bipolar10,
 852                .ao_range_code  = ao_range_code_60xx,
 853                .ai_fifo        = &ai_fifo_60xx,
 854                .has_8255       = 0,
 855        },
 856        [BOARD_PCIDAS6036] = {
 857                .name           = "pci-das6036",
 858                .ai_se_chans    = 16,
 859                .ai_bits        = 16,
 860                .ai_speed       = 5000,
 861                .ao_nchan       = 2,
 862                .ao_bits        = 16,
 863                .ao_scan_speed  = 100000,
 864                .layout         = LAYOUT_60XX,
 865                .ai_range_table = &ai_ranges_60xx,
 866                .ao_range_table = &range_bipolar10,
 867                .ao_range_code  = ao_range_code_60xx,
 868                .ai_fifo        = &ai_fifo_60xx,
 869                .has_8255       = 0,
 870        },
 871        [BOARD_PCIDAS6040] = {
 872                .name           = "pci-das6040",
 873                .ai_se_chans    = 16,
 874                .ai_bits        = 12,
 875                .ai_speed       = 2000,
 876                .ao_nchan       = 2,
 877                .ao_bits        = 12,
 878                .ao_scan_speed  = 1000,
 879                .layout         = LAYOUT_60XX,
 880                .ai_range_table = &ai_ranges_6052,
 881                .ao_range_table = &ao_ranges_6030,
 882                .ao_range_code  = ao_range_code_6030,
 883                .ai_fifo        = &ai_fifo_60xx,
 884                .has_8255       = 0,
 885        },
 886        [BOARD_PCIDAS6052] = {
 887                .name           = "pci-das6052",
 888                .ai_se_chans    = 16,
 889                .ai_bits        = 16,
 890                .ai_speed       = 3333,
 891                .ao_nchan       = 2,
 892                .ao_bits        = 16,
 893                .ao_scan_speed  = 3333,
 894                .layout         = LAYOUT_60XX,
 895                .ai_range_table = &ai_ranges_6052,
 896                .ao_range_table = &ao_ranges_6030,
 897                .ao_range_code  = ao_range_code_6030,
 898                .ai_fifo        = &ai_fifo_60xx,
 899                .has_8255       = 0,
 900        },
 901        [BOARD_PCIDAS6070] = {
 902                .name           = "pci-das6070",
 903                .ai_se_chans    = 16,
 904                .ai_bits        = 12,
 905                .ai_speed       = 800,
 906                .ao_nchan       = 2,
 907                .ao_bits        = 12,
 908                .ao_scan_speed  = 1000,
 909                .layout         = LAYOUT_60XX,
 910                .ai_range_table = &ai_ranges_6052,
 911                .ao_range_table = &ao_ranges_6030,
 912                .ao_range_code  = ao_range_code_6030,
 913                .ai_fifo        = &ai_fifo_60xx,
 914                .has_8255       = 0,
 915        },
 916        [BOARD_PCIDAS6071] = {
 917                .name           = "pci-das6071",
 918                .ai_se_chans    = 64,
 919                .ai_bits        = 12,
 920                .ai_speed       = 800,
 921                .ao_nchan       = 2,
 922                .ao_bits        = 12,
 923                .ao_scan_speed  = 1000,
 924                .layout         = LAYOUT_60XX,
 925                .ai_range_table = &ai_ranges_6052,
 926                .ao_range_table = &ao_ranges_6030,
 927                .ao_range_code  = ao_range_code_6030,
 928                .ai_fifo        = &ai_fifo_60xx,
 929                .has_8255       = 0,
 930        },
 931        [BOARD_PCIDAS4020_12] = {
 932                .name           = "pci-das4020/12",
 933                .ai_se_chans    = 4,
 934                .ai_bits        = 12,
 935                .ai_speed       = 50,
 936                .ao_bits        = 12,
 937                .ao_nchan       = 2,
 938                .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
 939                .layout         = LAYOUT_4020,
 940                .ai_range_table = &ai_ranges_4020,
 941                .ao_range_table = &ao_ranges_4020,
 942                .ao_range_code  = ao_range_code_4020,
 943                .ai_fifo        = &ai_fifo_4020,
 944                .has_8255       = 1,
 945        },
 946#if 0
 947        /*
 948         * The device id for these boards is unknown
 949         */
 950
 951        [BOARD_PCIDAS6402_16_JR] = {
 952                .name           = "pci-das6402/16/jr",
 953                .ai_se_chans    = 64,
 954                .ai_bits        = 16,
 955                .ai_speed       = 5000,
 956                .ao_nchan       = 0,
 957                .ao_scan_speed  = 10000,
 958                .layout         = LAYOUT_64XX,
 959                .ai_range_table = &ai_ranges_64xx,
 960                .ai_fifo        = ai_fifo_64xx,
 961                .has_8255       = 1,
 962        },
 963        [BOARD_PCIDAS64_M1_16_JR] = {
 964                .name           = "pci-das64/m1/16/jr",
 965                .ai_se_chans    = 64,
 966                .ai_bits        = 16,
 967                .ai_speed       = 1000,
 968                .ao_nchan       = 0,
 969                .ao_scan_speed  = 10000,
 970                .layout         = LAYOUT_64XX,
 971                .ai_range_table = &ai_ranges_64xx,
 972                .ai_fifo        = ai_fifo_64xx,
 973                .has_8255       = 1,
 974        },
 975        [BOARD_PCIDAS64_M2_16_JR] = {
 976                .name = "pci-das64/m2/16/jr",
 977                .ai_se_chans    = 64,
 978                .ai_bits        = 16,
 979                .ai_speed       = 500,
 980                .ao_nchan       = 0,
 981                .ao_scan_speed  = 10000,
 982                .layout         = LAYOUT_64XX,
 983                .ai_range_table = &ai_ranges_64xx,
 984                .ai_fifo        = ai_fifo_64xx,
 985                .has_8255       = 1,
 986        },
 987        [BOARD_PCIDAS64_M3_16_JR] = {
 988                .name           = "pci-das64/m3/16/jr",
 989                .ai_se_chans    = 64,
 990                .ai_bits        = 16,
 991                .ai_speed       = 333,
 992                .ao_nchan       = 0,
 993                .ao_scan_speed  = 10000,
 994                .layout         = LAYOUT_64XX,
 995                .ai_range_table = &ai_ranges_64xx,
 996                .ai_fifo        = ai_fifo_64xx,
 997                .has_8255       = 1,
 998        },
 999        [BOARD_PCIDAS64_M1_14] = {
1000                .name           = "pci-das64/m1/14",
1001                .ai_se_chans    = 64,
1002                .ai_bits        = 14,
1003                .ai_speed       = 1000,
1004                .ao_nchan       = 2,
1005                .ao_scan_speed  = 10000,
1006                .layout         = LAYOUT_64XX,
1007                .ai_range_table = &ai_ranges_64xx,
1008                .ai_fifo        = ai_fifo_64xx,
1009                .has_8255       = 1,
1010        },
1011        [BOARD_PCIDAS64_M2_14] = {
1012                .name           = "pci-das64/m2/14",
1013                .ai_se_chans    = 64,
1014                .ai_bits        = 14,
1015                .ai_speed       = 500,
1016                .ao_nchan       = 2,
1017                .ao_scan_speed  = 10000,
1018                .layout         = LAYOUT_64XX,
1019                .ai_range_table = &ai_ranges_64xx,
1020                .ai_fifo        = ai_fifo_64xx,
1021                .has_8255       = 1,
1022        },
1023        [BOARD_PCIDAS64_M3_14] = {
1024                .name           = "pci-das64/m3/14",
1025                .ai_se_chans    = 64,
1026                .ai_bits        = 14,
1027                .ai_speed       = 333,
1028                .ao_nchan       = 2,
1029                .ao_scan_speed  = 10000,
1030                .layout         = LAYOUT_64XX,
1031                .ai_range_table = &ai_ranges_64xx,
1032                .ai_fifo        = ai_fifo_64xx,
1033                .has_8255       = 1,
1034        },
1035#endif
1036};
1037
1038static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1039                                              int use_differential)
1040{
1041        const struct pcidas64_board *thisboard = dev->board_ptr;
1042
1043        if ((thisboard->layout == LAYOUT_64XX && !use_differential) ||
1044            (thisboard->layout == LAYOUT_60XX && use_differential))
1045                return ADC_SE_DIFF_BIT;
1046
1047        return 0;
1048}
1049
1050struct ext_clock_info {
1051        /*  master clock divisor to use for scans with external master clock */
1052        unsigned int divisor;
1053        /*  chanspec for master clock input when used as scan begin src */
1054        unsigned int chanspec;
1055};
1056
1057/* this structure is for data unique to this hardware driver. */
1058struct pcidas64_private {
1059        /*  base addresses (physical) */
1060        resource_size_t main_phys_iobase;
1061        resource_size_t dio_counter_phys_iobase;
1062        /*  base addresses (ioremapped) */
1063        void __iomem *plx9080_iobase;
1064        void __iomem *main_iobase;
1065        /*  local address (used by dma controller) */
1066        uint32_t local0_iobase;
1067        uint32_t local1_iobase;
1068        /*  dma buffers for analog input */
1069        uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1070        /*  physical addresses of ai dma buffers */
1071        dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1072        /*  array of ai dma descriptors read by plx9080,
1073         *  allocated to get proper alignment */
1074        struct plx_dma_desc *ai_dma_desc;
1075        /*  physical address of ai dma descriptor array */
1076        dma_addr_t ai_dma_desc_bus_addr;
1077        /*  index of the ai dma descriptor/buffer
1078         *  that is currently being used */
1079        unsigned int ai_dma_index;
1080        /*  dma buffers for analog output */
1081        uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1082        /*  physical addresses of ao dma buffers */
1083        dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1084        struct plx_dma_desc *ao_dma_desc;
1085        dma_addr_t ao_dma_desc_bus_addr;
1086        /*  keeps track of buffer where the next ao sample should go */
1087        unsigned int ao_dma_index;
1088        unsigned int hw_revision;       /*  stc chip hardware revision number */
1089        /*  last bits sent to INTR_ENABLE_REG register */
1090        unsigned int intr_enable_bits;
1091        /*  last bits sent to ADC_CONTROL1_REG register */
1092        uint16_t adc_control1_bits;
1093        /*  last bits sent to FIFO_SIZE_REG register */
1094        uint16_t fifo_size_bits;
1095        /*  last bits sent to HW_CONFIG_REG register */
1096        uint16_t hw_config_bits;
1097        uint16_t dac_control1_bits;
1098        /*  last bits written to plx9080 control register */
1099        uint32_t plx_control_bits;
1100        /*  last bits written to plx interrupt control and status register */
1101        uint32_t plx_intcsr_bits;
1102        /*  index of calibration source readable through ai ch0 */
1103        int calibration_source;
1104        /*  bits written to i2c calibration/range register */
1105        uint8_t i2c_cal_range_bits;
1106        /*  configure digital triggers to trigger on falling edge */
1107        unsigned int ext_trig_falling;
1108        short ai_cmd_running;
1109        unsigned int ai_fifo_segment_length;
1110        struct ext_clock_info ext_clock;
1111        unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1112};
1113
1114static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1115                                       unsigned int range_index)
1116{
1117        const struct pcidas64_board *thisboard = dev->board_ptr;
1118        const struct comedi_krange *range =
1119                &thisboard->ai_range_table->range[range_index];
1120        unsigned int bits = 0;
1121
1122        switch (range->max) {
1123        case 10000000:
1124                bits = 0x000;
1125                break;
1126        case 5000000:
1127                bits = 0x100;
1128                break;
1129        case 2000000:
1130        case 2500000:
1131                bits = 0x200;
1132                break;
1133        case 1000000:
1134        case 1250000:
1135                bits = 0x300;
1136                break;
1137        case 500000:
1138                bits = 0x400;
1139                break;
1140        case 200000:
1141        case 250000:
1142                bits = 0x500;
1143                break;
1144        case 100000:
1145                bits = 0x600;
1146                break;
1147        case 50000:
1148                bits = 0x700;
1149                break;
1150        default:
1151                dev_err(dev->class_dev, "bug! in %s\n", __func__);
1152                break;
1153        }
1154        if (range->min == 0)
1155                bits += 0x900;
1156        return bits;
1157}
1158
1159static unsigned int hw_revision(const struct comedi_device *dev,
1160                                uint16_t hw_status_bits)
1161{
1162        const struct pcidas64_board *thisboard = dev->board_ptr;
1163
1164        if (thisboard->layout == LAYOUT_4020)
1165                return (hw_status_bits >> 13) & 0x7;
1166
1167        return (hw_status_bits >> 12) & 0xf;
1168}
1169
1170static void set_dac_range_bits(struct comedi_device *dev,
1171                               uint16_t *bits, unsigned int channel,
1172                               unsigned int range)
1173{
1174        const struct pcidas64_board *thisboard = dev->board_ptr;
1175        unsigned int code = thisboard->ao_range_code[range];
1176
1177        if (channel > 1)
1178                dev_err(dev->class_dev, "bug! bad channel?\n");
1179        if (code & ~0x3)
1180                dev_err(dev->class_dev, "bug! bad range code?\n");
1181
1182        *bits &= ~(0x3 << (2 * channel));
1183        *bits |= code << (2 * channel);
1184};
1185
1186static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1187{
1188        return board->ao_nchan && board->layout != LAYOUT_4020;
1189}
1190
1191static void abort_dma(struct comedi_device *dev, unsigned int channel)
1192{
1193        struct pcidas64_private *devpriv = dev->private;
1194        unsigned long flags;
1195
1196        /*  spinlock for plx dma control/status reg */
1197        spin_lock_irqsave(&dev->spinlock, flags);
1198
1199        plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1200
1201        spin_unlock_irqrestore(&dev->spinlock, flags);
1202}
1203
1204static void disable_plx_interrupts(struct comedi_device *dev)
1205{
1206        struct pcidas64_private *devpriv = dev->private;
1207
1208        devpriv->plx_intcsr_bits = 0;
1209        writel(devpriv->plx_intcsr_bits,
1210               devpriv->plx9080_iobase + PLX_INTRCS_REG);
1211}
1212
1213static void disable_ai_interrupts(struct comedi_device *dev)
1214{
1215        struct pcidas64_private *devpriv = dev->private;
1216        unsigned long flags;
1217
1218        spin_lock_irqsave(&dev->spinlock, flags);
1219        devpriv->intr_enable_bits &=
1220                ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1221                ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1222                ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1223        writew(devpriv->intr_enable_bits,
1224               devpriv->main_iobase + INTR_ENABLE_REG);
1225        spin_unlock_irqrestore(&dev->spinlock, flags);
1226}
1227
1228static void enable_ai_interrupts(struct comedi_device *dev,
1229                                 const struct comedi_cmd *cmd)
1230{
1231        const struct pcidas64_board *thisboard = dev->board_ptr;
1232        struct pcidas64_private *devpriv = dev->private;
1233        uint32_t bits;
1234        unsigned long flags;
1235
1236        bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1237               EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1238        /*  Use pio transfer and interrupt on end of conversion
1239         *  if CMDF_WAKE_EOS flag is set. */
1240        if (cmd->flags & CMDF_WAKE_EOS) {
1241                /*  4020 doesn't support pio transfers except for fifo dregs */
1242                if (thisboard->layout != LAYOUT_4020)
1243                        bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1244        }
1245        spin_lock_irqsave(&dev->spinlock, flags);
1246        devpriv->intr_enable_bits |= bits;
1247        writew(devpriv->intr_enable_bits,
1248               devpriv->main_iobase + INTR_ENABLE_REG);
1249        spin_unlock_irqrestore(&dev->spinlock, flags);
1250}
1251
1252/* initialize plx9080 chip */
1253static void init_plx9080(struct comedi_device *dev)
1254{
1255        const struct pcidas64_board *thisboard = dev->board_ptr;
1256        struct pcidas64_private *devpriv = dev->private;
1257        uint32_t bits;
1258        void __iomem *plx_iobase = devpriv->plx9080_iobase;
1259
1260        devpriv->plx_control_bits =
1261                readl(devpriv->plx9080_iobase + PLX_CONTROL_REG);
1262
1263#ifdef __BIG_ENDIAN
1264        bits = BIGEND_DMA0 | BIGEND_DMA1;
1265#else
1266        bits = 0;
1267#endif
1268        writel(bits, devpriv->plx9080_iobase + PLX_BIGEND_REG);
1269
1270        disable_plx_interrupts(dev);
1271
1272        abort_dma(dev, 0);
1273        abort_dma(dev, 1);
1274
1275        /*  configure dma0 mode */
1276        bits = 0;
1277        /*  enable ready input, not sure if this is necessary */
1278        bits |= PLX_DMA_EN_READYIN_BIT;
1279        /*  enable bterm, not sure if this is necessary */
1280        bits |= PLX_EN_BTERM_BIT;
1281        /*  enable dma chaining */
1282        bits |= PLX_EN_CHAIN_BIT;
1283        /*  enable interrupt on dma done
1284         *  (probably don't need this, since chain never finishes) */
1285        bits |= PLX_EN_DMA_DONE_INTR_BIT;
1286        /*  don't increment local address during transfers
1287         *  (we are transferring from a fixed fifo register) */
1288        bits |= PLX_LOCAL_ADDR_CONST_BIT;
1289        /*  route dma interrupt to pci bus */
1290        bits |= PLX_DMA_INTR_PCI_BIT;
1291        /*  enable demand mode */
1292        bits |= PLX_DEMAND_MODE_BIT;
1293        /*  enable local burst mode */
1294        bits |= PLX_DMA_LOCAL_BURST_EN_BIT;
1295        /*  4020 uses 32 bit dma */
1296        if (thisboard->layout == LAYOUT_4020)
1297                bits |= PLX_LOCAL_BUS_32_WIDE_BITS;
1298        else            /*  localspace0 bus is 16 bits wide */
1299                bits |= PLX_LOCAL_BUS_16_WIDE_BITS;
1300        writel(bits, plx_iobase + PLX_DMA1_MODE_REG);
1301        if (ao_cmd_is_supported(thisboard))
1302                writel(bits, plx_iobase + PLX_DMA0_MODE_REG);
1303
1304        /*  enable interrupts on plx 9080 */
1305        devpriv->plx_intcsr_bits |=
1306            ICS_AERR | ICS_PERR | ICS_PIE | ICS_PLIE | ICS_PAIE | ICS_LIE |
1307            ICS_DMA0_E | ICS_DMA1_E;
1308        writel(devpriv->plx_intcsr_bits,
1309               devpriv->plx9080_iobase + PLX_INTRCS_REG);
1310}
1311
1312static void disable_ai_pacing(struct comedi_device *dev)
1313{
1314        struct pcidas64_private *devpriv = dev->private;
1315        unsigned long flags;
1316
1317        disable_ai_interrupts(dev);
1318
1319        spin_lock_irqsave(&dev->spinlock, flags);
1320        devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1321        writew(devpriv->adc_control1_bits,
1322               devpriv->main_iobase + ADC_CONTROL1_REG);
1323        spin_unlock_irqrestore(&dev->spinlock, flags);
1324
1325        /* disable pacing, triggering, etc */
1326        writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1327               devpriv->main_iobase + ADC_CONTROL0_REG);
1328}
1329
1330static int set_ai_fifo_segment_length(struct comedi_device *dev,
1331                                      unsigned int num_entries)
1332{
1333        const struct pcidas64_board *thisboard = dev->board_ptr;
1334        struct pcidas64_private *devpriv = dev->private;
1335        static const int increment_size = 0x100;
1336        const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1337        unsigned int num_increments;
1338        uint16_t bits;
1339
1340        if (num_entries < increment_size)
1341                num_entries = increment_size;
1342        if (num_entries > fifo->max_segment_length)
1343                num_entries = fifo->max_segment_length;
1344
1345        /*  1 == 256 entries, 2 == 512 entries, etc */
1346        num_increments = (num_entries + increment_size / 2) / increment_size;
1347
1348        bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1349        devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1350        devpriv->fifo_size_bits |= bits;
1351        writew(devpriv->fifo_size_bits,
1352               devpriv->main_iobase + FIFO_SIZE_REG);
1353
1354        devpriv->ai_fifo_segment_length = num_increments * increment_size;
1355
1356        return devpriv->ai_fifo_segment_length;
1357}
1358
1359/* adjusts the size of hardware fifo (which determines block size for dma xfers) */
1360static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1361{
1362        const struct pcidas64_board *thisboard = dev->board_ptr;
1363        unsigned int num_fifo_entries;
1364        int retval;
1365        const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1366
1367        num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1368
1369        retval = set_ai_fifo_segment_length(dev,
1370                                            num_fifo_entries /
1371                                            fifo->num_segments);
1372        if (retval < 0)
1373                return retval;
1374
1375        num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1376
1377        return num_samples;
1378}
1379
1380/* query length of fifo */
1381static unsigned int ai_fifo_size(struct comedi_device *dev)
1382{
1383        const struct pcidas64_board *thisboard = dev->board_ptr;
1384        struct pcidas64_private *devpriv = dev->private;
1385
1386        return devpriv->ai_fifo_segment_length *
1387               thisboard->ai_fifo->num_segments *
1388               thisboard->ai_fifo->sample_packing_ratio;
1389}
1390
1391static void init_stc_registers(struct comedi_device *dev)
1392{
1393        const struct pcidas64_board *thisboard = dev->board_ptr;
1394        struct pcidas64_private *devpriv = dev->private;
1395        uint16_t bits;
1396        unsigned long flags;
1397
1398        spin_lock_irqsave(&dev->spinlock, flags);
1399
1400        /*  bit should be set for 6025,
1401         *  although docs say boards with <= 16 chans should be cleared XXX */
1402        if (1)
1403                devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1404        writew(devpriv->adc_control1_bits,
1405               devpriv->main_iobase + ADC_CONTROL1_REG);
1406
1407        /*  6402/16 manual says this register must be initialized to 0xff? */
1408        writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1409
1410        bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1411        if (thisboard->layout == LAYOUT_4020)
1412                bits |= INTERNAL_CLOCK_4020_BITS;
1413        devpriv->hw_config_bits |= bits;
1414        writew(devpriv->hw_config_bits,
1415               devpriv->main_iobase + HW_CONFIG_REG);
1416
1417        writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1418        writew(0, devpriv->main_iobase + CALIBRATION_REG);
1419
1420        spin_unlock_irqrestore(&dev->spinlock, flags);
1421
1422        /*  set fifos to maximum size */
1423        devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1424        set_ai_fifo_segment_length(dev,
1425                                   thisboard->ai_fifo->max_segment_length);
1426
1427        devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1428        devpriv->intr_enable_bits =
1429                /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1430                EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1431        writew(devpriv->intr_enable_bits,
1432               devpriv->main_iobase + INTR_ENABLE_REG);
1433
1434        disable_ai_pacing(dev);
1435};
1436
1437static int alloc_and_init_dma_members(struct comedi_device *dev)
1438{
1439        const struct pcidas64_board *thisboard = dev->board_ptr;
1440        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1441        struct pcidas64_private *devpriv = dev->private;
1442        int i;
1443
1444        /*  allocate pci dma buffers */
1445        for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1446                devpriv->ai_buffer[i] =
1447                        pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1448                                             &devpriv->ai_buffer_bus_addr[i]);
1449                if (devpriv->ai_buffer[i] == NULL)
1450                        return -ENOMEM;
1451
1452        }
1453        for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1454                if (ao_cmd_is_supported(thisboard)) {
1455                        devpriv->ao_buffer[i] =
1456                                pci_alloc_consistent(pcidev, DMA_BUFFER_SIZE,
1457                                                     &devpriv->
1458                                                      ao_buffer_bus_addr[i]);
1459                        if (devpriv->ao_buffer[i] == NULL)
1460                                return -ENOMEM;
1461
1462                }
1463        }
1464        /*  allocate dma descriptors */
1465        devpriv->ai_dma_desc =
1466                pci_alloc_consistent(pcidev, sizeof(struct plx_dma_desc) *
1467                                     ai_dma_ring_count(thisboard),
1468                                     &devpriv->ai_dma_desc_bus_addr);
1469        if (devpriv->ai_dma_desc == NULL)
1470                return -ENOMEM;
1471
1472        if (ao_cmd_is_supported(thisboard)) {
1473                devpriv->ao_dma_desc =
1474                        pci_alloc_consistent(pcidev,
1475                                             sizeof(struct plx_dma_desc) *
1476                                             AO_DMA_RING_COUNT,
1477                                             &devpriv->ao_dma_desc_bus_addr);
1478                if (devpriv->ao_dma_desc == NULL)
1479                        return -ENOMEM;
1480        }
1481        /*  initialize dma descriptors */
1482        for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1483                devpriv->ai_dma_desc[i].pci_start_addr =
1484                        cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1485                if (thisboard->layout == LAYOUT_4020)
1486                        devpriv->ai_dma_desc[i].local_start_addr =
1487                                cpu_to_le32(devpriv->local1_iobase +
1488                                            ADC_FIFO_REG);
1489                else
1490                        devpriv->ai_dma_desc[i].local_start_addr =
1491                                cpu_to_le32(devpriv->local0_iobase +
1492                                            ADC_FIFO_REG);
1493                devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1494                devpriv->ai_dma_desc[i].next =
1495                        cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1496                                     ((i + 1) % ai_dma_ring_count(thisboard)) *
1497                                     sizeof(devpriv->ai_dma_desc[0])) |
1498                                    PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT |
1499                                    PLX_XFER_LOCAL_TO_PCI);
1500        }
1501        if (ao_cmd_is_supported(thisboard)) {
1502                for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1503                        devpriv->ao_dma_desc[i].pci_start_addr =
1504                                cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1505                        devpriv->ao_dma_desc[i].local_start_addr =
1506                                cpu_to_le32(devpriv->local0_iobase +
1507                                            DAC_FIFO_REG);
1508                        devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1509                        devpriv->ao_dma_desc[i].next =
1510                                cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1511                                             ((i + 1) % (AO_DMA_RING_COUNT)) *
1512                                             sizeof(devpriv->ao_dma_desc[0])) |
1513                                            PLX_DESC_IN_PCI_BIT |
1514                                            PLX_INTR_TERM_COUNT);
1515                }
1516        }
1517        return 0;
1518}
1519
1520static void cb_pcidas64_free_dma(struct comedi_device *dev)
1521{
1522        const struct pcidas64_board *thisboard = dev->board_ptr;
1523        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1524        struct pcidas64_private *devpriv = dev->private;
1525        int i;
1526
1527        if (!devpriv)
1528                return;
1529
1530        /* free pci dma buffers */
1531        for (i = 0; i < ai_dma_ring_count(thisboard); i++) {
1532                if (devpriv->ai_buffer[i])
1533                        pci_free_consistent(pcidev,
1534                                            DMA_BUFFER_SIZE,
1535                                            devpriv->ai_buffer[i],
1536                                            devpriv->ai_buffer_bus_addr[i]);
1537        }
1538        for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1539                if (devpriv->ao_buffer[i])
1540                        pci_free_consistent(pcidev,
1541                                            DMA_BUFFER_SIZE,
1542                                            devpriv->ao_buffer[i],
1543                                            devpriv->ao_buffer_bus_addr[i]);
1544        }
1545        /* free dma descriptors */
1546        if (devpriv->ai_dma_desc)
1547                pci_free_consistent(pcidev,
1548                                    sizeof(struct plx_dma_desc) *
1549                                    ai_dma_ring_count(thisboard),
1550                                    devpriv->ai_dma_desc,
1551                                    devpriv->ai_dma_desc_bus_addr);
1552        if (devpriv->ao_dma_desc)
1553                pci_free_consistent(pcidev,
1554                                    sizeof(struct plx_dma_desc) *
1555                                    AO_DMA_RING_COUNT,
1556                                    devpriv->ao_dma_desc,
1557                                    devpriv->ao_dma_desc_bus_addr);
1558}
1559
1560static inline void warn_external_queue(struct comedi_device *dev)
1561{
1562        dev_err(dev->class_dev,
1563                "AO command and AI external channel queue cannot be used simultaneously\n");
1564        dev_err(dev->class_dev,
1565                "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1566}
1567
1568/* Their i2c requires a huge delay on setting clock or data high for some reason */
1569static const int i2c_high_udelay = 1000;
1570static const int i2c_low_udelay = 10;
1571
1572/* set i2c data line high or low */
1573static void i2c_set_sda(struct comedi_device *dev, int state)
1574{
1575        struct pcidas64_private *devpriv = dev->private;
1576        static const int data_bit = CTL_EE_W;
1577        void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1578                                         PLX_CONTROL_REG;
1579
1580        if (state) {
1581                /*  set data line high */
1582                devpriv->plx_control_bits &= ~data_bit;
1583                writel(devpriv->plx_control_bits, plx_control_addr);
1584                udelay(i2c_high_udelay);
1585        } else {                /*  set data line low */
1586
1587                devpriv->plx_control_bits |= data_bit;
1588                writel(devpriv->plx_control_bits, plx_control_addr);
1589                udelay(i2c_low_udelay);
1590        }
1591}
1592
1593/* set i2c clock line high or low */
1594static void i2c_set_scl(struct comedi_device *dev, int state)
1595{
1596        struct pcidas64_private *devpriv = dev->private;
1597        static const int clock_bit = CTL_USERO;
1598        void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1599                                         PLX_CONTROL_REG;
1600
1601        if (state) {
1602                /*  set clock line high */
1603                devpriv->plx_control_bits &= ~clock_bit;
1604                writel(devpriv->plx_control_bits, plx_control_addr);
1605                udelay(i2c_high_udelay);
1606        } else {                /*  set clock line low */
1607
1608                devpriv->plx_control_bits |= clock_bit;
1609                writel(devpriv->plx_control_bits, plx_control_addr);
1610                udelay(i2c_low_udelay);
1611        }
1612}
1613
1614static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1615{
1616        uint8_t bit;
1617        unsigned int num_bits = 8;
1618
1619        for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1620                i2c_set_scl(dev, 0);
1621                if ((byte & bit))
1622                        i2c_set_sda(dev, 1);
1623                else
1624                        i2c_set_sda(dev, 0);
1625                i2c_set_scl(dev, 1);
1626        }
1627}
1628
1629/* we can't really read the lines, so fake it */
1630static int i2c_read_ack(struct comedi_device *dev)
1631{
1632        i2c_set_scl(dev, 0);
1633        i2c_set_sda(dev, 1);
1634        i2c_set_scl(dev, 1);
1635
1636        return 0;               /*  return fake acknowledge bit */
1637}
1638
1639/* send start bit */
1640static void i2c_start(struct comedi_device *dev)
1641{
1642        i2c_set_scl(dev, 1);
1643        i2c_set_sda(dev, 1);
1644        i2c_set_sda(dev, 0);
1645}
1646
1647/* send stop bit */
1648static void i2c_stop(struct comedi_device *dev)
1649{
1650        i2c_set_scl(dev, 0);
1651        i2c_set_sda(dev, 0);
1652        i2c_set_scl(dev, 1);
1653        i2c_set_sda(dev, 1);
1654}
1655
1656static void i2c_write(struct comedi_device *dev, unsigned int address,
1657                      const uint8_t *data, unsigned int length)
1658{
1659        struct pcidas64_private *devpriv = dev->private;
1660        unsigned int i;
1661        uint8_t bitstream;
1662        static const int read_bit = 0x1;
1663
1664        /* XXX need mutex to prevent simultaneous attempts to access
1665         * eeprom and i2c bus */
1666
1667        /*  make sure we dont send anything to eeprom */
1668        devpriv->plx_control_bits &= ~CTL_EE_CS;
1669
1670        i2c_stop(dev);
1671        i2c_start(dev);
1672
1673        /*  send address and write bit */
1674        bitstream = (address << 1) & ~read_bit;
1675        i2c_write_byte(dev, bitstream);
1676
1677        /*  get acknowledge */
1678        if (i2c_read_ack(dev) != 0) {
1679                dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1680                        __func__);
1681                i2c_stop(dev);
1682                return;
1683        }
1684        /*  write data bytes */
1685        for (i = 0; i < length; i++) {
1686                i2c_write_byte(dev, data[i]);
1687                if (i2c_read_ack(dev) != 0) {
1688                        dev_err(dev->class_dev, "%s failed: no acknowledge\n",
1689                                __func__);
1690                        i2c_stop(dev);
1691                        return;
1692                }
1693        }
1694        i2c_stop(dev);
1695}
1696
1697static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1698                              struct comedi_subdevice *s,
1699                              struct comedi_insn *insn,
1700                              unsigned long context)
1701{
1702        const struct pcidas64_board *thisboard = dev->board_ptr;
1703        struct pcidas64_private *devpriv = dev->private;
1704        unsigned int status;
1705
1706        status = readw(devpriv->main_iobase + HW_STATUS_REG);
1707        if (thisboard->layout == LAYOUT_4020) {
1708                status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1709                if (status)
1710                        return 0;
1711        } else {
1712                if (pipe_full_bits(status))
1713                        return 0;
1714        }
1715        return -EBUSY;
1716}
1717
1718static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1719                    struct comedi_insn *insn, unsigned int *data)
1720{
1721        const struct pcidas64_board *thisboard = dev->board_ptr;
1722        struct pcidas64_private *devpriv = dev->private;
1723        unsigned int bits = 0, n;
1724        unsigned int channel, range, aref;
1725        unsigned long flags;
1726        int ret;
1727
1728        channel = CR_CHAN(insn->chanspec);
1729        range = CR_RANGE(insn->chanspec);
1730        aref = CR_AREF(insn->chanspec);
1731
1732        /*  disable card's analog input interrupt sources and pacing */
1733        /*  4020 generates dac done interrupts even though they are disabled */
1734        disable_ai_pacing(dev);
1735
1736        spin_lock_irqsave(&dev->spinlock, flags);
1737        if (insn->chanspec & CR_ALT_FILTER)
1738                devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1739        else
1740                devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1741        writew(devpriv->adc_control1_bits,
1742               devpriv->main_iobase + ADC_CONTROL1_REG);
1743        spin_unlock_irqrestore(&dev->spinlock, flags);
1744
1745        if (thisboard->layout != LAYOUT_4020) {
1746                /*  use internal queue */
1747                devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1748                writew(devpriv->hw_config_bits,
1749                       devpriv->main_iobase + HW_CONFIG_REG);
1750
1751                /*  ALT_SOURCE is internal calibration reference */
1752                if (insn->chanspec & CR_ALT_SOURCE) {
1753                        unsigned int cal_en_bit;
1754
1755                        if (thisboard->layout == LAYOUT_60XX)
1756                                cal_en_bit = CAL_EN_60XX_BIT;
1757                        else
1758                                cal_en_bit = CAL_EN_64XX_BIT;
1759                        /*  select internal reference source to connect
1760                         *  to channel 0 */
1761                        writew(cal_en_bit |
1762                               adc_src_bits(devpriv->calibration_source),
1763                               devpriv->main_iobase + CALIBRATION_REG);
1764                } else {
1765                        /*  make sure internal calibration source
1766                         *  is turned off */
1767                        writew(0, devpriv->main_iobase + CALIBRATION_REG);
1768                }
1769                /*  load internal queue */
1770                bits = 0;
1771                /*  set gain */
1772                bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1773                /*  set single-ended / differential */
1774                bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1775                if (aref == AREF_COMMON)
1776                        bits |= ADC_COMMON_BIT;
1777                bits |= adc_chan_bits(channel);
1778                /*  set stop channel */
1779                writew(adc_chan_bits(channel),
1780                       devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1781                /*  set start channel, and rest of settings */
1782                writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1783        } else {
1784                uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1785
1786                devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1787                if (insn->chanspec & CR_ALT_SOURCE) {
1788                        devpriv->i2c_cal_range_bits |=
1789                                adc_src_4020_bits(devpriv->calibration_source);
1790                } else {        /* select BNC inputs */
1791                        devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1792                }
1793                /*  select range */
1794                if (range == 0)
1795                        devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1796                else
1797                        devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1798                /*  update calibration/range i2c register only if necessary,
1799                 *  as it is very slow */
1800                if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1801                        uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1802
1803                        i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1804                                  sizeof(i2c_data));
1805                }
1806
1807                /* 4020 manual asks that sample interval register to be set
1808                 * before writing to convert register.
1809                 * Using somewhat arbitrary setting of 4 master clock ticks
1810                 * = 0.1 usec */
1811                writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1812                writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1813        }
1814
1815        for (n = 0; n < insn->n; n++) {
1816
1817                /*  clear adc buffer (inside loop for 4020 sake) */
1818                writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1819
1820                /* trigger conversion, bits sent only matter for 4020 */
1821                writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1822                       devpriv->main_iobase + ADC_CONVERT_REG);
1823
1824                /*  wait for data */
1825                ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1826                if (ret)
1827                        return ret;
1828
1829                if (thisboard->layout == LAYOUT_4020)
1830                        data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1831                else
1832                        data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1833        }
1834
1835        return n;
1836}
1837
1838static int ai_config_calibration_source(struct comedi_device *dev,
1839                                        unsigned int *data)
1840{
1841        const struct pcidas64_board *thisboard = dev->board_ptr;
1842        struct pcidas64_private *devpriv = dev->private;
1843        unsigned int source = data[1];
1844        int num_calibration_sources;
1845
1846        if (thisboard->layout == LAYOUT_60XX)
1847                num_calibration_sources = 16;
1848        else
1849                num_calibration_sources = 8;
1850        if (source >= num_calibration_sources) {
1851                dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1852                        source);
1853                return -EINVAL;
1854        }
1855
1856        devpriv->calibration_source = source;
1857
1858        return 2;
1859}
1860
1861static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1862{
1863        const struct pcidas64_board *thisboard = dev->board_ptr;
1864        int fifo_size;
1865        const struct hw_fifo_info *const fifo = thisboard->ai_fifo;
1866        unsigned int block_size, requested_block_size;
1867        int retval;
1868
1869        requested_block_size = data[1];
1870
1871        if (requested_block_size) {
1872                fifo_size = requested_block_size * fifo->num_segments /
1873                            bytes_in_sample;
1874
1875                retval = set_ai_fifo_size(dev, fifo_size);
1876                if (retval < 0)
1877                        return retval;
1878
1879        }
1880
1881        block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1882
1883        data[1] = block_size;
1884
1885        return 2;
1886}
1887
1888static int ai_config_master_clock_4020(struct comedi_device *dev,
1889                                       unsigned int *data)
1890{
1891        struct pcidas64_private *devpriv = dev->private;
1892        unsigned int divisor = data[4];
1893        int retval = 0;
1894
1895        if (divisor < 2) {
1896                divisor = 2;
1897                retval = -EAGAIN;
1898        }
1899
1900        switch (data[1]) {
1901        case COMEDI_EV_SCAN_BEGIN:
1902                devpriv->ext_clock.divisor = divisor;
1903                devpriv->ext_clock.chanspec = data[2];
1904                break;
1905        default:
1906                return -EINVAL;
1907        }
1908
1909        data[4] = divisor;
1910
1911        return retval ? retval : 5;
1912}
1913
1914/* XXX could add support for 60xx series */
1915static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1916{
1917        const struct pcidas64_board *thisboard = dev->board_ptr;
1918
1919        switch (thisboard->layout) {
1920        case LAYOUT_4020:
1921                return ai_config_master_clock_4020(dev, data);
1922        default:
1923                return -EINVAL;
1924        }
1925
1926        return -EINVAL;
1927}
1928
1929static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1930                          struct comedi_insn *insn, unsigned int *data)
1931{
1932        int id = data[0];
1933
1934        switch (id) {
1935        case INSN_CONFIG_ALT_SOURCE:
1936                return ai_config_calibration_source(dev, data);
1937        case INSN_CONFIG_BLOCK_SIZE:
1938                return ai_config_block_size(dev, data);
1939        case INSN_CONFIG_TIMER_1:
1940                return ai_config_master_clock(dev, data);
1941        default:
1942                return -EINVAL;
1943        }
1944        return -EINVAL;
1945}
1946
1947/* Gets nearest achievable timing given master clock speed, does not
1948 * take into account possible minimum/maximum divisor values.  Used
1949 * by other timing checking functions. */
1950static unsigned int get_divisor(unsigned int ns, unsigned int flags)
1951{
1952        unsigned int divisor;
1953
1954        switch (flags & CMDF_ROUND_MASK) {
1955        case CMDF_ROUND_UP:
1956                divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
1957                break;
1958        case CMDF_ROUND_DOWN:
1959                divisor = ns / TIMER_BASE;
1960                break;
1961        case CMDF_ROUND_NEAREST:
1962        default:
1963                divisor = (ns + TIMER_BASE / 2) / TIMER_BASE;
1964                break;
1965        }
1966        return divisor;
1967}
1968
1969/* utility function that rounds desired timing to an achievable time, and
1970 * sets cmd members appropriately.
1971 * adc paces conversions from master clock by dividing by (x + 3) where x is 24 bit number
1972 */
1973static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
1974{
1975        const struct pcidas64_board *thisboard = dev->board_ptr;
1976        unsigned int convert_divisor = 0, scan_divisor;
1977        static const int min_convert_divisor = 3;
1978        static const int max_convert_divisor =
1979                max_counter_value + min_convert_divisor;
1980        static const int min_scan_divisor_4020 = 2;
1981        unsigned long long max_scan_divisor, min_scan_divisor;
1982
1983        if (cmd->convert_src == TRIG_TIMER) {
1984                if (thisboard->layout == LAYOUT_4020) {
1985                        cmd->convert_arg = 0;
1986                } else {
1987                        convert_divisor = get_divisor(cmd->convert_arg,
1988                                                      cmd->flags);
1989                        if (convert_divisor > max_convert_divisor)
1990                                convert_divisor = max_convert_divisor;
1991                        if (convert_divisor < min_convert_divisor)
1992                                convert_divisor = min_convert_divisor;
1993                        cmd->convert_arg = convert_divisor * TIMER_BASE;
1994                }
1995        } else if (cmd->convert_src == TRIG_NOW) {
1996                cmd->convert_arg = 0;
1997        }
1998
1999        if (cmd->scan_begin_src == TRIG_TIMER) {
2000                scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2001                if (cmd->convert_src == TRIG_TIMER) {
2002                        /*  XXX check for integer overflows */
2003                        min_scan_divisor = convert_divisor * cmd->chanlist_len;
2004                        max_scan_divisor =
2005                                (convert_divisor * cmd->chanlist_len - 1) +
2006                                max_counter_value;
2007                } else {
2008                        min_scan_divisor = min_scan_divisor_4020;
2009                        max_scan_divisor = max_counter_value + min_scan_divisor;
2010                }
2011                if (scan_divisor > max_scan_divisor)
2012                        scan_divisor = max_scan_divisor;
2013                if (scan_divisor < min_scan_divisor)
2014                        scan_divisor = min_scan_divisor;
2015                cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2016        }
2017}
2018
2019static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2020                                         struct comedi_subdevice *s,
2021                                         struct comedi_cmd *cmd)
2022{
2023        const struct pcidas64_board *board = dev->board_ptr;
2024        unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2025        int i;
2026
2027        for (i = 1; i < cmd->chanlist_len; i++) {
2028                unsigned int aref = CR_AREF(cmd->chanlist[i]);
2029
2030                if (aref != aref0) {
2031                        dev_dbg(dev->class_dev,
2032                                "all elements in chanlist must use the same analog reference\n");
2033                        return -EINVAL;
2034                }
2035        }
2036
2037        if (board->layout == LAYOUT_4020) {
2038                unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2039
2040                for (i = 1; i < cmd->chanlist_len; i++) {
2041                        unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2042
2043                        if (chan != (chan0 + i)) {
2044                                dev_dbg(dev->class_dev,
2045                                        "chanlist must use consecutive channels\n");
2046                                return -EINVAL;
2047                        }
2048                }
2049                if (cmd->chanlist_len == 3) {
2050                        dev_dbg(dev->class_dev,
2051                                "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2052                        return -EINVAL;
2053                }
2054        }
2055
2056        return 0;
2057}
2058
2059static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2060                      struct comedi_cmd *cmd)
2061{
2062        const struct pcidas64_board *thisboard = dev->board_ptr;
2063        int err = 0;
2064        unsigned int tmp_arg, tmp_arg2;
2065        unsigned int triggers;
2066
2067        /* Step 1 : check if triggers are trivially valid */
2068
2069        err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2070
2071        triggers = TRIG_TIMER;
2072        if (thisboard->layout == LAYOUT_4020)
2073                triggers |= TRIG_OTHER;
2074        else
2075                triggers |= TRIG_FOLLOW;
2076        err |= cfc_check_trigger_src(&cmd->scan_begin_src, triggers);
2077
2078        triggers = TRIG_TIMER;
2079        if (thisboard->layout == LAYOUT_4020)
2080                triggers |= TRIG_NOW;
2081        else
2082                triggers |= TRIG_EXT;
2083        err |= cfc_check_trigger_src(&cmd->convert_src, triggers);
2084        err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2085        err |= cfc_check_trigger_src(&cmd->stop_src,
2086                                     TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2087
2088        if (err)
2089                return 1;
2090
2091        /* Step 2a : make sure trigger sources are unique */
2092
2093        err |= cfc_check_trigger_is_unique(cmd->start_src);
2094        err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
2095        err |= cfc_check_trigger_is_unique(cmd->convert_src);
2096        err |= cfc_check_trigger_is_unique(cmd->stop_src);
2097
2098        /* Step 2b : and mutually compatible */
2099
2100        if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2101                err |= -EINVAL;
2102
2103        if (err)
2104                return 2;
2105
2106        /* Step 3: check if arguments are trivially valid */
2107
2108        switch (cmd->start_src) {
2109        case TRIG_NOW:
2110                err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
2111                break;
2112        case TRIG_EXT:
2113                /*
2114                 * start_arg is the CR_CHAN | CR_INVERT of the
2115                 * external trigger.
2116                 */
2117                break;
2118        }
2119
2120        if (cmd->convert_src == TRIG_TIMER) {
2121                if (thisboard->layout == LAYOUT_4020) {
2122                        err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
2123                } else {
2124                        err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
2125                                                         thisboard->ai_speed);
2126                        /* if scans are timed faster than conversion rate allows */
2127                        if (cmd->scan_begin_src == TRIG_TIMER)
2128                                err |= cfc_check_trigger_arg_min(
2129                                                &cmd->scan_begin_arg,
2130                                                cmd->convert_arg *
2131                                                cmd->chanlist_len);
2132                }
2133        }
2134
2135        err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
2136        err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
2137
2138        switch (cmd->stop_src) {
2139        case TRIG_EXT:
2140                break;
2141        case TRIG_COUNT:
2142                err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
2143                break;
2144        case TRIG_NONE:
2145                err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
2146                break;
2147        default:
2148                break;
2149        }
2150
2151        if (err)
2152                return 3;
2153
2154        /* step 4: fix up any arguments */
2155
2156        if (cmd->convert_src == TRIG_TIMER) {
2157                tmp_arg = cmd->convert_arg;
2158                tmp_arg2 = cmd->scan_begin_arg;
2159                check_adc_timing(dev, cmd);
2160                if (tmp_arg != cmd->convert_arg)
2161                        err++;
2162                if (tmp_arg2 != cmd->scan_begin_arg)
2163                        err++;
2164        }
2165
2166        if (err)
2167                return 4;
2168
2169        /* Step 5: check channel list if it exists */
2170        if (cmd->chanlist && cmd->chanlist_len > 0)
2171                err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2172
2173        if (err)
2174                return 5;
2175
2176        return 0;
2177}
2178
2179static int use_hw_sample_counter(struct comedi_cmd *cmd)
2180{
2181/* disable for now until I work out a race */
2182        return 0;
2183
2184        if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2185                return 1;
2186
2187        return 0;
2188}
2189
2190static void setup_sample_counters(struct comedi_device *dev,
2191                                  struct comedi_cmd *cmd)
2192{
2193        struct pcidas64_private *devpriv = dev->private;
2194
2195        /*  load hardware conversion counter */
2196        if (use_hw_sample_counter(cmd)) {
2197                writew(cmd->stop_arg & 0xffff,
2198                       devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2199                writew((cmd->stop_arg >> 16) & 0xff,
2200                       devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2201        } else {
2202                writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2203        }
2204}
2205
2206static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2207{
2208        const struct pcidas64_board *thisboard = dev->board_ptr;
2209        struct pcidas64_private *devpriv = dev->private;
2210        unsigned int num_samples;
2211
2212        num_samples = devpriv->ai_fifo_segment_length *
2213                      thisboard->ai_fifo->sample_packing_ratio;
2214        if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2215                num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2216
2217        return num_samples;
2218}
2219
2220static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2221                                        const struct comedi_cmd *cmd)
2222{
2223        /*  supposed to load counter with desired divisor minus 3 */
2224        return cmd->convert_arg / TIMER_BASE - 3;
2225}
2226
2227static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2228                                     struct comedi_cmd *cmd)
2229{
2230        uint32_t count;
2231
2232        /*  figure out how long we need to delay at end of scan */
2233        switch (cmd->scan_begin_src) {
2234        case TRIG_TIMER:
2235                count = (cmd->scan_begin_arg -
2236                         (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2237                        TIMER_BASE;
2238                break;
2239        case TRIG_FOLLOW:
2240                count = cmd->convert_arg / TIMER_BASE;
2241                break;
2242        default:
2243                return 0;
2244        }
2245        return count - 3;
2246}
2247
2248static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2249                                        struct comedi_cmd *cmd)
2250{
2251        struct pcidas64_private *devpriv = dev->private;
2252        unsigned int divisor;
2253
2254        switch (cmd->scan_begin_src) {
2255        case TRIG_TIMER:
2256                divisor = cmd->scan_begin_arg / TIMER_BASE;
2257                break;
2258        case TRIG_OTHER:
2259                divisor = devpriv->ext_clock.divisor;
2260                break;
2261        default:                /*  should never happen */
2262                dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2263                divisor = 1000;
2264                break;
2265        }
2266
2267        /*  supposed to load counter with desired divisor minus 2 for 4020 */
2268        return divisor - 2;
2269}
2270
2271static void select_master_clock_4020(struct comedi_device *dev,
2272                                     const struct comedi_cmd *cmd)
2273{
2274        struct pcidas64_private *devpriv = dev->private;
2275
2276        /*  select internal/external master clock */
2277        devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2278        if (cmd->scan_begin_src == TRIG_OTHER) {
2279                int chanspec = devpriv->ext_clock.chanspec;
2280
2281                if (CR_CHAN(chanspec))
2282                        devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2283                else
2284                        devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2285        } else {
2286                devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2287        }
2288        writew(devpriv->hw_config_bits,
2289               devpriv->main_iobase + HW_CONFIG_REG);
2290}
2291
2292static void select_master_clock(struct comedi_device *dev,
2293                                const struct comedi_cmd *cmd)
2294{
2295        const struct pcidas64_board *thisboard = dev->board_ptr;
2296
2297        switch (thisboard->layout) {
2298        case LAYOUT_4020:
2299                select_master_clock_4020(dev, cmd);
2300                break;
2301        default:
2302                break;
2303        }
2304}
2305
2306static inline void dma_start_sync(struct comedi_device *dev,
2307                                  unsigned int channel)
2308{
2309        struct pcidas64_private *devpriv = dev->private;
2310        unsigned long flags;
2311
2312        /*  spinlock for plx dma control/status reg */
2313        spin_lock_irqsave(&dev->spinlock, flags);
2314        if (channel)
2315                writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2316                       PLX_CLEAR_DMA_INTR_BIT,
2317                       devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2318        else
2319                writeb(PLX_DMA_EN_BIT | PLX_DMA_START_BIT |
2320                       PLX_CLEAR_DMA_INTR_BIT,
2321                       devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2322        spin_unlock_irqrestore(&dev->spinlock, flags);
2323}
2324
2325static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2326{
2327        const struct pcidas64_board *thisboard = dev->board_ptr;
2328        struct pcidas64_private *devpriv = dev->private;
2329        uint32_t convert_counter = 0, scan_counter = 0;
2330
2331        check_adc_timing(dev, cmd);
2332
2333        select_master_clock(dev, cmd);
2334
2335        if (thisboard->layout == LAYOUT_4020) {
2336                convert_counter = ai_convert_counter_4020(dev, cmd);
2337        } else {
2338                convert_counter = ai_convert_counter_6xxx(dev, cmd);
2339                scan_counter = ai_scan_counter_6xxx(dev, cmd);
2340        }
2341
2342        /*  load lower 16 bits of convert interval */
2343        writew(convert_counter & 0xffff,
2344               devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2345        /*  load upper 8 bits of convert interval */
2346        writew((convert_counter >> 16) & 0xff,
2347               devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2348        /*  load lower 16 bits of scan delay */
2349        writew(scan_counter & 0xffff,
2350               devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2351        /*  load upper 8 bits of scan delay */
2352        writew((scan_counter >> 16) & 0xff,
2353               devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2354}
2355
2356static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2357{
2358        int i;
2359
2360        for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2361                if (CR_CHAN(cmd->chanlist[i + 1]) !=
2362                    CR_CHAN(cmd->chanlist[i]) + 1)
2363                        return 0;
2364                if (CR_RANGE(cmd->chanlist[i + 1]) !=
2365                    CR_RANGE(cmd->chanlist[i]))
2366                        return 0;
2367                if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2368                        return 0;
2369        }
2370        return 1;
2371}
2372
2373static int setup_channel_queue(struct comedi_device *dev,
2374                               const struct comedi_cmd *cmd)
2375{
2376        const struct pcidas64_board *thisboard = dev->board_ptr;
2377        struct pcidas64_private *devpriv = dev->private;
2378        unsigned short bits;
2379        int i;
2380
2381        if (thisboard->layout != LAYOUT_4020) {
2382                if (use_internal_queue_6xxx(cmd)) {
2383                        devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2384                        writew(devpriv->hw_config_bits,
2385                               devpriv->main_iobase + HW_CONFIG_REG);
2386                        bits = 0;
2387                        /*  set channel */
2388                        bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2389                        /*  set gain */
2390                        bits |= ai_range_bits_6xxx(dev,
2391                                                   CR_RANGE(cmd->chanlist[0]));
2392                        /*  set single-ended / differential */
2393                        bits |= se_diff_bit_6xxx(dev,
2394                                                 CR_AREF(cmd->chanlist[0]) ==
2395                                                 AREF_DIFF);
2396                        if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2397                                bits |= ADC_COMMON_BIT;
2398                        /*  set stop channel */
2399                        writew(adc_chan_bits
2400                               (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2401                               devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2402                        /*  set start channel, and rest of settings */
2403                        writew(bits,
2404                               devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2405                } else {
2406                        /*  use external queue */
2407                        if (dev->write_subdev && dev->write_subdev->busy) {
2408                                warn_external_queue(dev);
2409                                return -EBUSY;
2410                        }
2411                        devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2412                        writew(devpriv->hw_config_bits,
2413                               devpriv->main_iobase + HW_CONFIG_REG);
2414                        /*  clear DAC buffer to prevent weird interactions */
2415                        writew(0,
2416                               devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2417                        /*  clear queue pointer */
2418                        writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2419                        /*  load external queue */
2420                        for (i = 0; i < cmd->chanlist_len; i++) {
2421                                bits = 0;
2422                                /*  set channel */
2423                                bits |= adc_chan_bits(CR_CHAN(cmd->
2424                                                              chanlist[i]));
2425                                /*  set gain */
2426                                bits |= ai_range_bits_6xxx(dev,
2427                                                           CR_RANGE(cmd->
2428                                                                    chanlist
2429                                                                    [i]));
2430                                /*  set single-ended / differential */
2431                                bits |= se_diff_bit_6xxx(dev,
2432                                                         CR_AREF(cmd->
2433                                                                 chanlist[i]) ==
2434                                                         AREF_DIFF);
2435                                if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2436                                        bits |= ADC_COMMON_BIT;
2437                                /*  mark end of queue */
2438                                if (i == cmd->chanlist_len - 1)
2439                                        bits |= QUEUE_EOSCAN_BIT |
2440                                                QUEUE_EOSEQ_BIT;
2441                                writew(bits,
2442                                       devpriv->main_iobase +
2443                                       ADC_QUEUE_FIFO_REG);
2444                        }
2445                        /* doing a queue clear is not specified in board docs,
2446                         * but required for reliable operation */
2447                        writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2448                        /*  prime queue holding register */
2449                        writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2450                }
2451        } else {
2452                unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2453
2454                devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2455                /* select BNC inputs */
2456                devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2457                /*  select ranges */
2458                for (i = 0; i < cmd->chanlist_len; i++) {
2459                        unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2460                        unsigned int range = CR_RANGE(cmd->chanlist[i]);
2461
2462                        if (range == 0)
2463                                devpriv->i2c_cal_range_bits |=
2464                                        attenuate_bit(channel);
2465                        else
2466                                devpriv->i2c_cal_range_bits &=
2467                                        ~attenuate_bit(channel);
2468                }
2469                /*  update calibration/range i2c register only if necessary,
2470                 *  as it is very slow */
2471                if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2472                        uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2473
2474                        i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2475                                  sizeof(i2c_data));
2476                }
2477        }
2478        return 0;
2479}
2480
2481static inline void load_first_dma_descriptor(struct comedi_device *dev,
2482                                             unsigned int dma_channel,
2483                                             unsigned int descriptor_bits)
2484{
2485        struct pcidas64_private *devpriv = dev->private;
2486
2487        /* The transfer size, pci address, and local address registers
2488         * are supposedly unused during chained dma,
2489         * but I have found that left over values from last operation
2490         * occasionally cause problems with transfer of first dma
2491         * block.  Initializing them to zero seems to fix the problem. */
2492        if (dma_channel) {
2493                writel(0,
2494                       devpriv->plx9080_iobase + PLX_DMA1_TRANSFER_SIZE_REG);
2495                writel(0, devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG);
2496                writel(0,
2497                       devpriv->plx9080_iobase + PLX_DMA1_LOCAL_ADDRESS_REG);
2498                writel(descriptor_bits,
2499                       devpriv->plx9080_iobase + PLX_DMA1_DESCRIPTOR_REG);
2500        } else {
2501                writel(0,
2502                       devpriv->plx9080_iobase + PLX_DMA0_TRANSFER_SIZE_REG);
2503                writel(0, devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2504                writel(0,
2505                       devpriv->plx9080_iobase + PLX_DMA0_LOCAL_ADDRESS_REG);
2506                writel(descriptor_bits,
2507                       devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2508        }
2509}
2510
2511static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2512{
2513        const struct pcidas64_board *thisboard = dev->board_ptr;
2514        struct pcidas64_private *devpriv = dev->private;
2515        struct comedi_async *async = s->async;
2516        struct comedi_cmd *cmd = &async->cmd;
2517        uint32_t bits;
2518        unsigned int i;
2519        unsigned long flags;
2520        int retval;
2521
2522        disable_ai_pacing(dev);
2523        abort_dma(dev, 1);
2524
2525        retval = setup_channel_queue(dev, cmd);
2526        if (retval < 0)
2527                return retval;
2528
2529        /*  make sure internal calibration source is turned off */
2530        writew(0, devpriv->main_iobase + CALIBRATION_REG);
2531
2532        set_ai_pacing(dev, cmd);
2533
2534        setup_sample_counters(dev, cmd);
2535
2536        enable_ai_interrupts(dev, cmd);
2537
2538        spin_lock_irqsave(&dev->spinlock, flags);
2539        /* set mode, allow conversions through software gate */
2540        devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2541        devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2542        if (thisboard->layout != LAYOUT_4020) {
2543                devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2544                if (cmd->convert_src == TRIG_EXT)
2545                        /*  good old mode 13 */
2546                        devpriv->adc_control1_bits |= adc_mode_bits(13);
2547                else
2548                        /*  mode 8.  What else could you need? */
2549                        devpriv->adc_control1_bits |= adc_mode_bits(8);
2550        } else {
2551                devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2552                if (cmd->chanlist_len == 4)
2553                        devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2554                else if (cmd->chanlist_len == 2)
2555                        devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2556                devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2557                devpriv->adc_control1_bits |=
2558                        adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2559                devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2560                devpriv->adc_control1_bits |=
2561                        adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2562                                                      [cmd->chanlist_len - 1]));
2563        }
2564        writew(devpriv->adc_control1_bits,
2565               devpriv->main_iobase + ADC_CONTROL1_REG);
2566        spin_unlock_irqrestore(&dev->spinlock, flags);
2567
2568        /*  clear adc buffer */
2569        writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2570
2571        if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2572            thisboard->layout == LAYOUT_4020) {
2573                devpriv->ai_dma_index = 0;
2574
2575                /*  set dma transfer size */
2576                for (i = 0; i < ai_dma_ring_count(thisboard); i++)
2577                        devpriv->ai_dma_desc[i].transfer_size =
2578                                cpu_to_le32(dma_transfer_size(dev) *
2579                                            sizeof(uint16_t));
2580
2581                /*  give location of first dma descriptor */
2582                load_first_dma_descriptor(dev, 1,
2583                                          devpriv->ai_dma_desc_bus_addr |
2584                                          PLX_DESC_IN_PCI_BIT |
2585                                          PLX_INTR_TERM_COUNT |
2586                                          PLX_XFER_LOCAL_TO_PCI);
2587
2588                dma_start_sync(dev, 1);
2589        }
2590
2591        if (thisboard->layout == LAYOUT_4020) {
2592                /* set source for external triggers */
2593                bits = 0;
2594                if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2595                        bits |= EXT_START_TRIG_BNC_BIT;
2596                if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2597                        bits |= EXT_STOP_TRIG_BNC_BIT;
2598                writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2599        }
2600
2601        spin_lock_irqsave(&dev->spinlock, flags);
2602
2603        /* enable pacing, triggering, etc */
2604        bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2605        if (cmd->flags & CMDF_WAKE_EOS)
2606                bits |= ADC_DMA_DISABLE_BIT;
2607        /*  set start trigger */
2608        if (cmd->start_src == TRIG_EXT) {
2609                bits |= ADC_START_TRIG_EXT_BITS;
2610                if (cmd->start_arg & CR_INVERT)
2611                        bits |= ADC_START_TRIG_FALLING_BIT;
2612        } else if (cmd->start_src == TRIG_NOW)
2613                bits |= ADC_START_TRIG_SOFT_BITS;
2614        if (use_hw_sample_counter(cmd))
2615                bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2616        writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2617
2618        devpriv->ai_cmd_running = 1;
2619
2620        spin_unlock_irqrestore(&dev->spinlock, flags);
2621
2622        /*  start acquisition */
2623        if (cmd->start_src == TRIG_NOW)
2624                writew(0, devpriv->main_iobase + ADC_START_REG);
2625
2626        return 0;
2627}
2628
2629/* read num_samples from 16 bit wide ai fifo */
2630static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2631{
2632        struct pcidas64_private *devpriv = dev->private;
2633        struct comedi_subdevice *s = dev->read_subdev;
2634        unsigned int i;
2635        uint16_t prepost_bits;
2636        int read_segment, read_index, write_segment, write_index;
2637        int num_samples;
2638
2639        do {
2640                /*  get least significant 15 bits */
2641                read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2642                             0x7fff;
2643                write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2644                              0x7fff;
2645                /* Get most significant bits (grey code).
2646                 * Different boards use different code so use a scheme
2647                 * that doesn't depend on encoding.  This read must
2648                 * occur after reading least significant 15 bits to avoid race
2649                 * with fifo switching to next segment. */
2650                prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2651
2652                /* if read and write pointers are not on the same fifo segment,
2653                 * read to the end of the read segment */
2654                read_segment = adc_upper_read_ptr_code(prepost_bits);
2655                write_segment = adc_upper_write_ptr_code(prepost_bits);
2656
2657                if (read_segment != write_segment)
2658                        num_samples =
2659                                devpriv->ai_fifo_segment_length - read_index;
2660                else
2661                        num_samples = write_index - read_index;
2662                if (num_samples < 0) {
2663                        dev_err(dev->class_dev,
2664                                "cb_pcidas64: bug! num_samples < 0\n");
2665                        break;
2666                }
2667
2668                num_samples = comedi_nsamples_left(s, num_samples);
2669                if (num_samples == 0)
2670                        break;
2671
2672                for (i = 0; i < num_samples; i++) {
2673                        unsigned short val;
2674
2675                        val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2676                        comedi_buf_write_samples(s, &val, 1);
2677                }
2678
2679        } while (read_segment != write_segment);
2680}
2681
2682/* Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2683 * pointers.  The pci-4020 hardware only supports dma transfers (it only
2684 * supports the use of pio for draining the last remaining points from the
2685 * fifo when a data acquisition operation has completed).
2686 */
2687static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2688{
2689        struct pcidas64_private *devpriv = dev->private;
2690        struct comedi_subdevice *s = dev->read_subdev;
2691        unsigned int nsamples;
2692        unsigned int i;
2693        uint32_t fifo_data;
2694        int write_code =
2695                readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2696        int read_code =
2697                readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2698
2699        nsamples = comedi_nsamples_left(s, 100000);
2700        for (i = 0; read_code != write_code && i < nsamples;) {
2701                unsigned short val;
2702
2703                fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2704                val = fifo_data & 0xffff;
2705                comedi_buf_write_samples(s, &val, 1);
2706                i++;
2707                if (i < nsamples) {
2708                        val = (fifo_data >> 16) & 0xffff;
2709                        comedi_buf_write_samples(s, &val, 1);
2710                        i++;
2711                }
2712                read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2713                            0x7fff;
2714        }
2715}
2716
2717/* empty fifo */
2718static void pio_drain_ai_fifo(struct comedi_device *dev)
2719{
2720        const struct pcidas64_board *thisboard = dev->board_ptr;
2721
2722        if (thisboard->layout == LAYOUT_4020)
2723                pio_drain_ai_fifo_32(dev);
2724        else
2725                pio_drain_ai_fifo_16(dev);
2726}
2727
2728static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2729{
2730        const struct pcidas64_board *thisboard = dev->board_ptr;
2731        struct pcidas64_private *devpriv = dev->private;
2732        struct comedi_subdevice *s = dev->read_subdev;
2733        uint32_t next_transfer_addr;
2734        int j;
2735        int num_samples = 0;
2736        void __iomem *pci_addr_reg;
2737
2738        if (channel)
2739                pci_addr_reg =
2740                    devpriv->plx9080_iobase + PLX_DMA1_PCI_ADDRESS_REG;
2741        else
2742                pci_addr_reg =
2743                    devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2744
2745        /*  loop until we have read all the full buffers */
2746        for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2747             (next_transfer_addr <
2748              devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2749              next_transfer_addr >=
2750              devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2751              DMA_BUFFER_SIZE) && j < ai_dma_ring_count(thisboard); j++) {
2752                /*  transfer data from dma buffer to comedi buffer */
2753                num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2754                comedi_buf_write_samples(s,
2755                                devpriv->ai_buffer[devpriv->ai_dma_index],
2756                                num_samples);
2757                devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2758                                        ai_dma_ring_count(thisboard);
2759        }
2760        /* XXX check for dma ring buffer overrun
2761         * (use end-of-chain bit to mark last unused buffer) */
2762}
2763
2764static void handle_ai_interrupt(struct comedi_device *dev,
2765                                unsigned short status,
2766                                unsigned int plx_status)
2767{
2768        const struct pcidas64_board *thisboard = dev->board_ptr;
2769        struct pcidas64_private *devpriv = dev->private;
2770        struct comedi_subdevice *s = dev->read_subdev;
2771        struct comedi_async *async = s->async;
2772        struct comedi_cmd *cmd = &async->cmd;
2773        uint8_t dma1_status;
2774        unsigned long flags;
2775
2776        /*  check for fifo overrun */
2777        if (status & ADC_OVERRUN_BIT) {
2778                dev_err(dev->class_dev, "fifo overrun\n");
2779                async->events |= COMEDI_CB_EOA | COMEDI_CB_ERROR;
2780        }
2781        /*  spin lock makes sure no one else changes plx dma control reg */
2782        spin_lock_irqsave(&dev->spinlock, flags);
2783        dma1_status = readb(devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2784        if (plx_status & ICS_DMA1_A) {  /*  dma chan 1 interrupt */
2785                writeb((dma1_status & PLX_DMA_EN_BIT) | PLX_CLEAR_DMA_INTR_BIT,
2786                       devpriv->plx9080_iobase + PLX_DMA1_CS_REG);
2787
2788                if (dma1_status & PLX_DMA_EN_BIT)
2789                        drain_dma_buffers(dev, 1);
2790        }
2791        spin_unlock_irqrestore(&dev->spinlock, flags);
2792
2793        /*  drain fifo with pio */
2794        if ((status & ADC_DONE_BIT) ||
2795            ((cmd->flags & CMDF_WAKE_EOS) &&
2796             (status & ADC_INTR_PENDING_BIT) &&
2797             (thisboard->layout != LAYOUT_4020))) {
2798                spin_lock_irqsave(&dev->spinlock, flags);
2799                if (devpriv->ai_cmd_running) {
2800                        spin_unlock_irqrestore(&dev->spinlock, flags);
2801                        pio_drain_ai_fifo(dev);
2802                } else
2803                        spin_unlock_irqrestore(&dev->spinlock, flags);
2804        }
2805        /*  if we are have all the data, then quit */
2806        if ((cmd->stop_src == TRIG_COUNT &&
2807             async->scans_done >= cmd->stop_arg) ||
2808            (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2809                async->events |= COMEDI_CB_EOA;
2810
2811        comedi_handle_events(dev, s);
2812}
2813
2814static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2815{
2816        struct pcidas64_private *devpriv = dev->private;
2817        unsigned int buffer_index;
2818
2819        if (devpriv->ao_dma_index == 0)
2820                buffer_index = AO_DMA_RING_COUNT - 1;
2821        else
2822                buffer_index = devpriv->ao_dma_index - 1;
2823        return buffer_index;
2824}
2825
2826static int last_ao_dma_load_completed(struct comedi_device *dev)
2827{
2828        struct pcidas64_private *devpriv = dev->private;
2829        unsigned int buffer_index;
2830        unsigned int transfer_address;
2831        unsigned short dma_status;
2832
2833        buffer_index = prev_ao_dma_index(dev);
2834        dma_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2835        if ((dma_status & PLX_DMA_DONE_BIT) == 0)
2836                return 0;
2837
2838        transfer_address =
2839                readl(devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG);
2840        if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2841                return 0;
2842
2843        return 1;
2844}
2845
2846static inline int ao_dma_needs_restart(struct comedi_device *dev,
2847                                       unsigned short dma_status)
2848{
2849        if ((dma_status & PLX_DMA_DONE_BIT) == 0 ||
2850            (dma_status & PLX_DMA_EN_BIT) == 0)
2851                return 0;
2852        if (last_ao_dma_load_completed(dev))
2853                return 0;
2854
2855        return 1;
2856}
2857
2858static void restart_ao_dma(struct comedi_device *dev)
2859{
2860        struct pcidas64_private *devpriv = dev->private;
2861        unsigned int dma_desc_bits;
2862
2863        dma_desc_bits =
2864                readl(devpriv->plx9080_iobase + PLX_DMA0_DESCRIPTOR_REG);
2865        dma_desc_bits &= ~PLX_END_OF_CHAIN_BIT;
2866        load_first_dma_descriptor(dev, 0, dma_desc_bits);
2867
2868        dma_start_sync(dev, 0);
2869}
2870
2871static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2872                                               struct comedi_subdevice *s,
2873                                               unsigned short *dest,
2874                                               unsigned int max_bytes)
2875{
2876        unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2877        unsigned int actual_bytes;
2878
2879        nsamples = comedi_nsamples_left(s, nsamples);
2880        actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2881
2882        return comedi_bytes_to_samples(s, actual_bytes);
2883}
2884
2885static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2886                                       const struct comedi_cmd *cmd)
2887{
2888        struct pcidas64_private *devpriv = dev->private;
2889        struct comedi_subdevice *s = dev->write_subdev;
2890        unsigned int buffer_index = devpriv->ao_dma_index;
2891        unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2892        unsigned int nsamples;
2893        unsigned int nbytes;
2894        unsigned int next_bits;
2895
2896        nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2897                                              devpriv->ao_buffer[buffer_index],
2898                                              DMA_BUFFER_SIZE);
2899        if (nsamples == 0)
2900                return 0;
2901
2902        nbytes = comedi_samples_to_bytes(s, nsamples);
2903        devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2904        /* set end of chain bit so we catch underruns */
2905        next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2906        next_bits |= PLX_END_OF_CHAIN_BIT;
2907        devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2908        /* clear end of chain bit on previous buffer now that we have set it
2909         * for the last buffer */
2910        next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2911        next_bits &= ~PLX_END_OF_CHAIN_BIT;
2912        devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2913
2914        devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2915
2916        return nbytes;
2917}
2918
2919static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2920{
2921        struct pcidas64_private *devpriv = dev->private;
2922        unsigned int num_bytes;
2923        unsigned int next_transfer_addr;
2924        void __iomem *pci_addr_reg =
2925                devpriv->plx9080_iobase + PLX_DMA0_PCI_ADDRESS_REG;
2926        unsigned int buffer_index;
2927
2928        do {
2929                buffer_index = devpriv->ao_dma_index;
2930                /* don't overwrite data that hasn't been transferred yet */
2931                next_transfer_addr = readl(pci_addr_reg);
2932                if (next_transfer_addr >=
2933                    devpriv->ao_buffer_bus_addr[buffer_index] &&
2934                    next_transfer_addr <
2935                    devpriv->ao_buffer_bus_addr[buffer_index] +
2936                    DMA_BUFFER_SIZE)
2937                        return;
2938                num_bytes = load_ao_dma_buffer(dev, cmd);
2939        } while (num_bytes >= DMA_BUFFER_SIZE);
2940}
2941
2942static void handle_ao_interrupt(struct comedi_device *dev,
2943                                unsigned short status, unsigned int plx_status)
2944{
2945        struct pcidas64_private *devpriv = dev->private;
2946        struct comedi_subdevice *s = dev->write_subdev;
2947        struct comedi_async *async;
2948        struct comedi_cmd *cmd;
2949        uint8_t dma0_status;
2950        unsigned long flags;
2951
2952        /* board might not support ao, in which case write_subdev is NULL */
2953        if (s == NULL)
2954                return;
2955        async = s->async;
2956        cmd = &async->cmd;
2957
2958        /*  spin lock makes sure no one else changes plx dma control reg */
2959        spin_lock_irqsave(&dev->spinlock, flags);
2960        dma0_status = readb(devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2961        if (plx_status & ICS_DMA0_A) {  /*  dma chan 0 interrupt */
2962                if ((dma0_status & PLX_DMA_EN_BIT) &&
2963                    !(dma0_status & PLX_DMA_DONE_BIT))
2964                        writeb(PLX_DMA_EN_BIT | PLX_CLEAR_DMA_INTR_BIT,
2965                               devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2966                else
2967                        writeb(PLX_CLEAR_DMA_INTR_BIT,
2968                               devpriv->plx9080_iobase + PLX_DMA0_CS_REG);
2969                spin_unlock_irqrestore(&dev->spinlock, flags);
2970                if (dma0_status & PLX_DMA_EN_BIT) {
2971                        load_ao_dma(dev, cmd);
2972                        /* try to recover from dma end-of-chain event */
2973                        if (ao_dma_needs_restart(dev, dma0_status))
2974                                restart_ao_dma(dev);
2975                }
2976        } else {
2977                spin_unlock_irqrestore(&dev->spinlock, flags);
2978        }
2979
2980        if ((status & DAC_DONE_BIT)) {
2981                if ((cmd->stop_src == TRIG_COUNT &&
2982                     async->scans_done >= cmd->stop_arg) ||
2983                    last_ao_dma_load_completed(dev))
2984                        async->events |= COMEDI_CB_EOA;
2985                else
2986                        async->events |= COMEDI_CB_ERROR;
2987        }
2988        comedi_handle_events(dev, s);
2989}
2990
2991static irqreturn_t handle_interrupt(int irq, void *d)
2992{
2993        struct comedi_device *dev = d;
2994        struct pcidas64_private *devpriv = dev->private;
2995        unsigned short status;
2996        uint32_t plx_status;
2997        uint32_t plx_bits;
2998
2999        plx_status = readl(devpriv->plx9080_iobase + PLX_INTRCS_REG);
3000        status = readw(devpriv->main_iobase + HW_STATUS_REG);
3001
3002        /* an interrupt before all the postconfig stuff gets done could
3003         * cause a NULL dereference if we continue through the
3004         * interrupt handler */
3005        if (!dev->attached)
3006                return IRQ_HANDLED;
3007
3008        handle_ai_interrupt(dev, status, plx_status);
3009        handle_ao_interrupt(dev, status, plx_status);
3010
3011        /*  clear possible plx9080 interrupt sources */
3012        if (plx_status & ICS_LDIA) {    /*  clear local doorbell interrupt */
3013                plx_bits = readl(devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3014                writel(plx_bits, devpriv->plx9080_iobase + PLX_DBR_OUT_REG);
3015        }
3016
3017        return IRQ_HANDLED;
3018}
3019
3020static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3021{
3022        struct pcidas64_private *devpriv = dev->private;
3023        unsigned long flags;
3024
3025        spin_lock_irqsave(&dev->spinlock, flags);
3026        if (devpriv->ai_cmd_running == 0) {
3027                spin_unlock_irqrestore(&dev->spinlock, flags);
3028                return 0;
3029        }
3030        devpriv->ai_cmd_running = 0;
3031        spin_unlock_irqrestore(&dev->spinlock, flags);
3032
3033        disable_ai_pacing(dev);
3034
3035        abort_dma(dev, 1);
3036
3037        return 0;
3038}
3039
3040static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3041                    struct comedi_insn *insn, unsigned int *data)
3042{
3043        const struct pcidas64_board *thisboard = dev->board_ptr;
3044        struct pcidas64_private *devpriv = dev->private;
3045        int chan = CR_CHAN(insn->chanspec);
3046        int range = CR_RANGE(insn->chanspec);
3047
3048        /*  do some initializing */
3049        writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3050
3051        /*  set range */
3052        set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3053        writew(devpriv->dac_control1_bits,
3054               devpriv->main_iobase + DAC_CONTROL1_REG);
3055
3056        /*  write to channel */
3057        if (thisboard->layout == LAYOUT_4020) {
3058                writew(data[0] & 0xff,
3059                       devpriv->main_iobase + dac_lsb_4020_reg(chan));
3060                writew((data[0] >> 8) & 0xf,
3061                       devpriv->main_iobase + dac_msb_4020_reg(chan));
3062        } else {
3063                writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3064        }
3065
3066        /*  remember output value */
3067        s->readback[chan] = data[0];
3068
3069        return 1;
3070}
3071
3072static void set_dac_control0_reg(struct comedi_device *dev,
3073                                 const struct comedi_cmd *cmd)
3074{
3075        struct pcidas64_private *devpriv = dev->private;
3076        unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3077                            WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3078
3079        if (cmd->start_src == TRIG_EXT) {
3080                bits |= WAVEFORM_TRIG_EXT_BITS;
3081                if (cmd->start_arg & CR_INVERT)
3082                        bits |= WAVEFORM_TRIG_FALLING_BIT;
3083        } else {
3084                bits |= WAVEFORM_TRIG_SOFT_BITS;
3085        }
3086        if (cmd->scan_begin_src == TRIG_EXT) {
3087                bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3088                if (cmd->scan_begin_arg & CR_INVERT)
3089                        bits |= DAC_EXT_UPDATE_FALLING_BIT;
3090        }
3091        writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3092}
3093
3094static void set_dac_control1_reg(struct comedi_device *dev,
3095                                 const struct comedi_cmd *cmd)
3096{
3097        struct pcidas64_private *devpriv = dev->private;
3098        int i;
3099
3100        for (i = 0; i < cmd->chanlist_len; i++) {
3101                int channel, range;
3102
3103                channel = CR_CHAN(cmd->chanlist[i]);
3104                range = CR_RANGE(cmd->chanlist[i]);
3105                set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3106                                   range);
3107        }
3108        devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3109        writew(devpriv->dac_control1_bits,
3110               devpriv->main_iobase + DAC_CONTROL1_REG);
3111}
3112
3113static void set_dac_select_reg(struct comedi_device *dev,
3114                               const struct comedi_cmd *cmd)
3115{
3116        struct pcidas64_private *devpriv = dev->private;
3117        uint16_t bits;
3118        unsigned int first_channel, last_channel;
3119
3120        first_channel = CR_CHAN(cmd->chanlist[0]);
3121        last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3122        if (last_channel < first_channel)
3123                dev_err(dev->class_dev,
3124                        "bug! last ao channel < first ao channel\n");
3125
3126        bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3127
3128        writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3129}
3130
3131static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3132{
3133        return get_divisor(ns, flags) - 2;
3134}
3135
3136static void set_dac_interval_regs(struct comedi_device *dev,
3137                                  const struct comedi_cmd *cmd)
3138{
3139        struct pcidas64_private *devpriv = dev->private;
3140        unsigned int divisor;
3141
3142        if (cmd->scan_begin_src != TRIG_TIMER)
3143                return;
3144
3145        divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3146        if (divisor > max_counter_value) {
3147                dev_err(dev->class_dev, "bug! ao divisor too big\n");
3148                divisor = max_counter_value;
3149        }
3150        writew(divisor & 0xffff,
3151               devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3152        writew((divisor >> 16) & 0xff,
3153               devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3154}
3155
3156static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3157{
3158        struct pcidas64_private *devpriv = dev->private;
3159        struct comedi_subdevice *s = dev->write_subdev;
3160        unsigned int nsamples;
3161        unsigned int nbytes;
3162        int i;
3163
3164        /* clear queue pointer too, since external queue has
3165         * weird interactions with ao fifo */
3166        writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3167        writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3168
3169        nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3170                                              devpriv->ao_bounce_buffer,
3171                                              DAC_FIFO_SIZE);
3172        if (nsamples == 0)
3173                return -1;
3174
3175        for (i = 0; i < nsamples; i++) {
3176                writew(devpriv->ao_bounce_buffer[i],
3177                       devpriv->main_iobase + DAC_FIFO_REG);
3178        }
3179
3180        if (cmd->stop_src == TRIG_COUNT &&
3181            s->async->scans_done >= cmd->stop_arg)
3182                return 0;
3183
3184        nbytes = load_ao_dma_buffer(dev, cmd);
3185        if (nbytes == 0)
3186                return -1;
3187        load_ao_dma(dev, cmd);
3188
3189        dma_start_sync(dev, 0);
3190
3191        return 0;
3192}
3193
3194static inline int external_ai_queue_in_use(struct comedi_device *dev,
3195                                           struct comedi_subdevice *s,
3196                                           struct comedi_cmd *cmd)
3197{
3198        const struct pcidas64_board *thisboard = dev->board_ptr;
3199
3200        if (s->busy)
3201                return 0;
3202        if (thisboard->layout == LAYOUT_4020)
3203                return 0;
3204        else if (use_internal_queue_6xxx(cmd))
3205                return 0;
3206        return 1;
3207}
3208
3209static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3210                      unsigned int trig_num)
3211{
3212        struct pcidas64_private *devpriv = dev->private;
3213        struct comedi_cmd *cmd = &s->async->cmd;
3214        int retval;
3215
3216        if (trig_num != cmd->start_arg)
3217                return -EINVAL;
3218
3219        retval = prep_ao_dma(dev, cmd);
3220        if (retval < 0)
3221                return -EPIPE;
3222
3223        set_dac_control0_reg(dev, cmd);
3224
3225        if (cmd->start_src == TRIG_INT)
3226                writew(0, devpriv->main_iobase + DAC_START_REG);
3227
3228        s->async->inttrig = NULL;
3229
3230        return 0;
3231}
3232
3233static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3234{
3235        struct pcidas64_private *devpriv = dev->private;
3236        struct comedi_cmd *cmd = &s->async->cmd;
3237
3238        if (external_ai_queue_in_use(dev, s, cmd)) {
3239                warn_external_queue(dev);
3240                return -EBUSY;
3241        }
3242        /* disable analog output system during setup */
3243        writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3244
3245        devpriv->ao_dma_index = 0;
3246
3247        set_dac_select_reg(dev, cmd);
3248        set_dac_interval_regs(dev, cmd);
3249        load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3250                                  PLX_DESC_IN_PCI_BIT | PLX_INTR_TERM_COUNT);
3251
3252        set_dac_control1_reg(dev, cmd);
3253        s->async->inttrig = ao_inttrig;
3254
3255        return 0;
3256}
3257
3258static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3259                                         struct comedi_subdevice *s,
3260                                         struct comedi_cmd *cmd)
3261{
3262        unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3263        int i;
3264
3265        for (i = 1; i < cmd->chanlist_len; i++) {
3266                unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3267
3268                if (chan != (chan0 + i)) {
3269                        dev_dbg(dev->class_dev,
3270                                "chanlist must use consecutive channels\n");
3271                        return -EINVAL;
3272                }
3273        }
3274
3275        return 0;
3276}
3277
3278static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3279                      struct comedi_cmd *cmd)
3280{
3281        const struct pcidas64_board *thisboard = dev->board_ptr;
3282        int err = 0;
3283        unsigned int tmp_arg;
3284
3285        /* Step 1 : check if triggers are trivially valid */
3286
3287        err |= cfc_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3288        err |= cfc_check_trigger_src(&cmd->scan_begin_src,
3289                                     TRIG_TIMER | TRIG_EXT);
3290        err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3291        err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3292        err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3293
3294        if (err)
3295                return 1;
3296
3297        /* Step 2a : make sure trigger sources are unique */
3298
3299        err |= cfc_check_trigger_is_unique(cmd->start_src);
3300        err |= cfc_check_trigger_is_unique(cmd->scan_begin_src);
3301
3302        /* Step 2b : and mutually compatible */
3303
3304        if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3305                err |= -EINVAL;
3306        if (cmd->stop_src != TRIG_COUNT &&
3307            cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3308                err |= -EINVAL;
3309
3310        if (err)
3311                return 2;
3312
3313        /* Step 3: check if arguments are trivially valid */
3314
3315        err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
3316
3317        if (cmd->scan_begin_src == TRIG_TIMER) {
3318                err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg,
3319                                                 thisboard->ao_scan_speed);
3320                if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3321                    max_counter_value) {
3322                        cmd->scan_begin_arg = (max_counter_value + 2) *
3323                                              TIMER_BASE;
3324                        err |= -EINVAL;
3325                }
3326        }
3327
3328        err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
3329        err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
3330
3331        if (err)
3332                return 3;
3333
3334        /* step 4: fix up any arguments */
3335
3336        if (cmd->scan_begin_src == TRIG_TIMER) {
3337                tmp_arg = cmd->scan_begin_arg;
3338                cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3339                                                  cmd->flags) * TIMER_BASE;
3340                if (tmp_arg != cmd->scan_begin_arg)
3341                        err++;
3342        }
3343
3344        if (err)
3345                return 4;
3346
3347        /* Step 5: check channel list if it exists */
3348        if (cmd->chanlist && cmd->chanlist_len > 0)
3349                err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3350
3351        if (err)
3352                return 5;
3353
3354        return 0;
3355}
3356
3357static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3358{
3359        struct pcidas64_private *devpriv = dev->private;
3360
3361        writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3362        abort_dma(dev, 0);
3363        return 0;
3364}
3365
3366static int dio_callback_4020(struct comedi_device *dev,
3367                             int dir, int port, int data, unsigned long iobase)
3368{
3369        struct pcidas64_private *devpriv = dev->private;
3370
3371        if (dir) {
3372                writew(data, devpriv->main_iobase + iobase + 2 * port);
3373                return 0;
3374        }
3375        return readw(devpriv->main_iobase + iobase + 2 * port);
3376}
3377
3378static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3379                    struct comedi_insn *insn, unsigned int *data)
3380{
3381        unsigned int bits;
3382
3383        bits = readb(dev->mmio + DI_REG);
3384        bits &= 0xf;
3385        data[1] = bits;
3386        data[0] = 0;
3387
3388        return insn->n;
3389}
3390
3391static int do_wbits(struct comedi_device *dev,
3392                    struct comedi_subdevice *s,
3393                    struct comedi_insn *insn,
3394                    unsigned int *data)
3395{
3396        if (comedi_dio_update_state(s, data))
3397                writeb(s->state, dev->mmio + DO_REG);
3398
3399        data[1] = s->state;
3400
3401        return insn->n;
3402}
3403
3404static int dio_60xx_config_insn(struct comedi_device *dev,
3405                                struct comedi_subdevice *s,
3406                                struct comedi_insn *insn,
3407                                unsigned int *data)
3408{
3409        int ret;
3410
3411        ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3412        if (ret)
3413                return ret;
3414
3415        writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3416
3417        return insn->n;
3418}
3419
3420static int dio_60xx_wbits(struct comedi_device *dev,
3421                          struct comedi_subdevice *s,
3422                          struct comedi_insn *insn,
3423                          unsigned int *data)
3424{
3425        if (comedi_dio_update_state(s, data))
3426                writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3427
3428        data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3429
3430        return insn->n;
3431}
3432
3433/* pci-6025 8800 caldac:
3434 * address 0 == dac channel 0 offset
3435 * address 1 == dac channel 0 gain
3436 * address 2 == dac channel 1 offset
3437 * address 3 == dac channel 1 gain
3438 * address 4 == fine adc offset
3439 * address 5 == coarse adc offset
3440 * address 6 == coarse adc gain
3441 * address 7 == fine adc gain
3442 */
3443/* pci-6402/16 uses all 8 channels for dac:
3444 * address 0 == dac channel 0 fine gain
3445 * address 1 == dac channel 0 coarse gain
3446 * address 2 == dac channel 0 coarse offset
3447 * address 3 == dac channel 1 coarse offset
3448 * address 4 == dac channel 1 fine gain
3449 * address 5 == dac channel 1 coarse gain
3450 * address 6 == dac channel 0 fine offset
3451 * address 7 == dac channel 1 fine offset
3452*/
3453
3454static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3455                             uint8_t value)
3456{
3457        struct pcidas64_private *devpriv = dev->private;
3458        static const int num_caldac_channels = 8;
3459        static const int bitstream_length = 11;
3460        unsigned int bitstream = ((address & 0x7) << 8) | value;
3461        unsigned int bit, register_bits;
3462        static const int caldac_8800_udelay = 1;
3463
3464        if (address >= num_caldac_channels) {
3465                dev_err(dev->class_dev, "illegal caldac channel\n");
3466                return -1;
3467        }
3468        for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3469                register_bits = 0;
3470                if (bitstream & bit)
3471                        register_bits |= SERIAL_DATA_IN_BIT;
3472                udelay(caldac_8800_udelay);
3473                writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3474                register_bits |= SERIAL_CLOCK_BIT;
3475                udelay(caldac_8800_udelay);
3476                writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3477        }
3478        udelay(caldac_8800_udelay);
3479        writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3480        udelay(caldac_8800_udelay);
3481        writew(0, devpriv->main_iobase + CALIBRATION_REG);
3482        udelay(caldac_8800_udelay);
3483        return 0;
3484}
3485
3486/* 4020 caldacs */
3487static int caldac_i2c_write(struct comedi_device *dev,
3488                            unsigned int caldac_channel, unsigned int value)
3489{
3490        uint8_t serial_bytes[3];
3491        uint8_t i2c_addr;
3492        enum pointer_bits {
3493                /*  manual has gain and offset bits switched */
3494                OFFSET_0_2 = 0x1,
3495                GAIN_0_2 = 0x2,
3496                OFFSET_1_3 = 0x4,
3497                GAIN_1_3 = 0x8,
3498        };
3499        enum data_bits {
3500                NOT_CLEAR_REGISTERS = 0x20,
3501        };
3502
3503        switch (caldac_channel) {
3504        case 0:         /*  chan 0 offset */
3505                i2c_addr = CALDAC0_I2C_ADDR;
3506                serial_bytes[0] = OFFSET_0_2;
3507                break;
3508        case 1:         /*  chan 1 offset */
3509                i2c_addr = CALDAC0_I2C_ADDR;
3510                serial_bytes[0] = OFFSET_1_3;
3511                break;
3512        case 2:         /*  chan 2 offset */
3513                i2c_addr = CALDAC1_I2C_ADDR;
3514                serial_bytes[0] = OFFSET_0_2;
3515                break;
3516        case 3:         /*  chan 3 offset */
3517                i2c_addr = CALDAC1_I2C_ADDR;
3518                serial_bytes[0] = OFFSET_1_3;
3519                break;
3520        case 4:         /*  chan 0 gain */
3521                i2c_addr = CALDAC0_I2C_ADDR;
3522                serial_bytes[0] = GAIN_0_2;
3523                break;
3524        case 5:         /*  chan 1 gain */
3525                i2c_addr = CALDAC0_I2C_ADDR;
3526                serial_bytes[0] = GAIN_1_3;
3527                break;
3528        case 6:         /*  chan 2 gain */
3529                i2c_addr = CALDAC1_I2C_ADDR;
3530                serial_bytes[0] = GAIN_0_2;
3531                break;
3532        case 7:         /*  chan 3 gain */
3533                i2c_addr = CALDAC1_I2C_ADDR;
3534                serial_bytes[0] = GAIN_1_3;
3535                break;
3536        default:
3537                dev_err(dev->class_dev, "invalid caldac channel\n");
3538                return -1;
3539        }
3540        serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3541        serial_bytes[2] = value & 0xff;
3542        i2c_write(dev, i2c_addr, serial_bytes, 3);
3543        return 0;
3544}
3545
3546static void caldac_write(struct comedi_device *dev, unsigned int channel,
3547                         unsigned int value)
3548{
3549        const struct pcidas64_board *thisboard = dev->board_ptr;
3550
3551        switch (thisboard->layout) {
3552        case LAYOUT_60XX:
3553        case LAYOUT_64XX:
3554                caldac_8800_write(dev, channel, value);
3555                break;
3556        case LAYOUT_4020:
3557                caldac_i2c_write(dev, channel, value);
3558                break;
3559        default:
3560                break;
3561        }
3562}
3563
3564static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3565                                        struct comedi_subdevice *s,
3566                                        struct comedi_insn *insn,
3567                                        unsigned int *data)
3568{
3569        unsigned int chan = CR_CHAN(insn->chanspec);
3570
3571        /*
3572         * Programming the calib device is slow. Only write the
3573         * last data value if the value has changed.
3574         */
3575        if (insn->n) {
3576                unsigned int val = data[insn->n - 1];
3577
3578                if (s->readback[chan] != val) {
3579                        caldac_write(dev, chan, val);
3580                        s->readback[chan] = val;
3581                }
3582        }
3583
3584        return insn->n;
3585}
3586
3587static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3588                         unsigned int value)
3589{
3590        struct pcidas64_private *devpriv = dev->private;
3591        static const int bitstream_length = 10;
3592        unsigned int bit, register_bits;
3593        unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3594        static const int ad8402_udelay = 1;
3595
3596        register_bits = SELECT_8402_64XX_BIT;
3597        udelay(ad8402_udelay);
3598        writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3599
3600        for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3601                if (bitstream & bit)
3602                        register_bits |= SERIAL_DATA_IN_BIT;
3603                else
3604                        register_bits &= ~SERIAL_DATA_IN_BIT;
3605                udelay(ad8402_udelay);
3606                writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3607                udelay(ad8402_udelay);
3608                writew(register_bits | SERIAL_CLOCK_BIT,
3609                       devpriv->main_iobase + CALIBRATION_REG);
3610        }
3611
3612        udelay(ad8402_udelay);
3613        writew(0, devpriv->main_iobase + CALIBRATION_REG);
3614}
3615
3616/* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3617static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3618                                         struct comedi_subdevice *s,
3619                                         struct comedi_insn *insn,
3620                                         unsigned int *data)
3621{
3622        unsigned int chan = CR_CHAN(insn->chanspec);
3623
3624        /*
3625         * Programming the calib device is slow. Only write the
3626         * last data value if the value has changed.
3627         */
3628        if (insn->n) {
3629                unsigned int val = data[insn->n - 1];
3630
3631                if (s->readback[chan] != val) {
3632                        ad8402_write(dev, chan, val);
3633                        s->readback[chan] = val;
3634                }
3635        }
3636
3637        return insn->n;
3638}
3639
3640static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3641{
3642        struct pcidas64_private *devpriv = dev->private;
3643        static const int bitstream_length = 11;
3644        static const int read_command = 0x6;
3645        unsigned int bitstream = (read_command << 8) | address;
3646        unsigned int bit;
3647        void __iomem * const plx_control_addr =
3648                devpriv->plx9080_iobase + PLX_CONTROL_REG;
3649        uint16_t value;
3650        static const int value_length = 16;
3651        static const int eeprom_udelay = 1;
3652
3653        udelay(eeprom_udelay);
3654        devpriv->plx_control_bits &= ~CTL_EE_CLK & ~CTL_EE_CS;
3655        /*  make sure we don't send anything to the i2c bus on 4020 */
3656        devpriv->plx_control_bits |= CTL_USERO;
3657        writel(devpriv->plx_control_bits, plx_control_addr);
3658        /*  activate serial eeprom */
3659        udelay(eeprom_udelay);
3660        devpriv->plx_control_bits |= CTL_EE_CS;
3661        writel(devpriv->plx_control_bits, plx_control_addr);
3662
3663        /*  write read command and desired memory address */
3664        for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3665                /*  set bit to be written */
3666                udelay(eeprom_udelay);
3667                if (bitstream & bit)
3668                        devpriv->plx_control_bits |= CTL_EE_W;
3669                else
3670                        devpriv->plx_control_bits &= ~CTL_EE_W;
3671                writel(devpriv->plx_control_bits, plx_control_addr);
3672                /*  clock in bit */
3673                udelay(eeprom_udelay);
3674                devpriv->plx_control_bits |= CTL_EE_CLK;
3675                writel(devpriv->plx_control_bits, plx_control_addr);
3676                udelay(eeprom_udelay);
3677                devpriv->plx_control_bits &= ~CTL_EE_CLK;
3678                writel(devpriv->plx_control_bits, plx_control_addr);
3679        }
3680        /*  read back value from eeprom memory location */
3681        value = 0;
3682        for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3683                /*  clock out bit */
3684                udelay(eeprom_udelay);
3685                devpriv->plx_control_bits |= CTL_EE_CLK;
3686                writel(devpriv->plx_control_bits, plx_control_addr);
3687                udelay(eeprom_udelay);
3688                devpriv->plx_control_bits &= ~CTL_EE_CLK;
3689                writel(devpriv->plx_control_bits, plx_control_addr);
3690                udelay(eeprom_udelay);
3691                if (readl(plx_control_addr) & CTL_EE_R)
3692                        value |= bit;
3693        }
3694
3695        /*  deactivate eeprom serial input */
3696        udelay(eeprom_udelay);
3697        devpriv->plx_control_bits &= ~CTL_EE_CS;
3698        writel(devpriv->plx_control_bits, plx_control_addr);
3699
3700        return value;
3701}
3702
3703static int eeprom_read_insn(struct comedi_device *dev,
3704                            struct comedi_subdevice *s,
3705                            struct comedi_insn *insn, unsigned int *data)
3706{
3707        data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3708
3709        return 1;
3710}
3711
3712/* Allocate and initialize the subdevice structures.
3713 */
3714static int setup_subdevices(struct comedi_device *dev)
3715{
3716        const struct pcidas64_board *thisboard = dev->board_ptr;
3717        struct pcidas64_private *devpriv = dev->private;
3718        struct comedi_subdevice *s;
3719        int i;
3720        int ret;
3721
3722        ret = comedi_alloc_subdevices(dev, 10);
3723        if (ret)
3724                return ret;
3725
3726        s = &dev->subdevices[0];
3727        /* analog input subdevice */
3728        dev->read_subdev = s;
3729        s->type = COMEDI_SUBD_AI;
3730        s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3731        if (thisboard->layout == LAYOUT_60XX)
3732                s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3733        else if (thisboard->layout == LAYOUT_64XX)
3734                s->subdev_flags |= SDF_DIFF;
3735        /* XXX Number of inputs in differential mode is ignored */
3736        s->n_chan = thisboard->ai_se_chans;
3737        s->len_chanlist = 0x2000;
3738        s->maxdata = (1 << thisboard->ai_bits) - 1;
3739        s->range_table = thisboard->ai_range_table;
3740        s->insn_read = ai_rinsn;
3741        s->insn_config = ai_config_insn;
3742        s->do_cmd = ai_cmd;
3743        s->do_cmdtest = ai_cmdtest;
3744        s->cancel = ai_cancel;
3745        if (thisboard->layout == LAYOUT_4020) {
3746                uint8_t data;
3747                /*  set adc to read from inputs
3748                 *  (not internal calibration sources) */
3749                devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3750                /*  set channels to +-5 volt input ranges */
3751                for (i = 0; i < s->n_chan; i++)
3752                        devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3753                data = devpriv->i2c_cal_range_bits;
3754                i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3755        }
3756
3757        /* analog output subdevice */
3758        s = &dev->subdevices[1];
3759        if (thisboard->ao_nchan) {
3760                s->type = COMEDI_SUBD_AO;
3761                s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3762                                  SDF_GROUND | SDF_CMD_WRITE;
3763                s->n_chan = thisboard->ao_nchan;
3764                s->maxdata = (1 << thisboard->ao_bits) - 1;
3765                s->range_table = thisboard->ao_range_table;
3766                s->insn_write = ao_winsn;
3767
3768                ret = comedi_alloc_subdev_readback(s);
3769                if (ret)
3770                        return ret;
3771
3772                if (ao_cmd_is_supported(thisboard)) {
3773                        dev->write_subdev = s;
3774                        s->do_cmdtest = ao_cmdtest;
3775                        s->do_cmd = ao_cmd;
3776                        s->len_chanlist = thisboard->ao_nchan;
3777                        s->cancel = ao_cancel;
3778                }
3779        } else {
3780                s->type = COMEDI_SUBD_UNUSED;
3781        }
3782
3783        /*  digital input */
3784        s = &dev->subdevices[2];
3785        if (thisboard->layout == LAYOUT_64XX) {
3786                s->type = COMEDI_SUBD_DI;
3787                s->subdev_flags = SDF_READABLE;
3788                s->n_chan = 4;
3789                s->maxdata = 1;
3790                s->range_table = &range_digital;
3791                s->insn_bits = di_rbits;
3792        } else
3793                s->type = COMEDI_SUBD_UNUSED;
3794
3795        /*  digital output */
3796        if (thisboard->layout == LAYOUT_64XX) {
3797                s = &dev->subdevices[3];
3798                s->type = COMEDI_SUBD_DO;
3799                s->subdev_flags = SDF_WRITABLE;
3800                s->n_chan = 4;
3801                s->maxdata = 1;
3802                s->range_table = &range_digital;
3803                s->insn_bits = do_wbits;
3804        } else
3805                s->type = COMEDI_SUBD_UNUSED;
3806
3807        /* 8255 */
3808        s = &dev->subdevices[4];
3809        if (thisboard->has_8255) {
3810                if (thisboard->layout == LAYOUT_4020) {
3811                        ret = subdev_8255_init(dev, s, dio_callback_4020,
3812                                               I8255_4020_REG);
3813                } else {
3814                        ret = subdev_8255_mm_init(dev, s, NULL,
3815                                                  DIO_8255_OFFSET);
3816                }
3817                if (ret)
3818                        return ret;
3819        } else {
3820                s->type = COMEDI_SUBD_UNUSED;
3821        }
3822
3823        /*  8 channel dio for 60xx */
3824        s = &dev->subdevices[5];
3825        if (thisboard->layout == LAYOUT_60XX) {
3826                s->type = COMEDI_SUBD_DIO;
3827                s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3828                s->n_chan = 8;
3829                s->maxdata = 1;
3830                s->range_table = &range_digital;
3831                s->insn_config = dio_60xx_config_insn;
3832                s->insn_bits = dio_60xx_wbits;
3833        } else
3834                s->type = COMEDI_SUBD_UNUSED;
3835
3836        /*  caldac */
3837        s = &dev->subdevices[6];
3838        s->type = COMEDI_SUBD_CALIB;
3839        s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3840        s->n_chan = 8;
3841        if (thisboard->layout == LAYOUT_4020)
3842                s->maxdata = 0xfff;
3843        else
3844                s->maxdata = 0xff;
3845        s->insn_write = cb_pcidas64_calib_insn_write;
3846
3847        ret = comedi_alloc_subdev_readback(s);
3848        if (ret)
3849                return ret;
3850
3851        for (i = 0; i < s->n_chan; i++) {
3852                caldac_write(dev, i, s->maxdata / 2);
3853                s->readback[i] = s->maxdata / 2;
3854        }
3855
3856        /*  2 channel ad8402 potentiometer */
3857        s = &dev->subdevices[7];
3858        if (thisboard->layout == LAYOUT_64XX) {
3859                s->type = COMEDI_SUBD_CALIB;
3860                s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3861                s->n_chan = 2;
3862                s->maxdata = 0xff;
3863                s->insn_write = cb_pcidas64_ad8402_insn_write;
3864
3865                ret = comedi_alloc_subdev_readback(s);
3866                if (ret)
3867                        return ret;
3868
3869                for (i = 0; i < s->n_chan; i++) {
3870                        ad8402_write(dev, i, s->maxdata / 2);
3871                        s->readback[i] = s->maxdata / 2;
3872                }
3873        } else
3874                s->type = COMEDI_SUBD_UNUSED;
3875
3876        /* serial EEPROM, if present */
3877        s = &dev->subdevices[8];
3878        if (readl(devpriv->plx9080_iobase + PLX_CONTROL_REG) & CTL_EECHK) {
3879                s->type = COMEDI_SUBD_MEMORY;
3880                s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3881                s->n_chan = 128;
3882                s->maxdata = 0xffff;
3883                s->insn_read = eeprom_read_insn;
3884        } else
3885                s->type = COMEDI_SUBD_UNUSED;
3886
3887        /*  user counter subd XXX */
3888        s = &dev->subdevices[9];
3889        s->type = COMEDI_SUBD_UNUSED;
3890
3891        return 0;
3892}
3893
3894static int auto_attach(struct comedi_device *dev,
3895                       unsigned long context)
3896{
3897        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3898        const struct pcidas64_board *thisboard = NULL;
3899        struct pcidas64_private *devpriv;
3900        uint32_t local_range, local_decode;
3901        int retval;
3902
3903        if (context < ARRAY_SIZE(pcidas64_boards))
3904                thisboard = &pcidas64_boards[context];
3905        if (!thisboard)
3906                return -ENODEV;
3907        dev->board_ptr = thisboard;
3908
3909        devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3910        if (!devpriv)
3911                return -ENOMEM;
3912
3913        retval = comedi_pci_enable(dev);
3914        if (retval)
3915                return retval;
3916        pci_set_master(pcidev);
3917
3918        /* Initialize dev->board_name */
3919        dev->board_name = thisboard->name;
3920
3921        devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3922        devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3923
3924        devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
3925        devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
3926        dev->mmio = pci_ioremap_bar(pcidev, 3);
3927
3928        if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
3929                dev_warn(dev->class_dev, "failed to remap io memory\n");
3930                return -ENOMEM;
3931        }
3932
3933        /*  figure out what local addresses are */
3934        local_range = readl(devpriv->plx9080_iobase + PLX_LAS0RNG_REG) &
3935                      LRNG_MEM_MASK;
3936        local_decode = readl(devpriv->plx9080_iobase + PLX_LAS0MAP_REG) &
3937                       local_range & LMAP_MEM_MASK;
3938        devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
3939                                  ~local_range) | local_decode;
3940        local_range = readl(devpriv->plx9080_iobase + PLX_LAS1RNG_REG) &
3941                      LRNG_MEM_MASK;
3942        local_decode = readl(devpriv->plx9080_iobase + PLX_LAS1MAP_REG) &
3943                       local_range & LMAP_MEM_MASK;
3944        devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
3945                                  ~local_range) | local_decode;
3946
3947        retval = alloc_and_init_dma_members(dev);
3948        if (retval < 0)
3949                return retval;
3950
3951        devpriv->hw_revision =
3952                hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
3953        dev_dbg(dev->class_dev, "stc hardware revision %i\n",
3954                devpriv->hw_revision);
3955        init_plx9080(dev);
3956        init_stc_registers(dev);
3957
3958        retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
3959                             dev->board_name, dev);
3960        if (retval) {
3961                dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
3962                        pcidev->irq);
3963                return retval;
3964        }
3965        dev->irq = pcidev->irq;
3966        dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
3967
3968        retval = setup_subdevices(dev);
3969        if (retval < 0)
3970                return retval;
3971
3972        return 0;
3973}
3974
3975static void detach(struct comedi_device *dev)
3976{
3977        struct pcidas64_private *devpriv = dev->private;
3978
3979        if (dev->irq)
3980                free_irq(dev->irq, dev);
3981        if (devpriv) {
3982                if (devpriv->plx9080_iobase) {
3983                        disable_plx_interrupts(dev);
3984                        iounmap(devpriv->plx9080_iobase);
3985                }
3986                if (devpriv->main_iobase)
3987                        iounmap(devpriv->main_iobase);
3988                if (dev->mmio)
3989                        iounmap(dev->mmio);
3990        }
3991        comedi_pci_disable(dev);
3992        cb_pcidas64_free_dma(dev);
3993}
3994
3995static struct comedi_driver cb_pcidas64_driver = {
3996        .driver_name    = "cb_pcidas64",
3997        .module         = THIS_MODULE,
3998        .auto_attach    = auto_attach,
3999        .detach         = detach,
4000};
4001
4002static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4003                                 const struct pci_device_id *id)
4004{
4005        return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4006                                      id->driver_data);
4007}
4008
4009static const struct pci_device_id cb_pcidas64_pci_table[] = {
4010        { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4011        { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4012        { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4013        { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4014        { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4015        { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4016        { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4017        { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4018        { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4019        { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4020        { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4021        { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4022        { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4023        { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4024        { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4025        { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4026        { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4027        { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4028        { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4029        { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4030        { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4031        { 0 }
4032};
4033MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4034
4035static struct pci_driver cb_pcidas64_pci_driver = {
4036        .name           = "cb_pcidas64",
4037        .id_table       = cb_pcidas64_pci_table,
4038        .probe          = cb_pcidas64_pci_probe,
4039        .remove         = comedi_pci_auto_unconfig,
4040};
4041module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4042
4043MODULE_AUTHOR("Comedi http://www.comedi.org");
4044MODULE_DESCRIPTION("Comedi low-level driver");
4045MODULE_LICENSE("GPL");
4046
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