linux/drivers/staging/comedi/drivers/addi_apci_1564.c
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   1/*
   2 * addi_apci_1564.c
   3 * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
   4 *
   5 *      ADDI-DATA GmbH
   6 *      Dieselstrasse 3
   7 *      D-77833 Ottersweier
   8 *      Tel: +19(0)7223/9493-0
   9 *      Fax: +49(0)7223/9493-92
  10 *      http://www.addi-data.com
  11 *      info@addi-data.com
  12 *
  13 * This program is free software; you can redistribute it and/or modify it under
  14 * the terms of the GNU General Public License as published by the Free Software
  15 * Foundation; either version 2 of the License, or (at your option) any later
  16 * version.
  17 *
  18 * This program is distributed in the hope that it will be useful, but WITHOUT
  19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
  20 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  21 * details.
  22 */
  23
  24/*
  25 * Driver: addi_apci_1564
  26 * Description: ADDI-DATA APCI-1564 Digital I/O board
  27 * Devices: [ADDI-DATA] APCI-1564 (addi_apci_1564)
  28 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
  29 * Updated: Thu, 02 Jun 2016 13:12:46 -0700
  30 * Status: untested
  31 *
  32 * Configuration Options: not applicable, uses comedi PCI auto config
  33 *
  34 * This board has the following features:
  35 *   - 32 optically isolated digital inputs (24V), 16 of which can
  36 *     generate change-of-state (COS) interrupts (channels 4 to 19)
  37 *   - 32 optically isolated digital outputs (10V to 36V)
  38 *   - 1 8-bit watchdog for resetting the outputs
  39 *   - 1 12-bit timer
  40 *   - 3 32-bit counters
  41 *   - 2 diagnostic inputs
  42 *
  43 * The COS, timer, and counter subdevices all use the dev->read_subdev to
  44 * return the interrupt status. The sample data is updated and returned when
  45 * any of these subdevices generate an interrupt. The sample data format is:
  46 *
  47 *    Bit   Description
  48 *   -----  ------------------------------------------
  49 *    31    COS interrupt
  50 *    30    timer interrupt
  51 *    29    counter 2 interrupt
  52 *    28    counter 1 interrupt
  53 *    27    counter 0 interrupt
  54 *   26:20  not used
  55 *   19:4   COS digital input state (channels 19 to 4)
  56 *    3:0   not used
  57 *
  58 * The COS interrupts must be configured using an INSN_CONFIG_DIGITAL_TRIG
  59 * instruction before they can be enabled by an async command. The COS
  60 * interrupts will stay active until canceled.
  61 *
  62 * The timer subdevice does not use an async command. All control is handled
  63 * by the (*insn_config).
  64 *
  65 * FIXME: The format of the ADDI_TCW_TIMEBASE_REG is not descibed in the
  66 * datasheet I have. The INSN_CONFIG_SET_CLOCK_SRC currently just writes
  67 * the raw data[1] to this register along with the raw data[2] value to the
  68 * ADDI_TCW_RELOAD_REG. If anyone tests this and can determine the actual
  69 * timebase/reload operation please let me know.
  70 *
  71 * The counter subdevice also does not use an async command. All control is
  72 * handled by the (*insn_config).
  73 *
  74 * FIXME: The operation of the counters is not really described in the
  75 * datasheet I have. The (*insn_config) needs more work.
  76 */
  77
  78#include <linux/module.h>
  79#include <linux/interrupt.h>
  80
  81#include "../comedi_pci.h"
  82#include "addi_tcw.h"
  83#include "addi_watchdog.h"
  84
  85/*
  86 * PCI BAR 0
  87 *
  88 * PLD Revision 1.0 I/O Mapping
  89 *   0x00         93C76 EEPROM
  90 *   0x04 - 0x18  Timer 12-Bit
  91 *
  92 * PLD Revision 2.x I/O Mapping
  93 *   0x00         93C76 EEPROM
  94 *   0x04 - 0x14  Digital Input
  95 *   0x18 - 0x25  Digital Output
  96 *   0x28 - 0x44  Watchdog 8-Bit
  97 *   0x48 - 0x64  Timer 12-Bit
  98 */
  99#define APCI1564_EEPROM_REG                     0x00
 100#define APCI1564_EEPROM_VCC_STATUS              BIT(8)
 101#define APCI1564_EEPROM_TO_REV(x)               (((x) >> 4) & 0xf)
 102#define APCI1564_EEPROM_DI                      BIT(3)
 103#define APCI1564_EEPROM_DO                      BIT(2)
 104#define APCI1564_EEPROM_CS                      BIT(1)
 105#define APCI1564_EEPROM_CLK                     BIT(0)
 106#define APCI1564_REV1_TIMER_IOBASE              0x04
 107#define APCI1564_REV2_MAIN_IOBASE               0x04
 108#define APCI1564_REV2_TIMER_IOBASE              0x48
 109
 110/*
 111 * PCI BAR 1
 112 *
 113 * PLD Revision 1.0 I/O Mapping
 114 *   0x00 - 0x10  Digital Input
 115 *   0x14 - 0x20  Digital Output
 116 *   0x24 - 0x3c  Watchdog 8-Bit
 117 *
 118 * PLD Revision 2.x I/O Mapping
 119 *   0x00         Counter_0
 120 *   0x20         Counter_1
 121 *   0x30         Counter_3
 122 */
 123#define APCI1564_REV1_MAIN_IOBASE               0x00
 124
 125/*
 126 * dev->iobase Register Map
 127 *   PLD Revision 1.0 - PCI BAR 1 + 0x00
 128 *   PLD Revision 2.x - PCI BAR 0 + 0x04
 129 */
 130#define APCI1564_DI_REG                         0x00
 131#define APCI1564_DI_INT_MODE1_REG               0x04
 132#define APCI1564_DI_INT_MODE2_REG               0x08
 133#define APCI1564_DI_INT_MODE_MASK               0x000ffff0 /* chans [19:4] */
 134#define APCI1564_DI_INT_STATUS_REG              0x0c
 135#define APCI1564_DI_IRQ_REG                     0x10
 136#define APCI1564_DI_IRQ_ENA                     BIT(2)
 137#define APCI1564_DI_IRQ_MODE                    BIT(1)  /* 1=AND, 0=OR */
 138#define APCI1564_DO_REG                         0x14
 139#define APCI1564_DO_INT_CTRL_REG                0x18
 140#define APCI1564_DO_INT_CTRL_CC_INT_ENA         BIT(1)
 141#define APCI1564_DO_INT_CTRL_VCC_INT_ENA        BIT(0)
 142#define APCI1564_DO_INT_STATUS_REG              0x1c
 143#define APCI1564_DO_INT_STATUS_CC               BIT(1)
 144#define APCI1564_DO_INT_STATUS_VCC              BIT(0)
 145#define APCI1564_DO_IRQ_REG                     0x20
 146#define APCI1564_DO_IRQ_INTR                    BIT(0)
 147#define APCI1564_WDOG_IOBASE                    0x24
 148
 149/*
 150 * devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
 151 *   PLD Revision 1.0 - PCI BAR 0 + 0x04
 152 *   PLD Revision 2.x - PCI BAR 0 + 0x48
 153 */
 154
 155/*
 156 * devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
 157 *   PLD Revision 2.x - PCI BAR 1 + 0x00
 158 */
 159#define APCI1564_COUNTER(x)                     ((x) * 0x20)
 160
 161/*
 162 * The dev->read_subdev is used to return the interrupt events along with
 163 * the state of the interrupt capable inputs.
 164 */
 165#define APCI1564_EVENT_COS                      BIT(31)
 166#define APCI1564_EVENT_TIMER                    BIT(30)
 167#define APCI1564_EVENT_COUNTER(x)               BIT(27 + (x)) /* counter 0-2 */
 168#define APCI1564_EVENT_MASK                     0xfff0000f /* all but [19:4] */
 169
 170struct apci1564_private {
 171        unsigned long eeprom;   /* base address of EEPROM register */
 172        unsigned long timer;    /* base address of 12-bit timer */
 173        unsigned long counters; /* base address of 32-bit counters */
 174        unsigned int mode1;     /* rising-edge/high level channels */
 175        unsigned int mode2;     /* falling-edge/low level channels */
 176        unsigned int ctrl;      /* interrupt mode OR (edge) . AND (level) */
 177};
 178
 179static int apci1564_reset(struct comedi_device *dev)
 180{
 181        struct apci1564_private *devpriv = dev->private;
 182
 183        /* Disable the input interrupts and reset status register */
 184        outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
 185        inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
 186        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 187        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 188
 189        /* Reset the output channels and disable interrupts */
 190        outl(0x0, dev->iobase + APCI1564_DO_REG);
 191        outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG);
 192
 193        /* Reset the watchdog registers */
 194        addi_watchdog_reset(dev->iobase + APCI1564_WDOG_IOBASE);
 195
 196        /* Reset the timer registers */
 197        outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
 198        outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
 199
 200        if (devpriv->counters) {
 201                unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
 202
 203                /* Reset the counter registers */
 204                outl(0x0, iobase + APCI1564_COUNTER(0));
 205                outl(0x0, iobase + APCI1564_COUNTER(1));
 206                outl(0x0, iobase + APCI1564_COUNTER(2));
 207        }
 208
 209        return 0;
 210}
 211
 212static irqreturn_t apci1564_interrupt(int irq, void *d)
 213{
 214        struct comedi_device *dev = d;
 215        struct apci1564_private *devpriv = dev->private;
 216        struct comedi_subdevice *s = dev->read_subdev;
 217        unsigned int status;
 218        unsigned int ctrl;
 219        unsigned int chan;
 220
 221        s->state &= ~APCI1564_EVENT_MASK;
 222
 223        status = inl(dev->iobase + APCI1564_DI_IRQ_REG);
 224        if (status & APCI1564_DI_IRQ_ENA) {
 225                /* get the COS interrupt state and set the event flag */
 226                s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
 227                s->state &= APCI1564_DI_INT_MODE_MASK;
 228                s->state |= APCI1564_EVENT_COS;
 229
 230                /* clear the interrupt */
 231                outl(status & ~APCI1564_DI_IRQ_ENA,
 232                     dev->iobase + APCI1564_DI_IRQ_REG);
 233                outl(status, dev->iobase + APCI1564_DI_IRQ_REG);
 234        }
 235
 236        status = inl(devpriv->timer + ADDI_TCW_IRQ_REG);
 237        if (status & ADDI_TCW_IRQ) {
 238                s->state |= APCI1564_EVENT_TIMER;
 239
 240                /* clear the interrupt */
 241                ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
 242                outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
 243                outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
 244        }
 245
 246        if (devpriv->counters) {
 247                for (chan = 0; chan < 3; chan++) {
 248                        unsigned long iobase;
 249
 250                        iobase = devpriv->counters + APCI1564_COUNTER(chan);
 251
 252                        status = inl(iobase + ADDI_TCW_IRQ_REG);
 253                        if (status & ADDI_TCW_IRQ) {
 254                                s->state |= APCI1564_EVENT_COUNTER(chan);
 255
 256                                /* clear the interrupt */
 257                                ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
 258                                outl(0x0, iobase + ADDI_TCW_CTRL_REG);
 259                                outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
 260                        }
 261                }
 262        }
 263
 264        if (s->state & APCI1564_EVENT_MASK) {
 265                comedi_buf_write_samples(s, &s->state, 1);
 266                comedi_handle_events(dev, s);
 267        }
 268
 269        return IRQ_HANDLED;
 270}
 271
 272static int apci1564_di_insn_bits(struct comedi_device *dev,
 273                                 struct comedi_subdevice *s,
 274                                 struct comedi_insn *insn,
 275                                 unsigned int *data)
 276{
 277        data[1] = inl(dev->iobase + APCI1564_DI_REG);
 278
 279        return insn->n;
 280}
 281
 282static int apci1564_do_insn_bits(struct comedi_device *dev,
 283                                 struct comedi_subdevice *s,
 284                                 struct comedi_insn *insn,
 285                                 unsigned int *data)
 286{
 287        s->state = inl(dev->iobase + APCI1564_DO_REG);
 288
 289        if (comedi_dio_update_state(s, data))
 290                outl(s->state, dev->iobase + APCI1564_DO_REG);
 291
 292        data[1] = s->state;
 293
 294        return insn->n;
 295}
 296
 297static int apci1564_diag_insn_bits(struct comedi_device *dev,
 298                                   struct comedi_subdevice *s,
 299                                   struct comedi_insn *insn,
 300                                   unsigned int *data)
 301{
 302        data[1] = inl(dev->iobase + APCI1564_DO_INT_STATUS_REG) & 3;
 303
 304        return insn->n;
 305}
 306
 307/*
 308 * Change-Of-State (COS) interrupt configuration
 309 *
 310 * Channels 4 to 19 are interruptible. These channels can be configured
 311 * to generate interrupts based on AND/OR logic for the desired channels.
 312 *
 313 *      OR logic
 314 *              - reacts to rising or falling edges
 315 *              - interrupt is generated when any enabled channel
 316 *                meet the desired interrupt condition
 317 *
 318 *      AND logic
 319 *              - reacts to changes in level of the selected inputs
 320 *              - interrupt is generated when all enabled channels
 321 *                meet the desired interrupt condition
 322 *              - after an interrupt, a change in level must occur on
 323 *                the selected inputs to release the IRQ logic
 324 *
 325 * The COS interrupt must be configured before it can be enabled.
 326 *
 327 *      data[0] : INSN_CONFIG_DIGITAL_TRIG
 328 *      data[1] : trigger number (= 0)
 329 *      data[2] : configuration operation:
 330 *                COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
 331 *                COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
 332 *                COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
 333 *      data[3] : left-shift for data[4] and data[5]
 334 *      data[4] : rising-edge/high level channels
 335 *      data[5] : falling-edge/low level channels
 336 */
 337static int apci1564_cos_insn_config(struct comedi_device *dev,
 338                                    struct comedi_subdevice *s,
 339                                    struct comedi_insn *insn,
 340                                    unsigned int *data)
 341{
 342        struct apci1564_private *devpriv = dev->private;
 343        unsigned int shift, oldmask;
 344
 345        switch (data[0]) {
 346        case INSN_CONFIG_DIGITAL_TRIG:
 347                if (data[1] != 0)
 348                        return -EINVAL;
 349                shift = data[3];
 350                oldmask = (1U << shift) - 1;
 351                switch (data[2]) {
 352                case COMEDI_DIGITAL_TRIG_DISABLE:
 353                        devpriv->ctrl = 0;
 354                        devpriv->mode1 = 0;
 355                        devpriv->mode2 = 0;
 356                        outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
 357                        inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
 358                        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 359                        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 360                        break;
 361                case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
 362                        if (devpriv->ctrl != APCI1564_DI_IRQ_ENA) {
 363                                /* switching to 'OR' mode */
 364                                devpriv->ctrl = APCI1564_DI_IRQ_ENA;
 365                                /* wipe old channels */
 366                                devpriv->mode1 = 0;
 367                                devpriv->mode2 = 0;
 368                        } else {
 369                                /* preserve unspecified channels */
 370                                devpriv->mode1 &= oldmask;
 371                                devpriv->mode2 &= oldmask;
 372                        }
 373                        /* configure specified channels */
 374                        devpriv->mode1 |= data[4] << shift;
 375                        devpriv->mode2 |= data[5] << shift;
 376                        break;
 377                case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
 378                        if (devpriv->ctrl != (APCI1564_DI_IRQ_ENA |
 379                                              APCI1564_DI_IRQ_MODE)) {
 380                                /* switching to 'AND' mode */
 381                                devpriv->ctrl = APCI1564_DI_IRQ_ENA |
 382                                                APCI1564_DI_IRQ_MODE;
 383                                /* wipe old channels */
 384                                devpriv->mode1 = 0;
 385                                devpriv->mode2 = 0;
 386                        } else {
 387                                /* preserve unspecified channels */
 388                                devpriv->mode1 &= oldmask;
 389                                devpriv->mode2 &= oldmask;
 390                        }
 391                        /* configure specified channels */
 392                        devpriv->mode1 |= data[4] << shift;
 393                        devpriv->mode2 |= data[5] << shift;
 394                        break;
 395                default:
 396                        return -EINVAL;
 397                }
 398
 399                /* ensure the mode bits are in-range for channels [19:4] */
 400                devpriv->mode1 &= APCI1564_DI_INT_MODE_MASK;
 401                devpriv->mode2 &= APCI1564_DI_INT_MODE_MASK;
 402                break;
 403        default:
 404                return -EINVAL;
 405        }
 406        return insn->n;
 407}
 408
 409static int apci1564_cos_insn_bits(struct comedi_device *dev,
 410                                  struct comedi_subdevice *s,
 411                                  struct comedi_insn *insn,
 412                                  unsigned int *data)
 413{
 414        data[1] = s->state;
 415
 416        return 0;
 417}
 418
 419static int apci1564_cos_cmdtest(struct comedi_device *dev,
 420                                struct comedi_subdevice *s,
 421                                struct comedi_cmd *cmd)
 422{
 423        int err = 0;
 424
 425        /* Step 1 : check if triggers are trivially valid */
 426
 427        err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
 428        err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
 429        err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 430        err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 431        err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
 432
 433        if (err)
 434                return 1;
 435
 436        /* Step 2a : make sure trigger sources are unique */
 437        /* Step 2b : and mutually compatible */
 438
 439        /* Step 3: check if arguments are trivially valid */
 440
 441        err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 442        err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 443        err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 444        err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 445                                           cmd->chanlist_len);
 446        err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 447
 448        if (err)
 449                return 3;
 450
 451        /* Step 4: fix up any arguments */
 452
 453        /* Step 5: check channel list if it exists */
 454
 455        return 0;
 456}
 457
 458/*
 459 * Change-Of-State (COS) 'do_cmd' operation
 460 *
 461 * Enable the COS interrupt as configured by apci1564_cos_insn_config().
 462 */
 463static int apci1564_cos_cmd(struct comedi_device *dev,
 464                            struct comedi_subdevice *s)
 465{
 466        struct apci1564_private *devpriv = dev->private;
 467
 468        if (!devpriv->ctrl && !(devpriv->mode1 || devpriv->mode2)) {
 469                dev_warn(dev->class_dev,
 470                         "Interrupts disabled due to mode configuration!\n");
 471                return -EINVAL;
 472        }
 473
 474        outl(devpriv->mode1, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 475        outl(devpriv->mode2, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 476        outl(devpriv->ctrl, dev->iobase + APCI1564_DI_IRQ_REG);
 477
 478        return 0;
 479}
 480
 481static int apci1564_cos_cancel(struct comedi_device *dev,
 482                               struct comedi_subdevice *s)
 483{
 484        outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
 485        inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
 486        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 487        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 488
 489        return 0;
 490}
 491
 492static int apci1564_timer_insn_config(struct comedi_device *dev,
 493                                      struct comedi_subdevice *s,
 494                                      struct comedi_insn *insn,
 495                                      unsigned int *data)
 496{
 497        struct apci1564_private *devpriv = dev->private;
 498        unsigned int val;
 499
 500        switch (data[0]) {
 501        case INSN_CONFIG_ARM:
 502                if (data[1] > s->maxdata)
 503                        return -EINVAL;
 504                outl(data[1], devpriv->timer + ADDI_TCW_RELOAD_REG);
 505                outl(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_TIMER_ENA,
 506                     devpriv->timer + ADDI_TCW_CTRL_REG);
 507                break;
 508        case INSN_CONFIG_DISARM:
 509                outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
 510                break;
 511        case INSN_CONFIG_GET_COUNTER_STATUS:
 512                data[1] = 0;
 513                val = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
 514                if (val & ADDI_TCW_CTRL_IRQ_ENA)
 515                        data[1] |= COMEDI_COUNTER_ARMED;
 516                if (val & ADDI_TCW_CTRL_TIMER_ENA)
 517                        data[1] |= COMEDI_COUNTER_COUNTING;
 518                val = inl(devpriv->timer + ADDI_TCW_STATUS_REG);
 519                if (val & ADDI_TCW_STATUS_OVERFLOW)
 520                        data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
 521                data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
 522                          COMEDI_COUNTER_TERMINAL_COUNT;
 523                break;
 524        case INSN_CONFIG_SET_CLOCK_SRC:
 525                if (data[2] > s->maxdata)
 526                        return -EINVAL;
 527                outl(data[1], devpriv->timer + ADDI_TCW_TIMEBASE_REG);
 528                outl(data[2], devpriv->timer + ADDI_TCW_RELOAD_REG);
 529                break;
 530        case INSN_CONFIG_GET_CLOCK_SRC:
 531                data[1] = inl(devpriv->timer + ADDI_TCW_TIMEBASE_REG);
 532                data[2] = inl(devpriv->timer + ADDI_TCW_RELOAD_REG);
 533                break;
 534        default:
 535                return -EINVAL;
 536        }
 537
 538        return insn->n;
 539}
 540
 541static int apci1564_timer_insn_write(struct comedi_device *dev,
 542                                     struct comedi_subdevice *s,
 543                                     struct comedi_insn *insn,
 544                                     unsigned int *data)
 545{
 546        struct apci1564_private *devpriv = dev->private;
 547
 548        /* just write the last last to the reload register */
 549        if (insn->n) {
 550                unsigned int val = data[insn->n - 1];
 551
 552                outl(val, devpriv->timer + ADDI_TCW_RELOAD_REG);
 553        }
 554
 555        return insn->n;
 556}
 557
 558static int apci1564_timer_insn_read(struct comedi_device *dev,
 559                                    struct comedi_subdevice *s,
 560                                    struct comedi_insn *insn,
 561                                    unsigned int *data)
 562{
 563        struct apci1564_private *devpriv = dev->private;
 564        int i;
 565
 566        /* return the actual value of the timer */
 567        for (i = 0; i < insn->n; i++)
 568                data[i] = inl(devpriv->timer + ADDI_TCW_VAL_REG);
 569
 570        return insn->n;
 571}
 572
 573static int apci1564_counter_insn_config(struct comedi_device *dev,
 574                                        struct comedi_subdevice *s,
 575                                        struct comedi_insn *insn,
 576                                        unsigned int *data)
 577{
 578        struct apci1564_private *devpriv = dev->private;
 579        unsigned int chan = CR_CHAN(insn->chanspec);
 580        unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
 581        unsigned int val;
 582
 583        switch (data[0]) {
 584        case INSN_CONFIG_ARM:
 585                val = inl(iobase + ADDI_TCW_CTRL_REG);
 586                val |= ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA;
 587                outl(data[1], iobase + ADDI_TCW_RELOAD_REG);
 588                outl(val, iobase + ADDI_TCW_CTRL_REG);
 589                break;
 590        case INSN_CONFIG_DISARM:
 591                val = inl(iobase + ADDI_TCW_CTRL_REG);
 592                val &= ~(ADDI_TCW_CTRL_IRQ_ENA | ADDI_TCW_CTRL_CNTR_ENA);
 593                outl(val, iobase + ADDI_TCW_CTRL_REG);
 594                break;
 595        case INSN_CONFIG_SET_COUNTER_MODE:
 596                /*
 597                 * FIXME: The counter operation is not described in the
 598                 * datasheet. For now just write the raw data[1] value to
 599                 * the control register.
 600                 */
 601                outl(data[1], iobase + ADDI_TCW_CTRL_REG);
 602                break;
 603        case INSN_CONFIG_GET_COUNTER_STATUS:
 604                data[1] = 0;
 605                val = inl(iobase + ADDI_TCW_CTRL_REG);
 606                if (val & ADDI_TCW_CTRL_IRQ_ENA)
 607                        data[1] |= COMEDI_COUNTER_ARMED;
 608                if (val & ADDI_TCW_CTRL_CNTR_ENA)
 609                        data[1] |= COMEDI_COUNTER_COUNTING;
 610                val = inl(iobase + ADDI_TCW_STATUS_REG);
 611                if (val & ADDI_TCW_STATUS_OVERFLOW)
 612                        data[1] |= COMEDI_COUNTER_TERMINAL_COUNT;
 613                data[2] = COMEDI_COUNTER_ARMED | COMEDI_COUNTER_COUNTING |
 614                          COMEDI_COUNTER_TERMINAL_COUNT;
 615                break;
 616        default:
 617                return -EINVAL;
 618        }
 619
 620        return insn->n;
 621}
 622
 623static int apci1564_counter_insn_write(struct comedi_device *dev,
 624                                       struct comedi_subdevice *s,
 625                                       struct comedi_insn *insn,
 626                                       unsigned int *data)
 627{
 628        struct apci1564_private *devpriv = dev->private;
 629        unsigned int chan = CR_CHAN(insn->chanspec);
 630        unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
 631
 632        /* just write the last last to the reload register */
 633        if (insn->n) {
 634                unsigned int val = data[insn->n - 1];
 635
 636                outl(val, iobase + ADDI_TCW_RELOAD_REG);
 637        }
 638
 639        return insn->n;
 640}
 641
 642static int apci1564_counter_insn_read(struct comedi_device *dev,
 643                                      struct comedi_subdevice *s,
 644                                      struct comedi_insn *insn,
 645                                      unsigned int *data)
 646{
 647        struct apci1564_private *devpriv = dev->private;
 648        unsigned int chan = CR_CHAN(insn->chanspec);
 649        unsigned long iobase = devpriv->counters + APCI1564_COUNTER(chan);
 650        int i;
 651
 652        /* return the actual value of the counter */
 653        for (i = 0; i < insn->n; i++)
 654                data[i] = inl(iobase + ADDI_TCW_VAL_REG);
 655
 656        return insn->n;
 657}
 658
 659static int apci1564_auto_attach(struct comedi_device *dev,
 660                                unsigned long context_unused)
 661{
 662        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 663        struct apci1564_private *devpriv;
 664        struct comedi_subdevice *s;
 665        unsigned int val;
 666        int ret;
 667
 668        devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 669        if (!devpriv)
 670                return -ENOMEM;
 671
 672        ret = comedi_pci_enable(dev);
 673        if (ret)
 674                return ret;
 675
 676        /* read the EEPROM register and check the I/O map revision */
 677        devpriv->eeprom = pci_resource_start(pcidev, 0);
 678        val = inl(devpriv->eeprom + APCI1564_EEPROM_REG);
 679        if (APCI1564_EEPROM_TO_REV(val) == 0) {
 680                /* PLD Revision 1.0 I/O Mapping */
 681                dev->iobase = pci_resource_start(pcidev, 1) +
 682                              APCI1564_REV1_MAIN_IOBASE;
 683                devpriv->timer = devpriv->eeprom + APCI1564_REV1_TIMER_IOBASE;
 684        } else {
 685                /* PLD Revision 2.x I/O Mapping */
 686                dev->iobase = devpriv->eeprom + APCI1564_REV2_MAIN_IOBASE;
 687                devpriv->timer = devpriv->eeprom + APCI1564_REV2_TIMER_IOBASE;
 688                devpriv->counters = pci_resource_start(pcidev, 1);
 689        }
 690
 691        apci1564_reset(dev);
 692
 693        if (pcidev->irq > 0) {
 694                ret = request_irq(pcidev->irq, apci1564_interrupt, IRQF_SHARED,
 695                                  dev->board_name, dev);
 696                if (ret == 0)
 697                        dev->irq = pcidev->irq;
 698        }
 699
 700        ret = comedi_alloc_subdevices(dev, 7);
 701        if (ret)
 702                return ret;
 703
 704        /*  Allocate and Initialise DI Subdevice Structures */
 705        s = &dev->subdevices[0];
 706        s->type         = COMEDI_SUBD_DI;
 707        s->subdev_flags = SDF_READABLE;
 708        s->n_chan       = 32;
 709        s->maxdata      = 1;
 710        s->range_table  = &range_digital;
 711        s->insn_bits    = apci1564_di_insn_bits;
 712
 713        /*  Allocate and Initialise DO Subdevice Structures */
 714        s = &dev->subdevices[1];
 715        s->type         = COMEDI_SUBD_DO;
 716        s->subdev_flags = SDF_WRITABLE;
 717        s->n_chan       = 32;
 718        s->maxdata      = 1;
 719        s->range_table  = &range_digital;
 720        s->insn_bits    = apci1564_do_insn_bits;
 721
 722        /* Change-Of-State (COS) interrupt subdevice */
 723        s = &dev->subdevices[2];
 724        if (dev->irq) {
 725                dev->read_subdev = s;
 726                s->type         = COMEDI_SUBD_DI;
 727                s->subdev_flags = SDF_READABLE | SDF_CMD_READ | SDF_LSAMPL;
 728                s->n_chan       = 1;
 729                s->maxdata      = 1;
 730                s->range_table  = &range_digital;
 731                s->len_chanlist = 1;
 732                s->insn_config  = apci1564_cos_insn_config;
 733                s->insn_bits    = apci1564_cos_insn_bits;
 734                s->do_cmdtest   = apci1564_cos_cmdtest;
 735                s->do_cmd       = apci1564_cos_cmd;
 736                s->cancel       = apci1564_cos_cancel;
 737        } else {
 738                s->type         = COMEDI_SUBD_UNUSED;
 739        }
 740
 741        /* Timer subdevice */
 742        s = &dev->subdevices[3];
 743        s->type         = COMEDI_SUBD_TIMER;
 744        s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
 745        s->n_chan       = 1;
 746        s->maxdata      = 0x0fff;
 747        s->range_table  = &range_digital;
 748        s->insn_config  = apci1564_timer_insn_config;
 749        s->insn_write   = apci1564_timer_insn_write;
 750        s->insn_read    = apci1564_timer_insn_read;
 751
 752        /* Counter subdevice */
 753        s = &dev->subdevices[4];
 754        if (devpriv->counters) {
 755                s->type         = COMEDI_SUBD_COUNTER;
 756                s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
 757                s->n_chan       = 3;
 758                s->maxdata      = 0xffffffff;
 759                s->range_table  = &range_digital;
 760                s->insn_config  = apci1564_counter_insn_config;
 761                s->insn_write   = apci1564_counter_insn_write;
 762                s->insn_read    = apci1564_counter_insn_read;
 763        } else {
 764                s->type         = COMEDI_SUBD_UNUSED;
 765        }
 766
 767        /* Initialize the watchdog subdevice */
 768        s = &dev->subdevices[5];
 769        ret = addi_watchdog_init(s, dev->iobase + APCI1564_WDOG_IOBASE);
 770        if (ret)
 771                return ret;
 772
 773        /* Initialize the diagnostic status subdevice */
 774        s = &dev->subdevices[6];
 775        s->type         = COMEDI_SUBD_DI;
 776        s->subdev_flags = SDF_READABLE;
 777        s->n_chan       = 2;
 778        s->maxdata      = 1;
 779        s->range_table  = &range_digital;
 780        s->insn_bits    = apci1564_diag_insn_bits;
 781
 782        return 0;
 783}
 784
 785static void apci1564_detach(struct comedi_device *dev)
 786{
 787        if (dev->iobase)
 788                apci1564_reset(dev);
 789        comedi_pci_detach(dev);
 790}
 791
 792static struct comedi_driver apci1564_driver = {
 793        .driver_name    = "addi_apci_1564",
 794        .module         = THIS_MODULE,
 795        .auto_attach    = apci1564_auto_attach,
 796        .detach         = apci1564_detach,
 797};
 798
 799static int apci1564_pci_probe(struct pci_dev *dev,
 800                              const struct pci_device_id *id)
 801{
 802        return comedi_pci_auto_config(dev, &apci1564_driver, id->driver_data);
 803}
 804
 805static const struct pci_device_id apci1564_pci_table[] = {
 806        { PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1006) },
 807        { 0 }
 808};
 809MODULE_DEVICE_TABLE(pci, apci1564_pci_table);
 810
 811static struct pci_driver apci1564_pci_driver = {
 812        .name           = "addi_apci_1564",
 813        .id_table       = apci1564_pci_table,
 814        .probe          = apci1564_pci_probe,
 815        .remove         = comedi_pci_auto_unconfig,
 816};
 817module_comedi_pci_driver(apci1564_driver, apci1564_pci_driver);
 818
 819MODULE_AUTHOR("Comedi http://www.comedi.org");
 820MODULE_DESCRIPTION("ADDI-DATA APCI-1564, 32 channel DI / 32 channel DO boards");
 821MODULE_LICENSE("GPL");
 822
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