linux/drivers/staging/comedi/drivers/addi_apci_1564.c
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   1/*
   2 * addi_apci_1564.c
   3 * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
   4 *
   5 *      ADDI-DATA GmbH
   6 *      Dieselstrasse 3
   7 *      D-77833 Ottersweier
   8 *      Tel: +19(0)7223/9493-0
   9 *      Fax: +49(0)7223/9493-92
  10 *      http://www.addi-data.com
  11 *      info@addi-data.com
  12 *
  13 * This program is free software; you can redistribute it and/or modify it under
  14 * the terms of the GNU General Public License as published by the Free Software
  15 * Foundation; either version 2 of the License, or (at your option) any later
  16 * version.
  17 *
  18 * This program is distributed in the hope that it will be useful, but WITHOUT
  19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
  20 * FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
  21 * details.
  22 */
  23
  24#include <linux/module.h>
  25#include <linux/interrupt.h>
  26#include <linux/sched.h>
  27
  28#include "../comedi_pci.h"
  29#include "addi_tcw.h"
  30#include "addi_watchdog.h"
  31
  32/*
  33 * PCI BAR 0
  34 *
  35 * PLD Revision 1.0 I/O Mapping
  36 *   0x00         93C76 EEPROM
  37 *   0x04 - 0x18  Timer 12-Bit
  38 *
  39 * PLD Revision 2.x I/O Mapping
  40 *   0x00         93C76 EEPROM
  41 *   0x04 - 0x14  Digital Input
  42 *   0x18 - 0x25  Digital Output
  43 *   0x28 - 0x44  Watchdog 8-Bit
  44 *   0x48 - 0x64  Timer 12-Bit
  45 */
  46#define APCI1564_EEPROM_REG                     0x00
  47#define APCI1564_EEPROM_VCC_STATUS              BIT(8)
  48#define APCI1564_EEPROM_TO_REV(x)               (((x) >> 4) & 0xf)
  49#define APCI1564_EEPROM_DI                      BIT(3)
  50#define APCI1564_EEPROM_DO                      BIT(2)
  51#define APCI1564_EEPROM_CS                      BIT(1)
  52#define APCI1564_EEPROM_CLK                     BIT(0)
  53#define APCI1564_REV1_TIMER_IOBASE              0x04
  54#define APCI1564_REV2_MAIN_IOBASE               0x04
  55#define APCI1564_REV2_TIMER_IOBASE              0x48
  56
  57/*
  58 * PCI BAR 1
  59 *
  60 * PLD Revision 1.0 I/O Mapping
  61 *   0x00 - 0x10  Digital Input
  62 *   0x14 - 0x20  Digital Output
  63 *   0x24 - 0x3c  Watchdog 8-Bit
  64 *
  65 * PLD Revision 2.x I/O Mapping
  66 *   0x00         Counter_0
  67 *   0x20         Counter_1
  68 *   0x30         Counter_3
  69 */
  70#define APCI1564_REV1_MAIN_IOBASE               0x00
  71
  72/*
  73 * dev->iobase Register Map
  74 *   PLD Revision 1.0 - PCI BAR 1 + 0x00
  75 *   PLD Revision 2.x - PCI BAR 0 + 0x04
  76 */
  77#define APCI1564_DI_REG                         0x00
  78#define APCI1564_DI_INT_MODE1_REG               0x04
  79#define APCI1564_DI_INT_MODE2_REG               0x08
  80#define APCI1564_DI_INT_STATUS_REG              0x0c
  81#define APCI1564_DI_IRQ_REG                     0x10
  82#define APCI1564_DI_IRQ_ENA                     BIT(2)
  83#define APCI1564_DI_IRQ_MODE                    BIT(1)  /* 1=AND, 0=OR */
  84#define APCI1564_DO_REG                         0x14
  85#define APCI1564_DO_INT_CTRL_REG                0x18
  86#define APCI1564_DO_INT_CTRL_CC_INT_ENA         BIT(1)
  87#define APCI1564_DO_INT_CTRL_VCC_INT_ENA        BIT(0)
  88#define APCI1564_DO_INT_STATUS_REG              0x1c
  89#define APCI1564_DO_INT_STATUS_CC               BIT(1)
  90#define APCI1564_DO_INT_STATUS_VCC              BIT(0)
  91#define APCI1564_DO_IRQ_REG                     0x20
  92#define APCI1564_DO_IRQ_INTR                    BIT(0)
  93#define APCI1564_WDOG_REG                       0x24
  94#define APCI1564_WDOG_RELOAD_REG                0x28
  95#define APCI1564_WDOG_TIMEBASE_REG              0x2c
  96#define APCI1564_WDOG_CTRL_REG                  0x30
  97#define APCI1564_WDOG_STATUS_REG                0x34
  98#define APCI1564_WDOG_IRQ_REG                   0x38
  99#define APCI1564_WDOG_WARN_TIMEVAL_REG          0x3c
 100#define APCI1564_WDOG_WARN_TIMEBASE_REG         0x40
 101
 102/*
 103 * devpriv->timer Register Map (see addi_tcw.h for register/bit defines)
 104 *   PLD Revision 1.0 - PCI BAR 0 + 0x04
 105 *   PLD Revision 2.x - PCI BAR 0 + 0x48
 106 */
 107
 108/*
 109 * devpriv->counters Register Map (see addi_tcw.h for register/bit defines)
 110 *   PLD Revision 2.x - PCI BAR 1 + 0x00
 111 */
 112#define APCI1564_COUNTER(x)                     ((x) * 0x20)
 113
 114struct apci1564_private {
 115        unsigned long eeprom;   /* base address of EEPROM register */
 116        unsigned long timer;    /* base address of 12-bit timer */
 117        unsigned long counters; /* base address of 32-bit counters */
 118        unsigned int mode1;     /* riding-edge/high level channels */
 119        unsigned int mode2;     /* falling-edge/low level channels */
 120        unsigned int ctrl;      /* interrupt mode OR (edge) . AND (level) */
 121        struct task_struct *tsk_current;
 122};
 123
 124#include "addi-data/hwdrv_apci1564.c"
 125
 126static int apci1564_reset(struct comedi_device *dev)
 127{
 128        struct apci1564_private *devpriv = dev->private;
 129
 130        /* Disable the input interrupts and reset status register */
 131        outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
 132        inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
 133        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 134        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 135
 136        /* Reset the output channels and disable interrupts */
 137        outl(0x0, dev->iobase + APCI1564_DO_REG);
 138        outl(0x0, dev->iobase + APCI1564_DO_INT_CTRL_REG);
 139
 140        /* Reset the watchdog registers */
 141        addi_watchdog_reset(dev->iobase + APCI1564_WDOG_REG);
 142
 143        /* Reset the timer registers */
 144        outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
 145        outl(0x0, devpriv->timer + ADDI_TCW_RELOAD_REG);
 146
 147        if (devpriv->counters) {
 148                unsigned long iobase = devpriv->counters + ADDI_TCW_CTRL_REG;
 149
 150                /* Reset the counter registers */
 151                outl(0x0, iobase + APCI1564_COUNTER(0));
 152                outl(0x0, iobase + APCI1564_COUNTER(1));
 153                outl(0x0, iobase + APCI1564_COUNTER(2));
 154        }
 155
 156        return 0;
 157}
 158
 159static irqreturn_t apci1564_interrupt(int irq, void *d)
 160{
 161        struct comedi_device *dev = d;
 162        struct apci1564_private *devpriv = dev->private;
 163        struct comedi_subdevice *s = dev->read_subdev;
 164        unsigned int status;
 165        unsigned int ctrl;
 166        unsigned int chan;
 167
 168        status = inl(dev->iobase + APCI1564_DI_IRQ_REG);
 169        if (status & APCI1564_DI_IRQ_ENA) {
 170                /* disable the interrupt */
 171                outl(status & ~APCI1564_DI_IRQ_ENA,
 172                     dev->iobase + APCI1564_DI_IRQ_REG);
 173
 174                s->state = inl(dev->iobase + APCI1564_DI_INT_STATUS_REG) &
 175                           0xffff;
 176                comedi_buf_write_samples(s, &s->state, 1);
 177                comedi_handle_events(dev, s);
 178
 179                /* enable the interrupt */
 180                outl(status, dev->iobase + APCI1564_DI_IRQ_REG);
 181        }
 182
 183        status = inl(devpriv->timer + ADDI_TCW_IRQ_REG);
 184        if (status & 0x01) {
 185                /*  Disable Timer Interrupt */
 186                ctrl = inl(devpriv->timer + ADDI_TCW_CTRL_REG);
 187                outl(0x0, devpriv->timer + ADDI_TCW_CTRL_REG);
 188
 189                /* Send a signal to from kernel to user space */
 190                send_sig(SIGIO, devpriv->tsk_current, 0);
 191
 192                /*  Enable Timer Interrupt */
 193                outl(ctrl, devpriv->timer + ADDI_TCW_CTRL_REG);
 194        }
 195
 196        if (devpriv->counters) {
 197                for (chan = 0; chan < 4; chan++) {
 198                        unsigned long iobase;
 199
 200                        iobase = devpriv->counters + APCI1564_COUNTER(chan);
 201
 202                        status = inl(iobase + ADDI_TCW_IRQ_REG);
 203                        if (status & 0x01) {
 204                                /*  Disable Counter Interrupt */
 205                                ctrl = inl(iobase + ADDI_TCW_CTRL_REG);
 206                                outl(0x0, iobase + ADDI_TCW_CTRL_REG);
 207
 208                                /* Send a signal to from kernel to user space */
 209                                send_sig(SIGIO, devpriv->tsk_current, 0);
 210
 211                                /*  Enable Counter Interrupt */
 212                                outl(ctrl, iobase + ADDI_TCW_CTRL_REG);
 213                        }
 214                }
 215        }
 216
 217        return IRQ_HANDLED;
 218}
 219
 220static int apci1564_di_insn_bits(struct comedi_device *dev,
 221                                 struct comedi_subdevice *s,
 222                                 struct comedi_insn *insn,
 223                                 unsigned int *data)
 224{
 225        data[1] = inl(dev->iobase + APCI1564_DI_REG);
 226
 227        return insn->n;
 228}
 229
 230static int apci1564_do_insn_bits(struct comedi_device *dev,
 231                                 struct comedi_subdevice *s,
 232                                 struct comedi_insn *insn,
 233                                 unsigned int *data)
 234{
 235        s->state = inl(dev->iobase + APCI1564_DO_REG);
 236
 237        if (comedi_dio_update_state(s, data))
 238                outl(s->state, dev->iobase + APCI1564_DO_REG);
 239
 240        data[1] = s->state;
 241
 242        return insn->n;
 243}
 244
 245static int apci1564_diag_insn_bits(struct comedi_device *dev,
 246                                   struct comedi_subdevice *s,
 247                                   struct comedi_insn *insn,
 248                                   unsigned int *data)
 249{
 250        data[1] = inl(dev->iobase + APCI1564_DO_INT_STATUS_REG) & 3;
 251
 252        return insn->n;
 253}
 254
 255/*
 256 * Change-Of-State (COS) interrupt configuration
 257 *
 258 * Channels 0 to 15 are interruptible. These channels can be configured
 259 * to generate interrupts based on AND/OR logic for the desired channels.
 260 *
 261 *      OR logic
 262 *              - reacts to rising or falling edges
 263 *              - interrupt is generated when any enabled channel
 264 *                meet the desired interrupt condition
 265 *
 266 *      AND logic
 267 *              - reacts to changes in level of the selected inputs
 268 *              - interrupt is generated when all enabled channels
 269 *                meet the desired interrupt condition
 270 *              - after an interrupt, a change in level must occur on
 271 *                the selected inputs to release the IRQ logic
 272 *
 273 * The COS interrupt must be configured before it can be enabled.
 274 *
 275 *      data[0] : INSN_CONFIG_DIGITAL_TRIG
 276 *      data[1] : trigger number (= 0)
 277 *      data[2] : configuration operation:
 278 *                COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
 279 *                COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
 280 *                COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
 281 *      data[3] : left-shift for data[4] and data[5]
 282 *      data[4] : rising-edge/high level channels
 283 *      data[5] : falling-edge/low level channels
 284 */
 285static int apci1564_cos_insn_config(struct comedi_device *dev,
 286                                    struct comedi_subdevice *s,
 287                                    struct comedi_insn *insn,
 288                                    unsigned int *data)
 289{
 290        struct apci1564_private *devpriv = dev->private;
 291        unsigned int shift, oldmask;
 292
 293        switch (data[0]) {
 294        case INSN_CONFIG_DIGITAL_TRIG:
 295                if (data[1] != 0)
 296                        return -EINVAL;
 297                shift = data[3];
 298                oldmask = (1U << shift) - 1;
 299                switch (data[2]) {
 300                case COMEDI_DIGITAL_TRIG_DISABLE:
 301                        devpriv->ctrl = 0;
 302                        devpriv->mode1 = 0;
 303                        devpriv->mode2 = 0;
 304                        outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
 305                        inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
 306                        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 307                        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 308                        break;
 309                case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
 310                        if (devpriv->ctrl != APCI1564_DI_IRQ_ENA) {
 311                                /* switching to 'OR' mode */
 312                                devpriv->ctrl = APCI1564_DI_IRQ_ENA;
 313                                /* wipe old channels */
 314                                devpriv->mode1 = 0;
 315                                devpriv->mode2 = 0;
 316                        } else {
 317                                /* preserve unspecified channels */
 318                                devpriv->mode1 &= oldmask;
 319                                devpriv->mode2 &= oldmask;
 320                        }
 321                        /* configure specified channels */
 322                        devpriv->mode1 |= data[4] << shift;
 323                        devpriv->mode2 |= data[5] << shift;
 324                        break;
 325                case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
 326                        if (devpriv->ctrl != (APCI1564_DI_IRQ_ENA |
 327                                              APCI1564_DI_IRQ_MODE)) {
 328                                /* switching to 'AND' mode */
 329                                devpriv->ctrl = APCI1564_DI_IRQ_ENA |
 330                                                APCI1564_DI_IRQ_MODE;
 331                                /* wipe old channels */
 332                                devpriv->mode1 = 0;
 333                                devpriv->mode2 = 0;
 334                        } else {
 335                                /* preserve unspecified channels */
 336                                devpriv->mode1 &= oldmask;
 337                                devpriv->mode2 &= oldmask;
 338                        }
 339                        /* configure specified channels */
 340                        devpriv->mode1 |= data[4] << shift;
 341                        devpriv->mode2 |= data[5] << shift;
 342                        break;
 343                default:
 344                        return -EINVAL;
 345                }
 346                break;
 347        default:
 348                return -EINVAL;
 349        }
 350        return insn->n;
 351}
 352
 353static int apci1564_cos_insn_bits(struct comedi_device *dev,
 354                                  struct comedi_subdevice *s,
 355                                  struct comedi_insn *insn,
 356                                  unsigned int *data)
 357{
 358        data[1] = s->state;
 359
 360        return 0;
 361}
 362
 363static int apci1564_cos_cmdtest(struct comedi_device *dev,
 364                                struct comedi_subdevice *s,
 365                                struct comedi_cmd *cmd)
 366{
 367        int err = 0;
 368
 369        /* Step 1 : check if triggers are trivially valid */
 370
 371        err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW);
 372        err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
 373        err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
 374        err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
 375        err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
 376
 377        if (err)
 378                return 1;
 379
 380        /* Step 2a : make sure trigger sources are unique */
 381        /* Step 2b : and mutually compatible */
 382
 383        /* Step 3: check if arguments are trivially valid */
 384
 385        err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
 386        err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
 387        err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
 388        err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
 389                                           cmd->chanlist_len);
 390        err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
 391
 392        if (err)
 393                return 3;
 394
 395        /* Step 4: fix up any arguments */
 396
 397        /* Step 5: check channel list if it exists */
 398
 399        return 0;
 400}
 401
 402/*
 403 * Change-Of-State (COS) 'do_cmd' operation
 404 *
 405 * Enable the COS interrupt as configured by apci1564_cos_insn_config().
 406 */
 407static int apci1564_cos_cmd(struct comedi_device *dev,
 408                            struct comedi_subdevice *s)
 409{
 410        struct apci1564_private *devpriv = dev->private;
 411
 412        if (!devpriv->ctrl) {
 413                dev_warn(dev->class_dev,
 414                         "Interrupts disabled due to mode configuration!\n");
 415                return -EINVAL;
 416        }
 417
 418        outl(devpriv->mode1, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 419        outl(devpriv->mode2, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 420        outl(devpriv->ctrl, dev->iobase + APCI1564_DI_IRQ_REG);
 421
 422        return 0;
 423}
 424
 425static int apci1564_cos_cancel(struct comedi_device *dev,
 426                               struct comedi_subdevice *s)
 427{
 428        outl(0x0, dev->iobase + APCI1564_DI_IRQ_REG);
 429        inl(dev->iobase + APCI1564_DI_INT_STATUS_REG);
 430        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE1_REG);
 431        outl(0x0, dev->iobase + APCI1564_DI_INT_MODE2_REG);
 432
 433        return 0;
 434}
 435
 436static int apci1564_auto_attach(struct comedi_device *dev,
 437                                unsigned long context_unused)
 438{
 439        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 440        struct apci1564_private *devpriv;
 441        struct comedi_subdevice *s;
 442        unsigned int val;
 443        int ret;
 444
 445        devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
 446        if (!devpriv)
 447                return -ENOMEM;
 448
 449        ret = comedi_pci_enable(dev);
 450        if (ret)
 451                return ret;
 452
 453        /* read the EEPROM register and check the I/O map revision */
 454        devpriv->eeprom = pci_resource_start(pcidev, 0);
 455        val = inl(devpriv->eeprom + APCI1564_EEPROM_REG);
 456        if (APCI1564_EEPROM_TO_REV(val) == 0) {
 457                /* PLD Revision 1.0 I/O Mapping */
 458                dev->iobase = pci_resource_start(pcidev, 1) +
 459                              APCI1564_REV1_MAIN_IOBASE;
 460                devpriv->timer = devpriv->eeprom + APCI1564_REV1_TIMER_IOBASE;
 461        } else {
 462                /* PLD Revision 2.x I/O Mapping */
 463                dev->iobase = devpriv->eeprom + APCI1564_REV2_MAIN_IOBASE;
 464                devpriv->timer = devpriv->eeprom + APCI1564_REV2_TIMER_IOBASE;
 465                devpriv->counters = pci_resource_start(pcidev, 1);
 466        }
 467
 468        apci1564_reset(dev);
 469
 470        if (pcidev->irq > 0) {
 471                ret = request_irq(pcidev->irq, apci1564_interrupt, IRQF_SHARED,
 472                                  dev->board_name, dev);
 473                if (ret == 0)
 474                        dev->irq = pcidev->irq;
 475        }
 476
 477        ret = comedi_alloc_subdevices(dev, 7);
 478        if (ret)
 479                return ret;
 480
 481        /*  Allocate and Initialise DI Subdevice Structures */
 482        s = &dev->subdevices[0];
 483        s->type         = COMEDI_SUBD_DI;
 484        s->subdev_flags = SDF_READABLE;
 485        s->n_chan       = 32;
 486        s->maxdata      = 1;
 487        s->range_table  = &range_digital;
 488        s->insn_bits    = apci1564_di_insn_bits;
 489
 490        /*  Allocate and Initialise DO Subdevice Structures */
 491        s = &dev->subdevices[1];
 492        s->type         = COMEDI_SUBD_DO;
 493        s->subdev_flags = SDF_WRITABLE;
 494        s->n_chan       = 32;
 495        s->maxdata      = 1;
 496        s->range_table  = &range_digital;
 497        s->insn_bits    = apci1564_do_insn_bits;
 498
 499        /* Change-Of-State (COS) interrupt subdevice */
 500        s = &dev->subdevices[2];
 501        if (dev->irq) {
 502                dev->read_subdev = s;
 503                s->type         = COMEDI_SUBD_DI;
 504                s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
 505                s->n_chan       = 1;
 506                s->maxdata      = 1;
 507                s->range_table  = &range_digital;
 508                s->len_chanlist = 1;
 509                s->insn_config  = apci1564_cos_insn_config;
 510                s->insn_bits    = apci1564_cos_insn_bits;
 511                s->do_cmdtest   = apci1564_cos_cmdtest;
 512                s->do_cmd       = apci1564_cos_cmd;
 513                s->cancel       = apci1564_cos_cancel;
 514        } else {
 515                s->type         = COMEDI_SUBD_UNUSED;
 516        }
 517
 518        /* Timer subdevice */
 519        s = &dev->subdevices[3];
 520        s->type         = COMEDI_SUBD_TIMER;
 521        s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
 522        s->n_chan       = 1;
 523        s->maxdata      = 0x0fff;
 524        s->range_table  = &range_digital;
 525        s->insn_config  = apci1564_timer_insn_config;
 526        s->insn_write   = apci1564_timer_insn_write;
 527        s->insn_read    = apci1564_timer_insn_read;
 528
 529        /* Counter subdevice */
 530        s = &dev->subdevices[4];
 531        if (devpriv->counters) {
 532                s->type         = COMEDI_SUBD_COUNTER;
 533                s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
 534                s->n_chan       = 3;
 535                s->maxdata      = 0xffffffff;
 536                s->range_table  = &range_digital;
 537                s->insn_config  = apci1564_counter_insn_config;
 538                s->insn_write   = apci1564_counter_insn_write;
 539                s->insn_read    = apci1564_counter_insn_read;
 540        } else {
 541                s->type         = COMEDI_SUBD_UNUSED;
 542        }
 543
 544        /* Initialize the watchdog subdevice */
 545        s = &dev->subdevices[5];
 546        ret = addi_watchdog_init(s, dev->iobase + APCI1564_WDOG_REG);
 547        if (ret)
 548                return ret;
 549
 550        /* Initialize the diagnostic status subdevice */
 551        s = &dev->subdevices[6];
 552        s->type         = COMEDI_SUBD_DI;
 553        s->subdev_flags = SDF_READABLE;
 554        s->n_chan       = 2;
 555        s->maxdata      = 1;
 556        s->range_table  = &range_digital;
 557        s->insn_bits    = apci1564_diag_insn_bits;
 558
 559        return 0;
 560}
 561
 562static void apci1564_detach(struct comedi_device *dev)
 563{
 564        if (dev->iobase)
 565                apci1564_reset(dev);
 566        comedi_pci_detach(dev);
 567}
 568
 569static struct comedi_driver apci1564_driver = {
 570        .driver_name    = "addi_apci_1564",
 571        .module         = THIS_MODULE,
 572        .auto_attach    = apci1564_auto_attach,
 573        .detach         = apci1564_detach,
 574};
 575
 576static int apci1564_pci_probe(struct pci_dev *dev,
 577                              const struct pci_device_id *id)
 578{
 579        return comedi_pci_auto_config(dev, &apci1564_driver, id->driver_data);
 580}
 581
 582static const struct pci_device_id apci1564_pci_table[] = {
 583        { PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1006) },
 584        { 0 }
 585};
 586MODULE_DEVICE_TABLE(pci, apci1564_pci_table);
 587
 588static struct pci_driver apci1564_pci_driver = {
 589        .name           = "addi_apci_1564",
 590        .id_table       = apci1564_pci_table,
 591        .probe          = apci1564_pci_probe,
 592        .remove         = comedi_pci_auto_unconfig,
 593};
 594module_comedi_pci_driver(apci1564_driver, apci1564_pci_driver);
 595
 596MODULE_AUTHOR("Comedi http://www.comedi.org");
 597MODULE_DESCRIPTION("ADDI-DATA APCI-1564, 32 channel DI / 32 channel DO boards");
 598MODULE_LICENSE("GPL");
 599
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