linux/drivers/ptp/ptp_pch.c
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   1/*
   2 * PTP 1588 clock using the EG20T PCH
   3 *
   4 * Copyright (C) 2010 OMICRON electronics GmbH
   5 * Copyright (C) 2011-2012 LAPIS SEMICONDUCTOR Co., LTD.
   6 *
   7 * This code was derived from the IXP46X driver.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License as published by
  11 * the Free Software Foundation; version 2 of the License.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  21 */
  22
  23#include <linux/device.h>
  24#include <linux/err.h>
  25#include <linux/init.h>
  26#include <linux/interrupt.h>
  27#include <linux/io.h>
  28#include <linux/irq.h>
  29#include <linux/kernel.h>
  30#include <linux/module.h>
  31#include <linux/pci.h>
  32#include <linux/ptp_clock_kernel.h>
  33#include <linux/slab.h>
  34
  35#define STATION_ADDR_LEN        20
  36#define PCI_DEVICE_ID_PCH_1588  0x8819
  37#define IO_MEM_BAR 1
  38
  39#define DEFAULT_ADDEND 0xA0000000
  40#define TICKS_NS_SHIFT  5
  41#define N_EXT_TS        2
  42
  43enum pch_status {
  44        PCH_SUCCESS,
  45        PCH_INVALIDPARAM,
  46        PCH_NOTIMESTAMP,
  47        PCH_INTERRUPTMODEINUSE,
  48        PCH_FAILED,
  49        PCH_UNSUPPORTED,
  50};
  51/**
  52 * struct pch_ts_regs - IEEE 1588 registers
  53 */
  54struct pch_ts_regs {
  55        u32 control;
  56        u32 event;
  57        u32 addend;
  58        u32 accum;
  59        u32 test;
  60        u32 ts_compare;
  61        u32 rsystime_lo;
  62        u32 rsystime_hi;
  63        u32 systime_lo;
  64        u32 systime_hi;
  65        u32 trgt_lo;
  66        u32 trgt_hi;
  67        u32 asms_lo;
  68        u32 asms_hi;
  69        u32 amms_lo;
  70        u32 amms_hi;
  71        u32 ch_control;
  72        u32 ch_event;
  73        u32 tx_snap_lo;
  74        u32 tx_snap_hi;
  75        u32 rx_snap_lo;
  76        u32 rx_snap_hi;
  77        u32 src_uuid_lo;
  78        u32 src_uuid_hi;
  79        u32 can_status;
  80        u32 can_snap_lo;
  81        u32 can_snap_hi;
  82        u32 ts_sel;
  83        u32 ts_st[6];
  84        u32 reserve1[14];
  85        u32 stl_max_set_en;
  86        u32 stl_max_set;
  87        u32 reserve2[13];
  88        u32 srst;
  89};
  90
  91#define PCH_TSC_RESET           (1 << 0)
  92#define PCH_TSC_TTM_MASK        (1 << 1)
  93#define PCH_TSC_ASMS_MASK       (1 << 2)
  94#define PCH_TSC_AMMS_MASK       (1 << 3)
  95#define PCH_TSC_PPSM_MASK       (1 << 4)
  96#define PCH_TSE_TTIPEND         (1 << 1)
  97#define PCH_TSE_SNS             (1 << 2)
  98#define PCH_TSE_SNM             (1 << 3)
  99#define PCH_TSE_PPS             (1 << 4)
 100#define PCH_CC_MM               (1 << 0)
 101#define PCH_CC_TA               (1 << 1)
 102
 103#define PCH_CC_MODE_SHIFT       16
 104#define PCH_CC_MODE_MASK        0x001F0000
 105#define PCH_CC_VERSION          (1 << 31)
 106#define PCH_CE_TXS              (1 << 0)
 107#define PCH_CE_RXS              (1 << 1)
 108#define PCH_CE_OVR              (1 << 0)
 109#define PCH_CE_VAL              (1 << 1)
 110#define PCH_ECS_ETH             (1 << 0)
 111
 112#define PCH_ECS_CAN             (1 << 1)
 113#define PCH_STATION_BYTES       6
 114
 115#define PCH_IEEE1588_ETH        (1 << 0)
 116#define PCH_IEEE1588_CAN        (1 << 1)
 117/**
 118 * struct pch_dev - Driver private data
 119 */
 120struct pch_dev {
 121        struct pch_ts_regs __iomem *regs;
 122        struct ptp_clock *ptp_clock;
 123        struct ptp_clock_info caps;
 124        int exts0_enabled;
 125        int exts1_enabled;
 126
 127        u32 mem_base;
 128        u32 mem_size;
 129        u32 irq;
 130        struct pci_dev *pdev;
 131        spinlock_t register_lock;
 132};
 133
 134/**
 135 * struct pch_params - 1588 module parameter
 136 */
 137struct pch_params {
 138        u8 station[STATION_ADDR_LEN];
 139};
 140
 141/* structure to hold the module parameters */
 142static struct pch_params pch_param = {
 143        "00:00:00:00:00:00"
 144};
 145
 146/*
 147 * Register access functions
 148 */
 149static inline void pch_eth_enable_set(struct pch_dev *chip)
 150{
 151        u32 val;
 152        /* SET the eth_enable bit */
 153        val = ioread32(&chip->regs->ts_sel) | (PCH_ECS_ETH);
 154        iowrite32(val, (&chip->regs->ts_sel));
 155}
 156
 157static u64 pch_systime_read(struct pch_ts_regs __iomem *regs)
 158{
 159        u64 ns;
 160        u32 lo, hi;
 161
 162        lo = ioread32(&regs->systime_lo);
 163        hi = ioread32(&regs->systime_hi);
 164
 165        ns = ((u64) hi) << 32;
 166        ns |= lo;
 167        ns <<= TICKS_NS_SHIFT;
 168
 169        return ns;
 170}
 171
 172static void pch_systime_write(struct pch_ts_regs __iomem *regs, u64 ns)
 173{
 174        u32 hi, lo;
 175
 176        ns >>= TICKS_NS_SHIFT;
 177        hi = ns >> 32;
 178        lo = ns & 0xffffffff;
 179
 180        iowrite32(lo, &regs->systime_lo);
 181        iowrite32(hi, &regs->systime_hi);
 182}
 183
 184static inline void pch_block_reset(struct pch_dev *chip)
 185{
 186        u32 val;
 187        /* Reset Hardware Assist block */
 188        val = ioread32(&chip->regs->control) | PCH_TSC_RESET;
 189        iowrite32(val, (&chip->regs->control));
 190        val = val & ~PCH_TSC_RESET;
 191        iowrite32(val, (&chip->regs->control));
 192}
 193
 194u32 pch_ch_control_read(struct pci_dev *pdev)
 195{
 196        struct pch_dev *chip = pci_get_drvdata(pdev);
 197        u32 val;
 198
 199        val = ioread32(&chip->regs->ch_control);
 200
 201        return val;
 202}
 203EXPORT_SYMBOL(pch_ch_control_read);
 204
 205void pch_ch_control_write(struct pci_dev *pdev, u32 val)
 206{
 207        struct pch_dev *chip = pci_get_drvdata(pdev);
 208
 209        iowrite32(val, (&chip->regs->ch_control));
 210}
 211EXPORT_SYMBOL(pch_ch_control_write);
 212
 213u32 pch_ch_event_read(struct pci_dev *pdev)
 214{
 215        struct pch_dev *chip = pci_get_drvdata(pdev);
 216        u32 val;
 217
 218        val = ioread32(&chip->regs->ch_event);
 219
 220        return val;
 221}
 222EXPORT_SYMBOL(pch_ch_event_read);
 223
 224void pch_ch_event_write(struct pci_dev *pdev, u32 val)
 225{
 226        struct pch_dev *chip = pci_get_drvdata(pdev);
 227
 228        iowrite32(val, (&chip->regs->ch_event));
 229}
 230EXPORT_SYMBOL(pch_ch_event_write);
 231
 232u32 pch_src_uuid_lo_read(struct pci_dev *pdev)
 233{
 234        struct pch_dev *chip = pci_get_drvdata(pdev);
 235        u32 val;
 236
 237        val = ioread32(&chip->regs->src_uuid_lo);
 238
 239        return val;
 240}
 241EXPORT_SYMBOL(pch_src_uuid_lo_read);
 242
 243u32 pch_src_uuid_hi_read(struct pci_dev *pdev)
 244{
 245        struct pch_dev *chip = pci_get_drvdata(pdev);
 246        u32 val;
 247
 248        val = ioread32(&chip->regs->src_uuid_hi);
 249
 250        return val;
 251}
 252EXPORT_SYMBOL(pch_src_uuid_hi_read);
 253
 254u64 pch_rx_snap_read(struct pci_dev *pdev)
 255{
 256        struct pch_dev *chip = pci_get_drvdata(pdev);
 257        u64 ns;
 258        u32 lo, hi;
 259
 260        lo = ioread32(&chip->regs->rx_snap_lo);
 261        hi = ioread32(&chip->regs->rx_snap_hi);
 262
 263        ns = ((u64) hi) << 32;
 264        ns |= lo;
 265        ns <<= TICKS_NS_SHIFT;
 266
 267        return ns;
 268}
 269EXPORT_SYMBOL(pch_rx_snap_read);
 270
 271u64 pch_tx_snap_read(struct pci_dev *pdev)
 272{
 273        struct pch_dev *chip = pci_get_drvdata(pdev);
 274        u64 ns;
 275        u32 lo, hi;
 276
 277        lo = ioread32(&chip->regs->tx_snap_lo);
 278        hi = ioread32(&chip->regs->tx_snap_hi);
 279
 280        ns = ((u64) hi) << 32;
 281        ns |= lo;
 282        ns <<= TICKS_NS_SHIFT;
 283
 284        return ns;
 285}
 286EXPORT_SYMBOL(pch_tx_snap_read);
 287
 288/* This function enables all 64 bits in system time registers [high & low].
 289This is a work-around for non continuous value in the SystemTtp/pnr_pch.c#L229" id="L229" class="line"stemTtp/pline" name="L193"> 193
u32!h_rx_s);
pci_dev *chip)
 182     2   273}
ns <<= val, (0x01gs->regs->src_uuid_hi);
tl_maxdtp/peSTATION_ADDR_LEN" l_maxdtp/peS id="L287" class="line" name="L287"> 287
ns = ((val, (0xFFFFFFFFgs->regs->src_uuid_hi);
tl_maxdtp/TATION_ADDR_LEN" l_maxdtp/ id="L287" class="line" name="L287"> 287      f="+code=u32" class="sre2">u3229s="sref">iowrite32(val, (0x00gs->regs->src_uuid_hi);
tl_maxdtp/peSTATION_ADDR_LEN" l_maxdtp/peS id="L287" class="line" name="L287"> 287}
 286     2  struct  277     2  u32!h_rx_s);
pch_dev *chip)
 182
 152     2  val = 
 193
ns = (( 283     3  return  233}

 193
ns = (( 283<4a>}
 283void 3a href="+code=pch_ch_con3rol_w30id="L176" class="line" name="L176"> 173{
 143     3  struct  143<8a>     3 f="drivers/ptp/ptp_pch.3#L20930ef="drivers/ptp/ptp_pch.c#L14                                  IEEEers/pthvers/ptpwhenc#Loking at PTP" id="L147" class="line" name="L147"> 143<9a>     3   143}
 283 193
exts1_enabledstatio)
;
pci_dev *pdev)
 273u3231 id="L234" class="line" name="L234"> 233{
iowrite32( 283     3  struct pch_dev *chip = pci_get_drvdata(pdev);
 213     3   273
 193
val = if) regs->pci_get_drvdaNUL+code=pch_tx_snaNUL+_pch.c|">PCH_TSC_RESET;
< =ef"
statio))">pci_get_drvdaNUL+code=pch_tx_snaNUL+_pch.cL234" class="line" name="L234"> 233<9a>     3ef="drivers/ptp/ptp_pch.3#L22031f">val = ef">iowrite32(chip->-> 233     3  return vall = ef">iowri"
;
 213}
vall = a>;
 283 283
 193
iowrnr_p"
 233{
val = ef">iowrite32(val;
 243     3  struct iowrite32( 243
 223     3  iowref">iowrite32(pci_get_drvdahex_to_biSTATION_ADDR_LENhex_to_biS);
;
<[a href="drivers/=val" class="sreid="l* 3]"L216" class="line" name="L216"> 213<9a>     3ref="drivers/ptp/ptp_pch3c#L2332f">val = ef">iowrif) ite32( 233vall = ef">iowrite32(chip->-> 233
vall = l = ef">iowri"
;
 213u32332s="sref">vall = l = a>;
 283{
vall = L286" class="line" name="L286"> 283     3  struct iowrite32(ioread32(& 283{
val = ef">iowrite32(pci_get_drvdahex_to_biSTATION_ADDR_LENhex_to_biS);
;
<["
 213
iowrif) ite32( 233
val = l = ef">iowrite32(chip->-> 233     3ef="drivers/ptp/ptp_pch.3#L23933s="sref">iowref">iowrl = ef">iowri"
;
 213<9a>     3  return val = ef">iowrrrrrrrrra>;
 283}
vall = L286" class="line" name="L286"> 283vall = ite32(ior+ead32(& 283vall = 0"
 193
u32343s="sref">vall = if) -_pch.c);
;
<["

 233{
iowrl = ite32(chip->-> 233     3  struct val = ef">iowrref">vall = 0"
;
 213     3  iowrrrrrrrrra>;
 283
val = l = L286" class="line" name="L286"> 283     3   233
val = ef">iowri"
 193
 193
vall = ite32(chip->-> 213vall = 0val, (&chi->regs->tx_snap_hi);
 213
valL286" class="line" name="L286"> 283u6435s="sref">ns;
 213     3ref="drivers/ptp/ptp_pch3c#L2535 id="L286" class="line" name="L286"> 283     3  struct EXPORT_SYMBOL(pch_tx_snap_readtp/pt class_addasssa href="+code=pch_dtp/pt class_addassssref"L216" class="line" name="L216"> 213
 223     3   193
 143     3   193
hi void ;
exts1_enabledchix_s);)

 273
 273     3  pch_dev *chip = chipef">pci_get_drvdat>
 213     3  ns |= <>pch_dev *;
 = chip-> 213     3  pch_dev *;
L216" class="line" name="L216"> 213     3ef="drivers/ptp/ptp_pch.3#L26736f">u32 val;
hi;
 243     3  return  223}
val = ioread32(&chip->tx_snap_hi);
<="drivers/ptp/ptp_pc="dria>;
"L216" class="line" name="L216"> 213 283
valif) ite32( 233u64371s="sref">vall = ite32(;
L216" class="line" name="L216"> 213{
vall = if) ite32(chip->;
"cL234" class="line" name="L234"> 233     3  struct vall = l = ite32(ioread32(&chip->tx_snap_hi);
;
"L216" class="line" name="L216"> 213     3  iowrl = ite32(ioread32(&chip->tx_snap_hi);
;
"L216" class="line" name="L216"> 213     3  val = ef">iowrref">valsnap_hi);
<="drivers/ptp/ptp_pc="dria>;
.snap_hi);
ioread32(&;
L216" class="line" name="L216"> 213     3ef="drivers/ptp/ptp_pch.3#L27737 class="sref"ef">iowrrrrrrrrrsnap_hi);
<="drivers/ptp/ptp_pc="dria>;
.snap_hi);
 213     3  val = l = ef">iowrite32(;
.snap_hi);
hi) << 32;
 283     3  iowref">iowrl = ite32(;
.snap_hi);
 283
val = ef">iowrrrrrrrrrite32(;
.snap_hi);
TICKS_NS_SHIFT;
 283     3  vall = ef">iowrite32(chip->chi-> 213     3  vall = L286" class="line" name="L286"> 283     3   283
 283     3  return ns( 233}
val = ef">iowrite32(;
L216" class="line" name="L216"> 213     3f="+code=EXPORT_SYMBOL" 3lass=38 class="sref"ef">iowrif) ite32(chip->;
"cL234" class="line" name="L234"> 233
val = l = ef">iowrite32(ioread32(&chip->tx_snap_hi);
;
"L216" class="line" name="L216"> 213/* This 3uncti38s="sref">iowref">iowrl = ite32(ioread32(&chip->tx_snap_hi);
;
"L216" class="line" name="L216"> 213This is 3 work38f">val = ef">iowrrrrrrrrrite32(;
.snap_hi);
ioread32(&;
L216" class="line" name="L216"> 213s9" id="L369" clas1L289"6221" id="37ass=39ss="sref">vall = ef">iowrite32(;
.snap_hi);
 213s/a>     3  vall = l = ite32(;
.snap_hi);
hi) << 32;
 283}
vall = l = ite32(;
.snap_hi);
 283
vall = l = ite32(;
.snap_hi);
TICKS_NS_SHIFT;
 283     3f="+code=u32" class="sre3">u3239 class="sref"ef">iowrl = ite32(chip->chi-> 213}
val = ef">iowrL286" class="line" name="L286"> 283     3  struct  283
 223
val = if) ite32( 273     3  val = ef">iowrite32( 193
 274     4  return val = if) ite32( 234}
vall = 0val, (&tx_snap_hi);
<="drivers/ptp/ptp_pc="dria>;
"L216" class="line" name="L216"> 214<3a>}
vall = a>;
 284<4a>}
 284<5a>}
val = ef">iowra>;
 284<6a>}
 284     4  struct  224<8a>     4 f="drivers/ptp/ptp_pch.4#L20940ef="drivers/ptp/ptp_pch.c#Lteame="L193"> 193
 193
 193
 234
exts1_enabled, (>pch_dev *val =  274u3241 id="L234" class="line" name="L234"> 234{
iowrite32(ns;
 284     4  struct u32 lo, lo 284<6a>}
exts1_enabled 214
chip = chipef">pci_get_drvda#L22acler_oflass="sref">lo<#L22acler_ofa>;
 ite32(pch_dev *chip;
"L216" class="line" name="L216"> 214<8a>     4  val = >pch_dev *;
 = chip-> 214<9a>     4ef="drivers/ptp/ptp_pch.4#L22041id="L280" class="line" name="L280"> 284     4  return valif) ite32( 234}
vall = exts1_enabled 214vall = 0 214valL286" class="line" name="L286"> 284void 4a href="+code=pch_ch_eve4t_wri42s="sref">iowrite32( * 214     4ref="drivers/ptp/ptp_pch4c#L2242f">u32  284     4  struct u32  214
lo = lo *ns, (& 214     4   234<9a>     4ref="drivers/ptp/ptp_pch4c#L2342f">val = ite32( *lo(lo 214 274
ns |= val, (&tx_snap_hi);
 214u3243id="L263" class="line" name="L263"> 264{
vala>;
 214     4  struct  284{
 174
exts1_enabled, (>pch_dev *val = ns;
 274
vaL234" class="line" name="L234"> 234     4ef="drivers/ptp/ptp_pch.4#L23943f">val = ns;
 214<9a>     4  return val = unsigned long href="drivers/pflae=tx_snap_hi" claflae=id="L216" class="line" name="L216"> 214}
val>pch_dev *chip = chipef">pci_get_drvda#L22acler_oflass="sref">lo<#L22acler_ofa>;
 ite32(pch_dev *chip;
"L216" class="line" name="L216"> 214val>pch_dev *;
 = chip-> 214 264u32443s="sref">val;
 ->chip-> 214     4ref="drivers/ptp/ptp_pch4c#L2444s="sref">iowrite32( 214{
u32  214
u32 valef="drivers/ptp/ptptp_p#L18">vala>;
 ite32( 214
lo = ;
 ->chip-> 214     4   234
val = a>;
 214     4  return  284}
 234exts1_enabled, (>pch_dev *val = pch_dev *nsval =  274
 234u6445s="sref">iowrite32(ns;
 284     4ref="drivers/ptp/ptp_pch4c#L2545f">u32 lo,  284
u32  214
chip = chipef">pci_get_drvda#L22acler_oflass="sref">lo<#L22acler_ofa>;
 ite32(pch_dev *chip;
"L216" class="line" name="L216"> 214     4  val = >pch_dev *;
 = chip-> 214
 284     4  ns = ((;
 ->chip-> 214     4  ns |=  214
ns <<= ;
 ->chip-> 214
 284     4  iowrite32(tx_snap_hi);
;
 ite32( 214     4  u32 tx_snap_hi);
 284     4ef="drivers/ptp/ptp_pch.4#L26746f">u32 ;
 214     4  return  284}
 234exts1_enabled, (>pch_dev *val =  234
vall = ef">iowrrrr#L2sti>pch_dev *nsval =  274u64471s="sL234" class="line" name="L234"> 234{
ns <<= ns;
 284     4  struct valunsigned long href="drivers/pflae=tx_snap_hi" claflae=id="L216" class="line" name="L216"> 214     4  pch_dev *chip = chipef">pci_get_drvda#L22acler_oflass="sref">lo<#L22acler_ofa>;
 ite32(pch_dev *chip;
"L216" class="line" name="L216"> 214     4  pch_dev *;
 = chip-> 214     4ef="drivers/ptp/ptp_pch.4#L27747id="L277" class="line" name="L277"> 274     4  lo = tx_snap_hi);
 214}
val = tx_snap_hi);
 214 284     4  ns = ((;
 ->chip-> 284ns |= valef="drivers/ptp/ptptp_p#L18">vala>;
 ite32( 284{
ns <<= ;
 ->chip-> 284     4ef="drivers/ptp/ptp_pch.4#L2844 id="L284" class="line" name="L284"> 284     4  return ns;
 214}
 284     4f="+code=EXPORT_SYMBOL" 4lass=48id="L277" class="line" name="L277"> 274
vainlineexts1_enabled, (>pch_dev *val =  234/* This 4uncti48s="sref">iowref">iowrl = f">pch_dev * = chief">exts1_enabled 274This is 4 work48f">vaL234" class="line" name="L234"> 234s9" id="L469" clas1L289"6221" id="47ass=49ss="sref">val>pch_dev *chip = chipef">pci_get_drvda#L22acler_oflass="sref">lo<#L22acler_ofa>;
 ite32(pch_dev *chip;
"L216" class="line" name="L216"> 214s/a>     4   234}
valswitch) ite32(c">tx_snap_hi);
io.cL234" class="line" name="L234"> 234
valcase href="drivers/p_TP_CLK_REQ_EXTTSptp/ptp_pch.c#L_TP_CLK_REQ_EXTTSs="s:234" class="line" name="L234"> 234     4f="+code=u32" class="sre4">u3249 class="sref"ef">iowrswitch) ite32(c">tx_snap_hi);
c.snap_hi);
 234}
val = ef">iowrcase 0:234" class="line" name="L234"> 234     4  struct chip->;
>ef">pci_get_drvdaoSTATION_ADDR_LENonid=" ? 1 : 0L216" class="line" name="L216"> 214
val = l = ef">iowrbreakL216" class="line" name="L216"> 214iowref">iowrcase 1:234" class="line" name="L234"> 234val = ef">iowr"""""""">chip->;
>ef">pci_get_drvdaoSTATION_ADDR_LENonid=" ? 1 : 0L216" class="line" name="L216"> 215
vall = ef">iowrbreakL216" class="line" name="L216"> 215     5  return vall = default:234" class="line" name="L234"> 235}
vall =         a>;
 215<3a>}
vall = L286" class="line" name="L286"> 285<4a>}
iowra>;
 215<5a>}
val = default:234" class="line" name="L234"> 235<6a>}
 215<7a>}
val = L286" class="line" name="L286"> 285<8a>}
 235<9a>     5  val = a>;
 215}
 285 235
pch_dev *valexts1_enabled;
>efL234" class="line" name="L234"> 235u32513s="sref">val.snap_hi);
TICKS_NS_SHIFT 235{
iowr.snap_hi);
,  s="sref"""f">"
 235<5a>}
u32 );
u32  235<6a>}
);
TICKS_NS_SHIFTN_EXT_TSptp/ptp_pch.c#LN_EXT_TSid="h239" class="line" name="L239"> 235<7a>}
,  s="sref"ef0a239" class="line" name="L239"> 235<8a>}
val = .snap_hi);
 235<9a>     5ef="drivers/ptp/ptp_pch.5#L220519">val = .snap_hi);
TICKS_NS_SHIFTc"L232"_adjfreqregs" class="src"L232"_adjfreqa>, a239" class="line" name="L239"> 235     5  return val.snap_hi);
TICKS_NS_SHIFTc"L232"_adjtimeregs" class="src"L232"_adjtimea>, a239" class="line" name="L239"> 235val.snap_hi);
nsvf">TICKS_NS_SHIFTc"L232"_gettimeregs" class="src"L232"_gettimea>, a239" class="line" name="L239"> 235
val.snap_hi);
nsvf">TICKS_NS_SHIFTc"L232"_settimeregs" class="src"L232"_settimea>, a239" class="line" name="L239"> 235val.snap_hi);
TICKS_NS_SHIFTc"L232"_tp_pchregs" class="src"L232"_tp_pcha>, a239" class="line" name="L239"> 235{
 215     5ref="drivers/ptp/ptp_pch5c#L2252id="L176" class="line" name="L176"> 175     5  struct  275
lo<#ifdef">TICKS_NS_SHIFTCONFIG_PMptp/ptp_pch.c#LCONFIG_PMd="L277" class="line" name="L277"> 275<8a>}
, (>pch_dev * 275<9a>     5ref="drivers/ptp/ptp_pch5c#L2352f">vaL234" class="line" name="L234"> 235ns = ((cis_pch>chiicla>;
 ite32( 215
ns |= tp_pch_wakla>;
 ite32( 215
u3253id="L263" class="line" name="L263"> 265{
valif) ite32(;
 ite32( 235     5  struct iowrite32(;
 -> 215     5  val = ef">iowra>;
 215
 285
lo = ;
 ite32(;
 ite32( 215<8a>}
 235<9a>     5  return val = a>;
 215}
 285 235 void , (>pch_dev * 275u3254 id="L234" class="line" name="L234"> 235     5ref="drivers/ptp/ptp_pch5c#L2454s="sref">iowrite32(;regs" class="srretid="L216" class="line" name="L216"> 215{
 175
u32 ;
 ite32( 215
lo = ;
 ite32( 215     5  val =  *tp_pch_chiicla>;
 ite32( 215<9a>     5ef="drivers/ptp/ptp_pch.5#L25054f">val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 235     5  return vall = ite32(;
 ->tp_pch_chiicl failed\nc#L144" id="L"L216" class="line" name="L216"> 215}
vall = a>;
 215 2852" class=5ef="drivers/ptp/ptp_pch.5 534 284     4r5f="dr5vers/p#="drivers/ptp/ptp_pch.4lass=403s="sre5ass="sref5remasndeaid="L285" class5"line5 name=#def"L2p_pch.5#L22852">lo<#ifdef">TICKS_NS_SHIFTCONFIG_PMptp/ptpa>);
     5  recUL1 5ref="drivers/ptp/ptp_pch5c#L2454s="ss="sref">5o<#L22acler_ofa>;
 ite325/a>(<5 hr"t=#def"L2p_pch.5#L22852">lo<#"L286"> 285     5  recUL1 5ref="drivers/ptp/ptp_pch5c#L2454s="ss54f">val<_hi" cla__iomemp = <5 href5"+codo#ptpiff="drivers/ptp/ptp_pch5c#L2454s="s *lo;
 lo<#"Lmocid="L216" class=lo<#"LmociXPORT_SYMBOL" 5lass=54id="L232" class="line" name="L232"> 235 void 5s |=  274;
 ite32 215     5  vf">    5  ;
 ite32ne" name="un" cla4s= class="src"L232"_sname="un" cla4s=echip 283     3f="+code=u32" class="sre3>     5  u32 val = ef">iowrite5hi" clatv5nsecid=" =ev *valcase ihref="53id="l3ss="s39f">val = ef">iowrite5h="sref">5name="L285"> 284    54ef="56_LENonid=" ? 1 : 0L21tid=".cL234" clfree_is="sref">valcase free_is=echip 215valcase ihref="      5  val<16" class="line" name="L516"> 56ref="+code=tp/ptp_pch.c#L285" id=" +ea5_enabled<5c"L232"_settimeregs" cla5s="sr5"L232"_settime72" class="line" name="L2unmap the virtual IO mLmory 2" ss=de=val" cl3ss="s39f">val = ef">iowrite5ef="drive5s/ptp/ptp_pch.4#L27147ss5"sref57n>
 2line" name="L216"> 214  !/a>);
     5  recUL1 5reers/ptp/pi>tp_pch_chiicla>;
 ite32ns5timei57me="L234"> 234}
valcase iounmapechip 2lass="line" name="L216"> 214     4   534}
 2line" name="L216"> 214  /a>);
     5  recUL1 5re     4   s/ptp/ptp_pch.4#L2844 id="L284" cl5s="sref">5o<#L22acler_ofa>;
 ite325/a>(<5 hr"t=regs" cl72" class="line" name="L2rele" clthe coderved IO mLmory 2" ss=de=val" cl3ss="s39f">val = ef">iowrite5eline" na5_hi" cla__iomemp = <5 href576>
 2mLm_b" c47ass=49ss="sremLm_b" cef="53id="rs/ptp/pi>tp_pch_chiicla>;
 ite32chip-& name="L283"> 2lile" c_mLm_" cl 234 2mLm_b" c47ass=49ss="sremLm_b" cef="  2mLm_sizc47ass=49ss="sremLm_sizc> 214     4  547">lo =  2mLm_b" c47ass=49ss="sremLm_b" cef="5ef">loval s/ptp/ptp_pch.4#L2844 id="L284" cl532(&a5p;t5_snap_hi);
 275<9a>     5ref="drivers/ptp/ptp_pch5c#L2352f">vaL234" class="line" name="L234"> 2ea>;
 chip->vaL234" class="line" name="L234"> 2e* |= valef="drivers/ptp/ptppch.id="L286" class="lipch.id="ave_inliea>;
 ite32( 235     5  struct iowrite32(ea>;
 vf">    5   284   5 4ef=5driver}
 284    54  re5urn  235 _i>TICKS_NS_SHIFTCONL232""> _i>> 235val = ef">iowrite5a>;
 58l =  275u3254 id="wrl =5f">pch_dev *val = ns;
chief">exts1_enabled 274ns;
pch_dev<5a> *ch59#L18">valef="drivers/ptp/ptpchi"47ass=49ss="srechi"regs" class="sr"+i_reskzallo0000000ULLL216" kzallo0XPORT_izcofT_SYMBOL" 5lass=54id="L23_LENonid="L272" class="line" na)      5  reGFP_KERNE1regs>vaL234" class="line" name="L234"> 2ine" name5"L232"> 234}
);
     5  recUL1 5reeaL234" class="line" name="L234"> 2iivers_v"534" class="line" name="L534"> 534
u3249 5lass="sref"ef">iowrswitc5) ite59  5ref="drivers/ptp/ptp_pch5c#L2454s="snap_hi" c5aextt=f">c.snap_hi);5val = ef">iowrite5"""""""""5gt;;
 ite32( 215     5  pci_get_drvdaoSTAT5ON_AD5R_LENonid=" ? " =ev *iowrb6"> 215<9a>     5ef="drivers/ptp/ptp_pch.5#L25054f">val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 235     5  return iowrite32(chip-&gotob6"> 215<9a>    5#L_e=chip="line" name="L5#L_e=chipa href="dricould not save PCIr#L2fig i6tp_pchra>6
>ef">pci_get_drvdaoSTAT6ON_AD6R_LENonid=" ? s/ptp/ptp_pch.4#L2844 id="L284" cl6ef="drive6s/ptp/ptp_pch.5#L20150ss6"sref60"L286    5   = defau6t:234" class="line" name6"L23460ref="drivers/pa>;regs" classchi"47ass=49ss="srechi"regsline" name="L283"> 2mLm_b" c47ass=49ss="sremLm_b" cef="5eflass="sr"+i_restoreresourcsrechrval" class="srs
<_BARRT_SYMBOL" 5lasIO_>
<_BAR5     5   6         a>;
;regs" classchi"47ass=49ss="srechi"regsline" name="L283"> 2mLm_b" c47ass=49ss="sremLm_b" cef=""rs/ptp/pi>tp_pch_chiicla>;
 ite32}
<6 5rf="drivers/ptp/ptp_pc6.5las60echip-> 215<9a>     5ef="drivers/ptp/ptp_pch.5#L25054f">val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 235     5  return }
<6 extt=f">c.snap_hi);6re5#L60550 class="sref"ef">ir"+i_set_power_e=io"+i_restore_inlieregs" cde=chip" class="srcDEVchip-&gotob6"> 215<9a>    5#L_e=chechrval" class="srs<5#L_e=chechrva href="dricould not save PCIr#L2fig i6t8<3a>}
<6 >ef">pci_get_drvdaoSTAT6href=608LENonid=" ? s/ptp/ptp_pch.4#L2844 id="L284" cl6e9<3a>}
<6 "+code=u32" cl4ss="s49f6<7a>}60ref="+code=tp/ptp_pch.c#L285" id=" +ea6tp_pch.5#620950id="L239" class="li6e" na61L232"_settime72" class="line" name="L2lieriev6lthe availL216llength oflthe IO mLmory 2" ss=de=val" cl3ss="s39f">val = ef">iowrite6al" cl52"6cl50f">val = a>;
chip-> 2mLm_sizc47ass=49ss="sremLm_sizc> 215eflass="sr"+i_restoreresourcsrlip="line" name="Ltoreresourcsrlip5
<_BARRT_SYMBOL" 5lasIO_>
<_BAR5     5   61"L286    5  val = ef">iowrite6aall 6hr5f="+code=u32" class="6re5">61EINVALTATION_" =e!pa>;regs" classref="+c_mLm_" cl 234 2mLm_b" c47ass=49ss="sremLm_b" cef="  2mLm_sizc47ass=49ss="sremLm_sizc> 2135     5  return (<"rs/ptp/pi>tp_pch_chiicla>;
 ite32 265{
 215<9a>     5ef="drivers/ptp/ptp_pch.5#L25054f">val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 23/ptp/pi>tp_pch_chiicla>;
 ite32}
<6d="Lh239" class="line" n6me="L61550 class="sref"ef">iv *<72" class="lieturn iowrite32( 235<6a6}
chip-& name="L283"> 2liio"+i_restore_inlieregs" cde=chip" class="sBUSY 215<9a>    5#L_lif_mLm_" cl 234 s/ptp/ptp_pch.4#L2844 id="L284" cl6  5ef="dr6vers/ptp/ptp_pch.5#L220569">va62+code=iodifflass="sref">loval.snap_h72" class="line" name="L2get the virtual address tobthe 158< " cla4s=s=de=val" cl3ss="s39f">val = ef">iowrite65ref="dri6ers/ptp/ptp_pch5c#L225216="sre62#L18">valef="drivers/ptp/ptpchi"47ass=49ss="srechi"regsline" name="L283"> 2line" name="L216"> 214  /a>);
valcase io" napechip 2mLm_b" c47ass=49ss="sremLm_b" cef="  2mLm_sizc47ass=49ss="sremLm_sizc> 21chip->;regs" classchi"47ass=49ss="srechi"regsline" name="L283"> 2lass="line" name="L216"> 214rs/ptp/pi>tp_pch_chiicla>;
 ite32, ="sref"""f">TICKS_N6_SHIF62echip-> 215<9a>     5ef="drivers/ptp/ptp_pch.5#L25054f">val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 23<72" class="lieturn iowrite32(, a269" class="line" name="L269"> 262550 class="sref"ef">ir"+i_set_power_e=io"+i_restore_inlieregs" cde=chip" class="srchip
62="sref">chip-&gotob6"> 215<9a>    5#L_io" nap"sref">valcase 5#L_io" napa href="dricould not save PCIr#L2fig i6ip_pch.c#6f="+code=5ch_de52id="L276" cla628LENonid=" ? s/ptp/ptp_pch.4#L2844 id="L284" cl6" class="6refi>chip =  2ode=chip" class="sref">chipCKS_NS_SHIFTc"L232"_settimORT_SYMBOL" 5lass=51id="L232" classef="dricould not save PCIr#L2fig i635ns = (( 283     3f="+code=u32" class="sre3CKS_NS_SHIFTc"L232"_se= val = if) itechi"47ass=49ss="srechi"regsline" name="L283"> 2ode=chip" class="sref">chipf">iowrite32((;regs" class="srretid=".cL234" class="line" name="L234"> 2 |=  283     3f="+code=u32" class="sre3<"rs/ptp/pi>tp_pch_chiicla>;
 ite32}
 283     3f="+code=u32" class="sre3a hr5ef=6ef="drivers/ptp/ptp_pch56#L23563s="sref">valif) ite32gotob6"> 215<9a>    5#L_e"_sname="" cal" class="srs<5#L_e"_sname="" classef="dricould not save PCIr#L2fig i63="srtp_p6t;{
6al = ef">iowra>;
val = if) itechi"47ass=49ss="srechi"regsline" name="L283"> 2/a>{
nsp_pch.c#6/ahi= ;
6ite326valcase lif="+c_is=5valcase ihref=" val = if) iteis= class="src"L23is=he eth_enableL286" clIRQF_SHAREDRT_SYMBOL" 5lasIRQF_SHAREDhe eth_enableL286" clKBUILD2"_cNAMERT_SYMBOL" 5lasKBUILD2"_cNAMEef="  215<8a>}
<6 5ef=640INVALTATION_" =e_enableL286" cl"+i>tp_pch_chiiclef="driv53id="rs/ptp/pi>tp_pch_chiicla>;
 ite32 235<9a>    65  re64ass="srechip-&6"> 215<9a>     5ef="drivers/ptp/ptp_pch.5#L25054f">val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 23<72" class="lieturn vall = ite"L286" class="lineXPORT_SYMBOL" 5lass=55he e"srretid=".cL234" clis="sref">valcase ihref=" 64me="L234"> 234}
 215<9a>    5#L_lif_is="sref">valcase 5#L_lif_is=lassef="dricould not save PCIr#L2fig i6class="sr6;
 *    5   236 64hr"t=regs" cl72" class="line" name="L2indi0ate success de=val" cl3ss="s39f">val = ef">iowrite6ref">iowr6te32(;rechi"47ass=49ss="srechi"regsline" name="L283"> 2is="sref">valcase ihref="5KS_NS_SHIFTc"L232"XPORT_SYMBOL" 5lass=55he e"srretid=".cL234" clis="sref">valcase ihref="ef="dricould not save PCIr#L2fig i6c="s535">6ef="+code=va/pi_set_powe6_inli6regs" class="sr"+i_set_power_chi"47ass=49ss="srechi"regsline" name="L283"> 28XPORT_SYMBOL" 5lass=55he e5KS_NS_SHIFTc"L232"XPORT_SYMBOL" 5lass=55he eef="dricould not save PCIr#L2fig i6cp_pch.c#6a h5ef="drivers/ptp/ptp_6ch.5#624854">lo = ;
 ite32 2156/a> =  214 2/a>{
ns <<= ;
6->val.snap_h72" class="line" name="L2codet the ieee158< h/w de=val" cl3ss="s39f">val = ef">iowrite6icl faile6\nc#L144" id="L"L216" cl6ss="l65#L18">valef="drivers/ptp/ptpf="+cod+i>tp_pch_chiiclef="+cod+iechipvall = 6>;
chip->);
val = if) itechi"47ass=49ss="srechi"regsline" name="L283"> 2lass="line" name="L216"> 21line" name="L283"> 2addf">TICKS_NS_SHIFTCaddf">regsregs" class="srspin_unv" clirqresto6i234" cla6ass="line" name="L234"> 634;
 ite32ios_v"  class="srechipval = if) itechi"47ass=49ss="srechi"regsline" name="L283"> 2lass="line" name="L216"> 21line" name="L283"> 2trgt"sr="line" name="Ltrgt"srregsregs" class="srspin_unv" clirqresto6ief">iowr6e="L285"> 284     4r6f="dr65s;
val = if) itechi"47ass=49ss="srechi"regsline" name="L283"> 2lass="line" name="L216"> 21line" name="L283"> 2trgt"hi="line" name="Ltrgt"hiregsregs" class="srspin_unv" clirqresto6i="s535">6remasndeaid="L285" class6"line65egs" class="sr"+i_set_power_ios_v"  class="srechipval = if) itechi"47ass=49ss="srechi"regsline" name="L283"> 2lass="line" name="L216"> 21line" name="L283"> 2evnamesref">valcase 5vnamregsregs" class="srspin_unv" clirqresto6ip_pch.c#6o<#L22acler_ofa>;
 ite326/a>(<65lieregs" class="sr"+i_choose_inliea>;
6s54f">val6_hi" cla__iomemp = <6 href65hi= , _d+i>tp_pch_chiiclef="+ettimea>, _d+iechiplo;
 
tp_pch_chiiclef="+paramechi/a>);
 23<72" class="lieturn (<53id="rs/ptp/pi>tp_pch_chiicla>;
 ite326s |=  234}
tp_pch_chiiclef="+paramechi/a>);
 23<7/a"L216" class="line" name="L216"> 215tp_pch_chiicla>;
 ite32}
val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 23/ptp/pi>tp_pch_chiicla>;
 ite32valif) ite32l.snap_h72" class="lieturn vall = ite/ptp/pi>tp_pch_chiicla>;
 ite32->iowr646f">u32 iv *6nsecid=" =ev *chip-&s/ptp/ptp_pch.4#L2844 id="L284" cl6h="sref">6name="L285"> 284    64ef="668LENonid=" ? s/ptp/ptp_pch.4#L2844 id="L284" cl6e54f">val616" class="line" name="L616"> 66hi=  214 2/a>{
ns <<= pch_dev<6 *ns6timei67me="L6"> 215<9a>    5#L_lif_is="sref">valcase 5#L_lif_is=lass = L286" class="line" name="L286">6"sL234" c6ass="line" name="L234"> 634;regs" class=e" name="un" cla4s= class="src"L232"_sname="un" cla4s=echip 283     3f="+code=u32" class="sre3>     5   215<9a>    5#L_e"_sname="" cal" class="srs<5#L_e"_sname="" class = L286" class="line" name="L286">6"234" cla6o<#L22acler_ofa>;
 ite326/a>(<67cladiv_" c8a ma>;
 ite32iounmap"sref">valcase iounmapechip 2lass="line" name="L216"> 214     4   = <6 href67s;
 2line" name="L216"> 214  /a>);
     5  recUL1 5re     4       4  647">lo =  215<9a>    5#L_io" nap"sref">valcase 5#L_io" napa hr = L286" class="line" name="L286">6"54f">val6hi" cla4s="sr47f">val 2mLm_b" c47ass=49ss="sremLm_b" cef="  2mLm_sizc47ass=49ss="sremLm_sizc> 214   " class="line" name="L286">632(&a6p;t68+code=iodifflass="sref">lo;
  215<9a>    5#L_lif_mLm_" cl 2346e* |= valef="drivers/ptp/ptpchi"47ass=49ss="srechi"regsline" name="L283"> 2mLm_b" c47ass=49ss="sremLm_b" cef="5ef">lochip-> 215<9a>    5#L_e=chechrval" class="srs<5#L_e=chechrva hr = L286" class="line" name="L286">6e234" cla6 name="L280"> 284   6 4ef=68cladiv_" c8a ma>;
 ite32nclass="srsnlieid="L272" class="line" name="L272"> 275<9a>     5ref="drivers/ptp/ptp_pch5c#L2352f">vaL234" class="line" name="L234"> 6aline" na6name="L284"> 284    64  re68{
 68l = <6"> 215<9a>    5#L_e=chip="line" name="L5#L_e=chipa hr = L286" class="line" name="L286">6e="sref">6vaL234" class="line" name="L234"> 6wrl =6f">pch_dev *val = if) ite32(;regs" class="srretid=".cL234" class="line" name="L234"> 23<72" class="lieturn vall = ite"L286" class="lin"+i>tp_pch_chiiclef="drivevaL234" class="line" name="L234"> 6 p = 6a href="+codoqregs" clas6="srr69+code=iodifflass="sref">lo;
 ;
 ite326/a>(<69n>
tp_pch_ch6a> *ch69#L18"s/ptp/ptp_pch.4#L2844 id="L284" cl6ine" name6"L232"> 234}
chip-> 634}
 _i>TICKS_NS_SHIFTCONL232""> _i>> 235TICKS_NS_SHIFTCONFIieee158<_e=cpch.i>> 23[]5efs/ptp/pi>tp_pch_chiicla>;
 ite32u3249 6lass="sref"ef">iowrswitc6) ite69cladiv_" c8a s/ptp/pi>tp_pch_chiicla>;
 ite32c.snap_hi);6     5  re2852VENDOR_ID_INTE1"> 23/ptp/pi>tp_pch_chiicla>;
 ite32);
 275< /a>);
chip->6
>ef">pci_get_drvdaoSTAT6ON_AD6R_LENonid=" ?  }3/ptp/pi>tp_pch_chiicla>;
 ite32 =6="+code=u32" cl4ss="s49f6>val<6a> = l = e{0s/ptp/ptp_pch.4#L2844 id="L284" cl7r""""""""7gt;7
>ef">pci_get_drvdaoSTAT7ON_AD70hr"t=regs" class="sr"t=id="hi>pch_dev<7ef="drive7s/ptp/ptp_pch.5#L20150ss7"sref705}
 235 235efs/ptp/pi>tp_pch_chiicla>;
 ite32 = defau7t:234" class="line" name7"L23470ref="drivers//a>);
);
);
valcase id_tme="275< /a>);
TICKS_NS_SHIFTCONFIieee158<_e=cpch.i>> 23 /ptp/pi>tp_pch_chiicla>;
 ite325= defau7tass="sref"ef">iowrswitc7.5las70echip-/a>);
);
tp_pch_chiicla>;
 ite326= defau7textt=f">c.snap_hi);7re5#L70550 class="sr/a>);
tp_pch_chiicla>;
 ite327= defau7tt;chip);
TICKS_NS_SHIFTCG_PMptp/ptpa/a>);
TICKS_NS_SHIFTCONFIG_PMptp/ptp /ptp/pi>tp_pch_chiicla>;
 ite328= defau7t>ef">pci_get_drvdaoSTAT7href=708LENonid=" ? /a>);
 285);
 285val.snap_hi);
loval = a>;
__exiio"+i_restore_in__exii> 235 7SUPPid="L716" class="line" name="L716"> 71pch.cs/ptp/pi>tp_pch_chiicla>;
 ite32;regs" class=NL2un" cla4s=23="sr"TICKS_NS_SHIFTCONL2un" cla4s=23="sr"25054f">val = if) ite3o<#3="sr"TICKS_NS_SHIFTCONh23="sr"> 23evaL234" class="line" name="L234"> 7aall 7hr5f="+code=u32" class="7re5">71EINVAs/ptp/ptp_pch.4#L2844 id="L284" cl7"L239"> 275{
}
<7d="Lh239" class="line" n7me="L71550 c}
 7S7= defau7}
 275u3254 id=7t9<3a>}
<7>,  s="sref"ef0a239" cla7s="li71ref="+code=tp/ptp_pch.c#L285" id=" +ea7  5ef="dr7vers/ptp/ptp_pch.5#L220579">va72L232"_settime72" class="line" name="L2licla4s= the  p_pch withlthe ONL cors=de=val" cl3ss="s39f">val = ef">iowrite7  5  retu7n ns = ((val = if) ite3o<#3="sr"TICKS_NS_SHIFTCONh23="sr"> 23evaL234" class="line" name="L234"> 75ref="dri7ers/ptp/ptp_pch5c#L225217="sre72"L286    5  tp_pch_ch7TICKS_N7_SHIF72  5ref="drivers/ptp/ptp_pch5c#L2454s="7pcha>, a279" class="line" name="L279"> 272rn      5ref="driid="L23eniio"+i_restore_in=id="L23enii2505evaL234" class="line" name="L234"> 757= defau7216" class="line" name="7216">72l = <6"> 215<9a>    modu163exiio"+i_restore_inmodu163exii275<9a>     5ref="driid="L23exiio"+i_restore_in=id="L23exii2505evaL234" class="line" name="L234"> 75p_pch.c#7f="+code=5ch_de52id="L277" cla72/s="sref">chip-> 215<9a>    modu163param_eturn <"+i_restore_inmodu163param_eturn 275<9a>     5ref="drl
 23ref">chip->);
tp_pch_chiiclef="+paramechi/a>);
 23<_izcofT>);
tp_pch_chiiclef="+paramechi/a>);
 2), 0444evaL234" class="line" name="L234"> 735 215<9a>    MODULE_PARM_DESC34     5ref="drl
 23ref">chip->chip-> 215<9a>    MODULE_AUTHORRT_SYMBOL" 5lasMODULE_AUTHOR275<9a2" class="lieturn ( 215<9a>    MODULE_DESCRIPTIONRT_SYMBOL" 5lasMODULE_DESCRIPTION275<9a2" class="lieturn (, a274" id="L"L216" class="li7e" na73rn  = ef">iowra>;
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