linux/drivers/phy/phy-omap-control.c
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   1/*
   2 * omap-control-phy.c - The PHY part of control module.
   3 *
   4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; either version 2 of the License, or
   8 * (at your option) any later version.
   9 *
  10 * Author: Kishon Vijay Abraham I <kishon@ti.com>
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 */
  18
  19#include <linux/module.h>
  20#include <linux/platform_device.h>
  21#include <linux/slab.h>
  22#include <linux/of.h>
  23#include <linux/of_device.h>
  24#include <linux/err.h>
  25#include <linux/io.h>
  26#include <linux/clk.h>
  27#include <linux/phy/omap_control_phy.h>
  28
  29/**
  30 * omap_control_pcie_pcs - set the PCS delay count
  31 * @dev: the control module device
  32 * @delay: 8 bit delay value
  33 */
  34void omap_control_pcie_pcs(struct device *dev, u8 delay)
  35{
  36        u32 val;
  37        struct omap_control_phy *control_phy;
  38
  39        if (IS_ERR(dev) || !dev) {
  40                pr_err("%s: invalid device\n", __func__);
  41                return;
  42        }
  43
  44        control_phy = dev_get_drvdata(dev);
  45        if (!control_phy) {
  46                dev_err(dev, "%s: invalid control phy device\n", __func__);
  47                return;
  48        }
  49
  50        if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
  51                dev_err(dev, "%s: unsupported operation\n", __func__);
  52                return;
  53        }
  54
  55        val = readl(control_phy->pcie_pcs);
  56        val &= ~(OMAP_CTRL_PCIE_PCS_MASK <<
  57                OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
  58        val |= (delay << OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT);
  59        writel(val, control_phy->pcie_pcs);
  60}
  61EXPORT_SYMBOL_GPL(omap_control_pcie_pcs);
  62
  63/**
  64 * omap_control_phy_power - power on/off the phy using control module reg
  65 * @dev: the control module device
  66 * @on: 0 or 1, based on powering on or off the PHY
  67 */
  68void omap_control_phy_power(struct device *dev, int on)
  69{
  70        u32 val;
  71        unsigned long rate;
  72        struct omap_control_phy *control_phy;
  73
  74        if (IS_ERR(dev) || !dev) {
  75                pr_err("%s: invalid device\n", __func__);
  76                return;
  77        }
  78
  79        control_phy = dev_get_drvdata(dev);
  80        if (!control_phy) {
  81                dev_err(dev, "%s: invalid control phy device\n", __func__);
  82                return;
  83        }
  84
  85        if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
  86                return;
  87
  88        val = readl(control_phy->power);
  89
  90        switch (control_phy->type) {
  91        case OMAP_CTRL_TYPE_USB2:
  92                if (on)
  93                        val &= ~OMAP_CTRL_DEV_PHY_PD;
  94                else
  95                        val |= OMAP_CTRL_DEV_PHY_PD;
  96                break;
  97
  98        case OMAP_CTRL_TYPE_PCIE:
  99        case OMAP_CTRL_TYPE_PIPE3:
 100                rate = clk_get_rate(control_phy->sys_clk);
 101                rate = rate/1000000;
 102
 103                if (on) {
 104                        val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |
 105                                OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK);
 106                        val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<
 107                                OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 108                        val |= rate <<
 109                                OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT;
 110                } else {
 111                        val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;
 112                        val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<
 113                                OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT;
 114                }
 115                break;
 116
 117        case OMAP_CTRL_TYPE_DRA7USB2:
 118                if (on)
 119                        val &= ~OMAP_CTRL_USB2_PHY_PD;
 120                else
 121                        val |= OMAP_CTRL_USB2_PHY_PD;
 122                break;
 123
 124        case OMAP_CTRL_TYPE_AM437USB2:
 125                if (on) {
 126                        val &= ~(AM437X_CTRL_USB2_PHY_PD |
 127                                        AM437X_CTRL_USB2_OTG_PD);
 128                        val |= (AM437X_CTRL_USB2_OTGVDET_EN |
 129                                        AM437X_CTRL_USB2_OTGSESSEND_EN);
 130                } else {
 131                        val &= ~(AM437X_CTRL_USB2_OTGVDET_EN |
 132                                        AM437X_CTRL_USB2_OTGSESSEND_EN);
 133                        val |= (AM437X_CTRL_USB2_PHY_PD |
 134                                         AM437X_CTRL_USB2_OTG_PD);
 135                }
 136                break;
 137        default:
 138                dev_err(dev, "%s: type %d not recognized\n",
 139                        __func__, control_phy->type);
 140                break;
 141        }
 142
 143        writel(val, control_phy->power);
 144}
 145EXPORT_SYMBOL_GPL(omap_control_phy_power);
 146
 147/**
 148 * omap_control_usb_host_mode - set AVALID, VBUSVALID and ID pin in grounded
 149 * @ctrl_phy: struct omap_control_phy *
 150 *
 151 * Writes to the mailbox register to notify the usb core that a usb
 152 * device has been connected.
 153 */
 154static void omap_control_usb_host_mode(struct omap_control_phy *ctrl_phy)
 155{
 156        u32 val;
 157
 158        val = readl(ctrl_phy->otghs_control);
 159        val &= ~(OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND);
 160        val |= OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID;
 161        writel(val, ctrl_phy->otghs_control);
 162}
 163
 164/**
 165 * omap_control_usb_device_mode - set AVALID, VBUSVALID and ID pin in high
 166 * impedance
 167 * @ctrl_phy: struct omap_control_phy *
 168 *
 169 * Writes to the mailbox register to notify the usb core that it has been
 170 * connected to a usb host.
 171 */
 172static void omap_control_usb_device_mode(struct omap_control_phy *ctrl_phy)
 173{
 174        u32 val;
 175
 176        val = readl(ctrl_phy->otghs_control);
 177        val &= ~OMAP_CTRL_DEV_SESSEND;
 178        val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_AVALID |
 179                OMAP_CTRL_DEV_VBUSVALID;
 180        writel(val, ctrl_phy->otghs_control);
 181}
 182
 183/**
 184 * omap_control_usb_set_sessionend - Enable SESSIONEND and IDIG to high
 185 * impedance
 186 * @ctrl_phy: struct omap_control_phy *
 187 *
 188 * Writes to the mailbox register to notify the usb core it's now in
 189 * disconnected state.
 190 */
 191static void omap_control_usb_set_sessionend(struct omap_control_phy *ctrl_phy)
 192{
 193        u32 val;
 194
 195        val = readl(ctrl_phy->otghs_control);
 196        val &= ~(OMAP_CTRL_DEV_AVALID | OMAP_CTRL_DEV_VBUSVALID);
 197        val |= OMAP_CTRL_DEV_IDDIG | OMAP_CTRL_DEV_SESSEND;
 198        writel(val, ctrl_phy->otghs_control);
 199}
 200
 201/**
 202 * omap_control_usb_set_mode - Calls to functions to set USB in one of host mode
 203 * or device mode or to denote disconnected state
 204 * @dev: the control module device
 205 * @mode: The mode to which usb should be configured
 206 *
 207 * This is an API to write to the mailbox register to notify the usb core that
 208 * a usb device has been connected.
 209 */
 210void omap_control_usb_set_mode(struct device *dev,
 211        enum omap_control_usb_mode mode)
 212{
 213        struct omap_control_phy *ctrl_phy;
 214
 215        if (IS_ERR(dev) || !dev)
 216                return;
 217
 218        ctrl_phy = dev_get_drvdata(dev);
 219
 220        if (!ctrl_phy) {
 221                dev_err(dev, "Invalid control phy device\n");
 222                return;
 223        }
 224
 225        if (ctrl_phy->type != OMAP_CTRL_TYPE_OTGHS)
 226                return;
 227
 228        switch (mode) {
 229        case USB_MODE_HOST:
 230                omap_control_usb_host_mode(ctrl_phy);
 231                break;
 232        case USB_MODE_DEVICE:
 233                omap_control_usb_device_mode(ctrl_phy);
 234                break;
 235        case USB_MODE_DISCONNECT:
 236                omap_control_usb_set_sessionend(ctrl_phy);
 237                break;
 238        default:
 239                dev_vdbg(dev, "invalid omap control usb mode\n");
 240        }
 241}
 242EXPORT_SYMBOL_GPL(omap_control_usb_set_mode);
 243
 244#ifdef CONFIG_OF
 245
 246static const enum omap_control_phy_type otghs_data = OMAP_CTRL_TYPE_OTGHS;
 247static const enum omap_control_phy_type usb2_data = OMAP_CTRL_TYPE_USB2;
 248static const enum omap_control_phy_type pipe3_data = OMAP_CTRL_TYPE_PIPE3;
 249static const enum omap_control_phy_type pcie_data = OMAP_CTRL_TYPE_PCIE;
 250static const enum omap_control_phy_type dra7usb2_data = OMAP_CTRL_TYPE_DRA7USB2;
 251static const enum omap_control_phy_type am437usb2_data = OMAP_CTRL_TYPE_AM437USB2;
 252
 253static const struct of_device_id omap_control_phy_id_table[] = {
 254        {
 255                .compatible = "ti,control-phy-otghs",
 256                .data = &otghs_data,
 257        },
 258        {
 259                .compatible = "ti,control-phy-usb2",
 260                .data = &usb2_data,
 261        },
 262        {
 263                .compatible = "ti,control-phy-pipe3",
 264                .data = &pipe3_data,
 265        },
 266        {
 267                .compatible = "ti,control-phy-pcie",
 268                .data = &pcie_data,
 269        },
 270        {
 271                .compatible = "ti,control-phy-usb2-dra7",
 272                .data = &dra7usb2_data,
 273        },
 274        {
 275                .compatible = "ti,control-phy-usb2-am437",
 276                .data = &am437usb2_data,
 277        },
 278        {},
 279};
 280MODULE_DEVICE_TABLE(of, omap_control_phy_id_table);
 281#endif
 282
 283
 284static int omap_control_phy_probe(struct platform_device *pdev)
 285{
 286        struct resource *res;
 287        const struct of_device_id *of_id;
 288        struct omap_control_phy *control_phy;
 289
 290        of_id = of_match_device(of_match_ptr(omap_control_phy_id_table),
 291                                &pdev->dev);
 292        if (!of_id)
 293                return -EINVAL;
 294
 295        control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
 296                GFP_KERNEL);
 297        if (!control_phy)
 298                return -ENOMEM;
 299
 300        control_phy->dev = &pdev->dev;
 301        control_phy->type = *(enum omap_control_phy_type *)of_id->data;
 302
 303        if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
 304                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 305                        "otghs_control");
 306                control_phy->otghs_control = devm_ioremap_resource(
 307                        &pdev->dev, res);
 308                if (IS_ERR(control_phy->otghs_control))
 309                        return PTR_ERR(control_phy->otghs_control);
 310        } else {
 311                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 312                                "power");
 313                control_phy->power = devm_ioremap_resource(&pdev->dev, res);
 314                if (IS_ERR(control_phy->power)) {
 315                        dev_err(&pdev->dev, "Couldn't get power register\n");
 316                        return PTR_ERR(control_phy->power);
 317                }
 318        }
 319
 320        if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
 321            control_phy->type == OMAP_CTRL_TYPE_PCIE) {
 322                control_phy->sys_clk = devm_clk_get(control_phy->dev,
 323                        "sys_clkin");
 324                if (IS_ERR(control_phy->sys_clk)) {
 325                        pr_err("%s: unable to get sys_clkin\n", __func__);
 326                        return -EINVAL;
 327                }
 328        }
 329
 330        if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
 331                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 332                                                   "pcie_pcs");
 333                control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
 334                if (IS_ERR(control_phy->pcie_pcs))
 335                        return PTR_ERR(control_phy->pcie_pcs);
 336        }
 337
 338        dev_set_drvdata(control_phy->dev, control_phy);
 339
 340        return 0;
 341}
 342
 343static struct platform_driver omap_control_phy_driver = {
 344        .probe          = omap_control_phy_probe,
 345        .driver         = {
 346                .name   = "omap-control-phy",
 347                .of_match_table = of_match_ptr(omap_control_phy_id_table),
 348        },
 349};
 350
 351static int __init omap_control_phy_init(void)
 352{
 353        return platform_driver_register(&omap_control_phy_driver);
 354}
 355subsys_initcall(omap_control_phy_init);
 356
 357static void __exit omap_control_phy_exit(void)
 358{
 359        platform_driver_unregister(&omap_control_phy_driver);
 360}
 361module_exit(omap_control_phy_exit);
 362
 363MODULE_ALIAS("platform: omap_control_phy");
 364MODULE_AUTHOR("Texas Instruments Inc.");
 365MODULE_DESCRIPTION("OMAP Control Module PHY Driver");
 366MODULE_LICENSE("GPL v2");
 367
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