LXR linux/drivers/net/tulip/tulip.h

   1/*
   2        drivers/net/tulip/tulip.h
   3
   4        Copyright 2000,2001  The Linux Kernel Team
   5        Written/copyright 1994-2001 by Donald Becker.
   6
   7        This software may be used and distributed according to the terms
   8        of the GNU General Public License, incorporated herein by reference.
   9
  10        Please refer to Documentation/DocBook/tulip-user.{pdf,ps,html}
  11        for more information on this driver.
  12
  13        Please submit bugs to http://bugzilla.kernel.org/ .
  14*/
  15
  16#ifndef __NET_TULIP_H__
  17#define __NET_TULIP_H__
  18
  19#include <linux/kernel.h>
  20#include <linux/types.h>
  21#include <linux/spinlock.h>
  22#include <linux/netdevice.h>
  23#include <linux/timer.h>
  24#include <linux/delay.h>
  25#include <linux/pci.h>
  26#include <asm/io.h>
  27#include <asm/irq.h>
  28#include <asm/unaligned.h>
  29
  30
  31
  32/* undefine, or define to various debugging levels (>4 == obscene levels) */
  33#define TULIP_DEBUG 1
  34
  35#ifdef CONFIG_TULIP_MMIO
  36#define TULIP_BAR       1       /* CBMA */
  37#else
  38#define TULIP_BAR       0       /* CBIO */
  39#endif
  40
  41
  42
  43struct tulip_chip_table {
  44        char *chip_name;
  45        int io_size;
  46        int valid_intrs;        /* CSR7 interrupt enable settings */
  47        int flags;
  48        void (*media_timer) (unsigned long);
  49        work_func_t media_task;
  50};
  51
  52
  53enum tbl_flag {
  54        HAS_MII                 = 0x0001,
  55        HAS_MEDIA_TABLE         = 0x0002,
  56        CSR12_IN_SROM           = 0x0004,
  57        ALWAYS_CHECK_MII        = 0x0008,
  58        HAS_ACPI                = 0x0010,
  59        MC_HASH_ONLY            = 0x0020, /* Hash-only multicast filter. */
  60        HAS_PNICNWAY            = 0x0080,
  61        HAS_NWAY                = 0x0040, /* Uses internal NWay xcvr. */
  62        HAS_INTR_MITIGATION     = 0x0100,
  63        IS_ASIX                 = 0x0200,
  64        HAS_8023X               = 0x0400,
  65        COMET_MAC_ADDR          = 0x0800,
  66        HAS_PCI_MWI             = 0x1000,
  67        HAS_PHY_IRQ             = 0x2000,
  68        HAS_SWAPPED_SEEPROM     = 0x4000,
  69        NEEDS_FAKE_MEDIA_TABLE  = 0x8000,
  70};
  71
  72
  73/* chip types.  careful!  order is VERY IMPORTANT here, as these
  74 * are used throughout the driver as indices into arrays */
  75/* Note 21142 == 21143. */
  76enum chips {
  77        DC21040 = 0,
  78        DC21041 = 1,
  79        DC21140 = 2,
  80        DC21142 = 3, DC21143 = 3,
  81        LC82C168,
  82        MX98713,
  83        MX98715,
  84        MX98725,
  85        AX88140,
  86        PNIC2,
  87        COMET,
  88        COMPEX9881,
  89        I21145,
  90        DM910X,
  91        CONEXANT,
  92};
  93
  94
  95enum MediaIs {
  96        MediaIsFD = 1,
  97        MediaAlwaysFD = 2,
  98        MediaIsMII = 4,
  99        MediaIsFx = 8,
 100        MediaIs100 = 16
 101};
 102
 103
 104/* Offsets to the Command and Status Registers, "CSRs".  All accesses
 105   must be longword instructions and quadword aligned. */
 106enum tulip_offsets {
 107        CSR0 = 0,
 108        CSR1 = 0x08,
 109        CSR2 = 0x10,
 110        CSR3 = 0x18,
 111        CSR4 = 0x20,
 112        CSR5 = 0x28,
 113        CSR6 = 0x30,
 114        CSR7 = 0x38,
 115        CSR8 = 0x40,
 116        CSR9 = 0x48,
 117        CSR10 = 0x50,
 118        CSR11 = 0x58,
 119        CSR12 = 0x60,
 120        CSR13 = 0x68,
 121        CSR14 = 0x70,
 122        CSR15 = 0x78,
 123};
 124
 125/* register offset and bits for CFDD PCI config reg */
 126enum pci_cfg_driver_reg {
 127        CFDD = 0x40,
 128        CFDD_Sleep = (1 << 31),
 129        CFDD_Snooze = (1 << 30),
 130};
 131
 132#define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
 133
 134/* The bits in the CSR5 status registers, mostly interrupt sources. */
 135enum status_bits {
 136        TimerInt = 0x800,
 137        SystemError = 0x2000,
 138        TPLnkFail = 0x1000,
 139        TPLnkPass = 0x10,
 140        NormalIntr = 0x10000,
 141        AbnormalIntr = 0x8000,
 142        RxJabber = 0x200,
 143        RxDied = 0x100,
 144        RxNoBuf = 0x80,
 145        RxIntr = 0x40,
 146        TxFIFOUnderflow = 0x20,
 147        RxErrIntr = 0x10,
 148        TxJabber = 0x08,
 149        TxNoBuf = 0x04,
 150        TxDied = 0x02,
 151        TxIntr = 0x01,
 152};
 153
 154/* bit mask for CSR5 TX/RX process state */
 155#define CSR5_TS 0x00700000
 156#define CSR5_RS 0x000e0000
 157
 158enum tulip_mode_bits {
 159        TxThreshold             = (1 << 22),
 160        FullDuplex              = (1 << 9),
 161        TxOn                    = 0x2000,
 162        AcceptBroadcast         = 0x0100,
 163        AcceptAllMulticast      = 0x0080,
 164        AcceptAllPhys           = 0x0040,
 165        AcceptRunt              = 0x0008,
 166        RxOn                    = 0x0002,
 167        RxTx                    = (TxOn | RxOn),
 168};
 169
 170
 171enum tulip_busconfig_bits {
 172        MWI                     = (1 << 24),
 173        MRL                     = (1 << 23),
 174        MRM                     = (1 << 21),
 175        CALShift                = 14,
 176        BurstLenShift           = 8,
 177};
 178
 179
 180/* The Tulip Rx and Tx buffer descriptors. */
 181struct tulip_rx_desc {
 182        __le32 status;
 183        __le32 length;
 184        __le32 buffer1;
 185        __le32 buffer2;
 186};
 187
 188
 189struct tulip_tx_desc {
 190        __le32 status;
 191        __le32 length;
 192        __le32 buffer1;
 193        __le32 buffer2;         /* We use only buffer 1.  */
 194};
 195
 196
 197enum desc_status_bits {
 198        DescOwned    = 0x80000000,
 199        DescWholePkt = 0x60000000,
 200        DescEndPkt   = 0x40000000,
 201        DescStartPkt = 0x20000000,
 202        DescEndRing  = 0x02000000,
 203        DescUseLink  = 0x01000000,
 204
 205        /*
 206         * Error summary flag is logical or of 'CRC Error', 'Collision Seen',
 207         * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated
 208         * within tulip chip.
 209         */
 210        RxDescErrorSummary = 0x8000,
 211        RxDescCRCError = 0x0002,
 212        RxDescCollisionSeen = 0x0040,
 213
 214        /*
 215         * 'Frame Too Long' flag is set if packet length including CRC exceeds
 216         * 1518.  However, a full sized VLAN tagged frame is 1522 bytes
 217         * including CRC.
 218         *
 219         * The tulip chip does not block oversized frames, and if this flag is
 220         * set on a receive descriptor it does not indicate the frame has been
 221         * truncated.  The receive descriptor also includes the actual length.
 222         * Therefore we can safety ignore this flag and check the length
 223         * ourselves.
 224         */
 225        RxDescFrameTooLong = 0x0080,
 226        RxDescRunt = 0x0800,
 227        RxDescDescErr = 0x4000,
 228        RxWholePkt   = 0x00000300,
 229        /*
 230         * Top three bits of 14 bit frame length (status bits 27-29) should
 231         * never be set as that would make frame over 2047 bytes. The Receive
 232         * Watchdog flag (bit 4) may indicate the length is over 2048 and the
 233         * length field is invalid.
 234         */
 235        RxLengthOver2047 = 0x38000010
 236};
 237
 238
 239enum t21143_csr6_bits {
 240        csr6_sc = (1<<31),
 241        csr6_ra = (1<<30),
 242        csr6_ign_dest_msb = (1<<26),
 243        csr6_mbo = (1<<25),
 244        csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
 245        csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
 246        csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
 247        csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
 248        csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
 249        csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
 250        csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
 251        csr6_trh = (1<<15),  /* Transmit Threshold high bit */
 252        csr6_trl = (1<<14),  /* Transmit Threshold low bit */
 253
 254        /***************************************************************
 255         * This table shows transmit threshold values based on media   *
 256         * and these two registers (from PNIC1 & 2 docs) Note: this is *
 257         * all meaningless if sf is set.                               *
 258         ***************************************************************/
 259
 260        /***********************************
 261         * (trh,trl) * 100BaseTX * 10BaseT *
 262         ***********************************
 263         *   (0,0)   *     128   *    72   *
 264         *   (0,1)   *     256   *    96   *
 265         *   (1,0)   *     512   *   128   *
 266         *   (1,1)   *    1024   *   160   *
 267         ***********************************/
 268
 269        csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
 270        csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
 271        csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
 272        /* set both and you get (PHY) loopback */
 273        csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
 274        csr6_pm = (1<<7),    /* Pass All Multicast */
 275        csr6_pr = (1<<6),    /* Promiscuous mode */
 276        csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
 277        csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
 278        csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
 279        csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
 280        csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
 281
 282        csr6_mask_capture = (csr6_sc | csr6_ca),
 283        csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
 284        csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
 285        csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
 286        csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
 287        csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
 288        csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
 289        csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
 290};
 291
 292
 293/* Keep the ring sizes a power of two for efficiency.
 294   Making the Tx ring too large decreases the effectiveness of channel
 295   bonding and packet priority.
 296   There are no ill effects from too-large receive rings. */
 297
 298#define TX_RING_SIZE    32
 299#define RX_RING_SIZE    128
 300#define MEDIA_MASK     31
 301
 302/* The receiver on the DC21143 rev 65 can fail to close the last
 303 * receive descriptor in certain circumstances (see errata) when
 304 * using MWI. This can only occur if the receive buffer ends on
 305 * a cache line boundary, so the "+ 4" below ensures it doesn't.
 306 */
 307#define PKT_BUF_SZ      (1536 + 4)      /* Size of each temporary Rx buffer. */
 308
 309#define TULIP_MIN_CACHE_LINE    8       /* in units of 32-bit words */
 310
 311#if defined(__sparc__) || defined(__hppa__)
 312/* The UltraSparc PCI controllers will disconnect at every 64-byte
 313 * crossing anyways so it makes no sense to tell Tulip to burst
 314 * any more than that.
 315 */
 316#define TULIP_MAX_CACHE_LINE    16      /* in units of 32-bit words */
 317#else
 318#define TULIP_MAX_CACHE_LINE    32      /* in units of 32-bit words */
 319#endif
 320
 321
 322/* Ring-wrap flag in length field, use for last ring entry.
 323        0x01000000 means chain on buffer2 address,
 324        0x02000000 means use the ring start address in CSR2/3.
 325   Note: Some work-alike chips do not function correctly in chained mode.
 326   The ASIX chip works only in chained mode.
 327   Thus we indicates ring mode, but always write the 'next' field for
 328   chained mode as well.
 329*/
 330#define DESC_RING_WRAP 0x02000000
 331
 332
 333#define EEPROM_SIZE 512         /* 2 << EEPROM_ADDRLEN */
 334
 335
 336#define RUN_AT(x) (jiffies + (x))
 337
 338#define get_u16(ptr) get_unaligned_le16((ptr))
 339
 340struct medialeaf {
 341        u8 type;
 342        u8 media;
 343        unsigned char *leafdata;
 344};
 345
 346
 347struct mediatable {
 348        u16 defaultmedia;
 349        u8 leafcount;
 350        u8 csr12dir;            /* General purpose pin directions. */
 351        unsigned has_mii:1;
 352        unsigned has_nonmii:1;
 353        unsigned has_reset:6;
 354        u32 csr15dir;
 355        u32 csr15val;           /* 21143 NWay setting. */
 356        struct medialeaf mleaf[0];
 357};
 358
 359
 360struct mediainfo {
 361        struct mediainfo *next;
 362        int info_type;
 363        int index;
 364        unsigned char *info;
 365};
 366
 367struct ring_info {
 368        struct sk_buff  *skb;
 369        dma_addr_t      mapping;
 370};
 371
 372
 373struct tulip_private {
 374        const char *product_name;
 375        struct net_device *next_module;
 376        struct tulip_rx_desc *rx_ring;
 377        struct tulip_tx_desc *tx_ring;
 378        dma_addr_t rx_ring_dma;
 379        dma_addr_t tx_ring_dma;
 380        /* The saved address of a sent-in-place packet/buffer, for skfree(). */
 381        struct ring_info tx_buffers[TX_RING_SIZE];
 382        /* The addresses of receive-in-place skbuffs. */
 383        struct ring_info rx_buffers[RX_RING_SIZE];
 384        u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
 385        int chip_id;
 386        int revision;
 387        int flags;
 388        struct napi_struct napi;
 389        struct net_device_stats stats;
 390        struct timer_list timer;        /* Media selection timer. */
 391        struct timer_list oom_timer;    /* Out of memory timer. */
 392        u32 mc_filter[2];
 393        spinlock_t lock;
 394        spinlock_t mii_lock;
 395        unsigned int cur_rx, cur_tx;    /* The next free ring entry */
 396        unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */
 397
 398#ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
 399        int mit_on;
 400#endif
 401        unsigned int full_duplex:1;     /* Full-duplex operation requested. */
 402        unsigned int full_duplex_lock:1;
 403        unsigned int fake_addr:1;       /* Multiport board faked address. */
 404        unsigned int default_port:4;    /* Last dev->if_port value. */
 405        unsigned int media2:4;  /* Secondary monitored media port. */
 406        unsigned int medialock:1;       /* Don't sense media type. */
 407        unsigned int mediasense:1;      /* Media sensing in progress. */
 408        unsigned int nway:1, nwayset:1;         /* 21143 internal NWay. */
 409        unsigned int timeout_recovery:1;
 410        unsigned int csr0;      /* CSR0 setting. */
 411        unsigned int csr6;      /* Current CSR6 control settings. */
 412        unsigned char eeprom[EEPROM_SIZE];      /* Serial EEPROM contents. */
 413        void (*link_change) (struct net_device * dev, int csr5);
 414        u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
 415        u16 lpar;               /* 21143 Link partner ability. */
 416        u16 advertising[4];
 417        signed char phys[4], mii_cnt;   /* MII device addresses. */
 418        struct mediatable *mtable;
 419        int cur_index;          /* Current media index. */
 420        int saved_if_port;
 421        struct pci_dev *pdev;
 422        int ttimer;
 423        int susp_rx;
 424        unsigned long nir;
 425        void __iomem *base_addr;
 426        int csr12_shadow;
 427        int pad0;               /* Used for 8-byte alignment */
 428        struct work_struct media_work;
 429        struct net_device *dev;
 430};
 431
 432
 433struct eeprom_fixup {
 434        char *name;
 435        unsigned char addr0;
 436        unsigned char addr1;
 437        unsigned char addr2;
 438        u16 newtable[32];       /* Max length below. */
 439};
 440
 441
 442/* 21142.c */
 443extern u16 t21142_csr14[];
 444void t21142_media_task(struct work_struct *work);
 445void t21142_start_nway(struct net_device *dev);
 446void t21142_lnk_change(struct net_device *dev, int csr5);
 447
 448
 449/* PNIC2.c */
 450void pnic2_lnk_change(struct net_device *dev, int csr5);
 451void pnic2_timer(unsigned long data);
 452void pnic2_start_nway(struct net_device *dev);
 453void pnic2_lnk_change(struct net_device *dev, int csr5);
 454
 455/* eeprom.c */
 456void tulip_parse_eeprom(struct net_device *dev);
 457int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
 458
 459/* interrupt.c */
 460extern unsigned int tulip_max_interrupt_work;
 461extern int tulip_rx_copybreak;
 462irqreturn_t tulip_interrupt(int irq, void *dev_instance);
 463int tulip_refill_rx(struct net_device *dev);
 464#ifdef CONFIG_TULIP_NAPI
 465int tulip_poll(struct napi_struct *napi, int budget);
 466#endif
 467
 468
 469/* media.c */
 470int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
 471void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
 472void tulip_select_media(struct net_device *dev, int startup);
 473int tulip_check_duplex(struct net_device *dev);
 474void tulip_find_mii (struct net_device *dev, int board_idx);
 475
 476/* pnic.c */
 477void pnic_do_nway(struct net_device *dev);
 478void pnic_lnk_change(struct net_device *dev, int csr5);
 479void pnic_timer(unsigned long data);
 480
 481/* timer.c */
 482void tulip_media_task(struct work_struct *work);
 483void mxic_timer(unsigned long data);
 484void comet_timer(unsigned long data);
 485
 486/* tulip_core.c */
 487extern int tulip_debug;
 488extern const char * const medianame[];
 489extern const char tulip_media_cap[];
 490extern struct tulip_chip_table tulip_tbl[];
 491void oom_timer(unsigned long data);
 492extern u8 t21040_csr13[];
 493
 494static inline void tulip_start_rxtx(struct tulip_private *tp)
 495{
 496        void __iomem *ioaddr = tp->base_addr;
 497        iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
 498        barrier();
 499        (void) ioread32(ioaddr + CSR6); /* mmio sync */
 500}
 501
 502static inline void tulip_stop_rxtx(struct tulip_private *tp)
 503{
 504        void __iomem *ioaddr = tp->base_addr;
 505        u32 csr6 = ioread32(ioaddr + CSR6);
 506
 507        if (csr6 & RxTx) {
 508                unsigned i=1300/10;
 509                iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
 510                barrier();
 511                /* wait until in-flight frame completes.
 512                 * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
 513                 * Typically expect this loop to end in < 50 us on 100BT.
 514                 */
 515                while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
 516                        udelay(10);
 517
 518                if (!i)
 519                        printk(KERN_DEBUG "%s: tulip_stop_rxtx() failed"
 520                                        " (CSR5 0x%x CSR6 0x%x)\n",
 521                                        pci_name(tp->pdev),
 522                                        ioread32(ioaddr + CSR5),
 523                                        ioread32(ioaddr + CSR6));
 524        }
 525}
 526
 527static inline void tulip_restart_rxtx(struct tulip_private *tp)
 528{
 529        tulip_stop_rxtx(tp);
 530        udelay(5);
 531        tulip_start_rxtx(tp);
 532}
 533
 534static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
 535{
 536        /* Stop and restart the chip's Tx processes. */
 537        tulip_restart_rxtx(tp);
 538        /* Trigger an immediate transmit demand. */
 539        iowrite32(0, ioaddr + CSR1);
 540
 541        tp->stats.tx_errors++;
 542}
 543
 544#endif /* __NET_TULIP_H__ */
 545