linux/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c
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   1/*
   2 * Copyright (C) 1999 - 2010 Intel Corporation.
   3 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD.
   4 *
   5 * This code was derived from the Intel e1000e Linux driver.
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; version 2 of the License.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "pch_gbe.h"
  21#include "pch_gbe_api.h"
  22#include <linux/module.h>
  23#include <linux/net_tstamp.h>
  24#include <linux/ptp_classify.h>
  25#include <linux/gpio.h>
  26
  27#define DRV_VERSION     "1.01"
  28const char pch_driver_version[] = DRV_VERSION;
  29
  30#define PCI_DEVICE_ID_INTEL_IOH1_GBE    0x8802          /* Pci device ID */
  31#define PCH_GBE_MAR_ENTRIES             16
  32#define PCH_GBE_SHORT_PKT               64
  33#define DSC_INIT16                      0xC000
  34#define PCH_GBE_DMA_ALIGN               0
  35#define PCH_GBE_DMA_PADDING             2
  36#define PCH_GBE_WATCHDOG_PERIOD         (5 * HZ)        /* watchdog time */
  37#define PCH_GBE_COPYBREAK_DEFAULT       256
  38#define PCH_GBE_PCI_BAR                 1
  39#define PCH_GBE_RESERVE_MEMORY          0x200000        /* 2MB */
  40
  41/* Macros for ML7223 */
  42#define PCI_VENDOR_ID_ROHM                      0x10db
  43#define PCI_DEVICE_ID_ROHM_ML7223_GBE           0x8013
  44
  45/* Macros for ML7831 */
  46#define PCI_DEVICE_ID_ROHM_ML7831_GBE           0x8802
  47
  48#define PCH_GBE_TX_WEIGHT         64
  49#define PCH_GBE_RX_WEIGHT         64
  50#define PCH_GBE_RX_BUFFER_WRITE   16
  51
  52/* Initialize the wake-on-LAN settings */
  53#define PCH_GBE_WL_INIT_SETTING    (PCH_GBE_WLC_MP)
  54
  55#define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \
  56        PCH_GBE_CHIP_TYPE_INTERNAL | \
  57        PCH_GBE_RGMII_MODE_RGMII     \
  58        )
  59
  60/* Ethertype field values */
  61#define PCH_GBE_MAX_RX_BUFFER_SIZE      0x2880
  62#define PCH_GBE_MAX_JUMBO_FRAME_SIZE    10318
  63#define PCH_GBE_FRAME_SIZE_2048         2048
  64#define PCH_GBE_FRAME_SIZE_4096         4096
  65#define PCH_GBE_FRAME_SIZE_8192         8192
  66
  67#define PCH_GBE_GET_DESC(R, i, type)    (&(((struct type *)((R).desc))[i]))
  68#define PCH_GBE_RX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc)
  69#define PCH_GBE_TX_DESC(R, i)           PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc)
  70#define PCH_GBE_DESC_UNUSED(R) \
  71        ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  72        (R)->next_to_clean - (R)->next_to_use - 1)
  73
  74/* Pause packet value */
  75#define PCH_GBE_PAUSE_PKT1_VALUE    0x00C28001
  76#define PCH_GBE_PAUSE_PKT2_VALUE    0x00000100
  77#define PCH_GBE_PAUSE_PKT4_VALUE    0x01000888
  78#define PCH_GBE_PAUSE_PKT5_VALUE    0x0000FFFF
  79
  80
  81/* This defines the bits that are set in the Interrupt Mask
  82 * Set/Read Register.  Each bit is documented below:
  83 *   o RXT0   = Receiver Timer Interrupt (ring 0)
  84 *   o TXDW   = Transmit Descriptor Written Back
  85 *   o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
  86 *   o RXSEQ  = Receive Sequence Error
  87 *   o LSC    = Link Status Change
  88 */
  89#define PCH_GBE_INT_ENABLE_MASK ( \
  90        PCH_GBE_INT_RX_DMA_CMPLT |    \
  91        PCH_GBE_INT_RX_DSC_EMP   |    \
  92        PCH_GBE_INT_RX_FIFO_ERR  |    \
  93        PCH_GBE_INT_WOL_DET      |    \
  94        PCH_GBE_INT_TX_CMPLT          \
  95        )
  96
  97#define PCH_GBE_INT_DISABLE_ALL         0
  98
  99/* Macros for ieee1588 */
 100/* 0x40 Time Synchronization Channel Control Register Bits */
 101#define MASTER_MODE   (1<<0)
 102#define SLAVE_MODE    (0)
 103#define V2_MODE       (1<<31)
 104#define CAP_MODE0     (0)
 105#define CAP_MODE2     (1<<17)
 106
 107/* 0x44 Time Synchronization Channel Event Register Bits */
 108#define TX_SNAPSHOT_LOCKED (1<<0)
 109#define RX_SNAPSHOT_LOCKED (1<<1)
 110
 111#define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81"
 112#define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00"
 113
 114#define MINNOW_PHY_RESET_GPIO           13
 115
 116static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT;
 117
 118static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg);
 119static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg,
 120                               int data);
 121static void pch_gbe_set_multi(struct net_device *netdev);
 122
 123static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
 124{
 125        u8 *data = skb->data;
 126        unsigned int offset;
 127        u16 *hi, *id;
 128        u32 lo;
 129
 130        if (ptp_classify_raw(skb) == PTP_CLASS_NONE)
 131                return 0;
 132
 133        offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
 134
 135        if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
 136                return 0;
 137
 138        hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
 139        id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
 140
 141        memcpy(&lo, &hi[1], sizeof(lo));
 142
 143        return (uid_hi == *hi &&
 144                uid_lo == lo &&
 145                seqid  == *id);
 146}
 147
 148static void
 149pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 150{
 151        struct skb_shared_hwtstamps *shhwtstamps;
 152        struct pci_dev *pdev;
 153        u64 ns;
 154        u32 hi, lo, val;
 155        u16 uid, seq;
 156
 157        if (!adapter->hwts_rx_en)
 158                return;
 159
 160        /* Get ieee1588's dev information */
 161        pdev = adapter->ptp_pdev;
 162
 163        val = pch_ch_event_read(pdev);
 164
 165        if (!(val & RX_SNAPSHOT_LOCKED))
 166                return;
 167
 168        lo = pch_src_uuid_lo_read(pdev);
 169        hi = pch_src_uuid_hi_read(pdev);
 170
 171        uid = hi & 0xffff;
 172        seq = (hi >> 16) & 0xffff;
 173
 174        if (!pch_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
 175                goto out;
 176
 177        ns = pch_rx_snap_read(pdev);
 178
 179        shhwtstamps = skb_hwtstamps(skb);
 180        memset(shhwtstamps, 0, sizeof(*shhwtstamps));
 181        shhwtstamps->hwtstamp = ns_to_ktime(ns);
 182out:
 183        pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED);
 184}
 185
 186static void
 187pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb)
 188{
 189        struct skb_shared_hwtstamps shhwtstamps;
 190        struct pci_dev *pdev;
 191        struct skb_shared_info *shtx;
 192        u64 ns;
 193        u32 cnt, val;
 194
 195        shtx = skb_shinfo(skb);
 196        if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)))
 197                return;
 198
 199        shtx->tx_flags |= SKBTX_IN_PROGRESS;
 200
 201        /* Get ieee1588's dev information */
 202        pdev = adapter->ptp_pdev;
 203
 204        /*
 205         * This really stinks, but we have to poll for the Tx time stamp.
 206         */
 207        for (cnt = 0; cnt < 100; cnt++) {
 208                val = pch_ch_event_read(pdev);
 209                if (val & TX_SNAPSHOT_LOCKED)
 210                        break;
 211                udelay(1);
 212        }
 213        if (!(val & TX_SNAPSHOT_LOCKED)) {
 214                shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
 215                return;
 216        }
 217
 218        ns = pch_tx_snap_read(pdev);
 219
 220        memset(&shhwtstamps, 0, sizeof(shhwtstamps));
 221        shhwtstamps.hwtstamp = ns_to_ktime(ns);
 222        skb_tstamp_tx(skb, &shhwtstamps);
 223
 224        pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED);
 225}
 226
 227static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
 228{
 229        struct hwtstamp_config cfg;
 230        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 231        struct pci_dev *pdev;
 232        u8 station[20];
 233
 234        if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
 235                return -EFAULT;
 236
 237        if (cfg.flags) /* reserved for future extensions */
 238                return -EINVAL;
 239
 240        /* Get ieee1588's dev information */
 241        pdev = adapter->ptp_pdev;
 242
 243        if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
 244                return -ERANGE;
 245
 246        switch (cfg.rx_filter) {
 247        case HWTSTAMP_FILTER_NONE:
 248                adapter->hwts_rx_en = 0;
 249                break;
 250        case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 251                adapter->hwts_rx_en = 0;
 252                pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0);
 253                break;
 254        case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 255                adapter->hwts_rx_en = 1;
 256                pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0);
 257                break;
 258        case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 259                adapter->hwts_rx_en = 1;
 260                pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 261                strcpy(station, PTP_L4_MULTICAST_SA);
 262                pch_set_station_address(station, pdev);
 263                break;
 264        case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 265                adapter->hwts_rx_en = 1;
 266                pch_ch_control_write(pdev, V2_MODE | CAP_MODE2);
 267                strcpy(station, PTP_L2_MULTICAST_SA);
 268                pch_set_station_address(station, pdev);
 269                break;
 270        default:
 271                return -ERANGE;
 272        }
 273
 274        adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON;
 275
 276        /* Clear out any old time stamps. */
 277        pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED);
 278
 279        return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
 280}
 281
 282static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw)
 283{
 284        iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD);
 285}
 286
 287/**
 288 * pch_gbe_mac_read_mac_addr - Read MAC address
 289 * @hw:             Pointer to the HW structure
 290 * Returns:
 291 *      0:                      Successful.
 292 */
 293s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw)
 294{
 295        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 296        u32  adr1a, adr1b;
 297
 298        adr1a = ioread32(&hw->reg->mac_adr[0].high);
 299        adr1b = ioread32(&hw->reg->mac_adr[0].low);
 300
 301        hw->mac.addr[0] = (u8)(adr1a & 0xFF);
 302        hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF);
 303        hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF);
 304        hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF);
 305        hw->mac.addr[4] = (u8)(adr1b & 0xFF);
 306        hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF);
 307
 308        netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr);
 309        return 0;
 310}
 311
 312/**
 313 * pch_gbe_wait_clr_bit - Wait to clear a bit
 314 * @reg:        Pointer of register
 315 * @busy:       Busy bit
 316 */
 317static void pch_gbe_wait_clr_bit(void *reg, u32 bit)
 318{
 319        u32 tmp;
 320
 321        /* wait busy */
 322        tmp = 1000;
 323        while ((ioread32(reg) & bit) && --tmp)
 324                cpu_relax();
 325        if (!tmp)
 326                pr_err("Error: busy bit is not cleared\n");
 327}
 328
 329/**
 330 * pch_gbe_mac_mar_set - Set MAC address register
 331 * @hw:     Pointer to the HW structure
 332 * @addr:   Pointer to the MAC address
 333 * @index:  MAC address array register
 334 */
 335static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index)
 336{
 337        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 338        u32 mar_low, mar_high, adrmask;
 339
 340        netdev_dbg(adapter->netdev, "index : 0x%x\n", index);
 341
 342        /*
 343         * HW expects these in little endian so we reverse the byte order
 344         * from network order (big endian) to little endian
 345         */
 346        mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) |
 347                   ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 348        mar_low = ((u32) addr[4] | ((u32) addr[5] << 8));
 349        /* Stop the MAC Address of index. */
 350        adrmask = ioread32(&hw->reg->ADDR_MASK);
 351        iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK);
 352        /* wait busy */
 353        pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 354        /* Set the MAC address to the MAC address 1A/1B register */
 355        iowrite32(mar_high, &hw->reg->mac_adr[index].high);
 356        iowrite32(mar_low, &hw->reg->mac_adr[index].low);
 357        /* Start the MAC address of index */
 358        iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK);
 359        /* wait busy */
 360        pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 361}
 362
 363/**
 364 * pch_gbe_mac_reset_hw - Reset hardware
 365 * @hw: Pointer to the HW structure
 366 */
 367static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw)
 368{
 369        /* Read the MAC address. and store to the private data */
 370        pch_gbe_mac_read_mac_addr(hw);
 371        iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET);
 372#ifdef PCH_GBE_MAC_IFOP_RGMII
 373        iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE);
 374#endif
 375        pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST);
 376        /* Setup the receive addresses */
 377        pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 378        return;
 379}
 380
 381static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw)
 382{
 383        u32 rctl;
 384        /* Disables Receive MAC */
 385        rctl = ioread32(&hw->reg->MAC_RX_EN);
 386        iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 387}
 388
 389static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw)
 390{
 391        u32 rctl;
 392        /* Enables Receive MAC */
 393        rctl = ioread32(&hw->reg->MAC_RX_EN);
 394        iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN);
 395}
 396
 397/**
 398 * pch_gbe_mac_init_rx_addrs - Initialize receive address's
 399 * @hw: Pointer to the HW structure
 400 * @mar_count: Receive address registers
 401 */
 402static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count)
 403{
 404        u32 i;
 405
 406        /* Setup the receive address */
 407        pch_gbe_mac_mar_set(hw, hw->mac.addr, 0);
 408
 409        /* Zero out the other receive addresses */
 410        for (i = 1; i < mar_count; i++) {
 411                iowrite32(0, &hw->reg->mac_adr[i].high);
 412                iowrite32(0, &hw->reg->mac_adr[i].low);
 413        }
 414        iowrite32(0xFFFE, &hw->reg->ADDR_MASK);
 415        /* wait busy */
 416        pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 417}
 418
 419
 420/**
 421 * pch_gbe_mac_mc_addr_list_update - Update Multicast addresses
 422 * @hw:             Pointer to the HW structure
 423 * @mc_addr_list:   Array of multicast addresses to program
 424 * @mc_addr_count:  Number of multicast addresses to program
 425 * @mar_used_count: The first MAC Address register free to program
 426 * @mar_total_num:  Total number of supported MAC Address Registers
 427 */
 428static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw,
 429                                            u8 *mc_addr_list, u32 mc_addr_count,
 430                                            u32 mar_used_count, u32 mar_total_num)
 431{
 432        u32 i, adrmask;
 433
 434        /* Load the first set of multicast addresses into the exact
 435         * filters (RAR).  If there are not enough to fill the RAR
 436         * array, clear the filters.
 437         */
 438        for (i = mar_used_count; i < mar_total_num; i++) {
 439                if (mc_addr_count) {
 440                        pch_gbe_mac_mar_set(hw, mc_addr_list, i);
 441                        mc_addr_count--;
 442                        mc_addr_list += ETH_ALEN;
 443                } else {
 444                        /* Clear MAC address mask */
 445                        adrmask = ioread32(&hw->reg->ADDR_MASK);
 446                        iowrite32((adrmask | (0x0001 << i)),
 447                                        &hw->reg->ADDR_MASK);
 448                        /* wait busy */
 449                        pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY);
 450                        /* Clear MAC address */
 451                        iowrite32(0, &hw->reg->mac_adr[i].high);
 452                        iowrite32(0, &hw->reg->mac_adr[i].low);
 453                }
 454        }
 455}
 456
 457/**
 458 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings
 459 * @hw:             Pointer to the HW structure
 460 * Returns:
 461 *      0:                      Successful.
 462 *      Negative value:         Failed.
 463 */
 464s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw)
 465{
 466        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 467        struct pch_gbe_mac_info *mac = &hw->mac;
 468        u32 rx_fctrl;
 469
 470        netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc);
 471
 472        rx_fctrl = ioread32(&hw->reg->RX_FCTRL);
 473
 474        switch (mac->fc) {
 475        case PCH_GBE_FC_NONE:
 476                rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 477                mac->tx_fc_enable = false;
 478                break;
 479        case PCH_GBE_FC_RX_PAUSE:
 480                rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 481                mac->tx_fc_enable = false;
 482                break;
 483        case PCH_GBE_FC_TX_PAUSE:
 484                rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 485                mac->tx_fc_enable = true;
 486                break;
 487        case PCH_GBE_FC_FULL:
 488                rx_fctrl |= PCH_GBE_FL_CTRL_EN;
 489                mac->tx_fc_enable = true;
 490                break;
 491        default:
 492                netdev_err(adapter->netdev,
 493                           "Flow control param set incorrectly\n");
 494                return -EINVAL;
 495        }
 496        if (mac->link_duplex == DUPLEX_HALF)
 497                rx_fctrl &= ~PCH_GBE_FL_CTRL_EN;
 498        iowrite32(rx_fctrl, &hw->reg->RX_FCTRL);
 499        netdev_dbg(adapter->netdev,
 500                   "RX_FCTRL reg : 0x%08x  mac->tx_fc_enable : %d\n",
 501                   ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable);
 502        return 0;
 503}
 504
 505/**
 506 * pch_gbe_mac_set_wol_event - Set wake-on-lan event
 507 * @hw:     Pointer to the HW structure
 508 * @wu_evt: Wake up event
 509 */
 510static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt)
 511{
 512        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 513        u32 addr_mask;
 514
 515        netdev_dbg(adapter->netdev, "wu_evt : 0x%08x  ADDR_MASK reg : 0x%08x\n",
 516                   wu_evt, ioread32(&hw->reg->ADDR_MASK));
 517
 518        if (wu_evt) {
 519                /* Set Wake-On-Lan address mask */
 520                addr_mask = ioread32(&hw->reg->ADDR_MASK);
 521                iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK);
 522                /* wait busy */
 523                pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY);
 524                iowrite32(0, &hw->reg->WOL_ST);
 525                iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL);
 526                iowrite32(0x02, &hw->reg->TCPIP_ACC);
 527                iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 528        } else {
 529                iowrite32(0, &hw->reg->WOL_CTRL);
 530                iowrite32(0, &hw->reg->WOL_ST);
 531        }
 532        return;
 533}
 534
 535/**
 536 * pch_gbe_mac_ctrl_miim - Control MIIM interface
 537 * @hw:   Pointer to the HW structure
 538 * @addr: Address of PHY
 539 * @dir:  Operetion. (Write or Read)
 540 * @reg:  Access register of PHY
 541 * @data: Write data.
 542 *
 543 * Returns: Read date.
 544 */
 545u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
 546                        u16 data)
 547{
 548        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 549        u32 data_out = 0;
 550        unsigned int i;
 551        unsigned long flags;
 552
 553        spin_lock_irqsave(&hw->miim_lock, flags);
 554
 555        for (i = 100; i; --i) {
 556                if ((ioread32(&hw->reg->MIIM) & PCH_GBE_MIIM_OPER_READY))
 557                        break;
 558                udelay(20);
 559        }
 560        if (i == 0) {
 561                netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n");
 562                spin_unlock_irqrestore(&hw->miim_lock, flags);
 563                return 0;       /* No way to indicate timeout error */
 564        }
 565        iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
 566                  (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
 567                  dir | data), &hw->reg->MIIM);
 568        for (i = 0; i < 100; i++) {
 569                udelay(20);
 570                data_out = ioread32(&hw->reg->MIIM);
 571                if ((data_out & PCH_GBE_MIIM_OPER_READY))
 572                        break;
 573        }
 574        spin_unlock_irqrestore(&hw->miim_lock, flags);
 575
 576        netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n",
 577                   dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg,
 578                   dir == PCH_GBE_MIIM_OPER_READ ? data_out : data);
 579        return (u16) data_out;
 580}
 581
 582/**
 583 * pch_gbe_mac_set_pause_packet - Set pause packet
 584 * @hw:   Pointer to the HW structure
 585 */
 586static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw)
 587{
 588        struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw);
 589        unsigned long tmp2, tmp3;
 590
 591        /* Set Pause packet */
 592        tmp2 = hw->mac.addr[1];
 593        tmp2 = (tmp2 << 8) | hw->mac.addr[0];
 594        tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16);
 595
 596        tmp3 = hw->mac.addr[5];
 597        tmp3 = (tmp3 << 8) | hw->mac.addr[4];
 598        tmp3 = (tmp3 << 8) | hw->mac.addr[3];
 599        tmp3 = (tmp3 << 8) | hw->mac.addr[2];
 600
 601        iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1);
 602        iowrite32(tmp2, &hw->reg->PAUSE_PKT2);
 603        iowrite32(tmp3, &hw->reg->PAUSE_PKT3);
 604        iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4);
 605        iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5);
 606
 607        /* Transmit Pause Packet */
 608        iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ);
 609
 610        netdev_dbg(adapter->netdev,
 611                   "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
 612                   ioread32(&hw->reg->PAUSE_PKT1),
 613                   ioread32(&hw->reg->PAUSE_PKT2),
 614                   ioread32(&hw->reg->PAUSE_PKT3),
 615                   ioread32(&hw->reg->PAUSE_PKT4),
 616                   ioread32(&hw->reg->PAUSE_PKT5));
 617
 618        return;
 619}
 620
 621
 622/**
 623 * pch_gbe_alloc_queues - Allocate memory for all rings
 624 * @adapter:  Board private structure to initialize
 625 * Returns:
 626 *      0:      Successfully
 627 *      Negative value: Failed
 628 */
 629static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter)
 630{
 631        adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev,
 632                                        sizeof(*adapter->tx_ring), GFP_KERNEL);
 633        if (!adapter->tx_ring)
 634                return -ENOMEM;
 635
 636        adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev,
 637                                        sizeof(*adapter->rx_ring), GFP_KERNEL);
 638        if (!adapter->rx_ring)
 639                return -ENOMEM;
 640        return 0;
 641}
 642
 643/**
 644 * pch_gbe_init_stats - Initialize status
 645 * @adapter:  Board private structure to initialize
 646 */
 647static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter)
 648{
 649        memset(&adapter->stats, 0, sizeof(adapter->stats));
 650        return;
 651}
 652
 653/**
 654 * pch_gbe_init_phy - Initialize PHY
 655 * @adapter:  Board private structure to initialize
 656 * Returns:
 657 *      0:      Successfully
 658 *      Negative value: Failed
 659 */
 660static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter)
 661{
 662        struct net_device *netdev = adapter->netdev;
 663        u32 addr;
 664        u16 bmcr, stat;
 665
 666        /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */
 667        for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 668                adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr;
 669                bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR);
 670                stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 671                stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR);
 672                if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0))))
 673                        break;
 674        }
 675        adapter->hw.phy.addr = adapter->mii.phy_id;
 676        netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id);
 677        if (addr == PCH_GBE_PHY_REGS_LEN)
 678                return -EAGAIN;
 679        /* Selected the phy and isolate the rest */
 680        for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) {
 681                if (addr != adapter->mii.phy_id) {
 682                        pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 683                                           BMCR_ISOLATE);
 684                } else {
 685                        bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR);
 686                        pch_gbe_mdio_write(netdev, addr, MII_BMCR,
 687                                           bmcr & ~BMCR_ISOLATE);
 688                }
 689        }
 690
 691        /* MII setup */
 692        adapter->mii.phy_id_mask = 0x1F;
 693        adapter->mii.reg_num_mask = 0x1F;
 694        adapter->mii.dev = adapter->netdev;
 695        adapter->mii.mdio_read = pch_gbe_mdio_read;
 696        adapter->mii.mdio_write = pch_gbe_mdio_write;
 697        adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii);
 698        return 0;
 699}
 700
 701/**
 702 * pch_gbe_mdio_read - The read function for mii
 703 * @netdev: Network interface device structure
 704 * @addr:   Phy ID
 705 * @reg:    Access location
 706 * Returns:
 707 *      0:      Successfully
 708 *      Negative value: Failed
 709 */
 710static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg)
 711{
 712        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 713        struct pch_gbe_hw *hw = &adapter->hw;
 714
 715        return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg,
 716                                     (u16) 0);
 717}
 718
 719/**
 720 * pch_gbe_mdio_write - The write function for mii
 721 * @netdev: Network interface device structure
 722 * @addr:   Phy ID (not used)
 723 * @reg:    Access location
 724 * @data:   Write data
 725 */
 726static void pch_gbe_mdio_write(struct net_device *netdev,
 727                               int addr, int reg, int data)
 728{
 729        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
 730        struct pch_gbe_hw *hw = &adapter->hw;
 731
 732        pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data);
 733}
 734
 735/**
 736 * pch_gbe_reset_task - Reset processing at the time of transmission timeout
 737 * @work:  Pointer of board private structure
 738 */
 739static void pch_gbe_reset_task(struct work_struct *work)
 740{
 741        struct pch_gbe_adapter *adapter;
 742        adapter = container_of(work, struct pch_gbe_adapter, reset_task);
 743
 744        rtnl_lock();
 745        pch_gbe_reinit_locked(adapter);
 746        rtnl_unlock();
 747}
 748
 749/**
 750 * pch_gbe_reinit_locked- Re-initialization
 751 * @adapter:  Board private structure
 752 */
 753void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter)
 754{
 755        pch_gbe_down(adapter);
 756        pch_gbe_up(adapter);
 757}
 758
 759/**
 760 * pch_gbe_reset - Reset GbE
 761 * @adapter:  Board private structure
 762 */
 763void pch_gbe_reset(struct pch_gbe_adapter *adapter)
 764{
 765        struct net_device *netdev = adapter->netdev;
 766
 767        pch_gbe_mac_reset_hw(&adapter->hw);
 768        /* reprogram multicast address register after reset */
 769        pch_gbe_set_multi(netdev);
 770        /* Setup the receive address. */
 771        pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES);
 772        if (pch_gbe_hal_init_hw(&adapter->hw))
 773                netdev_err(netdev, "Hardware Error\n");
 774}
 775
 776/**
 777 * pch_gbe_free_irq - Free an interrupt
 778 * @adapter:  Board private structure
 779 */
 780static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter)
 781{
 782        struct net_device *netdev = adapter->netdev;
 783
 784        free_irq(adapter->pdev->irq, netdev);
 785        if (adapter->have_msi) {
 786                pci_disable_msi(adapter->pdev);
 787                netdev_dbg(netdev, "call pci_disable_msi\n");
 788        }
 789}
 790
 791/**
 792 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC
 793 * @adapter:  Board private structure
 794 */
 795static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter)
 796{
 797        struct pch_gbe_hw *hw = &adapter->hw;
 798
 799        atomic_inc(&adapter->irq_sem);
 800        iowrite32(0, &hw->reg->INT_EN);
 801        ioread32(&hw->reg->INT_ST);
 802        synchronize_irq(adapter->pdev->irq);
 803
 804        netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 805                   ioread32(&hw->reg->INT_EN));
 806}
 807
 808/**
 809 * pch_gbe_irq_enable - Enable default interrupt generation settings
 810 * @adapter:  Board private structure
 811 */
 812static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter)
 813{
 814        struct pch_gbe_hw *hw = &adapter->hw;
 815
 816        if (likely(atomic_dec_and_test(&adapter->irq_sem)))
 817                iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN);
 818        ioread32(&hw->reg->INT_ST);
 819        netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n",
 820                   ioread32(&hw->reg->INT_EN));
 821}
 822
 823
 824
 825/**
 826 * pch_gbe_setup_tctl - configure the Transmit control registers
 827 * @adapter:  Board private structure
 828 */
 829static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter)
 830{
 831        struct pch_gbe_hw *hw = &adapter->hw;
 832        u32 tx_mode, tcpip;
 833
 834        tx_mode = PCH_GBE_TM_LONG_PKT |
 835                PCH_GBE_TM_ST_AND_FD |
 836                PCH_GBE_TM_SHORT_PKT |
 837                PCH_GBE_TM_TH_TX_STRT_8 |
 838                PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8;
 839
 840        iowrite32(tx_mode, &hw->reg->TX_MODE);
 841
 842        tcpip = ioread32(&hw->reg->TCPIP_ACC);
 843        tcpip |= PCH_GBE_TX_TCPIPACC_EN;
 844        iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 845        return;
 846}
 847
 848/**
 849 * pch_gbe_configure_tx - Configure Transmit Unit after Reset
 850 * @adapter:  Board private structure
 851 */
 852static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter)
 853{
 854        struct pch_gbe_hw *hw = &adapter->hw;
 855        u32 tdba, tdlen, dctrl;
 856
 857        netdev_dbg(adapter->netdev, "dma addr = 0x%08llx  size = 0x%08x\n",
 858                   (unsigned long long)adapter->tx_ring->dma,
 859                   adapter->tx_ring->size);
 860
 861        /* Setup the HW Tx Head and Tail descriptor pointers */
 862        tdba = adapter->tx_ring->dma;
 863        tdlen = adapter->tx_ring->size - 0x10;
 864        iowrite32(tdba, &hw->reg->TX_DSC_BASE);
 865        iowrite32(tdlen, &hw->reg->TX_DSC_SIZE);
 866        iowrite32(tdba, &hw->reg->TX_DSC_SW_P);
 867
 868        /* Enables Transmission DMA */
 869        dctrl = ioread32(&hw->reg->DMA_CTRL);
 870        dctrl |= PCH_GBE_TX_DMA_EN;
 871        iowrite32(dctrl, &hw->reg->DMA_CTRL);
 872}
 873
 874/**
 875 * pch_gbe_setup_rctl - Configure the receive control registers
 876 * @adapter:  Board private structure
 877 */
 878static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter)
 879{
 880        struct pch_gbe_hw *hw = &adapter->hw;
 881        u32 rx_mode, tcpip;
 882
 883        rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN |
 884        PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8;
 885
 886        iowrite32(rx_mode, &hw->reg->RX_MODE);
 887
 888        tcpip = ioread32(&hw->reg->TCPIP_ACC);
 889
 890        tcpip |= PCH_GBE_RX_TCPIPACC_OFF;
 891        tcpip &= ~PCH_GBE_RX_TCPIPACC_EN;
 892        iowrite32(tcpip, &hw->reg->TCPIP_ACC);
 893        return;
 894}
 895
 896/**
 897 * pch_gbe_configure_rx - Configure Receive Unit after Reset
 898 * @adapter:  Board private structure
 899 */
 900static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter)
 901{
 902        struct pch_gbe_hw *hw = &adapter->hw;
 903        u32 rdba, rdlen, rxdma;
 904
 905        netdev_dbg(adapter->netdev, "dma adr = 0x%08llx  size = 0x%08x\n",
 906                   (unsigned long long)adapter->rx_ring->dma,
 907                   adapter->rx_ring->size);
 908
 909        pch_gbe_mac_force_mac_fc(hw);
 910
 911        pch_gbe_disable_mac_rx(hw);
 912
 913        /* Disables Receive DMA */
 914        rxdma = ioread32(&hw->reg->DMA_CTRL);
 915        rxdma &= ~PCH_GBE_RX_DMA_EN;
 916        iowrite32(rxdma, &hw->reg->DMA_CTRL);
 917
 918        netdev_dbg(adapter->netdev,
 919                   "MAC_RX_EN reg = 0x%08x  DMA_CTRL reg = 0x%08x\n",
 920                   ioread32(&hw->reg->MAC_RX_EN),
 921                   ioread32(&hw->reg->DMA_CTRL));
 922
 923        /* Setup the HW Rx Head and Tail Descriptor Pointers and
 924         * the Base and Length of the Rx Descriptor Ring */
 925        rdba = adapter->rx_ring->dma;
 926        rdlen = adapter->rx_ring->size - 0x10;
 927        iowrite32(rdba, &hw->reg->RX_DSC_BASE);
 928        iowrite32(rdlen, &hw->reg->RX_DSC_SIZE);
 929        iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P);
 930}
 931
 932/**
 933 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer
 934 * @adapter:     Board private structure
 935 * @buffer_info: Buffer information structure
 936 */
 937static void pch_gbe_unmap_and_free_tx_resource(
 938        struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info)
 939{
 940        if (buffer_info->mapped) {
 941                dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 942                                 buffer_info->length, DMA_TO_DEVICE);
 943                buffer_info->mapped = false;
 944        }
 945        if (buffer_info->skb) {
 946                dev_kfree_skb_any(buffer_info->skb);
 947                buffer_info->skb = NULL;
 948        }
 949}
 950
 951/**
 952 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer
 953 * @adapter:      Board private structure
 954 * @buffer_info:  Buffer information structure
 955 */
 956static void pch_gbe_unmap_and_free_rx_resource(
 957                                        struct pch_gbe_adapter *adapter,
 958                                        struct pch_gbe_buffer *buffer_info)
 959{
 960        if (buffer_info->mapped) {
 961                dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
 962                                 buffer_info->length, DMA_FROM_DEVICE);
 963                buffer_info->mapped = false;
 964        }
 965        if (buffer_info->skb) {
 966                dev_kfree_skb_any(buffer_info->skb);
 967                buffer_info->skb = NULL;
 968        }
 969}
 970
 971/**
 972 * pch_gbe_clean_tx_ring - Free Tx Buffers
 973 * @adapter:  Board private structure
 974 * @tx_ring:  Ring to be cleaned
 975 */
 976static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter,
 977                                   struct pch_gbe_tx_ring *tx_ring)
 978{
 979        struct pch_gbe_hw *hw = &adapter->hw;
 980        struct pch_gbe_buffer *buffer_info;
 981        unsigned long size;
 982        unsigned int i;
 983
 984        /* Free all the Tx ring sk_buffs */
 985        for (i = 0; i < tx_ring->count; i++) {
 986                buffer_info = &tx_ring->buffer_info[i];
 987                pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info);
 988        }
 989        netdev_dbg(adapter->netdev,
 990                   "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i);
 991
 992        size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count;
 993        memset(tx_ring->buffer_info, 0, size);
 994
 995        /* Zero out the descriptor ring */
 996        memset(tx_ring->desc, 0, tx_ring->size);
 997        tx_ring->next_to_use = 0;
 998        tx_ring->next_to_clean = 0;
 999        iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P);
1000        iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE);
1001}
1002
1003/**
1004 * pch_gbe_clean_rx_ring - Free Rx Buffers
1005 * @adapter:  Board private structure
1006 * @rx_ring:  Ring to free buffers from
1007 */
1008static void
1009pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter,
1010                      struct pch_gbe_rx_ring *rx_ring)
1011{
1012        struct pch_gbe_hw *hw = &adapter->hw;
1013        struct pch_gbe_buffer *buffer_info;
1014        unsigned long size;
1015        unsigned int i;
1016
1017        /* Free all the Rx ring sk_buffs */
1018        for (i = 0; i < rx_ring->count; i++) {
1019                buffer_info = &rx_ring->buffer_info[i];
1020                pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info);
1021        }
1022        netdev_dbg(adapter->netdev,
1023                   "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i);
1024        size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1025        memset(rx_ring->buffer_info, 0, size);
1026
1027        /* Zero out the descriptor ring */
1028        memset(rx_ring->desc, 0, rx_ring->size);
1029        rx_ring->next_to_clean = 0;
1030        rx_ring->next_to_use = 0;
1031        iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P);
1032        iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE);
1033}
1034
1035static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed,
1036                                    u16 duplex)
1037{
1038        struct pch_gbe_hw *hw = &adapter->hw;
1039        unsigned long rgmii = 0;
1040
1041        /* Set the RGMII control. */
1042#ifdef PCH_GBE_MAC_IFOP_RGMII
1043        switch (speed) {
1044        case SPEED_10:
1045                rgmii = (PCH_GBE_RGMII_RATE_2_5M |
1046                         PCH_GBE_MAC_RGMII_CTRL_SETTING);
1047                break;
1048        case SPEED_100:
1049                rgmii = (PCH_GBE_RGMII_RATE_25M |
1050                         PCH_GBE_MAC_RGMII_CTRL_SETTING);
1051                break;
1052        case SPEED_1000:
1053                rgmii = (PCH_GBE_RGMII_RATE_125M |
1054                         PCH_GBE_MAC_RGMII_CTRL_SETTING);
1055                break;
1056        }
1057        iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1058#else   /* GMII */
1059        rgmii = 0;
1060        iowrite32(rgmii, &hw->reg->RGMII_CTRL);
1061#endif
1062}
1063static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed,
1064                              u16 duplex)
1065{
1066        struct net_device *netdev = adapter->netdev;
1067        struct pch_gbe_hw *hw = &adapter->hw;
1068        unsigned long mode = 0;
1069
1070        /* Set the communication mode */
1071        switch (speed) {
1072        case SPEED_10:
1073                mode = PCH_GBE_MODE_MII_ETHER;
1074                netdev->tx_queue_len = 10;
1075                break;
1076        case SPEED_100:
1077                mode = PCH_GBE_MODE_MII_ETHER;
1078                netdev->tx_queue_len = 100;
1079                break;
1080        case SPEED_1000:
1081                mode = PCH_GBE_MODE_GMII_ETHER;
1082                break;
1083        }
1084        if (duplex == DUPLEX_FULL)
1085                mode |= PCH_GBE_MODE_FULL_DUPLEX;
1086        else
1087                mode |= PCH_GBE_MODE_HALF_DUPLEX;
1088        iowrite32(mode, &hw->reg->MODE);
1089}
1090
1091/**
1092 * pch_gbe_watchdog - Watchdog process
1093 * @data:  Board private structure
1094 */
1095static void pch_gbe_watchdog(unsigned long data)
1096{
1097        struct pch_gbe_adapter *adapter = (struct pch_gbe_adapter *)data;
1098        struct net_device *netdev = adapter->netdev;
1099        struct pch_gbe_hw *hw = &adapter->hw;
1100
1101        netdev_dbg(netdev, "right now = %ld\n", jiffies);
1102
1103        pch_gbe_update_stats(adapter);
1104        if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) {
1105                struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET };
1106                netdev->tx_queue_len = adapter->tx_queue_len;
1107                /* mii library handles link maintenance tasks */
1108                if (mii_ethtool_gset(&adapter->mii, &cmd)) {
1109                        netdev_err(netdev, "ethtool get setting Error\n");
1110                        mod_timer(&adapter->watchdog_timer,
1111                                  round_jiffies(jiffies +
1112                                                PCH_GBE_WATCHDOG_PERIOD));
1113                        return;
1114                }
1115                hw->mac.link_speed = ethtool_cmd_speed(&cmd);
1116                hw->mac.link_duplex = cmd.duplex;
1117                /* Set the RGMII control. */
1118                pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
1119                                                hw->mac.link_duplex);
1120                /* Set the communication mode */
1121                pch_gbe_set_mode(adapter, hw->mac.link_speed,
1122                                 hw->mac.link_duplex);
1123                netdev_dbg(netdev,
1124                           "Link is Up %d Mbps %s-Duplex\n",
1125                           hw->mac.link_speed,
1126                           cmd.duplex == DUPLEX_FULL ? "Full" : "Half");
1127                netif_carrier_on(netdev);
1128                netif_wake_queue(netdev);
1129        } else if ((!mii_link_ok(&adapter->mii)) &&
1130                   (netif_carrier_ok(netdev))) {
1131                netdev_dbg(netdev, "NIC Link is Down\n");
1132                hw->mac.link_speed = SPEED_10;
1133                hw->mac.link_duplex = DUPLEX_HALF;
1134                netif_carrier_off(netdev);
1135                netif_stop_queue(netdev);
1136        }
1137        mod_timer(&adapter->watchdog_timer,
1138                  round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD));
1139}
1140
1141/**
1142 * pch_gbe_tx_queue - Carry out queuing of the transmission data
1143 * @adapter:  Board private structure
1144 * @tx_ring:  Tx descriptor ring structure
1145 * @skb:      Sockt buffer structure
1146 */
1147static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter,
1148                              struct pch_gbe_tx_ring *tx_ring,
1149                              struct sk_buff *skb)
1150{
1151        struct pch_gbe_hw *hw = &adapter->hw;
1152        struct pch_gbe_tx_desc *tx_desc;
1153        struct pch_gbe_buffer *buffer_info;
1154        struct sk_buff *tmp_skb;
1155        unsigned int frame_ctrl;
1156        unsigned int ring_num;
1157
1158        /*-- Set frame control --*/
1159        frame_ctrl = 0;
1160        if (unlikely(skb->len < PCH_GBE_SHORT_PKT))
1161                frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
1162        if (skb->ip_summed == CHECKSUM_NONE)
1163                frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1164
1165        /* Performs checksum processing */
1166        /*
1167         * It is because the hardware accelerator does not support a checksum,
1168         * when the received data size is less than 64 bytes.
1169         */
1170        if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) {
1171                frame_ctrl |= PCH_GBE_TXD_CTRL_APAD |
1172                              PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF;
1173                if (skb->protocol == htons(ETH_P_IP)) {
1174                        struct iphdr *iph = ip_hdr(skb);
1175                        unsigned int offset;
1176                        offset = skb_transport_offset(skb);
1177                        if (iph->protocol == IPPROTO_TCP) {
1178                                skb->csum = 0;
1179                                tcp_hdr(skb)->check = 0;
1180                                skb->csum = skb_checksum(skb, offset,
1181                                                         skb->len - offset, 0);
1182                                tcp_hdr(skb)->check =
1183                                        csum_tcpudp_magic(iph->saddr,
1184                                                          iph->daddr,
1185                                                          skb->len - offset,
1186                                                          IPPROTO_TCP,
1187                                                          skb->csum);
1188                        } else if (iph->protocol == IPPROTO_UDP) {
1189                                skb->csum = 0;
1190                                udp_hdr(skb)->check = 0;
1191                                skb->csum =
1192                                        skb_checksum(skb, offset,
1193                                                     skb->len - offset, 0);
1194                                udp_hdr(skb)->check =
1195                                        csum_tcpudp_magic(iph->saddr,
1196                                                          iph->daddr,
1197                                                          skb->len - offset,
1198                                                          IPPROTO_UDP,
1199                                                          skb->csum);
1200                        }
1201                }
1202        }
1203
1204        ring_num = tx_ring->next_to_use;
1205        if (unlikely((ring_num + 1) == tx_ring->count))
1206                tx_ring->next_to_use = 0;
1207        else
1208                tx_ring->next_to_use = ring_num + 1;
1209
1210
1211        buffer_info = &tx_ring->buffer_info[ring_num];
1212        tmp_skb = buffer_info->skb;
1213
1214        /* [Header:14][payload] ---> [Header:14][paddong:2][payload]    */
1215        memcpy(tmp_skb->data, skb->data, ETH_HLEN);
1216        tmp_skb->data[ETH_HLEN] = 0x00;
1217        tmp_skb->data[ETH_HLEN + 1] = 0x00;
1218        tmp_skb->len = skb->len;
1219        memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN],
1220               (skb->len - ETH_HLEN));
1221        /*-- Set Buffer information --*/
1222        buffer_info->length = tmp_skb->len;
1223        buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data,
1224                                          buffer_info->length,
1225                                          DMA_TO_DEVICE);
1226        if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1227                netdev_err(adapter->netdev, "TX DMA map failed\n");
1228                buffer_info->dma = 0;
1229                buffer_info->time_stamp = 0;
1230                tx_ring->next_to_use = ring_num;
1231                return;
1232        }
1233        buffer_info->mapped = true;
1234        buffer_info->time_stamp = jiffies;
1235
1236        /*-- Set Tx descriptor --*/
1237        tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num);
1238        tx_desc->buffer_addr = (buffer_info->dma);
1239        tx_desc->length = (tmp_skb->len);
1240        tx_desc->tx_words_eob = ((tmp_skb->len + 3));
1241        tx_desc->tx_frame_ctrl = (frame_ctrl);
1242        tx_desc->gbec_status = (DSC_INIT16);
1243
1244        if (unlikely(++ring_num == tx_ring->count))
1245                ring_num = 0;
1246
1247        /* Update software pointer of TX descriptor */
1248        iowrite32(tx_ring->dma +
1249                  (int)sizeof(struct pch_gbe_tx_desc) * ring_num,
1250                  &hw->reg->TX_DSC_SW_P);
1251
1252        pch_tx_timestamp(adapter, skb);
1253
1254        dev_kfree_skb_any(skb);
1255}
1256
1257/**
1258 * pch_gbe_update_stats - Update the board statistics counters
1259 * @adapter:  Board private structure
1260 */
1261void pch_gbe_update_stats(struct pch_gbe_adapter *adapter)
1262{
1263        struct net_device *netdev = adapter->netdev;
1264        struct pci_dev *pdev = adapter->pdev;
1265        struct pch_gbe_hw_stats *stats = &adapter->stats;
1266        unsigned long flags;
1267
1268        /*
1269         * Prevent stats update while adapter is being reset, or if the pci
1270         * connection is down.
1271         */
1272        if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
1273                return;
1274
1275        spin_lock_irqsave(&adapter->stats_lock, flags);
1276
1277        /* Update device status "adapter->stats" */
1278        stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors;
1279        stats->tx_errors = stats->tx_length_errors +
1280            stats->tx_aborted_errors +
1281            stats->tx_carrier_errors + stats->tx_timeout_count;
1282
1283        /* Update network device status "adapter->net_stats" */
1284        netdev->stats.rx_packets = stats->rx_packets;
1285        netdev->stats.rx_bytes = stats->rx_bytes;
1286        netdev->stats.rx_dropped = stats->rx_dropped;
1287        netdev->stats.tx_packets = stats->tx_packets;
1288        netdev->stats.tx_bytes = stats->tx_bytes;
1289        netdev->stats.tx_dropped = stats->tx_dropped;
1290        /* Fill out the OS statistics structure */
1291        netdev->stats.multicast = stats->multicast;
1292        netdev->stats.collisions = stats->collisions;
1293        /* Rx Errors */
1294        netdev->stats.rx_errors = stats->rx_errors;
1295        netdev->stats.rx_crc_errors = stats->rx_crc_errors;
1296        netdev->stats.rx_frame_errors = stats->rx_frame_errors;
1297        /* Tx Errors */
1298        netdev->stats.tx_errors = stats->tx_errors;
1299        netdev->stats.tx_aborted_errors = stats->tx_aborted_errors;
1300        netdev->stats.tx_carrier_errors = stats->tx_carrier_errors;
1301
1302        spin_unlock_irqrestore(&adapter->stats_lock, flags);
1303}
1304
1305static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw)
1306{
1307        u32 rxdma;
1308
1309        /* Disable Receive DMA */
1310        rxdma = ioread32(&hw->reg->DMA_CTRL);
1311        rxdma &= ~PCH_GBE_RX_DMA_EN;
1312        iowrite32(rxdma, &hw->reg->DMA_CTRL);
1313}
1314
1315static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw)
1316{
1317        u32 rxdma;
1318
1319        /* Enables Receive DMA */
1320        rxdma = ioread32(&hw->reg->DMA_CTRL);
1321        rxdma |= PCH_GBE_RX_DMA_EN;
1322        iowrite32(rxdma, &hw->reg->DMA_CTRL);
1323}
1324
1325/**
1326 * pch_gbe_intr - Interrupt Handler
1327 * @irq:   Interrupt number
1328 * @data:  Pointer to a network interface device structure
1329 * Returns:
1330 *      - IRQ_HANDLED:  Our interrupt
1331 *      - IRQ_NONE:     Not our interrupt
1332 */
1333static irqreturn_t pch_gbe_intr(int irq, void *data)
1334{
1335        struct net_device *netdev = data;
1336        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
1337        struct pch_gbe_hw *hw = &adapter->hw;
1338        u32 int_st;
1339        u32 int_en;
1340
1341        /* Check request status */
1342        int_st = ioread32(&hw->reg->INT_ST);
1343        int_st = int_st & ioread32(&hw->reg->INT_EN);
1344        /* When request status is no interruption factor */
1345        if (unlikely(!int_st))
1346                return IRQ_NONE;        /* Not our interrupt. End processing. */
1347        netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st);
1348        if (int_st & PCH_GBE_INT_RX_FRAME_ERR)
1349                adapter->stats.intr_rx_frame_err_count++;
1350        if (int_st & PCH_GBE_INT_RX_FIFO_ERR)
1351                if (!adapter->rx_stop_flag) {
1352                        adapter->stats.intr_rx_fifo_err_count++;
1353                        netdev_dbg(netdev, "Rx fifo over run\n");
1354                        adapter->rx_stop_flag = true;
1355                        int_en = ioread32(&hw->reg->INT_EN);
1356                        iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR),
1357                                  &hw->reg->INT_EN);
1358                        pch_gbe_disable_dma_rx(&adapter->hw);
1359                        int_st |= ioread32(&hw->reg->INT_ST);
1360                        int_st = int_st & ioread32(&hw->reg->INT_EN);
1361                }
1362        if (int_st & PCH_GBE_INT_RX_DMA_ERR)
1363                adapter->stats.intr_rx_dma_err_count++;
1364        if (int_st & PCH_GBE_INT_TX_FIFO_ERR)
1365                adapter->stats.intr_tx_fifo_err_count++;
1366        if (int_st & PCH_GBE_INT_TX_DMA_ERR)
1367                adapter->stats.intr_tx_dma_err_count++;
1368        if (int_st & PCH_GBE_INT_TCPIP_ERR)
1369                adapter->stats.intr_tcpip_err_count++;
1370        /* When Rx descriptor is empty  */
1371        if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) {
1372                adapter->stats.intr_rx_dsc_empty_count++;
1373                netdev_dbg(netdev, "Rx descriptor is empty\n");
1374                int_en = ioread32(&hw->reg->INT_EN);
1375                iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN);
1376                if (hw->mac.tx_fc_enable) {
1377                        /* Set Pause packet */
1378                        pch_gbe_mac_set_pause_packet(hw);
1379                }
1380        }
1381
1382        /* When request status is Receive interruption */
1383        if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) ||
1384            (adapter->rx_stop_flag)) {
1385                if (likely(napi_schedule_prep(&adapter->napi))) {
1386                        /* Enable only Rx Descriptor empty */
1387                        atomic_inc(&adapter->irq_sem);
1388                        int_en = ioread32(&hw->reg->INT_EN);
1389                        int_en &=
1390                            ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT);
1391                        iowrite32(int_en, &hw->reg->INT_EN);
1392                        /* Start polling for NAPI */
1393                        __napi_schedule(&adapter->napi);
1394                }
1395        }
1396        netdev_dbg(netdev, "return = 0x%08x  INT_EN reg = 0x%08x\n",
1397                   IRQ_HANDLED, ioread32(&hw->reg->INT_EN));
1398        return IRQ_HANDLED;
1399}
1400
1401/**
1402 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended
1403 * @adapter:       Board private structure
1404 * @rx_ring:       Rx descriptor ring
1405 * @cleaned_count: Cleaned count
1406 */
1407static void
1408pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter,
1409                         struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1410{
1411        struct net_device *netdev = adapter->netdev;
1412        struct pci_dev *pdev = adapter->pdev;
1413        struct pch_gbe_hw *hw = &adapter->hw;
1414        struct pch_gbe_rx_desc *rx_desc;
1415        struct pch_gbe_buffer *buffer_info;
1416        struct sk_buff *skb;
1417        unsigned int i;
1418        unsigned int bufsz;
1419
1420        bufsz = adapter->rx_buffer_len + NET_IP_ALIGN;
1421        i = rx_ring->next_to_use;
1422
1423        while ((cleaned_count--)) {
1424                buffer_info = &rx_ring->buffer_info[i];
1425                skb = netdev_alloc_skb(netdev, bufsz);
1426                if (unlikely(!skb)) {
1427                        /* Better luck next round */
1428                        adapter->stats.rx_alloc_buff_failed++;
1429                        break;
1430                }
1431                /* align */
1432                skb_reserve(skb, NET_IP_ALIGN);
1433                buffer_info->skb = skb;
1434
1435                buffer_info->dma = dma_map_single(&pdev->dev,
1436                                                  buffer_info->rx_buffer,
1437                                                  buffer_info->length,
1438                                                  DMA_FROM_DEVICE);
1439                if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) {
1440                        dev_kfree_skb(skb);
1441                        buffer_info->skb = NULL;
1442                        buffer_info->dma = 0;
1443                        adapter->stats.rx_alloc_buff_failed++;
1444                        break; /* while !buffer_info->skb */
1445                }
1446                buffer_info->mapped = true;
1447                rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1448                rx_desc->buffer_addr = (buffer_info->dma);
1449                rx_desc->gbec_status = DSC_INIT16;
1450
1451                netdev_dbg(netdev,
1452                           "i = %d  buffer_info->dma = 0x08%llx  buffer_info->length = 0x%x\n",
1453                           i, (unsigned long long)buffer_info->dma,
1454                           buffer_info->length);
1455
1456                if (unlikely(++i == rx_ring->count))
1457                        i = 0;
1458        }
1459        if (likely(rx_ring->next_to_use != i)) {
1460                rx_ring->next_to_use = i;
1461                if (unlikely(i-- == 0))
1462                        i = (rx_ring->count - 1);
1463                iowrite32(rx_ring->dma +
1464                          (int)sizeof(struct pch_gbe_rx_desc) * i,
1465                          &hw->reg->RX_DSC_SW_P);
1466        }
1467        return;
1468}
1469
1470static int
1471pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter,
1472                         struct pch_gbe_rx_ring *rx_ring, int cleaned_count)
1473{
1474        struct pci_dev *pdev = adapter->pdev;
1475        struct pch_gbe_buffer *buffer_info;
1476        unsigned int i;
1477        unsigned int bufsz;
1478        unsigned int size;
1479
1480        bufsz = adapter->rx_buffer_len;
1481
1482        size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY;
1483        rx_ring->rx_buff_pool =
1484                dma_zalloc_coherent(&pdev->dev, size,
1485                                    &rx_ring->rx_buff_pool_logic, GFP_KERNEL);
1486        if (!rx_ring->rx_buff_pool)
1487                return -ENOMEM;
1488
1489        rx_ring->rx_buff_pool_size = size;
1490        for (i = 0; i < rx_ring->count; i++) {
1491                buffer_info = &rx_ring->buffer_info[i];
1492                buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i;
1493                buffer_info->length = bufsz;
1494        }
1495        return 0;
1496}
1497
1498/**
1499 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers
1500 * @adapter:   Board private structure
1501 * @tx_ring:   Tx descriptor ring
1502 */
1503static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter,
1504                                        struct pch_gbe_tx_ring *tx_ring)
1505{
1506        struct pch_gbe_buffer *buffer_info;
1507        struct sk_buff *skb;
1508        unsigned int i;
1509        unsigned int bufsz;
1510        struct pch_gbe_tx_desc *tx_desc;
1511
1512        bufsz =
1513            adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN;
1514
1515        for (i = 0; i < tx_ring->count; i++) {
1516                buffer_info = &tx_ring->buffer_info[i];
1517                skb = netdev_alloc_skb(adapter->netdev, bufsz);
1518                skb_reserve(skb, PCH_GBE_DMA_ALIGN);
1519                buffer_info->skb = skb;
1520                tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1521                tx_desc->gbec_status = (DSC_INIT16);
1522        }
1523        return;
1524}
1525
1526/**
1527 * pch_gbe_clean_tx - Reclaim resources after transmit completes
1528 * @adapter:   Board private structure
1529 * @tx_ring:   Tx descriptor ring
1530 * Returns:
1531 *      true:  Cleaned the descriptor
1532 *      false: Not cleaned the descriptor
1533 */
1534static bool
1535pch_gbe_clean_tx(struct pch_gbe_adapter *adapter,
1536                 struct pch_gbe_tx_ring *tx_ring)
1537{
1538        struct pch_gbe_tx_desc *tx_desc;
1539        struct pch_gbe_buffer *buffer_info;
1540        struct sk_buff *skb;
1541        unsigned int i;
1542        unsigned int cleaned_count = 0;
1543        bool cleaned = false;
1544        int unused, thresh;
1545
1546        netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1547                   tx_ring->next_to_clean);
1548
1549        i = tx_ring->next_to_clean;
1550        tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1551        netdev_dbg(adapter->netdev, "gbec_status:0x%04x  dma_status:0x%04x\n",
1552                   tx_desc->gbec_status, tx_desc->dma_status);
1553
1554        unused = PCH_GBE_DESC_UNUSED(tx_ring);
1555        thresh = tx_ring->count - PCH_GBE_TX_WEIGHT;
1556        if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh))
1557        {  /* current marked clean, tx queue filling up, do extra clean */
1558                int j, k;
1559                if (unused < 8) {  /* tx queue nearly full */
1560                        netdev_dbg(adapter->netdev,
1561                                   "clean_tx: transmit queue warning (%x,%x) unused=%d\n",
1562                                   tx_ring->next_to_clean, tx_ring->next_to_use,
1563                                   unused);
1564                }
1565
1566                /* current marked clean, scan for more that need cleaning. */
1567                k = i;
1568                for (j = 0; j < PCH_GBE_TX_WEIGHT; j++)
1569                {
1570                        tx_desc = PCH_GBE_TX_DESC(*tx_ring, k);
1571                        if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/
1572                        if (++k >= tx_ring->count) k = 0;  /*increment, wrap*/
1573                }
1574                if (j < PCH_GBE_TX_WEIGHT) {
1575                        netdev_dbg(adapter->netdev,
1576                                   "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n",
1577                                   unused, j, i, k, tx_ring->next_to_use,
1578                                   tx_desc->gbec_status);
1579                        i = k;  /*found one to clean, usu gbec_status==2000.*/
1580                }
1581        }
1582
1583        while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) {
1584                netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n",
1585                           tx_desc->gbec_status);
1586                buffer_info = &tx_ring->buffer_info[i];
1587                skb = buffer_info->skb;
1588                cleaned = true;
1589
1590                if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) {
1591                        adapter->stats.tx_aborted_errors++;
1592                        netdev_err(adapter->netdev, "Transfer Abort Error\n");
1593                } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER)
1594                          ) {
1595                        adapter->stats.tx_carrier_errors++;
1596                        netdev_err(adapter->netdev,
1597                                   "Transfer Carrier Sense Error\n");
1598                } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL)
1599                          ) {
1600                        adapter->stats.tx_aborted_errors++;
1601                        netdev_err(adapter->netdev,
1602                                   "Transfer Collision Abort Error\n");
1603                } else if ((tx_desc->gbec_status &
1604                            (PCH_GBE_TXD_GMAC_STAT_SNGCOL |
1605                             PCH_GBE_TXD_GMAC_STAT_MLTCOL))) {
1606                        adapter->stats.collisions++;
1607                        adapter->stats.tx_packets++;
1608                        adapter->stats.tx_bytes += skb->len;
1609                        netdev_dbg(adapter->netdev, "Transfer Collision\n");
1610                } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT)
1611                          ) {
1612                        adapter->stats.tx_packets++;
1613                        adapter->stats.tx_bytes += skb->len;
1614                }
1615                if (buffer_info->mapped) {
1616                        netdev_dbg(adapter->netdev,
1617                                   "unmap buffer_info->dma : %d\n", i);
1618                        dma_unmap_single(&adapter->pdev->dev, buffer_info->dma,
1619                                         buffer_info->length, DMA_TO_DEVICE);
1620                        buffer_info->mapped = false;
1621                }
1622                if (buffer_info->skb) {
1623                        netdev_dbg(adapter->netdev,
1624                                   "trim buffer_info->skb : %d\n", i);
1625                        skb_trim(buffer_info->skb, 0);
1626                }
1627                tx_desc->gbec_status = DSC_INIT16;
1628                if (unlikely(++i == tx_ring->count))
1629                        i = 0;
1630                tx_desc = PCH_GBE_TX_DESC(*tx_ring, i);
1631
1632                /* weight of a sort for tx, to avoid endless transmit cleanup */
1633                if (cleaned_count++ == PCH_GBE_TX_WEIGHT) {
1634                        cleaned = false;
1635                        break;
1636                }
1637        }
1638        netdev_dbg(adapter->netdev,
1639                   "called pch_gbe_unmap_and_free_tx_resource() %d count\n",
1640                   cleaned_count);
1641        if (cleaned_count > 0)  { /*skip this if nothing cleaned*/
1642                /* Recover from running out of Tx resources in xmit_frame */
1643                spin_lock(&tx_ring->tx_lock);
1644                if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev))))
1645                {
1646                        netif_wake_queue(adapter->netdev);
1647                        adapter->stats.tx_restart_count++;
1648                        netdev_dbg(adapter->netdev, "Tx wake queue\n");
1649                }
1650
1651                tx_ring->next_to_clean = i;
1652
1653                netdev_dbg(adapter->netdev, "next_to_clean : %d\n",
1654                           tx_ring->next_to_clean);
1655                spin_unlock(&tx_ring->tx_lock);
1656        }
1657        return cleaned;
1658}
1659
1660/**
1661 * pch_gbe_clean_rx - Send received data up the network stack; legacy
1662 * @adapter:     Board private structure
1663 * @rx_ring:     Rx descriptor ring
1664 * @work_done:   Completed count
1665 * @work_to_do:  Request count
1666 * Returns:
1667 *      true:  Cleaned the descriptor
1668 *      false: Not cleaned the descriptor
1669 */
1670static bool
1671pch_gbe_clean_rx(struct pch_gbe_adapter *adapter,
1672                 struct pch_gbe_rx_ring *rx_ring,
1673                 int *work_done, int work_to_do)
1674{
1675        struct net_device *netdev = adapter->netdev;
1676        struct pci_dev *pdev = adapter->pdev;
1677        struct pch_gbe_buffer *buffer_info;
1678        struct pch_gbe_rx_desc *rx_desc;
1679        u32 length;
1680        unsigned int i;
1681        unsigned int cleaned_count = 0;
1682        bool cleaned = false;
1683        struct sk_buff *skb;
1684        u8 dma_status;
1685        u16 gbec_status;
1686        u32 tcp_ip_status;
1687
1688        i = rx_ring->next_to_clean;
1689
1690        while (*work_done < work_to_do) {
1691                /* Check Rx descriptor status */
1692                rx_desc = PCH_GBE_RX_DESC(*rx_ring, i);
1693                if (rx_desc->gbec_status == DSC_INIT16)
1694                        break;
1695                cleaned = true;
1696                cleaned_count++;
1697
1698                dma_status = rx_desc->dma_status;
1699                gbec_status = rx_desc->gbec_status;
1700                tcp_ip_status = rx_desc->tcp_ip_status;
1701                rx_desc->gbec_status = DSC_INIT16;
1702                buffer_info = &rx_ring->buffer_info[i];
1703                skb = buffer_info->skb;
1704                buffer_info->skb = NULL;
1705
1706                /* unmap dma */
1707                dma_unmap_single(&pdev->dev, buffer_info->dma,
1708                                   buffer_info->length, DMA_FROM_DEVICE);
1709                buffer_info->mapped = false;
1710
1711                netdev_dbg(netdev,
1712                           "RxDecNo = 0x%04x  Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x]  BufInf = 0x%p\n",
1713                           i, dma_status, gbec_status, tcp_ip_status,
1714                           buffer_info);
1715                /* Error check */
1716                if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) {
1717                        adapter->stats.rx_frame_errors++;
1718                        netdev_err(netdev, "Receive Not Octal Error\n");
1719                } else if (unlikely(gbec_status &
1720                                PCH_GBE_RXD_GMAC_STAT_NBLERR)) {
1721                        adapter->stats.rx_frame_errors++;
1722                        netdev_err(netdev, "Receive Nibble Error\n");
1723                } else if (unlikely(gbec_status &
1724                                PCH_GBE_RXD_GMAC_STAT_CRCERR)) {
1725                        adapter->stats.rx_crc_errors++;
1726                        netdev_err(netdev, "Receive CRC Error\n");
1727                } else {
1728                        /* get receive length */
1729                        /* length convert[-3], length includes FCS length */
1730                        length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN;
1731                        if (rx_desc->rx_words_eob & 0x02)
1732                                length = length - 4;
1733                        /*
1734                         * buffer_info->rx_buffer: [Header:14][payload]
1735                         * skb->data: [Reserve:2][Header:14][payload]
1736                         */
1737                        memcpy(skb->data, buffer_info->rx_buffer, length);
1738
1739                        /* update status of driver */
1740                        adapter->stats.rx_bytes += length;
1741                        adapter->stats.rx_packets++;
1742                        if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT))
1743                                adapter->stats.multicast++;
1744                        /* Write meta date of skb */
1745                        skb_put(skb, length);
1746
1747                        pch_rx_timestamp(adapter, skb);
1748
1749                        skb->protocol = eth_type_trans(skb, netdev);
1750                        if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK)
1751                                skb->ip_summed = CHECKSUM_UNNECESSARY;
1752                        else
1753                                skb->ip_summed = CHECKSUM_NONE;
1754
1755                        napi_gro_receive(&adapter->napi, skb);
1756                        (*work_done)++;
1757                        netdev_dbg(netdev,
1758                                   "Receive skb->ip_summed: %d length: %d\n",
1759                                   skb->ip_summed, length);
1760                }
1761                /* return some buffers to hardware, one at a time is too slow */
1762                if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) {
1763                        pch_gbe_alloc_rx_buffers(adapter, rx_ring,
1764                                                 cleaned_count);
1765                        cleaned_count = 0;
1766                }
1767                if (++i == rx_ring->count)
1768                        i = 0;
1769        }
1770        rx_ring->next_to_clean = i;
1771        if (cleaned_count)
1772                pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1773        return cleaned;
1774}
1775
1776/**
1777 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors)
1778 * @adapter:  Board private structure
1779 * @tx_ring:  Tx descriptor ring (for a specific queue) to setup
1780 * Returns:
1781 *      0:              Successfully
1782 *      Negative value: Failed
1783 */
1784int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
1785                                struct pch_gbe_tx_ring *tx_ring)
1786{
1787        struct pci_dev *pdev = adapter->pdev;
1788        struct pch_gbe_tx_desc *tx_desc;
1789        int size;
1790        int desNo;
1791
1792        size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count;
1793        tx_ring->buffer_info = vzalloc(size);
1794        if (!tx_ring->buffer_info)
1795                return -ENOMEM;
1796
1797        tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc);
1798
1799        tx_ring->desc = dma_zalloc_coherent(&pdev->dev, tx_ring->size,
1800                                            &tx_ring->dma, GFP_KERNEL);
1801        if (!tx_ring->desc) {
1802                vfree(tx_ring->buffer_info);
1803                return -ENOMEM;
1804        }
1805
1806        tx_ring->next_to_use = 0;
1807        tx_ring->next_to_clean = 0;
1808        spin_lock_init(&tx_ring->tx_lock);
1809
1810        for (desNo = 0; desNo < tx_ring->count; desNo++) {
1811                tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo);
1812                tx_desc->gbec_status = DSC_INIT16;
1813        }
1814        netdev_dbg(adapter->netdev,
1815                   "tx_ring->desc = 0x%p  tx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1816                   tx_ring->desc, (unsigned long long)tx_ring->dma,
1817                   tx_ring->next_to_clean, tx_ring->next_to_use);
1818        return 0;
1819}
1820
1821/**
1822 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors)
1823 * @adapter:  Board private structure
1824 * @rx_ring:  Rx descriptor ring (for a specific queue) to setup
1825 * Returns:
1826 *      0:              Successfully
1827 *      Negative value: Failed
1828 */
1829int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
1830                                struct pch_gbe_rx_ring *rx_ring)
1831{
1832        struct pci_dev *pdev = adapter->pdev;
1833        struct pch_gbe_rx_desc *rx_desc;
1834        int size;
1835        int desNo;
1836
1837        size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count;
1838        rx_ring->buffer_info = vzalloc(size);
1839        if (!rx_ring->buffer_info)
1840                return -ENOMEM;
1841
1842        rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc);
1843        rx_ring->desc = dma_zalloc_coherent(&pdev->dev, rx_ring->size,
1844                                            &rx_ring->dma, GFP_KERNEL);
1845        if (!rx_ring->desc) {
1846                vfree(rx_ring->buffer_info);
1847                return -ENOMEM;
1848        }
1849        rx_ring->next_to_clean = 0;
1850        rx_ring->next_to_use = 0;
1851        for (desNo = 0; desNo < rx_ring->count; desNo++) {
1852                rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo);
1853                rx_desc->gbec_status = DSC_INIT16;
1854        }
1855        netdev_dbg(adapter->netdev,
1856                   "rx_ring->desc = 0x%p  rx_ring->dma = 0x%08llx next_to_clean = 0x%08x  next_to_use = 0x%08x\n",
1857                   rx_ring->desc, (unsigned long long)rx_ring->dma,
1858                   rx_ring->next_to_clean, rx_ring->next_to_use);
1859        return 0;
1860}
1861
1862/**
1863 * pch_gbe_free_tx_resources - Free Tx Resources
1864 * @adapter:  Board private structure
1865 * @tx_ring:  Tx descriptor ring for a specific queue
1866 */
1867void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
1868                                struct pch_gbe_tx_ring *tx_ring)
1869{
1870        struct pci_dev *pdev = adapter->pdev;
1871
1872        pch_gbe_clean_tx_ring(adapter, tx_ring);
1873        vfree(tx_ring->buffer_info);
1874        tx_ring->buffer_info = NULL;
1875        pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
1876        tx_ring->desc = NULL;
1877}
1878
1879/**
1880 * pch_gbe_free_rx_resources - Free Rx Resources
1881 * @adapter:  Board private structure
1882 * @rx_ring:  Ring to clean the resources from
1883 */
1884void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
1885                                struct pch_gbe_rx_ring *rx_ring)
1886{
1887        struct pci_dev *pdev = adapter->pdev;
1888
1889        pch_gbe_clean_rx_ring(adapter, rx_ring);
1890        vfree(rx_ring->buffer_info);
1891        rx_ring->buffer_info = NULL;
1892        pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
1893        rx_ring->desc = NULL;
1894}
1895
1896/**
1897 * pch_gbe_request_irq - Allocate an interrupt line
1898 * @adapter:  Board private structure
1899 * Returns:
1900 *      0:              Successfully
1901 *      Negative value: Failed
1902 */
1903static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter)
1904{
1905        struct net_device *netdev = adapter->netdev;
1906        int err;
1907        int flags;
1908
1909        flags = IRQF_SHARED;
1910        adapter->have_msi = false;
1911        err = pci_enable_msi(adapter->pdev);
1912        netdev_dbg(netdev, "call pci_enable_msi\n");
1913        if (err) {
1914                netdev_dbg(netdev, "call pci_enable_msi - Error: %d\n", err);
1915        } else {
1916                flags = 0;
1917                adapter->have_msi = true;
1918        }
1919        err = request_irq(adapter->pdev->irq, &pch_gbe_intr,
1920                          flags, netdev->name, netdev);
1921        if (err)
1922                netdev_err(netdev, "Unable to allocate interrupt Error: %d\n",
1923                           err);
1924        netdev_dbg(netdev,
1925                   "adapter->have_msi : %d  flags : 0x%04x  return : 0x%04x\n",
1926                   adapter->have_msi, flags, err);
1927        return err;
1928}
1929
1930
1931/**
1932 * pch_gbe_up - Up GbE network device
1933 * @adapter:  Board private structure
1934 * Returns:
1935 *      0:              Successfully
1936 *      Negative value: Failed
1937 */
1938int pch_gbe_up(struct pch_gbe_adapter *adapter)
1939{
1940        struct net_device *netdev = adapter->netdev;
1941        struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
1942        struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
1943        int err = -EINVAL;
1944
1945        /* Ensure we have a valid MAC */
1946        if (!is_valid_ether_addr(adapter->hw.mac.addr)) {
1947                netdev_err(netdev, "Error: Invalid MAC address\n");
1948                goto out;
1949        }
1950
1951        /* hardware has been reset, we need to reload some things */
1952        pch_gbe_set_multi(netdev);
1953
1954        pch_gbe_setup_tctl(adapter);
1955        pch_gbe_configure_tx(adapter);
1956        pch_gbe_setup_rctl(adapter);
1957        pch_gbe_configure_rx(adapter);
1958
1959        err = pch_gbe_request_irq(adapter);
1960        if (err) {
1961                netdev_err(netdev,
1962                           "Error: can't bring device up - irq request failed\n");
1963                goto out;
1964        }
1965        err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count);
1966        if (err) {
1967                netdev_err(netdev,
1968                           "Error: can't bring device up - alloc rx buffers pool failed\n");
1969                goto freeirq;
1970        }
1971        pch_gbe_alloc_tx_buffers(adapter, tx_ring);
1972        pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count);
1973        adapter->tx_queue_len = netdev->tx_queue_len;
1974        pch_gbe_enable_dma_rx(&adapter->hw);
1975        pch_gbe_enable_mac_rx(&adapter->hw);
1976
1977        mod_timer(&adapter->watchdog_timer, jiffies);
1978
1979        napi_enable(&adapter->napi);
1980        pch_gbe_irq_enable(adapter);
1981        netif_start_queue(adapter->netdev);
1982
1983        return 0;
1984
1985freeirq:
1986        pch_gbe_free_irq(adapter);
1987out:
1988        return err;
1989}
1990
1991/**
1992 * pch_gbe_down - Down GbE network device
1993 * @adapter:  Board private structure
1994 */
1995void pch_gbe_down(struct pch_gbe_adapter *adapter)
1996{
1997        struct net_device *netdev = adapter->netdev;
1998        struct pci_dev *pdev = adapter->pdev;
1999        struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring;
2000
2001        /* signal that we're down so the interrupt handler does not
2002         * reschedule our watchdog timer */
2003        napi_disable(&adapter->napi);
2004        atomic_set(&adapter->irq_sem, 0);
2005
2006        pch_gbe_irq_disable(adapter);
2007        pch_gbe_free_irq(adapter);
2008
2009        del_timer_sync(&adapter->watchdog_timer);
2010
2011        netdev->tx_queue_len = adapter->tx_queue_len;
2012        netif_carrier_off(netdev);
2013        netif_stop_queue(netdev);
2014
2015        if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal))
2016                pch_gbe_reset(adapter);
2017        pch_gbe_clean_tx_ring(adapter, adapter->tx_ring);
2018        pch_gbe_clean_rx_ring(adapter, adapter->rx_ring);
2019
2020        pci_free_consistent(adapter->pdev, rx_ring->rx_buff_pool_size,
2021                            rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic);
2022        rx_ring->rx_buff_pool_logic = 0;
2023        rx_ring->rx_buff_pool_size = 0;
2024        rx_ring->rx_buff_pool = NULL;
2025}
2026
2027/**
2028 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter)
2029 * @adapter:  Board private structure to initialize
2030 * Returns:
2031 *      0:              Successfully
2032 *      Negative value: Failed
2033 */
2034static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter)
2035{
2036        struct pch_gbe_hw *hw = &adapter->hw;
2037        struct net_device *netdev = adapter->netdev;
2038
2039        adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2040        hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2041        hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
2042
2043        /* Initialize the hardware-specific values */
2044        if (pch_gbe_hal_setup_init_funcs(hw)) {
2045                netdev_err(netdev, "Hardware Initialization Failure\n");
2046                return -EIO;
2047        }
2048        if (pch_gbe_alloc_queues(adapter)) {
2049                netdev_err(netdev, "Unable to allocate memory for queues\n");
2050                return -ENOMEM;
2051        }
2052        spin_lock_init(&adapter->hw.miim_lock);
2053        spin_lock_init(&adapter->stats_lock);
2054        spin_lock_init(&adapter->ethtool_lock);
2055        atomic_set(&adapter->irq_sem, 0);
2056        pch_gbe_irq_disable(adapter);
2057
2058        pch_gbe_init_stats(adapter);
2059
2060        netdev_dbg(netdev,
2061                   "rx_buffer_len : %d  mac.min_frame_size : %d  mac.max_frame_size : %d\n",
2062                   (u32) adapter->rx_buffer_len,
2063                   hw->mac.min_frame_size, hw->mac.max_frame_size);
2064        return 0;
2065}
2066
2067/**
2068 * pch_gbe_open - Called when a network interface is made active
2069 * @netdev:     Network interface device structure
2070 * Returns:
2071 *      0:              Successfully
2072 *      Negative value: Failed
2073 */
2074static int pch_gbe_open(struct net_device *netdev)
2075{
2076        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2077        struct pch_gbe_hw *hw = &adapter->hw;
2078        int err;
2079
2080        /* allocate transmit descriptors */
2081        err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring);
2082        if (err)
2083                goto err_setup_tx;
2084        /* allocate receive descriptors */
2085        err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring);
2086        if (err)
2087                goto err_setup_rx;
2088        pch_gbe_hal_power_up_phy(hw);
2089        err = pch_gbe_up(adapter);
2090        if (err)
2091                goto err_up;
2092        netdev_dbg(netdev, "Success End\n");
2093        return 0;
2094
2095err_up:
2096        if (!adapter->wake_up_evt)
2097                pch_gbe_hal_power_down_phy(hw);
2098        pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2099err_setup_rx:
2100        pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2101err_setup_tx:
2102        pch_gbe_reset(adapter);
2103        netdev_err(netdev, "Error End\n");
2104        return err;
2105}
2106
2107/**
2108 * pch_gbe_stop - Disables a network interface
2109 * @netdev:  Network interface device structure
2110 * Returns:
2111 *      0: Successfully
2112 */
2113static int pch_gbe_stop(struct net_device *netdev)
2114{
2115        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2116        struct pch_gbe_hw *hw = &adapter->hw;
2117
2118        pch_gbe_down(adapter);
2119        if (!adapter->wake_up_evt)
2120                pch_gbe_hal_power_down_phy(hw);
2121        pch_gbe_free_tx_resources(adapter, adapter->tx_ring);
2122        pch_gbe_free_rx_resources(adapter, adapter->rx_ring);
2123        return 0;
2124}
2125
2126/**
2127 * pch_gbe_xmit_frame - Packet transmitting start
2128 * @skb:     Socket buffer structure
2129 * @netdev:  Network interface device structure
2130 * Returns:
2131 *      - NETDEV_TX_OK:   Normal end
2132 *      - NETDEV_TX_BUSY: Error end
2133 */
2134static int pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2135{
2136        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2137        struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring;
2138        unsigned long flags;
2139
2140        if (!spin_trylock_irqsave(&tx_ring->tx_lock, flags)) {
2141                /* Collision - tell upper layer to requeue */
2142                return NETDEV_TX_LOCKED;
2143        }
2144        if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) {
2145                netif_stop_queue(netdev);
2146                spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2147                netdev_dbg(netdev,
2148                           "Return : BUSY  next_to use : 0x%08x  next_to clean : 0x%08x\n",
2149                           tx_ring->next_to_use, tx_ring->next_to_clean);
2150                return NETDEV_TX_BUSY;
2151        }
2152
2153        /* CRC,ITAG no support */
2154        pch_gbe_tx_queue(adapter, tx_ring, skb);
2155        spin_unlock_irqrestore(&tx_ring->tx_lock, flags);
2156        return NETDEV_TX_OK;
2157}
2158
2159/**
2160 * pch_gbe_get_stats - Get System Network Statistics
2161 * @netdev:  Network interface device structure
2162 * Returns:  The current stats
2163 */
2164static struct net_device_stats *pch_gbe_get_stats(struct net_device *netdev)
2165{
2166        /* only return the current stats */
2167        return &netdev->stats;
2168}
2169
2170/**
2171 * pch_gbe_set_multi - Multicast and Promiscuous mode set
2172 * @netdev:   Network interface device structure
2173 */
2174static void pch_gbe_set_multi(struct net_device *netdev)
2175{
2176        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2177        struct pch_gbe_hw *hw = &adapter->hw;
2178        struct netdev_hw_addr *ha;
2179        u8 *mta_list;
2180        u32 rctl;
2181        int i;
2182        int mc_count;
2183
2184        netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags);
2185
2186        /* Check for Promiscuous and All Multicast modes */
2187        rctl = ioread32(&hw->reg->RX_MODE);
2188        mc_count = netdev_mc_count(netdev);
2189        if ((netdev->flags & IFF_PROMISC)) {
2190                rctl &= ~PCH_GBE_ADD_FIL_EN;
2191                rctl &= ~PCH_GBE_MLT_FIL_EN;
2192        } else if ((netdev->flags & IFF_ALLMULTI)) {
2193                /* all the multicasting receive permissions */
2194                rctl |= PCH_GBE_ADD_FIL_EN;
2195                rctl &= ~PCH_GBE_MLT_FIL_EN;
2196        } else {
2197                if (mc_count >= PCH_GBE_MAR_ENTRIES) {
2198                        /* all the multicasting receive permissions */
2199                        rctl |= PCH_GBE_ADD_FIL_EN;
2200                        rctl &= ~PCH_GBE_MLT_FIL_EN;
2201                } else {
2202                        rctl |= (PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN);
2203                }
2204        }
2205        iowrite32(rctl, &hw->reg->RX_MODE);
2206
2207        if (mc_count >= PCH_GBE_MAR_ENTRIES)
2208                return;
2209        mta_list = kmalloc(mc_count * ETH_ALEN, GFP_ATOMIC);
2210        if (!mta_list)
2211                return;
2212
2213        /* The shared function expects a packed array of only addresses. */
2214        i = 0;
2215        netdev_for_each_mc_addr(ha, netdev) {
2216                if (i == mc_count)
2217                        break;
2218                memcpy(mta_list + (i++ * ETH_ALEN), &ha->addr, ETH_ALEN);
2219        }
2220        pch_gbe_mac_mc_addr_list_update(hw, mta_list, i, 1,
2221                                        PCH_GBE_MAR_ENTRIES);
2222        kfree(mta_list);
2223
2224        netdev_dbg(netdev,
2225                 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x  netdev->mc_count : 0x%08x\n",
2226                 ioread32(&hw->reg->RX_MODE), mc_count);
2227}
2228
2229/**
2230 * pch_gbe_set_mac - Change the Ethernet Address of the NIC
2231 * @netdev: Network interface device structure
2232 * @addr:   Pointer to an address structure
2233 * Returns:
2234 *      0:              Successfully
2235 *      -EADDRNOTAVAIL: Failed
2236 */
2237static int pch_gbe_set_mac(struct net_device *netdev, void *addr)
2238{
2239        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2240        struct sockaddr *skaddr = addr;
2241        int ret_val;
2242
2243        if (!is_valid_ether_addr(skaddr->sa_data)) {
2244                ret_val = -EADDRNOTAVAIL;
2245        } else {
2246                memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len);
2247                memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len);
2248                pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0);
2249                ret_val = 0;
2250        }
2251        netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val);
2252        netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr);
2253        netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr);
2254        netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n",
2255                   ioread32(&adapter->hw.reg->mac_adr[0].high),
2256                   ioread32(&adapter->hw.reg->mac_adr[0].low));
2257        return ret_val;
2258}
2259
2260/**
2261 * pch_gbe_change_mtu - Change the Maximum Transfer Unit
2262 * @netdev:   Network interface device structure
2263 * @new_mtu:  New value for maximum frame size
2264 * Returns:
2265 *      0:              Successfully
2266 *      -EINVAL:        Failed
2267 */
2268static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu)
2269{
2270        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2271        int max_frame;
2272        unsigned long old_rx_buffer_len = adapter->rx_buffer_len;
2273        int err;
2274
2275        max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2276        if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2277                (max_frame > PCH_GBE_MAX_JUMBO_FRAME_SIZE)) {
2278                netdev_err(netdev, "Invalid MTU setting\n");
2279                return -EINVAL;
2280        }
2281        if (max_frame <= PCH_GBE_FRAME_SIZE_2048)
2282                adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048;
2283        else if (max_frame <= PCH_GBE_FRAME_SIZE_4096)
2284                adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096;
2285        else if (max_frame <= PCH_GBE_FRAME_SIZE_8192)
2286                adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192;
2287        else
2288                adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE;
2289
2290        if (netif_running(netdev)) {
2291                pch_gbe_down(adapter);
2292                err = pch_gbe_up(adapter);
2293                if (err) {
2294                        adapter->rx_buffer_len = old_rx_buffer_len;
2295                        pch_gbe_up(adapter);
2296                        return err;
2297                } else {
2298                        netdev->mtu = new_mtu;
2299                        adapter->hw.mac.max_frame_size = max_frame;
2300                }
2301        } else {
2302                pch_gbe_reset(adapter);
2303                netdev->mtu = new_mtu;
2304                adapter->hw.mac.max_frame_size = max_frame;
2305        }
2306
2307        netdev_dbg(netdev,
2308                   "max_frame : %d  rx_buffer_len : %d  mtu : %d  max_frame_size : %d\n",
2309                   max_frame, (u32) adapter->rx_buffer_len, netdev->mtu,
2310                   adapter->hw.mac.max_frame_size);
2311        return 0;
2312}
2313
2314/**
2315 * pch_gbe_set_features - Reset device after features changed
2316 * @netdev:   Network interface device structure
2317 * @features:  New features
2318 * Returns:
2319 *      0:              HW state updated successfully
2320 */
2321static int pch_gbe_set_features(struct net_device *netdev,
2322        netdev_features_t features)
2323{
2324        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2325        netdev_features_t changed = features ^ netdev->features;
2326
2327        if (!(changed & NETIF_F_RXCSUM))
2328                return 0;
2329
2330        if (netif_running(netdev))
2331                pch_gbe_reinit_locked(adapter);
2332        else
2333                pch_gbe_reset(adapter);
2334
2335        return 0;
2336}
2337
2338/**
2339 * pch_gbe_ioctl - Controls register through a MII interface
2340 * @netdev:   Network interface device structure
2341 * @ifr:      Pointer to ifr structure
2342 * @cmd:      Control command
2343 * Returns:
2344 *      0:      Successfully
2345 *      Negative value: Failed
2346 */
2347static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2348{
2349        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2350
2351        netdev_dbg(netdev, "cmd : 0x%04x\n", cmd);
2352
2353        if (cmd == SIOCSHWTSTAMP)
2354                return hwtstamp_ioctl(netdev, ifr, cmd);
2355
2356        return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
2357}
2358
2359/**
2360 * pch_gbe_tx_timeout - Respond to a Tx Hang
2361 * @netdev:   Network interface device structure
2362 */
2363static void pch_gbe_tx_timeout(struct net_device *netdev)
2364{
2365        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2366
2367        /* Do the reset outside of interrupt context */
2368        adapter->stats.tx_timeout_count++;
2369        schedule_work(&adapter->reset_task);
2370}
2371
2372/**
2373 * pch_gbe_napi_poll - NAPI receive and transfer polling callback
2374 * @napi:    Pointer of polling device struct
2375 * @budget:  The maximum number of a packet
2376 * Returns:
2377 *      false:  Exit the polling mode
2378 *      true:   Continue the polling mode
2379 */
2380static int pch_gbe_napi_poll(struct napi_struct *napi, int budget)
2381{
2382        struct pch_gbe_adapter *adapter =
2383            container_of(napi, struct pch_gbe_adapter, napi);
2384        int work_done = 0;
2385        bool poll_end_flag = false;
2386        bool cleaned = false;
2387
2388        netdev_dbg(adapter->netdev, "budget : %d\n", budget);
2389
2390        pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget);
2391        cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring);
2392
2393        if (cleaned)
2394                work_done = budget;
2395        /* If no Tx and not enough Rx work done,
2396         * exit the polling mode
2397         */
2398        if (work_done < budget)
2399                poll_end_flag = true;
2400
2401        if (poll_end_flag) {
2402                napi_complete(napi);
2403                pch_gbe_irq_enable(adapter);
2404        }
2405
2406        if (adapter->rx_stop_flag) {
2407                adapter->rx_stop_flag = false;
2408                pch_gbe_enable_dma_rx(&adapter->hw);
2409        }
2410
2411        netdev_dbg(adapter->netdev,
2412                   "poll_end_flag : %d  work_done : %d  budget : %d\n",
2413                   poll_end_flag, work_done, budget);
2414
2415        return work_done;
2416}
2417
2418#ifdef CONFIG_NET_POLL_CONTROLLER
2419/**
2420 * pch_gbe_netpoll - Used by things like netconsole to send skbs
2421 * @netdev:  Network interface device structure
2422 */
2423static void pch_gbe_netpoll(struct net_device *netdev)
2424{
2425        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2426
2427        disable_irq(adapter->pdev->irq);
2428        pch_gbe_intr(adapter->pdev->irq, netdev);
2429        enable_irq(adapter->pdev->irq);
2430}
2431#endif
2432
2433static const struct net_device_ops pch_gbe_netdev_ops = {
2434        .ndo_open = pch_gbe_open,
2435        .ndo_stop = pch_gbe_stop,
2436        .ndo_start_xmit = pch_gbe_xmit_frame,
2437        .ndo_get_stats = pch_gbe_get_stats,
2438        .ndo_set_mac_address = pch_gbe_set_mac,
2439        .ndo_tx_timeout = pch_gbe_tx_timeout,
2440        .ndo_change_mtu = pch_gbe_change_mtu,
2441        .ndo_set_features = pch_gbe_set_features,
2442        .ndo_do_ioctl = pch_gbe_ioctl,
2443        .ndo_set_rx_mode = pch_gbe_set_multi,
2444#ifdef CONFIG_NET_POLL_CONTROLLER
2445        .ndo_poll_controller = pch_gbe_netpoll,
2446#endif
2447};
2448
2449static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev,
2450                                                pci_channel_state_t state)
2451{
2452        struct net_device *netdev = pci_get_drvdata(pdev);
2453        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2454
2455        netif_device_detach(netdev);
2456        if (netif_running(netdev))
2457                pch_gbe_down(adapter);
2458        pci_disable_device(pdev);
2459        /* Request a slot slot reset. */
2460        return PCI_ERS_RESULT_NEED_RESET;
2461}
2462
2463static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev)
2464{
2465        struct net_device *netdev = pci_get_drvdata(pdev);
2466        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2467        struct pch_gbe_hw *hw = &adapter->hw;
2468
2469        if (pci_enable_device(pdev)) {
2470                netdev_err(netdev, "Cannot re-enable PCI device after reset\n");
2471                return PCI_ERS_RESULT_DISCONNECT;
2472        }
2473        pci_set_master(pdev);
2474        pci_enable_wake(pdev, PCI_D0, 0);
2475        pch_gbe_hal_power_up_phy(hw);
2476        pch_gbe_reset(adapter);
2477        /* Clear wake up status */
2478        pch_gbe_mac_set_wol_event(hw, 0);
2479
2480        return PCI_ERS_RESULT_RECOVERED;
2481}
2482
2483static void pch_gbe_io_resume(struct pci_dev *pdev)
2484{
2485        struct net_device *netdev = pci_get_drvdata(pdev);
2486        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2487
2488        if (netif_running(netdev)) {
2489                if (pch_gbe_up(adapter)) {
2490                        netdev_dbg(netdev,
2491                                   "can't bring device back up after reset\n");
2492                        return;
2493                }
2494        }
2495        netif_device_attach(netdev);
2496}
2497
2498static int __pch_gbe_suspend(struct pci_dev *pdev)
2499{
2500        struct net_device *netdev = pci_get_drvdata(pdev);
2501        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2502        struct pch_gbe_hw *hw = &adapter->hw;
2503        u32 wufc = adapter->wake_up_evt;
2504        int retval = 0;
2505
2506        netif_device_detach(netdev);
2507        if (netif_running(netdev))
2508                pch_gbe_down(adapter);
2509        if (wufc) {
2510                pch_gbe_set_multi(netdev);
2511                pch_gbe_setup_rctl(adapter);
2512                pch_gbe_configure_rx(adapter);
2513                pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed,
2514                                        hw->mac.link_duplex);
2515                pch_gbe_set_mode(adapter, hw->mac.link_speed,
2516                                        hw->mac.link_duplex);
2517                pch_gbe_mac_set_wol_event(hw, wufc);
2518                pci_disable_device(pdev);
2519        } else {
2520                pch_gbe_hal_power_down_phy(hw);
2521                pch_gbe_mac_set_wol_event(hw, wufc);
2522                pci_disable_device(pdev);
2523        }
2524        return retval;
2525}
2526
2527#ifdef CONFIG_PM
2528static int pch_gbe_suspend(struct device *device)
2529{
2530        struct pci_dev *pdev = to_pci_dev(device);
2531
2532        return __pch_gbe_suspend(pdev);
2533}
2534
2535static int pch_gbe_resume(struct device *device)
2536{
2537        struct pci_dev *pdev = to_pci_dev(device);
2538        struct net_device *netdev = pci_get_drvdata(pdev);
2539        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2540        struct pch_gbe_hw *hw = &adapter->hw;
2541        u32 err;
2542
2543        err = pci_enable_device(pdev);
2544        if (err) {
2545                netdev_err(netdev, "Cannot enable PCI device from suspend\n");
2546                return err;
2547        }
2548        pci_set_master(pdev);
2549        pch_gbe_hal_power_up_phy(hw);
2550        pch_gbe_reset(adapter);
2551        /* Clear wake on lan control and status */
2552        pch_gbe_mac_set_wol_event(hw, 0);
2553
2554        if (netif_running(netdev))
2555                pch_gbe_up(adapter);
2556        netif_device_attach(netdev);
2557
2558        return 0;
2559}
2560#endif /* CONFIG_PM */
2561
2562static void pch_gbe_shutdown(struct pci_dev *pdev)
2563{
2564        __pch_gbe_suspend(pdev);
2565        if (system_state == SYSTEM_POWER_OFF) {
2566                pci_wake_from_d3(pdev, true);
2567                pci_set_power_state(pdev, PCI_D3hot);
2568        }
2569}
2570
2571static void pch_gbe_remove(struct pci_dev *pdev)
2572{
2573        struct net_device *netdev = pci_get_drvdata(pdev);
2574        struct pch_gbe_adapter *adapter = netdev_priv(netdev);
2575
2576        cancel_work_sync(&adapter->reset_task);
2577        unregister_netdev(netdev);
2578
2579        pch_gbe_hal_phy_hw_reset(&adapter->hw);
2580
2581        free_netdev(netdev);
2582}
2583
2584static int pch_gbe_probe(struct pci_dev *pdev,
2585                          const struct pci_device_id *pci_id)
2586{
2587        struct net_device *netdev;
2588        struct pch_gbe_adapter *adapter;
2589        int ret;
2590
2591        ret = pcim_enable_device(pdev);
2592        if (ret)
2593                return ret;
2594
2595        if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
2596                || pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2597                ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2598                if (ret) {
2599                        ret = pci_set_consistent_dma_mask(pdev,
2600                                                          DMA_BIT_MASK(32));
2601                        if (ret) {
2602                                dev_err(&pdev->dev, "ERR: No usable DMA "
2603                                        "configuration, aborting\n");
2604                                return ret;
2605                        }
2606                }
2607        }
2608
2609        ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev));
2610        if (ret) {
2611                dev_err(&pdev->dev,
2612                        "ERR: Can't reserve PCI I/O and memory resources\n");
2613                return ret;
2614        }
2615        pci_set_master(pdev);
2616
2617        netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter));
2618        if (!netdev)
2619                return -ENOMEM;
2620        SET_NETDEV_DEV(netdev, &pdev->dev);
2621
2622        pci_set_drvdata(pdev, netdev);
2623        adapter = netdev_priv(netdev);
2624        adapter->netdev = netdev;
2625        adapter->pdev = pdev;
2626        adapter->hw.back = adapter;
2627        adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR];
2628        adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data;
2629        if (adapter->pdata && adapter->pdata->platform_init)
2630                adapter->pdata->platform_init(pdev);
2631
2632        adapter->ptp_pdev = pci_get_bus_and_slot(adapter->pdev->bus->number,
2633                                               PCI_DEVFN(12, 4));
2634
2635        netdev->netdev_ops = &pch_gbe_netdev_ops;
2636        netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD;
2637        netif_napi_add(netdev, &adapter->napi,
2638                       pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT);
2639        netdev->hw_features = NETIF_F_RXCSUM |
2640                NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
2641        netdev->features = netdev->hw_features;
2642        pch_gbe_set_ethtool_ops(netdev);
2643
2644        pch_gbe_mac_load_mac_addr(&adapter->hw);
2645        pch_gbe_mac_reset_hw(&adapter->hw);
2646
2647        /* setup the private structure */
2648        ret = pch_gbe_sw_init(adapter);
2649        if (ret)
2650                goto err_free_netdev;
2651
2652        /* Initialize PHY */
2653        ret = pch_gbe_init_phy(adapter);
2654        if (ret) {
2655                dev_err(&pdev->dev, "PHY initialize error\n");
2656                goto err_free_adapter;
2657        }
2658        pch_gbe_hal_get_bus_info(&adapter->hw);
2659
2660        /* Read the MAC address. and store to the private data */
2661        ret = pch_gbe_hal_read_mac_addr(&adapter->hw);
2662        if (ret) {
2663                dev_err(&pdev->dev, "MAC address Read Error\n");
2664                goto err_free_adapter;
2665        }
2666
2667        memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len);
2668        if (!is_valid_ether_addr(netdev->dev_addr)) {
2669                /*
2670                 * If the MAC is invalid (or just missing), display a warning
2671                 * but do not abort setting up the device. pch_gbe_up will
2672                 * prevent the interface from being brought up until a valid MAC
2673                 * is set.
2674                 */
2675                dev_err(&pdev->dev, "Invalid MAC address, "
2676                                    "interface disabled.\n");
2677        }
2678        setup_timer(&adapter->watchdog_timer, pch_gbe_watchdog,
2679                    (unsigned long)adapter);
2680
2681        INIT_WORK(&adapter->reset_task, pch_gbe_reset_task);
2682
2683        pch_gbe_check_options(adapter);
2684
2685        /* initialize the wol settings based on the eeprom settings */
2686        adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING;
2687        dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr);
2688
2689        /* reset the hardware with the new settings */
2690        pch_gbe_reset(adapter);
2691
2692        ret = register_netdev(netdev);
2693        if (ret)
2694                goto err_free_adapter;
2695        /* tell the stack to leave us alone until pch_gbe_open() is called */
2696        netif_carrier_off(netdev);
2697        netif_stop_queue(netdev);
2698
2699        dev_dbg(&pdev->dev, "PCH Network Connection\n");
2700
2701        /* Disable hibernation on certain platforms */
2702        if (adapter->pdata && adapter->pdata->phy_disable_hibernate)
2703                pch_gbe_phy_disable_hibernate(&adapter->hw);
2704
2705        device_set_wakeup_enable(&pdev->dev, 1);
2706        return 0;
2707
2708err_free_adapter:
2709        pch_gbe_hal_phy_hw_reset(&adapter->hw);
2710err_free_netdev:
2711        free_netdev(netdev);
2712        return ret;
2713}
2714
2715/* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to
2716 * ensure it is awake for probe and init. Request the line and reset the PHY.
2717 */
2718static int pch_gbe_minnow_platform_init(struct pci_dev *pdev)
2719{
2720        unsigned long flags = GPIOF_DIR_OUT | GPIOF_INIT_HIGH | GPIOF_EXPORT;
2721        unsigned gpio = MINNOW_PHY_RESET_GPIO;
2722        int ret;
2723
2724        ret = devm_gpio_request_one(&pdev->dev, gpio, flags,
2725                                    "minnow_phy_reset");
2726        if (ret) {
2727                dev_err(&pdev->dev,
2728                        "ERR: Can't request PHY reset GPIO line '%d'\n", gpio);
2729                return ret;
2730        }
2731
2732        gpio_set_value(gpio, 0);
2733        usleep_range(1250, 1500);
2734        gpio_set_value(gpio, 1);
2735        usleep_range(1250, 1500);
2736
2737        return ret;
2738}
2739
2740static struct pch_gbe_privdata pch_gbe_minnow_privdata = {
2741        .phy_tx_clk_delay = true,
2742        .phy_disable_hibernate = true,
2743        .platform_init = pch_gbe_minnow_platform_init,
2744};
2745
2746static const struct pci_device_id pch_gbe_pcidev_id[] = {
2747        {.vendor = PCI_VENDOR_ID_INTEL,
2748         .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2749         .subvendor = PCI_VENDOR_ID_CIRCUITCO,
2750         .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD,
2751         .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2752         .class_mask = (0xFFFF00),
2753         .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata
2754         },
2755        {.vendor = PCI_VENDOR_ID_INTEL,
2756         .device = PCI_DEVICE_ID_INTEL_IOH1_GBE,
2757         .subvendor = PCI_ANY_ID,
2758         .subdevice = PCI_ANY_ID,
2759         .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2760         .class_mask = (0xFFFF00)
2761         },
2762        {.vendor = PCI_VENDOR_ID_ROHM,
2763         .device = PCI_DEVICE_ID_ROHM_ML7223_GBE,
2764         .subvendor = PCI_ANY_ID,
2765         .subdevice = PCI_ANY_ID,
2766         .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2767         .class_mask = (0xFFFF00)
2768         },
2769        {.vendor = PCI_VENDOR_ID_ROHM,
2770         .device = PCI_DEVICE_ID_ROHM_ML7831_GBE,
2771         .subvendor = PCI_ANY_ID,
2772         .subdevice = PCI_ANY_ID,
2773         .class = (PCI_CLASS_NETWORK_ETHERNET << 8),
2774         .class_mask = (0xFFFF00)
2775         },
2776        /* required last entry */
2777        {0}
2778};
2779
2780#ifdef CONFIG_PM
2781static const struct dev_pm_ops pch_gbe_pm_ops = {
2782        .suspend = pch_gbe_suspend,
2783        .resume = pch_gbe_resume,
2784        .freeze = pch_gbe_suspend,
2785        .thaw = pch_gbe_resume,
2786        .poweroff = pch_gbe_suspend,
2787        .restore = pch_gbe_resume,
2788};
2789#endif
2790
2791static const struct pci_error_handlers pch_gbe_err_handler = {
2792        .error_detected = pch_gbe_io_error_detected,
2793        .slot_reset = pch_gbe_io_slot_reset,
2794        .resume = pch_gbe_io_resume
2795};
2796
2797static struct pci_driver pch_gbe_driver = {
2798        .name = KBUILD_MODNAME,
2799        .id_table = pch_gbe_pcidev_id,
2800        .probe = pch_gbe_probe,
2801        .remove = pch_gbe_remove,
2802#ifdef CONFIG_PM
2803        .driver.pm = &pch_gbe_pm_ops,
2804#endif
2805        .shutdown = pch_gbe_shutdown,
2806        .err_handler = &pch_gbe_err_handler
2807};
2808
2809
2810static int __init pch_gbe_init_module(void)
2811{
2812        int ret;
2813
2814        pr_info("EG20T PCH Gigabit Ethernet Driver - version %s\n",DRV_VERSION);
2815        ret = pci_register_driver(&pch_gbe_driver);
2816        if (copybreak != PCH_GBE_COPYBREAK_DEFAULT) {
2817                if (copybreak == 0) {
2818                        pr_info("copybreak disabled\n");
2819                } else {
2820                        pr_info("copybreak enabled for packets <= %u bytes\n",
2821                                copybreak);
2822                }
2823        }
2824        return ret;
2825}
2826
2827static void __exit pch_gbe_exit_module(void)
2828{
2829        pci_unregister_driver(&pch_gbe_driver);
2830}
2831
2832module_init(pch_gbe_init_module);
2833module_exit(pch_gbe_exit_module);
2834
2835MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver");
2836MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>");
2837MODULE_LICENSE("GPL");
2838MODULE_VERSION(DRV_VERSION);
2839MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id);
2840
2841module_param(copybreak, uint, 0644);
2842MODULE_PARM_DESC(copybreak,
2843        "Maximum size of packet that is copied to a new buffer on receive");
2844
2845/* pch_gbe_main.c */
2846
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