linux/drivers/net/ethernet/ethoc.c
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   1/*
   2 * linux/drivers/net/ethernet/ethoc.c
   3 *
   4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
   5 * Copyright (C) 2008-2009 Avionic Design GmbH
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
  12 */
  13
  14#include <linux/dma-mapping.h>
  15#include <linux/etherdevice.h>
  16#include <linux/clk.h>
  17#include <linux/crc32.h>
  18#include <linux/interrupt.h>
  19#include <linux/io.h>
  20#include <linux/mii.h>
  21#include <linux/phy.h>
  22#include <linux/platform_device.h>
  23#include <linux/sched.h>
  24#include <linux/slab.h>
  25#include <linux/of.h>
  26#include <linux/module.h>
  27#include <net/ethoc.h>
  28
  29static int buffer_size = 0x8000; /* 32 KBytes */
  30module_param(buffer_size, int, 0);
  31MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
  32
  33/* register offsets */
  34#define MODER           0x00
  35#define INT_SOURCE      0x04
  36#define INT_MASK        0x08
  37#define IPGT            0x0c
  38#define IPGR1           0x10
  39#define IPGR2           0x14
  40#define PACKETLEN       0x18
  41#define COLLCONF        0x1c
  42#define TX_BD_NUM       0x20
  43#define CTRLMODER       0x24
  44#define MIIMODER        0x28
  45#define MIICOMMAND      0x2c
  46#define MIIADDRESS      0x30
  47#define MIITX_DATA      0x34
  48#define MIIRX_DATA      0x38
  49#define MIISTATUS       0x3c
  50#define MAC_ADDR0       0x40
  51#define MAC_ADDR1       0x44
  52#define ETH_HASH0       0x48
  53#define ETH_HASH1       0x4c
  54#define ETH_TXCTRL      0x50
  55#define ETH_END         0x54
  56
  57/* mode register */
  58#define MODER_RXEN      (1 <<  0) /* receive enable */
  59#define MODER_TXEN      (1 <<  1) /* transmit enable */
  60#define MODER_NOPRE     (1 <<  2) /* no preamble */
  61#define MODER_BRO       (1 <<  3) /* broadcast address */
  62#define MODER_IAM       (1 <<  4) /* individual address mode */
  63#define MODER_PRO       (1 <<  5) /* promiscuous mode */
  64#define MODER_IFG       (1 <<  6) /* interframe gap for incoming frames */
  65#define MODER_LOOP      (1 <<  7) /* loopback */
  66#define MODER_NBO       (1 <<  8) /* no back-off */
  67#define MODER_EDE       (1 <<  9) /* excess defer enable */
  68#define MODER_FULLD     (1 << 10) /* full duplex */
  69#define MODER_RESET     (1 << 11) /* FIXME: reset (undocumented) */
  70#define MODER_DCRC      (1 << 12) /* delayed CRC enable */
  71#define MODER_CRC       (1 << 13) /* CRC enable */
  72#define MODER_HUGE      (1 << 14) /* huge packets enable */
  73#define MODER_PAD       (1 << 15) /* padding enabled */
  74#define MODER_RSM       (1 << 16) /* receive small packets */
  75
  76/* interrupt source and mask registers */
  77#define INT_MASK_TXF    (1 << 0) /* transmit frame */
  78#define INT_MASK_TXE    (1 << 1) /* transmit error */
  79#define INT_MASK_RXF    (1 << 2) /* receive frame */
  80#define INT_MASK_RXE    (1 << 3) /* receive error */
  81#define INT_MASK_BUSY   (1 << 4)
  82#define INT_MASK_TXC    (1 << 5) /* transmit control frame */
  83#define INT_MASK_RXC    (1 << 6) /* receive control frame */
  84
  85#define INT_MASK_TX     (INT_MASK_TXF | INT_MASK_TXE)
  86#define INT_MASK_RX     (INT_MASK_RXF | INT_MASK_RXE)
  87
  88#define INT_MASK_ALL ( \
  89                INT_MASK_TXF | INT_MASK_TXE | \
  90                INT_MASK_RXF | INT_MASK_RXE | \
  91                INT_MASK_TXC | INT_MASK_RXC | \
  92                INT_MASK_BUSY \
  93        )
  94
  95/* packet length register */
  96#define PACKETLEN_MIN(min)              (((min) & 0xffff) << 16)
  97#define PACKETLEN_MAX(max)              (((max) & 0xffff) <<  0)
  98#define PACKETLEN_MIN_MAX(min, max)     (PACKETLEN_MIN(min) | \
  99                                        PACKETLEN_MAX(max))
 100
 101/* transmit buffer number register */
 102#define TX_BD_NUM_VAL(x)        (((x) <= 0x80) ? (x) : 0x80)
 103
 104/* control module mode register */
 105#define CTRLMODER_PASSALL       (1 << 0) /* pass all receive frames */
 106#define CTRLMODER_RXFLOW        (1 << 1) /* receive control flow */
 107#define CTRLMODER_TXFLOW        (1 << 2) /* transmit control flow */
 108
 109/* MII mode register */
 110#define MIIMODER_CLKDIV(x)      ((x) & 0xfe) /* needs to be an even number */
 111#define MIIMODER_NOPRE          (1 << 8) /* no preamble */
 112
 113/* MII command register */
 114#define MIICOMMAND_SCAN         (1 << 0) /* scan status */
 115#define MIICOMMAND_READ         (1 << 1) /* read status */
 116#define MIICOMMAND_WRITE        (1 << 2) /* write control data */
 117
 118/* MII address register */
 119#define MIIADDRESS_FIAD(x)              (((x) & 0x1f) << 0)
 120#define MIIADDRESS_RGAD(x)              (((x) & 0x1f) << 8)
 121#define MIIADDRESS_ADDR(phy, reg)       (MIIADDRESS_FIAD(phy) | \
 122                                        MIIADDRESS_RGAD(reg))
 123
 124/* MII transmit data register */
 125#define MIITX_DATA_VAL(x)       ((x) & 0xffff)
 126
 127/* MII receive data register */
 128#define MIIRX_DATA_VAL(x)       ((x) & 0xffff)
 129
 130/* MII status register */
 131#define MIISTATUS_LINKFAIL      (1 << 0)
 132#define MIISTATUS_BUSY          (1 << 1)
 133#define MIISTATUS_INVALID       (1 << 2)
 134
 135/* TX buffer descriptor */
 136#define TX_BD_CS                (1 <<  0) /* carrier sense lost */
 137#define TX_BD_DF                (1 <<  1) /* defer indication */
 138#define TX_BD_LC                (1 <<  2) /* late collision */
 139#define TX_BD_RL                (1 <<  3) /* retransmission limit */
 140#define TX_BD_RETRY_MASK        (0x00f0)
 141#define TX_BD_RETRY(x)          (((x) & 0x00f0) >>  4)
 142#define TX_BD_UR                (1 <<  8) /* transmitter underrun */
 143#define TX_BD_CRC               (1 << 11) /* TX CRC enable */
 144#define TX_BD_PAD               (1 << 12) /* pad enable for short packets */
 145#define TX_BD_WRAP              (1 << 13)
 146#define TX_BD_IRQ               (1 << 14) /* interrupt request enable */
 147#define TX_BD_READY             (1 << 15) /* TX buffer ready */
 148#define TX_BD_LEN(x)            (((x) & 0xffff) << 16)
 149#define TX_BD_LEN_MASK          (0xffff << 16)
 150
 151#define TX_BD_STATS             (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
 152                                TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
 153
 154/* RX buffer descriptor */
 155#define RX_BD_LC        (1 <<  0) /* late collision */
 156#define RX_BD_CRC       (1 <<  1) /* RX CRC error */
 157#define RX_BD_SF        (1 <<  2) /* short frame */
 158#define RX_BD_TL        (1 <<  3) /* too long */
 159#define RX_BD_DN        (1 <<  4) /* dribble nibble */
 160#define RX_BD_IS        (1 <<  5) /* invalid symbol */
 161#define RX_BD_OR        (1 <<  6) /* receiver overrun */
 162#define RX_BD_MISS      (1 <<  7)
 163#define RX_BD_CF        (1 <<  8) /* control frame */
 164#define RX_BD_WRAP      (1 << 13)
 165#define RX_BD_IRQ       (1 << 14) /* interrupt request enable */
 166#define RX_BD_EMPTY     (1 << 15)
 167#define RX_BD_LEN(x)    (((x) & 0xffff) << 16)
 168
 169#define RX_BD_STATS     (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
 170                        RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
 171
 172#define ETHOC_BUFSIZ            1536
 173#define ETHOC_ZLEN              64
 174#define ETHOC_BD_BASE           0x400
 175#define ETHOC_TIMEOUT           (HZ / 2)
 176#define ETHOC_MII_TIMEOUT       (1 + (HZ / 5))
 177
 178/**
 179 * struct ethoc - driver-private device structure
 180 * @iobase:     pointer to I/O memory region
 181 * @membase:    pointer to buffer memory region
 182 * @dma_alloc:  dma allocated buffer size
 183 * @io_region_size:     I/O memory region size
 184 * @num_bd:     number of buffer descriptors
 185 * @num_tx:     number of send buffers
 186 * @cur_tx:     last send buffer written
 187 * @dty_tx:     last buffer actually sent
 188 * @num_rx:     number of receive buffers
 189 * @cur_rx:     current receive buffer
 190 * @vma:        pointer to array of virtual memory addresses for buffers
 191 * @netdev:     pointer to network device structure
 192 * @napi:       NAPI structure
 193 * @msg_enable: device state flags
 194 * @lock:       device lock
 195 * @phy:        attached PHY
 196 * @mdio:       MDIO bus for PHY access
 197 * @phy_id:     address of attached PHY
 198 */
 199struct ethoc {
 200        void __iomem *iobase;
 201        void __iomem *membase;
 202        int dma_alloc;
 203        resource_size_t io_region_size;
 204        bool big_endian;
 205
 206        unsigned int num_bd;
 207        unsigned int num_tx;
 208        unsigned int cur_tx;
 209        unsigned int dty_tx;
 210
 211        unsigned int num_rx;
 212        unsigned int cur_rx;
 213
 214        void **vma;
 215
 216        struct net_device *netdev;
 217        struct napi_struct napi;
 218        u32 msg_enable;
 219
 220        spinlock_t lock;
 221
 222        struct phy_device *phy;
 223        struct mii_bus *mdio;
 224        struct clk *clk;
 225        s8 phy_id;
 226};
 227
 228/**
 229 * struct ethoc_bd - buffer descriptor
 230 * @stat:       buffer statistics
 231 * @addr:       physical memory address
 232 */
 233struct ethoc_bd {
 234        u32 stat;
 235        u32 addr;
 236};
 237
 238static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
 239{
 240        if (dev->big_endian)
 241                return ioread32be(dev->iobase + offset);
 242        else
 243                return ioread32(dev->iobase + offset);
 244}
 245
 246static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
 247{
 248        if (dev->big_endian)
 249                iowrite32be(data, dev->iobase + offset);
 250        else
 251                iowrite32(data, dev->iobase + offset);
 252}
 253
 254static inline void ethoc_read_bd(struct ethoc *dev, int index,
 255                struct ethoc_bd *bd)
 256{
 257        loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 258        bd->stat = ethoc_read(dev, offset + 0);
 259        bd->addr = ethoc_read(dev, offset + 4);
 260}
 261
 262static inline void ethoc_write_bd(struct ethoc *dev, int index,
 263                const struct ethoc_bd *bd)
 264{
 265        loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 266        ethoc_write(dev, offset + 0, bd->stat);
 267        ethoc_write(dev, offset + 4, bd->addr);
 268}
 269
 270static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
 271{
 272        u32 imask = ethoc_read(dev, INT_MASK);
 273        imask |= mask;
 274        ethoc_write(dev, INT_MASK, imask);
 275}
 276
 277static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
 278{
 279        u32 imask = ethoc_read(dev, INT_MASK);
 280        imask &= ~mask;
 281        ethoc_write(dev, INT_MASK, imask);
 282}
 283
 284static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
 285{
 286        ethoc_write(dev, INT_SOURCE, mask);
 287}
 288
 289static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
 290{
 291        u32 mode = ethoc_read(dev, MODER);
 292        mode |= MODER_RXEN | MODER_TXEN;
 293        ethoc_write(dev, MODER, mode);
 294}
 295
 296static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
 297{
 298        u32 mode = ethoc_read(dev, MODER);
 299        mode &= ~(MODER_RXEN | MODER_TXEN);
 300        ethoc_write(dev, MODER, mode);
 301}
 302
 303static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
 304{
 305        struct ethoc_bd bd;
 306        int i;
 307        void *vma;
 308
 309        dev->cur_tx = 0;
 310        dev->dty_tx = 0;
 311        dev->cur_rx = 0;
 312
 313        ethoc_write(dev, TX_BD_NUM, dev->num_tx);
 314
 315        /* setup transmission buffers */
 316        bd.addr = mem_start;
 317        bd.stat = TX_BD_IRQ | TX_BD_CRC;
 318        vma = dev->membase;
 319
 320        for (i = 0; i < dev->num_tx; i++) {
 321                if (i == dev->num_tx - 1)
 322                        bd.stat |= TX_BD_WRAP;
 323
 324                ethoc_write_bd(dev, i, &bd);
 325                bd.addr += ETHOC_BUFSIZ;
 326
 327                dev->vma[i] = vma;
 328                vma += ETHOC_BUFSIZ;
 329        }
 330
 331        bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
 332
 333        for (i = 0; i < dev->num_rx; i++) {
 334                if (i == dev->num_rx - 1)
 335                        bd.stat |= RX_BD_WRAP;
 336
 337                ethoc_write_bd(dev, dev->num_tx + i, &bd);
 338                bd.addr += ETHOC_BUFSIZ;
 339
 340                dev->vma[dev->num_tx + i] = vma;
 341                vma += ETHOC_BUFSIZ;
 342        }
 343
 344        return 0;
 345}
 346
 347static int ethoc_reset(struct ethoc *dev)
 348{
 349        u32 mode;
 350
 351        /* TODO: reset controller? */
 352
 353        ethoc_disable_rx_and_tx(dev);
 354
 355        /* TODO: setup registers */
 356
 357        /* enable FCS generation and automatic padding */
 358        mode = ethoc_read(dev, MODER);
 359        mode |= MODER_CRC | MODER_PAD;
 360        ethoc_write(dev, MODER, mode);
 361
 362        /* set full-duplex mode */
 363        mode = ethoc_read(dev, MODER);
 364        mode |= MODER_FULLD;
 365        ethoc_write(dev, MODER, mode);
 366        ethoc_write(dev, IPGT, 0x15);
 367
 368        ethoc_ack_irq(dev, INT_MASK_ALL);
 369        ethoc_enable_irq(dev, INT_MASK_ALL);
 370        ethoc_enable_rx_and_tx(dev);
 371        return 0;
 372}
 373
 374static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
 375                struct ethoc_bd *bd)
 376{
 377        struct net_device *netdev = dev->netdev;
 378        unsigned int ret = 0;
 379
 380        if (bd->stat & RX_BD_TL) {
 381                dev_err(&netdev->dev, "RX: frame too long\n");
 382                netdev->stats.rx_length_errors++;
 383                ret++;
 384        }
 385
 386        if (bd->stat & RX_BD_SF) {
 387                dev_err(&netdev->dev, "RX: frame too short\n");
 388                netdev->stats.rx_length_errors++;
 389                ret++;
 390        }
 391
 392        if (bd->stat & RX_BD_DN) {
 393                dev_err(&netdev->dev, "RX: dribble nibble\n");
 394                netdev->stats.rx_frame_errors++;
 395        }
 396
 397        if (bd->stat & RX_BD_CRC) {
 398                dev_err(&netdev->dev, "RX: wrong CRC\n");
 399                netdev->stats.rx_crc_errors++;
 400                ret++;
 401        }
 402
 403        if (bd->stat & RX_BD_OR) {
 404                dev_err(&netdev->dev, "RX: overrun\n");
 405                netdev->stats.rx_over_errors++;
 406                ret++;
 407        }
 408
 409        if (bd->stat & RX_BD_MISS)
 410                netdev->stats.rx_missed_errors++;
 411
 412        if (bd->stat & RX_BD_LC) {
 413                dev_err(&netdev->dev, "RX: late collision\n");
 414                netdev->stats.collisions++;
 415                ret++;
 416        }
 417
 418        return ret;
 419}
 420
 421static int ethoc_rx(struct net_device *dev, int limit)
 422{
 423        struct ethoc *priv = netdev_priv(dev);
 424        int count;
 425
 426        for (count = 0; count < limit; ++count) {
 427                unsigned int entry;
 428                struct ethoc_bd bd;
 429
 430                entry = priv->num_tx + priv->cur_rx;
 431                ethoc_read_bd(priv, entry, &bd);
 432                if (bd.stat & RX_BD_EMPTY) {
 433                        ethoc_ack_irq(priv, INT_MASK_RX);
 434                        /* If packet (interrupt) came in between checking
 435                         * BD_EMTPY and clearing the interrupt source, then we
 436                         * risk missing the packet as the RX interrupt won't
 437                         * trigger right away when we reenable it; hence, check
 438                         * BD_EMTPY here again to make sure there isn't such a
 439                         * packet waiting for us...
 440                         */
 441                        ethoc_read_bd(priv, entry, &bd);
 442                        if (bd.stat & RX_BD_EMPTY)
 443                                break;
 444                }
 445
 446                if (ethoc_update_rx_stats(priv, &bd) == 0) {
 447                        int size = bd.stat >> 16;
 448                        struct sk_buff *skb;
 449
 450                        size -= 4; /* strip the CRC */
 451                        skb = netdev_alloc_skb_ip_align(dev, size);
 452
 453                        if (likely(skb)) {
 454                                void *src = priv->vma[entry];
 455                                memcpy_fromio(skb_put(skb, size), src, size);
 456                                skb->protocol = eth_type_trans(skb, dev);
 457                                dev->stats.rx_packets++;
 458                                dev->stats.rx_bytes += size;
 459                                netif_receive_skb(skb);
 460                        } else {
 461                                if (net_ratelimit())
 462                                        dev_warn(&dev->dev,
 463                                            "low on memory - packet dropped\n");
 464
 465                                dev->stats.rx_dropped++;
 466                                break;
 467                        }
 468                }
 469
 470                /* clear the buffer descriptor so it can be reused */
 471                bd.stat &= ~RX_BD_STATS;
 472                bd.stat |=  RX_BD_EMPTY;
 473                ethoc_write_bd(priv, entry, &bd);
 474                if (++priv->cur_rx == priv->num_rx)
 475                        priv->cur_rx = 0;
 476        }
 477
 478        return count;
 479}
 480
 481static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
 482{
 483        struct net_device *netdev = dev->netdev;
 484
 485        if (bd->stat & TX_BD_LC) {
 486                dev_err(&netdev->dev, "TX: late collision\n");
 487                netdev->stats.tx_window_errors++;
 488        }
 489
 490        if (bd->stat & TX_BD_RL) {
 491                dev_err(&netdev->dev, "TX: retransmit limit\n");
 492                netdev->stats.tx_aborted_errors++;
 493        }
 494
 495        if (bd->stat & TX_BD_UR) {
 496                dev_err(&netdev->dev, "TX: underrun\n");
 497                netdev->stats.tx_fifo_errors++;
 498        }
 499
 500        if (bd->stat & TX_BD_CS) {
 501                dev_err(&netdev->dev, "TX: carrier sense lost\n");
 502                netdev->stats.tx_carrier_errors++;
 503        }
 504
 505        if (bd->stat & TX_BD_STATS)
 506                netdev->stats.tx_errors++;
 507
 508        netdev->stats.collisions += (bd->stat >> 4) & 0xf;
 509        netdev->stats.tx_bytes += bd->stat >> 16;
 510        netdev->stats.tx_packets++;
 511}
 512
 513static int ethoc_tx(struct net_device *dev, int limit)
 514{
 515        struct ethoc *priv = netdev_priv(dev);
 516        int count;
 517        struct ethoc_bd bd;
 518
 519        for (count = 0; count < limit; ++count) {
 520                unsigned int entry;
 521
 522                entry = priv->dty_tx & (priv->num_tx-1);
 523
 524                ethoc_read_bd(priv, entry, &bd);
 525
 526                if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
 527                        ethoc_ack_irq(priv, INT_MASK_TX);
 528                        /* If interrupt came in between reading in the BD
 529                         * and clearing the interrupt source, then we risk
 530                         * missing the event as the TX interrupt won't trigger
 531                         * right away when we reenable it; hence, check
 532                         * BD_EMPTY here again to make sure there isn't such an
 533                         * event pending...
 534                         */
 535                        ethoc_read_bd(priv, entry, &bd);
 536                        if (bd.stat & TX_BD_READY ||
 537                            (priv->dty_tx == priv->cur_tx))
 538                                break;
 539                }
 540
 541                ethoc_update_tx_stats(priv, &bd);
 542                priv->dty_tx++;
 543        }
 544
 545        if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
 546                netif_wake_queue(dev);
 547
 548        return count;
 549}
 550
 551static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
 552{
 553        struct net_device *dev = dev_id;
 554        struct ethoc *priv = netdev_priv(dev);
 555        u32 pending;
 556        u32 mask;
 557
 558        /* Figure out what triggered the interrupt...
 559         * The tricky bit here is that the interrupt source bits get
 560         * set in INT_SOURCE for an event regardless of whether that
 561         * event is masked or not.  Thus, in order to figure out what
 562         * triggered the interrupt, we need to remove the sources
 563         * for all events that are currently masked.  This behaviour
 564         * is not particularly well documented but reasonable...
 565         */
 566        mask = ethoc_read(priv, INT_MASK);
 567        pending = ethoc_read(priv, INT_SOURCE);
 568        pending &= mask;
 569
 570        if (unlikely(pending == 0))
 571                return IRQ_NONE;
 572
 573        ethoc_ack_irq(priv, pending);
 574
 575        /* We always handle the dropped packet interrupt */
 576        if (pending & INT_MASK_BUSY) {
 577                dev_err(&dev->dev, "packet dropped\n");
 578                dev->stats.rx_dropped++;
 579        }
 580
 581        /* Handle receive/transmit event by switching to polling */
 582        if (pending & (INT_MASK_TX | INT_MASK_RX)) {
 583                ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 584                napi_schedule(&priv->napi);
 585        }
 586
 587        return IRQ_HANDLED;
 588}
 589
 590static int ethoc_get_mac_address(struct net_device *dev, void *addr)
 591{
 592        struct ethoc *priv = netdev_priv(dev);
 593        u8 *mac = (u8 *)addr;
 594        u32 reg;
 595
 596        reg = ethoc_read(priv, MAC_ADDR0);
 597        mac[2] = (reg >> 24) & 0xff;
 598        mac[3] = (reg >> 16) & 0xff;
 599        mac[4] = (reg >>  8) & 0xff;
 600        mac[5] = (reg >>  0) & 0xff;
 601
 602        reg = ethoc_read(priv, MAC_ADDR1);
 603        mac[0] = (reg >>  8) & 0xff;
 604        mac[1] = (reg >>  0) & 0xff;
 605
 606        return 0;
 607}
 608
 609static int ethoc_poll(struct napi_struct *napi, int budget)
 610{
 611        struct ethoc *priv = container_of(napi, struct ethoc, napi);
 612        int rx_work_done = 0;
 613        int tx_work_done = 0;
 614
 615        rx_work_done = ethoc_rx(priv->netdev, budget);
 616        tx_work_done = ethoc_tx(priv->netdev, budget);
 617
 618        if (rx_work_done < budget && tx_work_done < budget) {
 619                napi_complete(napi);
 620                ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 621        }
 622
 623        return rx_work_done;
 624}
 625
 626static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
 627{
 628        struct ethoc *priv = bus->priv;
 629        int i;
 630
 631        ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
 632        ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
 633
 634        for (i = 0; i < 5; i++) {
 635                u32 status = ethoc_read(priv, MIISTATUS);
 636                if (!(status & MIISTATUS_BUSY)) {
 637                        u32 data = ethoc_read(priv, MIIRX_DATA);
 638                        /* reset MII command register */
 639                        ethoc_write(priv, MIICOMMAND, 0);
 640                        return data;
 641                }
 642                usleep_range(100, 200);
 643        }
 644
 645        return -EBUSY;
 646}
 647
 648static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
 649{
 650        struct ethoc *priv = bus->priv;
 651        int i;
 652
 653        ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
 654        ethoc_write(priv, MIITX_DATA, val);
 655        ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
 656
 657        for (i = 0; i < 5; i++) {
 658                u32 stat = ethoc_read(priv, MIISTATUS);
 659                if (!(stat & MIISTATUS_BUSY)) {
 660                        /* reset MII command register */
 661                        ethoc_write(priv, MIICOMMAND, 0);
 662                        return 0;
 663                }
 664                usleep_range(100, 200);
 665        }
 666
 667        return -EBUSY;
 668}
 669
 670static void ethoc_mdio_poll(struct net_device *dev)
 671{
 672}
 673
 674static int ethoc_mdio_probe(struct net_device *dev)
 675{
 676        struct ethoc *priv = netdev_priv(dev);
 677        struct phy_device *phy;
 678        int err;
 679
 680        if (priv->phy_id != -1)
 681                phy = mdiobus_get_phy(priv->mdio, priv->phy_id);
 682        else
 683                phy = phy_find_first(priv->mdio);
 684
 685        if (!phy) {
 686                dev_err(&dev->dev, "no PHY found\n");
 687                return -ENXIO;
 688        }
 689
 690        err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
 691                                 PHY_INTERFACE_MODE_GMII);
 692        if (err) {
 693                dev_err(&dev->dev, "could not attach to PHY\n");
 694                return err;
 695        }
 696
 697        priv->phy = phy;
 698        phy->advertising &= ~(ADVERTISED_1000baseT_Full |
 699                              ADVERTISED_1000baseT_Half);
 700        phy->supported &= ~(SUPPORTED_1000baseT_Full |
 701                            SUPPORTED_1000baseT_Half);
 702
 703        return 0;
 704}
 705
 706static int ethoc_open(struct net_device *dev)
 707{
 708        struct ethoc *priv = netdev_priv(dev);
 709        int ret;
 710
 711        ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
 712                        dev->name, dev);
 713        if (ret)
 714                return ret;
 715
 716        ethoc_init_ring(priv, dev->mem_start);
 717        ethoc_reset(priv);
 718
 719        if (netif_queue_stopped(dev)) {
 720                dev_dbg(&dev->dev, " resuming queue\n");
 721                netif_wake_queue(dev);
 722        } else {
 723                dev_dbg(&dev->dev, " starting queue\n");
 724                netif_start_queue(dev);
 725        }
 726
 727        phy_start(priv->phy);
 728        napi_enable(&priv->napi);
 729
 730        if (netif_msg_ifup(priv)) {
 731                dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
 732                                dev->base_addr, dev->mem_start, dev->mem_end);
 733        }
 734
 735        return 0;
 736}
 737
 738static int ethoc_stop(struct net_device *dev)
 739{
 740        struct ethoc *priv = netdev_priv(dev);
 741
 742        napi_disable(&priv->napi);
 743
 744        if (priv->phy)
 745                phy_stop(priv->phy);
 746
 747        ethoc_disable_rx_and_tx(priv);
 748        free_irq(dev->irq, dev);
 749
 750        if (!netif_queue_stopped(dev))
 751                netif_stop_queue(dev);
 752
 753        return 0;
 754}
 755
 756static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 757{
 758        struct ethoc *priv = netdev_priv(dev);
 759        struct mii_ioctl_data *mdio = if_mii(ifr);
 760        struct phy_device *phy = NULL;
 761
 762        if (!netif_running(dev))
 763                return -EINVAL;
 764
 765        if (cmd != SIOCGMIIPHY) {
 766                if (mdio->phy_id >= PHY_MAX_ADDR)
 767                        return -ERANGE;
 768
 769                phy = mdiobus_get_phy(priv->mdio, mdio->phy_id);
 770                if (!phy)
 771                        return -ENODEV;
 772        } else {
 773                phy = priv->phy;
 774        }
 775
 776        return phy_mii_ioctl(phy, ifr, cmd);
 777}
 778
 779static void ethoc_do_set_mac_address(struct net_device *dev)
 780{
 781        struct ethoc *priv = netdev_priv(dev);
 782        unsigned char *mac = dev->dev_addr;
 783
 784        ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
 785                                     (mac[4] <<  8) | (mac[5] <<  0));
 786        ethoc_write(priv, MAC_ADDR1, (mac[0] <<  8) | (mac[1] <<  0));
 787}
 788
 789static int ethoc_set_mac_address(struct net_device *dev, void *p)
 790{
 791        const struct sockaddr *addr = p;
 792
 793        if (!is_valid_ether_addr(addr->sa_data))
 794                return -EADDRNOTAVAIL;
 795        memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 796        ethoc_do_set_mac_address(dev);
 797        return 0;
 798}
 799
 800static void ethoc_set_multicast_list(struct net_device *dev)
 801{
 802        struct ethoc *priv = netdev_priv(dev);
 803        u32 mode = ethoc_read(priv, MODER);
 804        struct netdev_hw_addr *ha;
 805        u32 hash[2] = { 0, 0 };
 806
 807        /* set loopback mode if requested */
 808        if (dev->flags & IFF_LOOPBACK)
 809                mode |=  MODER_LOOP;
 810        else
 811                mode &= ~MODER_LOOP;
 812
 813        /* receive broadcast frames if requested */
 814        if (dev->flags & IFF_BROADCAST)
 815                mode &= ~MODER_BRO;
 816        else
 817                mode |=  MODER_BRO;
 818
 819        /* enable promiscuous mode if requested */
 820        if (dev->flags & IFF_PROMISC)
 821                mode |=  MODER_PRO;
 822        else
 823                mode &= ~MODER_PRO;
 824
 825        ethoc_write(priv, MODER, mode);
 826
 827        /* receive multicast frames */
 828        if (dev->flags & IFF_ALLMULTI) {
 829                hash[0] = 0xffffffff;
 830                hash[1] = 0xffffffff;
 831        } else {
 832                netdev_for_each_mc_addr(ha, dev) {
 833                        u32 crc = ether_crc(ETH_ALEN, ha->addr);
 834                        int bit = (crc >> 26) & 0x3f;
 835                        hash[bit >> 5] |= 1 << (bit & 0x1f);
 836                }
 837        }
 838
 839        ethoc_write(priv, ETH_HASH0, hash[0]);
 840        ethoc_write(priv, ETH_HASH1, hash[1]);
 841}
 842
 843static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
 844{
 845        return -ENOSYS;
 846}
 847
 848static void ethoc_tx_timeout(struct net_device *dev)
 849{
 850        struct ethoc *priv = netdev_priv(dev);
 851        u32 pending = ethoc_read(priv, INT_SOURCE);
 852        if (likely(pending))
 853                ethoc_interrupt(dev->irq, dev);
 854}
 855
 856static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
 857{
 858        struct ethoc *priv = netdev_priv(dev);
 859        struct ethoc_bd bd;
 860        unsigned int entry;
 861        void *dest;
 862
 863        if (skb_put_padto(skb, ETHOC_ZLEN)) {
 864                dev->stats.tx_errors++;
 865                goto out_no_free;
 866        }
 867
 868        if (unlikely(skb->len > ETHOC_BUFSIZ)) {
 869                dev->stats.tx_errors++;
 870                goto out;
 871        }
 872
 873        entry = priv->cur_tx % priv->num_tx;
 874        spin_lock_irq(&priv->lock);
 875        priv->cur_tx++;
 876
 877        ethoc_read_bd(priv, entry, &bd);
 878        if (unlikely(skb->len < ETHOC_ZLEN))
 879                bd.stat |=  TX_BD_PAD;
 880        else
 881                bd.stat &= ~TX_BD_PAD;
 882
 883        dest = priv->vma[entry];
 884        memcpy_toio(dest, skb->data, skb->len);
 885
 886        bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
 887        bd.stat |= TX_BD_LEN(skb->len);
 888        ethoc_write_bd(priv, entry, &bd);
 889
 890        bd.stat |= TX_BD_READY;
 891        ethoc_write_bd(priv, entry, &bd);
 892
 893        if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
 894                dev_dbg(&dev->dev, "stopping queue\n");
 895                netif_stop_queue(dev);
 896        }
 897
 898        spin_unlock_irq(&priv->lock);
 899        skb_tx_timestamp(skb);
 900out:
 901        dev_kfree_skb(skb);
 902out_no_free:
 903        return NETDEV_TX_OK;
 904}
 905
 906static int ethoc_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 907{
 908        struct ethoc *priv = netdev_priv(dev);
 909        struct phy_device *phydev = priv->phy;
 910
 911        if (!phydev)
 912                return -EOPNOTSUPP;
 913
 914        return phy_ethtool_gset(phydev, cmd);
 915}
 916
 917static int ethoc_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 918{
 919        struct ethoc *priv = netdev_priv(dev);
 920        struct phy_device *phydev = priv->phy;
 921
 922        if (!phydev)
 923                return -EOPNOTSUPP;
 924
 925        return phy_ethtool_sset(phydev, cmd);
 926}
 927
 928static int ethoc_get_regs_len(struct net_device *netdev)
 929{
 930        return ETH_END;
 931}
 932
 933static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 934                           void *p)
 935{
 936        struct ethoc *priv = netdev_priv(dev);
 937        u32 *regs_buff = p;
 938        unsigned i;
 939
 940        regs->version = 0;
 941        for (i = 0; i < ETH_END / sizeof(u32); ++i)
 942                regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
 943}
 944
 945static void ethoc_get_ringparam(struct net_device *dev,
 946                                struct ethtool_ringparam *ring)
 947{
 948        struct ethoc *priv = netdev_priv(dev);
 949
 950        ring->rx_max_pending = priv->num_bd - 1;
 951        ring->rx_mini_max_pending = 0;
 952        ring->rx_jumbo_max_pending = 0;
 953        ring->tx_max_pending = priv->num_bd - 1;
 954
 955        ring->rx_pending = priv->num_rx;
 956        ring->rx_mini_pending = 0;
 957        ring->rx_jumbo_pending = 0;
 958        ring->tx_pending = priv->num_tx;
 959}
 960
 961static int ethoc_set_ringparam(struct net_device *dev,
 962                               struct ethtool_ringparam *ring)
 963{
 964        struct ethoc *priv = netdev_priv(dev);
 965
 966        if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
 967            ring->tx_pending + ring->rx_pending > priv->num_bd)
 968                return -EINVAL;
 969        if (ring->rx_mini_pending || ring->rx_jumbo_pending)
 970                return -EINVAL;
 971
 972        if (netif_running(dev)) {
 973                netif_tx_disable(dev);
 974                ethoc_disable_rx_and_tx(priv);
 975                ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 976                synchronize_irq(dev->irq);
 977        }
 978
 979        priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
 980        priv->num_rx = ring->rx_pending;
 981        ethoc_init_ring(priv, dev->mem_start);
 982
 983        if (netif_running(dev)) {
 984                ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 985                ethoc_enable_rx_and_tx(priv);
 986                netif_wake_queue(dev);
 987        }
 988        return 0;
 989}
 990
 991const struct ethtool_ops ethoc_ethtool_ops = {
 992        .get_settings = ethoc_get_settings,
 993        .set_settings = ethoc_set_settings,
 994        .get_regs_len = ethoc_get_regs_len,
 995        .get_regs = ethoc_get_regs,
 996        .get_link = ethtool_op_get_link,
 997        .get_ringparam = ethoc_get_ringparam,
 998        .set_ringparam = ethoc_set_ringparam,
 999        .get_ts_info = ethtool_op_get_ts_info,
1000};
1001
1002static const struct net_device_ops ethoc_netdev_ops = {
1003        .ndo_open = ethoc_open,
1004        .ndo_stop = ethoc_stop,
1005        .ndo_do_ioctl = ethoc_ioctl,
1006        .ndo_set_mac_address = ethoc_set_mac_address,
1007        .ndo_set_rx_mode = ethoc_set_multicast_list,
1008        .ndo_change_mtu = ethoc_change_mtu,
1009        .ndo_tx_timeout = ethoc_tx_timeout,
1010        .ndo_start_xmit = ethoc_start_xmit,
1011};
1012
1013/**
1014 * ethoc_probe - initialize OpenCores ethernet MAC
1015 * pdev:        platform device
1016 */
1017static int ethoc_probe(struct platform_device *pdev)
1018{
1019        struct net_device *netdev = NULL;
1020        struct resource *res = NULL;
1021        struct resource *mmio = NULL;
1022        struct resource *mem = NULL;
1023        struct ethoc *priv = NULL;
1024        int num_bd;
1025        int ret = 0;
1026        bool random_mac = false;
1027        struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1028        u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
1029
1030        /* allocate networking device */
1031        netdev = alloc_etherdev(sizeof(struct ethoc));
1032        if (!netdev) {
1033                ret = -ENOMEM;
1034                goto out;
1035        }
1036
1037        SET_NETDEV_DEV(netdev, &pdev->dev);
1038        platform_set_drvdata(pdev, netdev);
1039
1040        /* obtain I/O memory space */
1041        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1042        if (!res) {
1043                dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
1044                ret = -ENXIO;
1045                goto free;
1046        }
1047
1048        mmio = devm_request_mem_region(&pdev->dev, res->start,
1049                        resource_size(res), res->name);
1050        if (!mmio) {
1051                dev_err(&pdev->dev, "cannot request I/O memory space\n");
1052                ret = -ENXIO;
1053                goto free;
1054        }
1055
1056        netdev->base_addr = mmio->start;
1057
1058        /* obtain buffer memory space */
1059        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1060        if (res) {
1061                mem = devm_request_mem_region(&pdev->dev, res->start,
1062                        resource_size(res), res->name);
1063                if (!mem) {
1064                        dev_err(&pdev->dev, "cannot request memory space\n");
1065                        ret = -ENXIO;
1066                        goto free;
1067                }
1068
1069                netdev->mem_start = mem->start;
1070                netdev->mem_end   = mem->end;
1071        }
1072
1073
1074        /* obtain device IRQ number */
1075        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1076        if (!res) {
1077                dev_err(&pdev->dev, "cannot obtain IRQ\n");
1078                ret = -ENXIO;
1079                goto free;
1080        }
1081
1082        netdev->irq = res->start;
1083
1084        /* setup driver-private data */
1085        priv = netdev_priv(netdev);
1086        priv->netdev = netdev;
1087        priv->dma_alloc = 0;
1088        priv->io_region_size = resource_size(mmio);
1089
1090        priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
1091                        resource_size(mmio));
1092        if (!priv->iobase) {
1093                dev_err(&pdev->dev, "cannot remap I/O memory space\n");
1094                ret = -ENXIO;
1095                goto free;
1096        }
1097
1098        if (netdev->mem_end) {
1099                priv->membase = devm_ioremap_nocache(&pdev->dev,
1100                        netdev->mem_start, resource_size(mem));
1101                if (!priv->membase) {
1102                        dev_err(&pdev->dev, "cannot remap memory space\n");
1103                        ret = -ENXIO;
1104                        goto free;
1105                }
1106        } else {
1107                /* Allocate buffer memory */
1108                priv->membase = dmam_alloc_coherent(&pdev->dev,
1109                        buffer_size, (void *)&netdev->mem_start,
1110                        GFP_KERNEL);
1111                if (!priv->membase) {
1112                        dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
1113                                buffer_size);
1114                        ret = -ENOMEM;
1115                        goto free;
1116                }
1117                netdev->mem_end = netdev->mem_start + buffer_size;
1118                priv->dma_alloc = buffer_size;
1119        }
1120
1121        priv->big_endian = pdata ? pdata->big_endian :
1122                of_device_is_big_endian(pdev->dev.of_node);
1123
1124        /* calculate the number of TX/RX buffers, maximum 128 supported */
1125        num_bd = min_t(unsigned int,
1126                128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
1127        if (num_bd < 4) {
1128                ret = -ENODEV;
1129                goto free;
1130        }
1131        priv->num_bd = num_bd;
1132        /* num_tx must be a power of two */
1133        priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
1134        priv->num_rx = num_bd - priv->num_tx;
1135
1136        dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
1137                priv->num_tx, priv->num_rx);
1138
1139        priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
1140        if (!priv->vma) {
1141                ret = -ENOMEM;
1142                goto free;
1143        }
1144
1145        /* Allow the platform setup code to pass in a MAC address. */
1146        if (pdata) {
1147                memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
1148                priv->phy_id = pdata->phy_id;
1149        } else {
1150                const uint8_t *mac;
1151
1152                mac = of_get_property(pdev->dev.of_node,
1153                                      "local-mac-address",
1154                                      NULL);
1155                if (mac)
1156                        memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
1157                priv->phy_id = -1;
1158        }
1159
1160        /* Check that the given MAC address is valid. If it isn't, read the
1161         * current MAC from the controller.
1162         */
1163        if (!is_valid_ether_addr(netdev->dev_addr))
1164                ethoc_get_mac_address(netdev, netdev->dev_addr);
1165
1166        /* Check the MAC again for validity, if it still isn't choose and
1167         * program a random one.
1168         */
1169        if (!is_valid_ether_addr(netdev->dev_addr)) {
1170                eth_random_addr(netdev->dev_addr);
1171                random_mac = true;
1172        }
1173
1174        ethoc_do_set_mac_address(netdev);
1175
1176        if (random_mac)
1177                netdev->addr_assign_type = NET_ADDR_RANDOM;
1178
1179        /* Allow the platform setup code to adjust MII management bus clock. */
1180        if (!eth_clkfreq) {
1181                struct clk *clk = devm_clk_get(&pdev->dev, NULL);
1182
1183                if (!IS_ERR(clk)) {
1184                        priv->clk = clk;
1185                        clk_prepare_enable(clk);
1186                        eth_clkfreq = clk_get_rate(clk);
1187                }
1188        }
1189        if (eth_clkfreq) {
1190                u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
1191
1192                if (!clkdiv)
1193                        clkdiv = 2;
1194                dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
1195                ethoc_write(priv, MIIMODER,
1196                            (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
1197                            clkdiv);
1198        }
1199
1200        /* register MII bus */
1201        priv->mdio = mdiobus_alloc();
1202        if (!priv->mdio) {
1203                ret = -ENOMEM;
1204                goto free2;
1205        }
1206
1207        priv->mdio->name = "ethoc-mdio";
1208        snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1209                        priv->mdio->name, pdev->id);
1210        priv->mdio->read = ethoc_mdio_read;
1211        priv->mdio->write = ethoc_mdio_write;
1212        priv->mdio->priv = priv;
1213
1214        ret = mdiobus_register(priv->mdio);
1215        if (ret) {
1216                dev_err(&netdev->dev, "failed to register MDIO bus\n");
1217                goto free2;
1218        }
1219
1220        ret = ethoc_mdio_probe(netdev);
1221        if (ret) {
1222                dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1223                goto error;
1224        }
1225
1226        /* setup the net_device structure */
1227        netdev->netdev_ops = &ethoc_netdev_ops;
1228        netdev->watchdog_timeo = ETHOC_TIMEOUT;
1229        netdev->features |= 0;
1230        netdev->ethtool_ops = &ethoc_ethtool_ops;
1231
1232        /* setup NAPI */
1233        netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1234
1235        spin_lock_init(&priv->lock);
1236
1237        ret = register_netdev(netdev);
1238        if (ret < 0) {
1239                dev_err(&netdev->dev, "failed to register interface\n");
1240                goto error2;
1241        }
1242
1243        goto out;
1244
1245error2:
1246        netif_napi_del(&priv->napi);
1247error:
1248        mdiobus_unregister(priv->mdio);
1249        mdiobus_free(priv->mdio);
1250free2:
1251        if (priv->clk)
1252                clk_disable_unprepare(priv->clk);
1253free:
1254        free_netdev(netdev);
1255out:
1256        return ret;
1257}
1258
1259/**
1260 * ethoc_remove - shutdown OpenCores ethernet MAC
1261 * @pdev:       platform device
1262 */
1263static int ethoc_remove(struct platform_device *pdev)
1264{
1265        struct net_device *netdev = platform_get_drvdata(pdev);
1266        struct ethoc *priv = netdev_priv(netdev);
1267
1268        if (netdev) {
1269                netif_napi_del(&priv->napi);
1270                phy_disconnect(priv->phy);
1271                priv->phy = NULL;
1272
1273                if (priv->mdio) {
1274                        mdiobus_unregister(priv->mdio);
1275                        mdiobus_free(priv->mdio);
1276                }
1277                if (priv->clk)
1278                        clk_disable_unprepare(priv->clk);
1279                unregister_netdev(netdev);
1280                free_netdev(netdev);
1281        }
1282
1283        return 0;
1284}
1285
1286#ifdef CONFIG_PM
1287static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1288{
1289        return -ENOSYS;
1290}
1291
1292static int ethoc_resume(struct platform_device *pdev)
1293{
1294        return -ENOSYS;
1295}
1296#else
1297# define ethoc_suspend NULL
1298# define ethoc_resume  NULL
1299#endif
1300
1301static const struct of_device_id ethoc_match[] = {
1302        { .compatible = "opencores,ethoc", },
1303        {},
1304};
1305MODULE_DEVICE_TABLE(of, ethoc_match);
1306
1307static struct platform_driver ethoc_driver = {
1308        .probe   = ethoc_probe,
1309        .remove  = ethoc_remove,
1310        .suspend = ethoc_suspend,
1311        .resume  = ethoc_resume,
1312        .driver  = {
1313                .name = "ethoc",
1314                .of_match_table = ethoc_match,
1315        },
1316};
1317
1318module_platform_driver(ethoc_driver);
1319
1320MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1321MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1322MODULE_LICENSE("GPL v2");
1323
1324
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