linux/drivers/net/ethernet/ethoc.c
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   1/*
   2 * linux/drivers/net/ethernet/ethoc.c
   3 *
   4 * Copyright (C) 2007-2008 Avionic Design Development GmbH
   5 * Copyright (C) 2008-2009 Avionic Design GmbH
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 *
  11 * Written by Thierry Reding <thierry.reding@avionic-design.de>
  12 */
  13
  14#include <linux/dma-mapping.h>
  15#include <linux/etherdevice.h>
  16#include <linux/clk.h>
  17#include <linux/crc32.h>
  18#include <linux/interrupt.h>
  19#include <linux/io.h>
  20#include <linux/mii.h>
  21#include <linux/phy.h>
  22#include <linux/platform_device.h>
  23#include <linux/sched.h>
  24#include <linux/slab.h>
  25#include <linux/of.h>
  26#include <linux/module.h>
  27#include <net/ethoc.h>
  28
  29static int buffer_size = 0x8000; /* 32 KBytes */
  30module_param(buffer_size, int, 0);
  31MODULE_PARM_DESC(buffer_size, "DMA buffer allocation size");
  32
  33/* register offsets */
  34#define MODER           0x00
  35#define INT_SOURCE      0x04
  36#define INT_MASK        0x08
  37#define IPGT            0x0c
  38#define IPGR1           0x10
  39#define IPGR2           0x14
  40#define PACKETLEN       0x18
  41#define COLLCONF        0x1c
  42#define TX_BD_NUM       0x20
  43#define CTRLMODER       0x24
  44#define MIIMODER        0x28
  45#define MIICOMMAND      0x2c
  46#define MIIADDRESS      0x30
  47#define MIITX_DATA      0x34
  48#define MIIRX_DATA      0x38
  49#define MIISTATUS       0x3c
  50#define MAC_ADDR0       0x40
  51#define MAC_ADDR1       0x44
  52#define ETH_HASH0       0x48
  53#define ETH_HASH1       0x4c
  54#define ETH_TXCTRL      0x50
  55#define ETH_END         0x54
  56
  57/* mode register */
  58#define MODER_RXEN      (1 <<  0) /* receive enable */
  59#define MODER_TXEN      (1 <<  1) /* transmit enable */
  60#define MODER_NOPRE     (1 <<  2) /* no preamble */
  61#define MODER_BRO       (1 <<  3) /* broadcast address */
  62#define MODER_IAM       (1 <<  4) /* individual address mode */
  63#define MODER_PRO       (1 <<  5) /* promiscuous mode */
  64#define MODER_IFG       (1 <<  6) /* interframe gap for incoming frames */
  65#define MODER_LOOP      (1 <<  7) /* loopback */
  66#define MODER_NBO       (1 <<  8) /* no back-off */
  67#define MODER_EDE       (1 <<  9) /* excess defer enable */
  68#define MODER_FULLD     (1 << 10) /* full duplex */
  69#define MODER_RESET     (1 << 11) /* FIXME: reset (undocumented) */
  70#define MODER_DCRC      (1 << 12) /* delayed CRC enable */
  71#define MODER_CRC       (1 << 13) /* CRC enable */
  72#define MODER_HUGE      (1 << 14) /* huge packets enable */
  73#define MODER_PAD       (1 << 15) /* padding enabled */
  74#define MODER_RSM       (1 << 16) /* receive small packets */
  75
  76/* interrupt source and mask registers */
  77#define INT_MASK_TXF    (1 << 0) /* transmit frame */
  78#define INT_MASK_TXE    (1 << 1) /* transmit error */
  79#define INT_MASK_RXF    (1 << 2) /* receive frame */
  80#define INT_MASK_RXE    (1 << 3) /* receive error */
  81#define INT_MASK_BUSY   (1 << 4)
  82#define INT_MASK_TXC    (1 << 5) /* transmit control frame */
  83#define INT_MASK_RXC    (1 << 6) /* receive control frame */
  84
  85#define INT_MASK_TX     (INT_MASK_TXF | INT_MASK_TXE)
  86#define INT_MASK_RX     (INT_MASK_RXF | INT_MASK_RXE)
  87
  88#define INT_MASK_ALL ( \
  89                INT_MASK_TXF | INT_MASK_TXE | \
  90                INT_MASK_RXF | INT_MASK_RXE | \
  91                INT_MASK_TXC | INT_MASK_RXC | \
  92                INT_MASK_BUSY \
  93        )
  94
  95/* packet length register */
  96#define PACKETLEN_MIN(min)              (((min) & 0xffff) << 16)
  97#define PACKETLEN_MAX(max)              (((max) & 0xffff) <<  0)
  98#define PACKETLEN_MIN_MAX(min, max)     (PACKETLEN_MIN(min) | \
  99                                        PACKETLEN_MAX(max))
 100
 101/* transmit buffer number register */
 102#define TX_BD_NUM_VAL(x)        (((x) <= 0x80) ? (x) : 0x80)
 103
 104/* control module mode register */
 105#define CTRLMODER_PASSALL       (1 << 0) /* pass all receive frames */
 106#define CTRLMODER_RXFLOW        (1 << 1) /* receive control flow */
 107#define CTRLMODER_TXFLOW        (1 << 2) /* transmit control flow */
 108
 109/* MII mode register */
 110#define MIIMODER_CLKDIV(x)      ((x) & 0xfe) /* needs to be an even number */
 111#define MIIMODER_NOPRE          (1 << 8) /* no preamble */
 112
 113/* MII command register */
 114#define MIICOMMAND_SCAN         (1 << 0) /* scan status */
 115#define MIICOMMAND_READ         (1 << 1) /* read status */
 116#define MIICOMMAND_WRITE        (1 << 2) /* write control data */
 117
 118/* MII address register */
 119#define MIIADDRESS_FIAD(x)              (((x) & 0x1f) << 0)
 120#define MIIADDRESS_RGAD(x)              (((x) & 0x1f) << 8)
 121#define MIIADDRESS_ADDR(phy, reg)       (MIIADDRESS_FIAD(phy) | \
 122                                        MIIADDRESS_RGAD(reg))
 123
 124/* MII transmit data register */
 125#define MIITX_DATA_VAL(x)       ((x) & 0xffff)
 126
 127/* MII receive data register */
 128#define MIIRX_DATA_VAL(x)       ((x) & 0xffff)
 129
 130/* MII status register */
 131#define MIISTATUS_LINKFAIL      (1 << 0)
 132#define MIISTATUS_BUSY          (1 << 1)
 133#define MIISTATUS_INVALID       (1 << 2)
 134
 135/* TX buffer descriptor */
 136#define TX_BD_CS                (1 <<  0) /* carrier sense lost */
 137#define TX_BD_DF                (1 <<  1) /* defer indication */
 138#define TX_BD_LC                (1 <<  2) /* late collision */
 139#define TX_BD_RL                (1 <<  3) /* retransmission limit */
 140#define TX_BD_RETRY_MASK        (0x00f0)
 141#define TX_BD_RETRY(x)          (((x) & 0x00f0) >>  4)
 142#define TX_BD_UR                (1 <<  8) /* transmitter underrun */
 143#define TX_BD_CRC               (1 << 11) /* TX CRC enable */
 144#define TX_BD_PAD               (1 << 12) /* pad enable for short packets */
 145#define TX_BD_WRAP              (1 << 13)
 146#define TX_BD_IRQ               (1 << 14) /* interrupt request enable */
 147#define TX_BD_READY             (1 << 15) /* TX buffer ready */
 148#define TX_BD_LEN(x)            (((x) & 0xffff) << 16)
 149#define TX_BD_LEN_MASK          (0xffff << 16)
 150
 151#define TX_BD_STATS             (TX_BD_CS | TX_BD_DF | TX_BD_LC | \
 152                                TX_BD_RL | TX_BD_RETRY_MASK | TX_BD_UR)
 153
 154/* RX buffer descriptor */
 155#define RX_BD_LC        (1 <<  0) /* late collision */
 156#define RX_BD_CRC       (1 <<  1) /* RX CRC error */
 157#define RX_BD_SF        (1 <<  2) /* short frame */
 158#define RX_BD_TL        (1 <<  3) /* too long */
 159#define RX_BD_DN        (1 <<  4) /* dribble nibble */
 160#define RX_BD_IS        (1 <<  5) /* invalid symbol */
 161#define RX_BD_OR        (1 <<  6) /* receiver overrun */
 162#define RX_BD_MISS      (1 <<  7)
 163#define RX_BD_CF        (1 <<  8) /* control frame */
 164#define RX_BD_WRAP      (1 << 13)
 165#define RX_BD_IRQ       (1 << 14) /* interrupt request enable */
 166#define RX_BD_EMPTY     (1 << 15)
 167#define RX_BD_LEN(x)    (((x) & 0xffff) << 16)
 168
 169#define RX_BD_STATS     (RX_BD_LC | RX_BD_CRC | RX_BD_SF | RX_BD_TL | \
 170                        RX_BD_DN | RX_BD_IS | RX_BD_OR | RX_BD_MISS)
 171
 172#define ETHOC_BUFSIZ            1536
 173#define ETHOC_ZLEN              64
 174#define ETHOC_BD_BASE           0x400
 175#define ETHOC_TIMEOUT           (HZ / 2)
 176#define ETHOC_MII_TIMEOUT       (1 + (HZ / 5))
 177
 178/**
 179 * struct ethoc - driver-private device structure
 180 * @iobase:     pointer to I/O memory region
 181 * @membase:    pointer to buffer memory region
 182 * @dma_alloc:  dma allocated buffer size
 183 * @io_region_size:     I/O memory region size
 184 * @num_bd:     number of buffer descriptors
 185 * @num_tx:     number of send buffers
 186 * @cur_tx:     last send buffer written
 187 * @dty_tx:     last buffer actually sent
 188 * @num_rx:     number of receive buffers
 189 * @cur_rx:     current receive buffer
 190 * @vma:        pointer to array of virtual memory addresses for buffers
 191 * @netdev:     pointer to network device structure
 192 * @napi:       NAPI structure
 193 * @msg_enable: device state flags
 194 * @lock:       device lock
 195 * @phy:        attached PHY
 196 * @mdio:       MDIO bus for PHY access
 197 * @phy_id:     address of attached PHY
 198 */
 199struct ethoc {
 200        void __iomem *iobase;
 201        void __iomem *membase;
 202        int dma_alloc;
 203        resource_size_t io_region_size;
 204
 205        unsigned int num_bd;
 206        unsigned int num_tx;
 207        unsigned int cur_tx;
 208        unsigned int dty_tx;
 209
 210        unsigned int num_rx;
 211        unsigned int cur_rx;
 212
 213        void **vma;
 214
 215        struct net_device *netdev;
 216        struct napi_struct napi;
 217        u32 msg_enable;
 218
 219        spinlock_t lock;
 220
 221        struct phy_device *phy;
 222        struct mii_bus *mdio;
 223        struct clk *clk;
 224        s8 phy_id;
 225};
 226
 227/**
 228 * struct ethoc_bd - buffer descriptor
 229 * @stat:       buffer statistics
 230 * @addr:       physical memory address
 231 */
 232struct ethoc_bd {
 233        u32 stat;
 234        u32 addr;
 235};
 236
 237static inline u32 ethoc_read(struct ethoc *dev, loff_t offset)
 238{
 239        return ioread32(dev->iobase + offset);
 240}
 241
 242static inline void ethoc_write(struct ethoc *dev, loff_t offset, u32 data)
 243{
 244        iowrite32(data, dev->iobase + offset);
 245}
 246
 247static inline void ethoc_read_bd(struct ethoc *dev, int index,
 248                struct ethoc_bd *bd)
 249{
 250        loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 251        bd->stat = ethoc_read(dev, offset + 0);
 252        bd->addr = ethoc_read(dev, offset + 4);
 253}
 254
 255static inline void ethoc_write_bd(struct ethoc *dev, int index,
 256                const struct ethoc_bd *bd)
 257{
 258        loff_t offset = ETHOC_BD_BASE + (index * sizeof(struct ethoc_bd));
 259        ethoc_write(dev, offset + 0, bd->stat);
 260        ethoc_write(dev, offset + 4, bd->addr);
 261}
 262
 263static inline void ethoc_enable_irq(struct ethoc *dev, u32 mask)
 264{
 265        u32 imask = ethoc_read(dev, INT_MASK);
 266        imask |= mask;
 267        ethoc_write(dev, INT_MASK, imask);
 268}
 269
 270static inline void ethoc_disable_irq(struct ethoc *dev, u32 mask)
 271{
 272        u32 imask = ethoc_read(dev, INT_MASK);
 273        imask &= ~mask;
 274        ethoc_write(dev, INT_MASK, imask);
 275}
 276
 277static inline void ethoc_ack_irq(struct ethoc *dev, u32 mask)
 278{
 279        ethoc_write(dev, INT_SOURCE, mask);
 280}
 281
 282static inline void ethoc_enable_rx_and_tx(struct ethoc *dev)
 283{
 284        u32 mode = ethoc_read(dev, MODER);
 285        mode |= MODER_RXEN | MODER_TXEN;
 286        ethoc_write(dev, MODER, mode);
 287}
 288
 289static inline void ethoc_disable_rx_and_tx(struct ethoc *dev)
 290{
 291        u32 mode = ethoc_read(dev, MODER);
 292        mode &= ~(MODER_RXEN | MODER_TXEN);
 293        ethoc_write(dev, MODER, mode);
 294}
 295
 296static int ethoc_init_ring(struct ethoc *dev, unsigned long mem_start)
 297{
 298        struct ethoc_bd bd;
 299        int i;
 300        void *vma;
 301
 302        dev->cur_tx = 0;
 303        dev->dty_tx = 0;
 304        dev->cur_rx = 0;
 305
 306        ethoc_write(dev, TX_BD_NUM, dev->num_tx);
 307
 308        /* setup transmission buffers */
 309        bd.addr = mem_start;
 310        bd.stat = TX_BD_IRQ | TX_BD_CRC;
 311        vma = dev->membase;
 312
 313        for (i = 0; i < dev->num_tx; i++) {
 314                if (i == dev->num_tx - 1)
 315                        bd.stat |= TX_BD_WRAP;
 316
 317                ethoc_write_bd(dev, i, &bd);
 318                bd.addr += ETHOC_BUFSIZ;
 319
 320                dev->vma[i] = vma;
 321                vma += ETHOC_BUFSIZ;
 322        }
 323
 324        bd.stat = RX_BD_EMPTY | RX_BD_IRQ;
 325
 326        for (i = 0; i < dev->num_rx; i++) {
 327                if (i == dev->num_rx - 1)
 328                        bd.stat |= RX_BD_WRAP;
 329
 330                ethoc_write_bd(dev, dev->num_tx + i, &bd);
 331                bd.addr += ETHOC_BUFSIZ;
 332
 333                dev->vma[dev->num_tx + i] = vma;
 334                vma += ETHOC_BUFSIZ;
 335        }
 336
 337        return 0;
 338}
 339
 340static int ethoc_reset(struct ethoc *dev)
 341{
 342        u32 mode;
 343
 344        /* TODO: reset controller? */
 345
 346        ethoc_disable_rx_and_tx(dev);
 347
 348        /* TODO: setup registers */
 349
 350        /* enable FCS generation and automatic padding */
 351        mode = ethoc_read(dev, MODER);
 352        mode |= MODER_CRC | MODER_PAD;
 353        ethoc_write(dev, MODER, mode);
 354
 355        /* set full-duplex mode */
 356        mode = ethoc_read(dev, MODER);
 357        mode |= MODER_FULLD;
 358        ethoc_write(dev, MODER, mode);
 359        ethoc_write(dev, IPGT, 0x15);
 360
 361        ethoc_ack_irq(dev, INT_MASK_ALL);
 362        ethoc_enable_irq(dev, INT_MASK_ALL);
 363        ethoc_enable_rx_and_tx(dev);
 364        return 0;
 365}
 366
 367static unsigned int ethoc_update_rx_stats(struct ethoc *dev,
 368                struct ethoc_bd *bd)
 369{
 370        struct net_device *netdev = dev->netdev;
 371        unsigned int ret = 0;
 372
 373        if (bd->stat & RX_BD_TL) {
 374                dev_err(&netdev->dev, "RX: frame too long\n");
 375                netdev->stats.rx_length_errors++;
 376                ret++;
 377        }
 378
 379        if (bd->stat & RX_BD_SF) {
 380                dev_err(&netdev->dev, "RX: frame too short\n");
 381                netdev->stats.rx_length_errors++;
 382                ret++;
 383        }
 384
 385        if (bd->stat & RX_BD_DN) {
 386                dev_err(&netdev->dev, "RX: dribble nibble\n");
 387                netdev->stats.rx_frame_errors++;
 388        }
 389
 390        if (bd->stat & RX_BD_CRC) {
 391                dev_err(&netdev->dev, "RX: wrong CRC\n");
 392                netdev->stats.rx_crc_errors++;
 393                ret++;
 394        }
 395
 396        if (bd->stat & RX_BD_OR) {
 397                dev_err(&netdev->dev, "RX: overrun\n");
 398                netdev->stats.rx_over_errors++;
 399                ret++;
 400        }
 401
 402        if (bd->stat & RX_BD_MISS)
 403                netdev->stats.rx_missed_errors++;
 404
 405        if (bd->stat & RX_BD_LC) {
 406                dev_err(&netdev->dev, "RX: late collision\n");
 407                netdev->stats.collisions++;
 408                ret++;
 409        }
 410
 411        return ret;
 412}
 413
 414static int ethoc_rx(struct net_device *dev, int limit)
 415{
 416        struct ethoc *priv = netdev_priv(dev);
 417        int count;
 418
 419        for (count = 0; count < limit; ++count) {
 420                unsigned int entry;
 421                struct ethoc_bd bd;
 422
 423                entry = priv->num_tx + priv->cur_rx;
 424                ethoc_read_bd(priv, entry, &bd);
 425                if (bd.stat & RX_BD_EMPTY) {
 426                        ethoc_ack_irq(priv, INT_MASK_RX);
 427                        /* If packet (interrupt) came in between checking
 428                         * BD_EMTPY and clearing the interrupt source, then we
 429                         * risk missing the packet as the RX interrupt won't
 430                         * trigger right away when we reenable it; hence, check
 431                         * BD_EMTPY here again to make sure there isn't such a
 432                         * packet waiting for us...
 433                         */
 434                        ethoc_read_bd(priv, entry, &bd);
 435                        if (bd.stat & RX_BD_EMPTY)
 436                                break;
 437                }
 438
 439                if (ethoc_update_rx_stats(priv, &bd) == 0) {
 440                        int size = bd.stat >> 16;
 441                        struct sk_buff *skb;
 442
 443                        size -= 4; /* strip the CRC */
 444                        skb = netdev_alloc_skb_ip_align(dev, size);
 445
 446                        if (likely(skb)) {
 447                                void *src = priv->vma[entry];
 448                                memcpy_fromio(skb_put(skb, size), src, size);
 449                                skb->protocol = eth_type_trans(skb, dev);
 450                                dev->stats.rx_packets++;
 451                                dev->stats.rx_bytes += size;
 452                                netif_receive_skb(skb);
 453                        } else {
 454                                if (net_ratelimit())
 455                                        dev_warn(&dev->dev,
 456                                            "low on memory - packet dropped\n");
 457
 458                                dev->stats.rx_dropped++;
 459                                break;
 460                        }
 461                }
 462
 463                /* clear the buffer descriptor so it can be reused */
 464                bd.stat &= ~RX_BD_STATS;
 465                bd.stat |=  RX_BD_EMPTY;
 466                ethoc_write_bd(priv, entry, &bd);
 467                if (++priv->cur_rx == priv->num_rx)
 468                        priv->cur_rx = 0;
 469        }
 470
 471        return count;
 472}
 473
 474static void ethoc_update_tx_stats(struct ethoc *dev, struct ethoc_bd *bd)
 475{
 476        struct net_device *netdev = dev->netdev;
 477
 478        if (bd->stat & TX_BD_LC) {
 479                dev_err(&netdev->dev, "TX: late collision\n");
 480                netdev->stats.tx_window_errors++;
 481        }
 482
 483        if (bd->stat & TX_BD_RL) {
 484                dev_err(&netdev->dev, "TX: retransmit limit\n");
 485                netdev->stats.tx_aborted_errors++;
 486        }
 487
 488        if (bd->stat & TX_BD_UR) {
 489                dev_err(&netdev->dev, "TX: underrun\n");
 490                netdev->stats.tx_fifo_errors++;
 491        }
 492
 493        if (bd->stat & TX_BD_CS) {
 494                dev_err(&netdev->dev, "TX: carrier sense lost\n");
 495                netdev->stats.tx_carrier_errors++;
 496        }
 497
 498        if (bd->stat & TX_BD_STATS)
 499                netdev->stats.tx_errors++;
 500
 501        netdev->stats.collisions += (bd->stat >> 4) & 0xf;
 502        netdev->stats.tx_bytes += bd->stat >> 16;
 503        netdev->stats.tx_packets++;
 504}
 505
 506static int ethoc_tx(struct net_device *dev, int limit)
 507{
 508        struct ethoc *priv = netdev_priv(dev);
 509        int count;
 510        struct ethoc_bd bd;
 511
 512        for (count = 0; count < limit; ++count) {
 513                unsigned int entry;
 514
 515                entry = priv->dty_tx & (priv->num_tx-1);
 516
 517                ethoc_read_bd(priv, entry, &bd);
 518
 519                if (bd.stat & TX_BD_READY || (priv->dty_tx == priv->cur_tx)) {
 520                        ethoc_ack_irq(priv, INT_MASK_TX);
 521                        /* If interrupt came in between reading in the BD
 522                         * and clearing the interrupt source, then we risk
 523                         * missing the event as the TX interrupt won't trigger
 524                         * right away when we reenable it; hence, check
 525                         * BD_EMPTY here again to make sure there isn't such an
 526                         * event pending...
 527                         */
 528                        ethoc_read_bd(priv, entry, &bd);
 529                        if (bd.stat & TX_BD_READY ||
 530                            (priv->dty_tx == priv->cur_tx))
 531                                break;
 532                }
 533
 534                ethoc_update_tx_stats(priv, &bd);
 535                priv->dty_tx++;
 536        }
 537
 538        if ((priv->cur_tx - priv->dty_tx) <= (priv->num_tx / 2))
 539                netif_wake_queue(dev);
 540
 541        return count;
 542}
 543
 544static irqreturn_t ethoc_interrupt(int irq, void *dev_id)
 545{
 546        struct net_device *dev = dev_id;
 547        struct ethoc *priv = netdev_priv(dev);
 548        u32 pending;
 549        u32 mask;
 550
 551        /* Figure out what triggered the interrupt...
 552         * The tricky bit here is that the interrupt source bits get
 553         * set in INT_SOURCE for an event regardless of whether that
 554         * event is masked or not.  Thus, in order to figure out what
 555         * triggered the interrupt, we need to remove the sources
 556         * for all events that are currently masked.  This behaviour
 557         * is not particularly well documented but reasonable...
 558         */
 559        mask = ethoc_read(priv, INT_MASK);
 560        pending = ethoc_read(priv, INT_SOURCE);
 561        pending &= mask;
 562
 563        if (unlikely(pending == 0))
 564                return IRQ_NONE;
 565
 566        ethoc_ack_irq(priv, pending);
 567
 568        /* We always handle the dropped packet interrupt */
 569        if (pending & INT_MASK_BUSY) {
 570                dev_err(&dev->dev, "packet dropped\n");
 571                dev->stats.rx_dropped++;
 572        }
 573
 574        /* Handle receive/transmit event by switching to polling */
 575        if (pending & (INT_MASK_TX | INT_MASK_RX)) {
 576                ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 577                napi_schedule(&priv->napi);
 578        }
 579
 580        return IRQ_HANDLED;
 581}
 582
 583static int ethoc_get_mac_address(struct net_device *dev, void *addr)
 584{
 585        struct ethoc *priv = netdev_priv(dev);
 586        u8 *mac = (u8 *)addr;
 587        u32 reg;
 588
 589        reg = ethoc_read(priv, MAC_ADDR0);
 590        mac[2] = (reg >> 24) & 0xff;
 591        mac[3] = (reg >> 16) & 0xff;
 592        mac[4] = (reg >>  8) & 0xff;
 593        mac[5] = (reg >>  0) & 0xff;
 594
 595        reg = ethoc_read(priv, MAC_ADDR1);
 596        mac[0] = (reg >>  8) & 0xff;
 597        mac[1] = (reg >>  0) & 0xff;
 598
 599        return 0;
 600}
 601
 602static int ethoc_poll(struct napi_struct *napi, int budget)
 603{
 604        struct ethoc *priv = container_of(napi, struct ethoc, napi);
 605        int rx_work_done = 0;
 606        int tx_work_done = 0;
 607
 608        rx_work_done = ethoc_rx(priv->netdev, budget);
 609        tx_work_done = ethoc_tx(priv->netdev, budget);
 610
 611        if (rx_work_done < budget && tx_work_done < budget) {
 612                napi_complete(napi);
 613                ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 614        }
 615
 616        return rx_work_done;
 617}
 618
 619static int ethoc_mdio_read(struct mii_bus *bus, int phy, int reg)
 620{
 621        struct ethoc *priv = bus->priv;
 622        int i;
 623
 624        ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
 625        ethoc_write(priv, MIICOMMAND, MIICOMMAND_READ);
 626
 627        for (i = 0; i < 5; i++) {
 628                u32 status = ethoc_read(priv, MIISTATUS);
 629                if (!(status & MIISTATUS_BUSY)) {
 630                        u32 data = ethoc_read(priv, MIIRX_DATA);
 631                        /* reset MII command register */
 632                        ethoc_write(priv, MIICOMMAND, 0);
 633                        return data;
 634                }
 635                usleep_range(100, 200);
 636        }
 637
 638        return -EBUSY;
 639}
 640
 641static int ethoc_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
 642{
 643        struct ethoc *priv = bus->priv;
 644        int i;
 645
 646        ethoc_write(priv, MIIADDRESS, MIIADDRESS_ADDR(phy, reg));
 647        ethoc_write(priv, MIITX_DATA, val);
 648        ethoc_write(priv, MIICOMMAND, MIICOMMAND_WRITE);
 649
 650        for (i = 0; i < 5; i++) {
 651                u32 stat = ethoc_read(priv, MIISTATUS);
 652                if (!(stat & MIISTATUS_BUSY)) {
 653                        /* reset MII command register */
 654                        ethoc_write(priv, MIICOMMAND, 0);
 655                        return 0;
 656                }
 657                usleep_range(100, 200);
 658        }
 659
 660        return -EBUSY;
 661}
 662
 663static void ethoc_mdio_poll(struct net_device *dev)
 664{
 665}
 666
 667static int ethoc_mdio_probe(struct net_device *dev)
 668{
 669        struct ethoc *priv = netdev_priv(dev);
 670        struct phy_device *phy;
 671        int err;
 672
 673        if (priv->phy_id != -1)
 674                phy = priv->mdio->phy_map[priv->phy_id];
 675        else
 676                phy = phy_find_first(priv->mdio);
 677
 678        if (!phy) {
 679                dev_err(&dev->dev, "no PHY found\n");
 680                return -ENXIO;
 681        }
 682
 683        err = phy_connect_direct(dev, phy, ethoc_mdio_poll,
 684                                 PHY_INTERFACE_MODE_GMII);
 685        if (err) {
 686                dev_err(&dev->dev, "could not attach to PHY\n");
 687                return err;
 688        }
 689
 690        priv->phy = phy;
 691        phy->advertising &= ~(ADVERTISED_1000baseT_Full |
 692                              ADVERTISED_1000baseT_Half);
 693        phy->supported &= ~(SUPPORTED_1000baseT_Full |
 694                            SUPPORTED_1000baseT_Half);
 695
 696        return 0;
 697}
 698
 699static int ethoc_open(struct net_device *dev)
 700{
 701        struct ethoc *priv = netdev_priv(dev);
 702        int ret;
 703
 704        ret = request_irq(dev->irq, ethoc_interrupt, IRQF_SHARED,
 705                        dev->name, dev);
 706        if (ret)
 707                return ret;
 708
 709        ethoc_init_ring(priv, dev->mem_start);
 710        ethoc_reset(priv);
 711
 712        if (netif_queue_stopped(dev)) {
 713                dev_dbg(&dev->dev, " resuming queue\n");
 714                netif_wake_queue(dev);
 715        } else {
 716                dev_dbg(&dev->dev, " starting queue\n");
 717                netif_start_queue(dev);
 718        }
 719
 720        phy_start(priv->phy);
 721        napi_enable(&priv->napi);
 722
 723        if (netif_msg_ifup(priv)) {
 724                dev_info(&dev->dev, "I/O: %08lx Memory: %08lx-%08lx\n",
 725                                dev->base_addr, dev->mem_start, dev->mem_end);
 726        }
 727
 728        return 0;
 729}
 730
 731static int ethoc_stop(struct net_device *dev)
 732{
 733        struct ethoc *priv = netdev_priv(dev);
 734
 735        napi_disable(&priv->napi);
 736
 737        if (priv->phy)
 738                phy_stop(priv->phy);
 739
 740        ethoc_disable_rx_and_tx(priv);
 741        free_irq(dev->irq, dev);
 742
 743        if (!netif_queue_stopped(dev))
 744                netif_stop_queue(dev);
 745
 746        return 0;
 747}
 748
 749static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 750{
 751        struct ethoc *priv = netdev_priv(dev);
 752        struct mii_ioctl_data *mdio = if_mii(ifr);
 753        struct phy_device *phy = NULL;
 754
 755        if (!netif_running(dev))
 756                return -EINVAL;
 757
 758        if (cmd != SIOCGMIIPHY) {
 759                if (mdio->phy_id >= PHY_MAX_ADDR)
 760                        return -ERANGE;
 761
 762                phy = priv->mdio->phy_map[mdio->phy_id];
 763                if (!phy)
 764                        return -ENODEV;
 765        } else {
 766                phy = priv->phy;
 767        }
 768
 769        return phy_mii_ioctl(phy, ifr, cmd);
 770}
 771
 772static void ethoc_do_set_mac_address(struct net_device *dev)
 773{
 774        struct ethoc *priv = netdev_priv(dev);
 775        unsigned char *mac = dev->dev_addr;
 776
 777        ethoc_write(priv, MAC_ADDR0, (mac[2] << 24) | (mac[3] << 16) |
 778                                     (mac[4] <<  8) | (mac[5] <<  0));
 779        ethoc_write(priv, MAC_ADDR1, (mac[0] <<  8) | (mac[1] <<  0));
 780}
 781
 782static int ethoc_set_mac_address(struct net_device *dev, void *p)
 783{
 784        const struct sockaddr *addr = p;
 785
 786        if (!is_valid_ether_addr(addr->sa_data))
 787                return -EADDRNOTAVAIL;
 788        memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 789        ethoc_do_set_mac_address(dev);
 790        return 0;
 791}
 792
 793static void ethoc_set_multicast_list(struct net_device *dev)
 794{
 795        struct ethoc *priv = netdev_priv(dev);
 796        u32 mode = ethoc_read(priv, MODER);
 797        struct netdev_hw_addr *ha;
 798        u32 hash[2] = { 0, 0 };
 799
 800        /* set loopback mode if requested */
 801        if (dev->flags & IFF_LOOPBACK)
 802                mode |=  MODER_LOOP;
 803        else
 804                mode &= ~MODER_LOOP;
 805
 806        /* receive broadcast frames if requested */
 807        if (dev->flags & IFF_BROADCAST)
 808                mode &= ~MODER_BRO;
 809        else
 810                mode |=  MODER_BRO;
 811
 812        /* enable promiscuous mode if requested */
 813        if (dev->flags & IFF_PROMISC)
 814                mode |=  MODER_PRO;
 815        else
 816                mode &= ~MODER_PRO;
 817
 818        ethoc_write(priv, MODER, mode);
 819
 820        /* receive multicast frames */
 821        if (dev->flags & IFF_ALLMULTI) {
 822                hash[0] = 0xffffffff;
 823                hash[1] = 0xffffffff;
 824        } else {
 825                netdev_for_each_mc_addr(ha, dev) {
 826                        u32 crc = ether_crc(ETH_ALEN, ha->addr);
 827                        int bit = (crc >> 26) & 0x3f;
 828                        hash[bit >> 5] |= 1 << (bit & 0x1f);
 829                }
 830        }
 831
 832        ethoc_write(priv, ETH_HASH0, hash[0]);
 833        ethoc_write(priv, ETH_HASH1, hash[1]);
 834}
 835
 836static int ethoc_change_mtu(struct net_device *dev, int new_mtu)
 837{
 838        return -ENOSYS;
 839}
 840
 841static void ethoc_tx_timeout(struct net_device *dev)
 842{
 843        struct ethoc *priv = netdev_priv(dev);
 844        u32 pending = ethoc_read(priv, INT_SOURCE);
 845        if (likely(pending))
 846                ethoc_interrupt(dev->irq, dev);
 847}
 848
 849static netdev_tx_t ethoc_start_xmit(struct sk_buff *skb, struct net_device *dev)
 850{
 851        struct ethoc *priv = netdev_priv(dev);
 852        struct ethoc_bd bd;
 853        unsigned int entry;
 854        void *dest;
 855
 856        if (unlikely(skb->len > ETHOC_BUFSIZ)) {
 857                dev->stats.tx_errors++;
 858                goto out;
 859        }
 860
 861        entry = priv->cur_tx % priv->num_tx;
 862        spin_lock_irq(&priv->lock);
 863        priv->cur_tx++;
 864
 865        ethoc_read_bd(priv, entry, &bd);
 866        if (unlikely(skb->len < ETHOC_ZLEN))
 867                bd.stat |=  TX_BD_PAD;
 868        else
 869                bd.stat &= ~TX_BD_PAD;
 870
 871        dest = priv->vma[entry];
 872        memcpy_toio(dest, skb->data, skb->len);
 873
 874        bd.stat &= ~(TX_BD_STATS | TX_BD_LEN_MASK);
 875        bd.stat |= TX_BD_LEN(skb->len);
 876        ethoc_write_bd(priv, entry, &bd);
 877
 878        bd.stat |= TX_BD_READY;
 879        ethoc_write_bd(priv, entry, &bd);
 880
 881        if (priv->cur_tx == (priv->dty_tx + priv->num_tx)) {
 882                dev_dbg(&dev->dev, "stopping queue\n");
 883                netif_stop_queue(dev);
 884        }
 885
 886        spin_unlock_irq(&priv->lock);
 887        skb_tx_timestamp(skb);
 888out:
 889        dev_kfree_skb(skb);
 890        return NETDEV_TX_OK;
 891}
 892
 893static int ethoc_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 894{
 895        struct ethoc *priv = netdev_priv(dev);
 896        struct phy_device *phydev = priv->phy;
 897
 898        if (!phydev)
 899                return -EOPNOTSUPP;
 900
 901        return phy_ethtool_gset(phydev, cmd);
 902}
 903
 904static int ethoc_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 905{
 906        struct ethoc *priv = netdev_priv(dev);
 907        struct phy_device *phydev = priv->phy;
 908
 909        if (!phydev)
 910                return -EOPNOTSUPP;
 911
 912        return phy_ethtool_sset(phydev, cmd);
 913}
 914
 915static int ethoc_get_regs_len(struct net_device *netdev)
 916{
 917        return ETH_END;
 918}
 919
 920static void ethoc_get_regs(struct net_device *dev, struct ethtool_regs *regs,
 921                           void *p)
 922{
 923        struct ethoc *priv = netdev_priv(dev);
 924        u32 *regs_buff = p;
 925        unsigned i;
 926
 927        regs->version = 0;
 928        for (i = 0; i < ETH_END / sizeof(u32); ++i)
 929                regs_buff[i] = ethoc_read(priv, i * sizeof(u32));
 930}
 931
 932static void ethoc_get_ringparam(struct net_device *dev,
 933                                struct ethtool_ringparam *ring)
 934{
 935        struct ethoc *priv = netdev_priv(dev);
 936
 937        ring->rx_max_pending = priv->num_bd - 1;
 938        ring->rx_mini_max_pending = 0;
 939        ring->rx_jumbo_max_pending = 0;
 940        ring->tx_max_pending = priv->num_bd - 1;
 941
 942        ring->rx_pending = priv->num_rx;
 943        ring->rx_mini_pending = 0;
 944        ring->rx_jumbo_pending = 0;
 945        ring->tx_pending = priv->num_tx;
 946}
 947
 948static int ethoc_set_ringparam(struct net_device *dev,
 949                               struct ethtool_ringparam *ring)
 950{
 951        struct ethoc *priv = netdev_priv(dev);
 952
 953        if (ring->tx_pending < 1 || ring->rx_pending < 1 ||
 954            ring->tx_pending + ring->rx_pending > priv->num_bd)
 955                return -EINVAL;
 956        if (ring->rx_mini_pending || ring->rx_jumbo_pending)
 957                return -EINVAL;
 958
 959        if (netif_running(dev)) {
 960                netif_tx_disable(dev);
 961                ethoc_disable_rx_and_tx(priv);
 962                ethoc_disable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 963                synchronize_irq(dev->irq);
 964        }
 965
 966        priv->num_tx = rounddown_pow_of_two(ring->tx_pending);
 967        priv->num_rx = ring->rx_pending;
 968        ethoc_init_ring(priv, dev->mem_start);
 969
 970        if (netif_running(dev)) {
 971                ethoc_enable_irq(priv, INT_MASK_TX | INT_MASK_RX);
 972                ethoc_enable_rx_and_tx(priv);
 973                netif_wake_queue(dev);
 974        }
 975        return 0;
 976}
 977
 978const struct ethtool_ops ethoc_ethtool_ops = {
 979        .get_settings = ethoc_get_settings,
 980        .set_settings = ethoc_set_settings,
 981        .get_regs_len = ethoc_get_regs_len,
 982        .get_regs = ethoc_get_regs,
 983        .get_link = ethtool_op_get_link,
 984        .get_ringparam = ethoc_get_ringparam,
 985        .set_ringparam = ethoc_set_ringparam,
 986        .get_ts_info = ethtool_op_get_ts_info,
 987};
 988
 989static const struct net_device_ops ethoc_netdev_ops = {
 990        .ndo_open = ethoc_open,
 991        .ndo_stop = ethoc_stop,
 992        .ndo_do_ioctl = ethoc_ioctl,
 993        .ndo_set_mac_address = ethoc_set_mac_address,
 994        .ndo_set_rx_mode = ethoc_set_multicast_list,
 995        .ndo_change_mtu = ethoc_change_mtu,
 996        .ndo_tx_timeout = ethoc_tx_timeout,
 997        .ndo_start_xmit = ethoc_start_xmit,
 998};
 999
1000/**
1001 * ethoc_probe - initialize OpenCores ethernet MAC
1002 * pdev:        platform device
1003 */
1004static int ethoc_probe(struct platform_device *pdev)
1005{
1006        struct net_device *netdev = NULL;
1007        struct resource *res = NULL;
1008        struct resource *mmio = NULL;
1009        struct resource *mem = NULL;
1010        struct ethoc *priv = NULL;
1011        unsigned int phy;
1012        int num_bd;
1013        int ret = 0;
1014        bool random_mac = false;
1015        struct ethoc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1016        u32 eth_clkfreq = pdata ? pdata->eth_clkfreq : 0;
1017
1018        /* allocate networking device */
1019        netdev = alloc_etherdev(sizeof(struct ethoc));
1020        if (!netdev) {
1021                ret = -ENOMEM;
1022                goto out;
1023        }
1024
1025        SET_NETDEV_DEV(netdev, &pdev->dev);
1026        platform_set_drvdata(pdev, netdev);
1027
1028        /* obtain I/O memory space */
1029        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1030        if (!res) {
1031                dev_err(&pdev->dev, "cannot obtain I/O memory space\n");
1032                ret = -ENXIO;
1033                goto free;
1034        }
1035
1036        mmio = devm_request_mem_region(&pdev->dev, res->start,
1037                        resource_size(res), res->name);
1038        if (!mmio) {
1039                dev_err(&pdev->dev, "cannot request I/O memory space\n");
1040                ret = -ENXIO;
1041                goto free;
1042        }
1043
1044        netdev->base_addr = mmio->start;
1045
1046        /* obtain buffer memory space */
1047        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1048        if (res) {
1049                mem = devm_request_mem_region(&pdev->dev, res->start,
1050                        resource_size(res), res->name);
1051                if (!mem) {
1052                        dev_err(&pdev->dev, "cannot request memory space\n");
1053                        ret = -ENXIO;
1054                        goto free;
1055                }
1056
1057                netdev->mem_start = mem->start;
1058                netdev->mem_end   = mem->end;
1059        }
1060
1061
1062        /* obtain device IRQ number */
1063        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1064        if (!res) {
1065                dev_err(&pdev->dev, "cannot obtain IRQ\n");
1066                ret = -ENXIO;
1067                goto free;
1068        }
1069
1070        netdev->irq = res->start;
1071
1072        /* setup driver-private data */
1073        priv = netdev_priv(netdev);
1074        priv->netdev = netdev;
1075        priv->dma_alloc = 0;
1076        priv->io_region_size = resource_size(mmio);
1077
1078        priv->iobase = devm_ioremap_nocache(&pdev->dev, netdev->base_addr,
1079                        resource_size(mmio));
1080        if (!priv->iobase) {
1081                dev_err(&pdev->dev, "cannot remap I/O memory space\n");
1082                ret = -ENXIO;
1083                goto error;
1084        }
1085
1086        if (netdev->mem_end) {
1087                priv->membase = devm_ioremap_nocache(&pdev->dev,
1088                        netdev->mem_start, resource_size(mem));
1089                if (!priv->membase) {
1090                        dev_err(&pdev->dev, "cannot remap memory space\n");
1091                        ret = -ENXIO;
1092                        goto error;
1093                }
1094        } else {
1095                /* Allocate buffer memory */
1096                priv->membase = dmam_alloc_coherent(&pdev->dev,
1097                        buffer_size, (void *)&netdev->mem_start,
1098                        GFP_KERNEL);
1099                if (!priv->membase) {
1100                        dev_err(&pdev->dev, "cannot allocate %dB buffer\n",
1101                                buffer_size);
1102                        ret = -ENOMEM;
1103                        goto error;
1104                }
1105                netdev->mem_end = netdev->mem_start + buffer_size;
1106                priv->dma_alloc = buffer_size;
1107        }
1108
1109        /* calculate the number of TX/RX buffers, maximum 128 supported */
1110        num_bd = min_t(unsigned int,
1111                128, (netdev->mem_end - netdev->mem_start + 1) / ETHOC_BUFSIZ);
1112        if (num_bd < 4) {
1113                ret = -ENODEV;
1114                goto error;
1115        }
1116        priv->num_bd = num_bd;
1117        /* num_tx must be a power of two */
1118        priv->num_tx = rounddown_pow_of_two(num_bd >> 1);
1119        priv->num_rx = num_bd - priv->num_tx;
1120
1121        dev_dbg(&pdev->dev, "ethoc: num_tx: %d num_rx: %d\n",
1122                priv->num_tx, priv->num_rx);
1123
1124        priv->vma = devm_kzalloc(&pdev->dev, num_bd*sizeof(void *), GFP_KERNEL);
1125        if (!priv->vma) {
1126                ret = -ENOMEM;
1127                goto error;
1128        }
1129
1130        /* Allow the platform setup code to pass in a MAC address. */
1131        if (pdata) {
1132                memcpy(netdev->dev_addr, pdata->hwaddr, IFHWADDRLEN);
1133                priv->phy_id = pdata->phy_id;
1134        } else {
1135                priv->phy_id = -1;
1136
1137#ifdef CONFIG_OF
1138                {
1139                const uint8_t *mac;
1140
1141                mac = of_get_property(pdev->dev.of_node,
1142                                      "local-mac-address",
1143                                      NULL);
1144                if (mac)
1145                        memcpy(netdev->dev_addr, mac, IFHWADDRLEN);
1146                }
1147#endif
1148        }
1149
1150        /* Check that the given MAC address is valid. If it isn't, read the
1151         * current MAC from the controller.
1152         */
1153        if (!is_valid_ether_addr(netdev->dev_addr))
1154                ethoc_get_mac_address(netdev, netdev->dev_addr);
1155
1156        /* Check the MAC again for validity, if it still isn't choose and
1157         * program a random one.
1158         */
1159        if (!is_valid_ether_addr(netdev->dev_addr)) {
1160                eth_random_addr(netdev->dev_addr);
1161                random_mac = true;
1162        }
1163
1164        ethoc_do_set_mac_address(netdev);
1165
1166        if (random_mac)
1167                netdev->addr_assign_type = NET_ADDR_RANDOM;
1168
1169        /* Allow the platform setup code to adjust MII management bus clock. */
1170        if (!eth_clkfreq) {
1171                struct clk *clk = devm_clk_get(&pdev->dev, NULL);
1172
1173                if (!IS_ERR(clk)) {
1174                        priv->clk = clk;
1175                        clk_prepare_enable(clk);
1176                        eth_clkfreq = clk_get_rate(clk);
1177                }
1178        }
1179        if (eth_clkfreq) {
1180                u32 clkdiv = MIIMODER_CLKDIV(eth_clkfreq / 2500000 + 1);
1181
1182                if (!clkdiv)
1183                        clkdiv = 2;
1184                dev_dbg(&pdev->dev, "setting MII clkdiv to %u\n", clkdiv);
1185                ethoc_write(priv, MIIMODER,
1186                            (ethoc_read(priv, MIIMODER) & MIIMODER_NOPRE) |
1187                            clkdiv);
1188        }
1189
1190        /* register MII bus */
1191        priv->mdio = mdiobus_alloc();
1192        if (!priv->mdio) {
1193                ret = -ENOMEM;
1194                goto free;
1195        }
1196
1197        priv->mdio->name = "ethoc-mdio";
1198        snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "%s-%d",
1199                        priv->mdio->name, pdev->id);
1200        priv->mdio->read = ethoc_mdio_read;
1201        priv->mdio->write = ethoc_mdio_write;
1202        priv->mdio->priv = priv;
1203
1204        priv->mdio->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
1205        if (!priv->mdio->irq) {
1206                ret = -ENOMEM;
1207                goto free_mdio;
1208        }
1209
1210        for (phy = 0; phy < PHY_MAX_ADDR; phy++)
1211                priv->mdio->irq[phy] = PHY_POLL;
1212
1213        ret = mdiobus_register(priv->mdio);
1214        if (ret) {
1215                dev_err(&netdev->dev, "failed to register MDIO bus\n");
1216                goto free_mdio;
1217        }
1218
1219        ret = ethoc_mdio_probe(netdev);
1220        if (ret) {
1221                dev_err(&netdev->dev, "failed to probe MDIO bus\n");
1222                goto error;
1223        }
1224
1225        /* setup the net_device structure */
1226        netdev->netdev_ops = &ethoc_netdev_ops;
1227        netdev->watchdog_timeo = ETHOC_TIMEOUT;
1228        netdev->features |= 0;
1229        netdev->ethtool_ops = &ethoc_ethtool_ops;
1230
1231        /* setup NAPI */
1232        netif_napi_add(netdev, &priv->napi, ethoc_poll, 64);
1233
1234        spin_lock_init(&priv->lock);
1235
1236        ret = register_netdev(netdev);
1237        if (ret < 0) {
1238                dev_err(&netdev->dev, "failed to register interface\n");
1239                goto error2;
1240        }
1241
1242        goto out;
1243
1244error2:
1245        netif_napi_del(&priv->napi);
1246error:
1247        mdiobus_unregister(priv->mdio);
1248free_mdio:
1249        kfree(priv->mdio->irq);
1250        mdiobus_free(priv->mdio);
1251free:
1252        if (priv->clk)
1253                clk_disable_unprepare(priv->clk);
1254        free_netdev(netdev);
1255out:
1256        return ret;
1257}
1258
1259/**
1260 * ethoc_remove - shutdown OpenCores ethernet MAC
1261 * @pdev:       platform device
1262 */
1263static int ethoc_remove(struct platform_device *pdev)
1264{
1265        struct net_device *netdev = platform_get_drvdata(pdev);
1266        struct ethoc *priv = netdev_priv(netdev);
1267
1268        if (netdev) {
1269                netif_napi_del(&priv->napi);
1270                phy_disconnect(priv->phy);
1271                priv->phy = NULL;
1272
1273                if (priv->mdio) {
1274                        mdiobus_unregister(priv->mdio);
1275                        kfree(priv->mdio->irq);
1276                        mdiobus_free(priv->mdio);
1277                }
1278                if (priv->clk)
1279                        clk_disable_unprepare(priv->clk);
1280                unregister_netdev(netdev);
1281                free_netdev(netdev);
1282        }
1283
1284        return 0;
1285}
1286
1287#ifdef CONFIG_PM
1288static int ethoc_suspend(struct platform_device *pdev, pm_message_t state)
1289{
1290        return -ENOSYS;
1291}
1292
1293static int ethoc_resume(struct platform_device *pdev)
1294{
1295        return -ENOSYS;
1296}
1297#else
1298# define ethoc_suspend NULL
1299# define ethoc_resume  NULL
1300#endif
1301
1302static struct of_device_id ethoc_match[] = {
1303        { .compatible = "opencores,ethoc", },
1304        {},
1305};
1306MODULE_DEVICE_TABLE(of, ethoc_match);
1307
1308static struct platform_driver ethoc_driver = {
1309        .probe   = ethoc_probe,
1310        .remove  = ethoc_remove,
1311        .suspend = ethoc_suspend,
1312        .resume  = ethoc_resume,
1313        .driver  = {
1314                .name = "ethoc",
1315                .of_match_table = ethoc_match,
1316        },
1317};
1318
1319module_platform_driver(ethoc_driver);
1320
1321MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1322MODULE_DESCRIPTION("OpenCores Ethernet MAC driver");
1323MODULE_LICENSE("GPL v2");
1324
1325
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