linux/drivers/net/ethernet/broadcom/genet/bcmgenet.c
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   1/*
   2 * Broadcom GENET (Gigabit Ethernet) controller driver
   3 *
   4 * Copyright (c) 2014 Broadcom Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13#include <linux/kernel.h>
  14#include <linux/module.h>
  15#include <linux/sched.h>
  16#include <linux/types.h>
  17#include <linux/fcntl.h>
  18#include <linux/interrupt.h>
  19#include <linux/string.h>
  20#include <linux/if_ether.h>
  21#include <linux/init.h>
  22#include <linux/errno.h>
  23#include <linux/delay.h>
  24#include <linux/platform_device.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/pm.h>
  27#include <linux/clk.h>
  28#include <linux/of.h>
  29#include <linux/of_address.h>
  30#include <linux/of_irq.h>
  31#include <linux/of_net.h>
  32#include <linux/of_platform.h>
  33#include <net/arp.h>
  34
  35#include <linux/mii.h>
  36#include <linux/ethtool.h>
  37#include <linux/netdevice.h>
  38#include <linux/inetdevice.h>
  39#include <linux/etherdevice.h>
  40#include <linux/skbuff.h>
  41#include <linux/in.h>
  42#include <linux/ip.h>
  43#include <linux/ipv6.h>
  44#include <linux/phy.h>
  45#include <linux/platform_data/bcmgenet.h>
  46
  47#include <asm/unaligned.h>
  48
  49#include "bcmgenet.h"
  50
  51/* Maximum number of hardware queues, downsized if needed */
  52#define GENET_MAX_MQ_CNT        4
  53
  54/* Default highest priority queue for multi queue support */
  55#define GENET_Q0_PRIORITY       0
  56
  57#define GENET_DEFAULT_BD_CNT    \
  58        (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
  59
  60#define RX_BUF_LENGTH           2048
  61#define SKB_ALIGNMENT           32
  62
  63/* Tx/Rx DMA register offset, skip 256 descriptors */
  64#define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  65#define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  66
  67#define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  68                                TOTAL_DESC * DMA_DESC_SIZE)
  69
  70#define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  71                                TOTAL_DESC * DMA_DESC_SIZE)
  72
  73static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  74                                             void __iomem *d, u32 value)
  75{
  76        __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  77}
  78
  79static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  80                                            void __iomem *d)
  81{
  82        return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  83}
  84
  85static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  86                                    void __iomem *d,
  87                                    dma_addr_t addr)
  88{
  89        __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  90
  91        /* Register writes to GISB bus can take couple hundred nanoseconds
  92         * and are done for each packet, save these expensive writes unless
  93         * the platform is explicitly configured for 64-bits/LPAE.
  94         */
  95#ifdef CONFIG_PHYS_ADDR_T_64BIT
  96        if (priv->hw_params->flags & GENET_HAS_40BITS)
  97                __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
  98#endif
  99}
 100
 101/* Combined address + length/status setter */
 102static inline void dmadesc_set(struct bcmgenet_priv *priv,
 103                               void __iomem *d, dma_addr_t addr, u32 val)
 104{
 105        dmadesc_set_length_status(priv, d, val);
 106        dmadesc_set_addr(priv, d, addr);
 107}
 108
 109static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 110                                          void __iomem *d)
 111{
 112        dma_addr_t addr;
 113
 114        addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 115
 116        /* Register writes to GISB bus can take couple hundred nanoseconds
 117         * and are done for each packet, save these expensive writes unless
 118         * the platform is explicitly configured for 64-bits/LPAE.
 119         */
 120#ifdef CONFIG_PHYS_ADDR_T_64BIT
 121        if (priv->hw_params->flags & GENET_HAS_40BITS)
 122                addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 123#endif
 124        return addr;
 125}
 126
 127#define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 128
 129#define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 130                                NETIF_MSG_LINK)
 131
 132static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 133{
 134        if (GENET_IS_V1(priv))
 135                return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 136        else
 137                return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 138}
 139
 140static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 141{
 142        if (GENET_IS_V1(priv))
 143                bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 144        else
 145                bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 146}
 147
 148/* These macros are defined to deal with register map change
 149 * between GENET1.1 and GENET2. Only those currently being used
 150 * by driver are defined.
 151 */
 152static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 153{
 154        if (GENET_IS_V1(priv))
 155                return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 156        else
 157                return __raw_readl(priv->base +
 158                                priv->hw_params->tbuf_offset + TBUF_CTRL);
 159}
 160
 161static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 162{
 163        if (GENET_IS_V1(priv))
 164                bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 165        else
 166                __raw_writel(val, priv->base +
 167                                priv->hw_params->tbuf_offset + TBUF_CTRL);
 168}
 169
 170static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 171{
 172        if (GENET_IS_V1(priv))
 173                return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 174        else
 175                return __raw_readl(priv->base +
 176                                priv->hw_params->tbuf_offset + TBUF_BP_MC);
 177}
 178
 179static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 180{
 181        if (GENET_IS_V1(priv))
 182                bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 183        else
 184                __raw_writel(val, priv->base +
 185                                priv->hw_params->tbuf_offset + TBUF_BP_MC);
 186}
 187
 188/* RX/TX DMA register accessors */
 189enum dma_reg {
 190        DMA_RING_CFG = 0,
 191        DMA_CTRL,
 192        DMA_STATUS,
 193        DMA_SCB_BURST_SIZE,
 194        DMA_ARB_CTRL,
 195        DMA_PRIORITY_0,
 196        DMA_PRIORITY_1,
 197        DMA_PRIORITY_2,
 198};
 199
 200static const u8 bcmgenet_dma_regs_v3plus[] = {
 201        [DMA_RING_CFG]          = 0x00,
 202        [DMA_CTRL]              = 0x04,
 203        [DMA_STATUS]            = 0x08,
 204        [DMA_SCB_BURST_SIZE]    = 0x0C,
 205        [DMA_ARB_CTRL]          = 0x2C,
 206        [DMA_PRIORITY_0]        = 0x30,
 207        [DMA_PRIORITY_1]        = 0x34,
 208        [DMA_PRIORITY_2]        = 0x38,
 209};
 210
 211static const u8 bcmgenet_dma_regs_v2[] = {
 212        [DMA_RING_CFG]          = 0x00,
 213        [DMA_CTRL]              = 0x04,
 214        [DMA_STATUS]            = 0x08,
 215        [DMA_SCB_BURST_SIZE]    = 0x0C,
 216        [DMA_ARB_CTRL]          = 0x30,
 217        [DMA_PRIORITY_0]        = 0x34,
 218        [DMA_PRIORITY_1]        = 0x38,
 219        [DMA_PRIORITY_2]        = 0x3C,
 220};
 221
 222static const u8 bcmgenet_dma_regs_v1[] = {
 223        [DMA_CTRL]              = 0x00,
 224        [DMA_STATUS]            = 0x04,
 225        [DMA_SCB_BURST_SIZE]    = 0x0C,
 226        [DMA_ARB_CTRL]          = 0x30,
 227        [DMA_PRIORITY_0]        = 0x34,
 228        [DMA_PRIORITY_1]        = 0x38,
 229        [DMA_PRIORITY_2]        = 0x3C,
 230};
 231
 232/* Set at runtime once bcmgenet version is known */
 233static const u8 *bcmgenet_dma_regs;
 234
 235static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 236{
 237        return netdev_priv(dev_get_drvdata(dev));
 238}
 239
 240static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 241                                      enum dma_reg r)
 242{
 243        return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 244                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 245}
 246
 247static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 248                                        u32 val, enum dma_reg r)
 249{
 250        __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 251                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 252}
 253
 254static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 255                                      enum dma_reg r)
 256{
 257        return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 258                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 259}
 260
 261static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 262                                        u32 val, enum dma_reg r)
 263{
 264        __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 265                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 266}
 267
 268/* RDMA/TDMA ring registers and accessors
 269 * we merge the common fields and just prefix with T/D the registers
 270 * having different meaning depending on the direction
 271 */
 272enum dma_ring_reg {
 273        TDMA_READ_PTR = 0,
 274        RDMA_WRITE_PTR = TDMA_READ_PTR,
 275        TDMA_READ_PTR_HI,
 276        RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 277        TDMA_CONS_INDEX,
 278        RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 279        TDMA_PROD_INDEX,
 280        RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 281        DMA_RING_BUF_SIZE,
 282        DMA_START_ADDR,
 283        DMA_START_ADDR_HI,
 284        DMA_END_ADDR,
 285        DMA_END_ADDR_HI,
 286        DMA_MBUF_DONE_THRESH,
 287        TDMA_FLOW_PERIOD,
 288        RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 289        TDMA_WRITE_PTR,
 290        RDMA_READ_PTR = TDMA_WRITE_PTR,
 291        TDMA_WRITE_PTR_HI,
 292        RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 293};
 294
 295/* GENET v4 supports 40-bits pointer addressing
 296 * for obvious reasons the LO and HI word parts
 297 * are contiguous, but this offsets the other
 298 * registers.
 299 */
 300static const u8 genet_dma_ring_regs_v4[] = {
 301        [TDMA_READ_PTR]                 = 0x00,
 302        [TDMA_READ_PTR_HI]              = 0x04,
 303        [TDMA_CONS_INDEX]               = 0x08,
 304        [TDMA_PROD_INDEX]               = 0x0C,
 305        [DMA_RING_BUF_SIZE]             = 0x10,
 306        [DMA_START_ADDR]                = 0x14,
 307        [DMA_START_ADDR_HI]             = 0x18,
 308        [DMA_END_ADDR]                  = 0x1C,
 309        [DMA_END_ADDR_HI]               = 0x20,
 310        [DMA_MBUF_DONE_THRESH]          = 0x24,
 311        [TDMA_FLOW_PERIOD]              = 0x28,
 312        [TDMA_WRITE_PTR]                = 0x2C,
 313        [TDMA_WRITE_PTR_HI]             = 0x30,
 314};
 315
 316static const u8 genet_dma_ring_regs_v123[] = {
 317        [TDMA_READ_PTR]                 = 0x00,
 318        [TDMA_CONS_INDEX]               = 0x04,
 319        [TDMA_PROD_INDEX]               = 0x08,
 320        [DMA_RING_BUF_SIZE]             = 0x0C,
 321        [DMA_START_ADDR]                = 0x10,
 322        [DMA_END_ADDR]                  = 0x14,
 323        [DMA_MBUF_DONE_THRESH]          = 0x18,
 324        [TDMA_FLOW_PERIOD]              = 0x1C,
 325        [TDMA_WRITE_PTR]                = 0x20,
 326};
 327
 328/* Set at runtime once GENET version is known */
 329static const u8 *genet_dma_ring_regs;
 330
 331static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 332                                           unsigned int ring,
 333                                           enum dma_ring_reg r)
 334{
 335        return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 336                        (DMA_RING_SIZE * ring) +
 337                        genet_dma_ring_regs[r]);
 338}
 339
 340static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 341                                             unsigned int ring, u32 val,
 342                                             enum dma_ring_reg r)
 343{
 344        __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 345                        (DMA_RING_SIZE * ring) +
 346                        genet_dma_ring_regs[r]);
 347}
 348
 349static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 350                                           unsigned int ring,
 351                                           enum dma_ring_reg r)
 352{
 353        return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 354                        (DMA_RING_SIZE * ring) +
 355                        genet_dma_ring_regs[r]);
 356}
 357
 358static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 359                                             unsigned int ring, u32 val,
 360                                             enum dma_ring_reg r)
 361{
 362        __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 363                        (DMA_RING_SIZE * ring) +
 364                        genet_dma_ring_regs[r]);
 365}
 366
 367static int bcmgenet_get_settings(struct net_device *dev,
 368                                 struct ethtool_cmd *cmd)
 369{
 370        struct bcmgenet_priv *priv = netdev_priv(dev);
 371
 372        if (!netif_running(dev))
 373                return -EINVAL;
 374
 375        if (!priv->phydev)
 376                return -ENODEV;
 377
 378        return phy_ethtool_gset(priv->phydev, cmd);
 379}
 380
 381static int bcmgenet_set_settings(struct net_device *dev,
 382                                 struct ethtool_cmd *cmd)
 383{
 384        struct bcmgenet_priv *priv = netdev_priv(dev);
 385
 386        if (!netif_running(dev))
 387                return -EINVAL;
 388
 389        if (!priv->phydev)
 390                return -ENODEV;
 391
 392        return phy_ethtool_sset(priv->phydev, cmd);
 393}
 394
 395static int bcmgenet_set_rx_csum(struct net_device *dev,
 396                                netdev_features_t wanted)
 397{
 398        struct bcmgenet_priv *priv = netdev_priv(dev);
 399        u32 rbuf_chk_ctrl;
 400        bool rx_csum_en;
 401
 402        rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 403
 404        rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 405
 406        /* enable rx checksumming */
 407        if (rx_csum_en)
 408                rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 409        else
 410                rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 411        priv->desc_rxchk_en = rx_csum_en;
 412
 413        /* If UniMAC forwards CRC, we need to skip over it to get
 414         * a valid CHK bit to be set in the per-packet status word
 415        */
 416        if (rx_csum_en && priv->crc_fwd_en)
 417                rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 418        else
 419                rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 420
 421        bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 422
 423        return 0;
 424}
 425
 426static int bcmgenet_set_tx_csum(struct net_device *dev,
 427                                netdev_features_t wanted)
 428{
 429        struct bcmgenet_priv *priv = netdev_priv(dev);
 430        bool desc_64b_en;
 431        u32 tbuf_ctrl, rbuf_ctrl;
 432
 433        tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 434        rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 435
 436        desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 437
 438        /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 439        if (desc_64b_en) {
 440                tbuf_ctrl |= RBUF_64B_EN;
 441                rbuf_ctrl |= RBUF_64B_EN;
 442        } else {
 443                tbuf_ctrl &= ~RBUF_64B_EN;
 444                rbuf_ctrl &= ~RBUF_64B_EN;
 445        }
 446        priv->desc_64b_en = desc_64b_en;
 447
 448        bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 449        bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 450
 451        return 0;
 452}
 453
 454static int bcmgenet_set_features(struct net_device *dev,
 455                                 netdev_features_t features)
 456{
 457        netdev_features_t changed = features ^ dev->features;
 458        netdev_features_t wanted = dev->wanted_features;
 459        int ret = 0;
 460
 461        if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 462                ret = bcmgenet_set_tx_csum(dev, wanted);
 463        if (changed & (NETIF_F_RXCSUM))
 464                ret = bcmgenet_set_rx_csum(dev, wanted);
 465
 466        return ret;
 467}
 468
 469static u32 bcmgenet_get_msglevel(struct net_device *dev)
 470{
 471        struct bcmgenet_priv *priv = netdev_priv(dev);
 472
 473        return priv->msg_enable;
 474}
 475
 476static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 477{
 478        struct bcmgenet_priv *priv = netdev_priv(dev);
 479
 480        priv->msg_enable = level;
 481}
 482
 483/* standard ethtool support functions. */
 484enum bcmgenet_stat_type {
 485        BCMGENET_STAT_NETDEV = -1,
 486        BCMGENET_STAT_MIB_RX,
 487        BCMGENET_STAT_MIB_TX,
 488        BCMGENET_STAT_RUNT,
 489        BCMGENET_STAT_MISC,
 490};
 491
 492struct bcmgenet_stats {
 493        char stat_string[ETH_GSTRING_LEN];
 494        int stat_sizeof;
 495        int stat_offset;
 496        enum bcmgenet_stat_type type;
 497        /* reg offset from UMAC base for misc counters */
 498        u16 reg_offset;
 499};
 500
 501#define STAT_NETDEV(m) { \
 502        .stat_string = __stringify(m), \
 503        .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 504        .stat_offset = offsetof(struct net_device_stats, m), \
 505        .type = BCMGENET_STAT_NETDEV, \
 506}
 507
 508#define STAT_GENET_MIB(str, m, _type) { \
 509        .stat_string = str, \
 510        .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 511        .stat_offset = offsetof(struct bcmgenet_priv, m), \
 512        .type = _type, \
 513}
 514
 515#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 516#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 517#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 518
 519#define STAT_GENET_MISC(str, m, offset) { \
 520        .stat_string = str, \
 521        .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 522        .stat_offset = offsetof(struct bcmgenet_priv, m), \
 523        .type = BCMGENET_STAT_MISC, \
 524        .reg_offset = offset, \
 525}
 526
 527
 528/* There is a 0xC gap between the end of RX and beginning of TX stats and then
 529 * between the end of TX stats and the beginning of the RX RUNT
 530 */
 531#define BCMGENET_STAT_OFFSET    0xc
 532
 533/* Hardware counters must be kept in sync because the order/offset
 534 * is important here (order in structure declaration = order in hardware)
 535 */
 536static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 537        /* general stats */
 538        STAT_NETDEV(rx_packets),
 539        STAT_NETDEV(tx_packets),
 540        STAT_NETDEV(rx_bytes),
 541        STAT_NETDEV(tx_bytes),
 542        STAT_NETDEV(rx_errors),
 543        STAT_NETDEV(tx_errors),
 544        STAT_NETDEV(rx_dropped),
 545        STAT_NETDEV(tx_dropped),
 546        STAT_NETDEV(multicast),
 547        /* UniMAC RSV counters */
 548        STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 549        STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 550        STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 551        STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 552        STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 553        STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 554        STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 555        STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 556        STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 557        STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 558        STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 559        STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 560        STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 561        STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 562        STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 563        STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 564        STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 565        STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 566        STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 567        STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 568        STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 569        STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 570        STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 571        STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 572        STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 573        STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 574        STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 575        STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 576        STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 577        /* UniMAC TSV counters */
 578        STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 579        STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 580        STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 581        STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 582        STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 583        STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 584        STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 585        STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 586        STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 587        STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 588        STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 589        STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 590        STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 591        STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 592        STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 593        STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 594        STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 595        STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 596        STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 597        STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 598        STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 599        STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 600        STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 601        STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 602        STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 603        STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 604        STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 605        STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 606        STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 607        /* UniMAC RUNT counters */
 608        STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 609        STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 610        STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 611        STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 612        /* Misc UniMAC counters */
 613        STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 614                        UMAC_RBUF_OVFL_CNT),
 615        STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 616        STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 617        STAT_GENET_MIB_RX("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 618        STAT_GENET_MIB_RX("rx_dma_failed", mib.rx_dma_failed),
 619        STAT_GENET_MIB_TX("tx_dma_failed", mib.tx_dma_failed),
 620};
 621
 622#define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 623
 624static void bcmgenet_get_drvinfo(struct net_device *dev,
 625                                 struct ethtool_drvinfo *info)
 626{
 627        strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 628        strlcpy(info->version, "v2.0", sizeof(info->version));
 629        info->n_stats = BCMGENET_STATS_LEN;
 630}
 631
 632static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 633{
 634        switch (string_set) {
 635        case ETH_SS_STATS:
 636                return BCMGENET_STATS_LEN;
 637        default:
 638                return -EOPNOTSUPP;
 639        }
 640}
 641
 642static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 643                                 u8 *data)
 644{
 645        int i;
 646
 647        switch (stringset) {
 648        case ETH_SS_STATS:
 649                for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 650                        memcpy(data + i * ETH_GSTRING_LEN,
 651                               bcmgenet_gstrings_stats[i].stat_string,
 652                               ETH_GSTRING_LEN);
 653                }
 654                break;
 655        }
 656}
 657
 658static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 659{
 660        int i, j = 0;
 661
 662        for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 663                const struct bcmgenet_stats *s;
 664                u8 offset = 0;
 665                u32 val = 0;
 666                char *p;
 667
 668                s = &bcmgenet_gstrings_stats[i];
 669                switch (s->type) {
 670                case BCMGENET_STAT_NETDEV:
 671                        continue;
 672                case BCMGENET_STAT_MIB_RX:
 673                case BCMGENET_STAT_MIB_TX:
 674                case BCMGENET_STAT_RUNT:
 675                        if (s->type != BCMGENET_STAT_MIB_RX)
 676                                offset = BCMGENET_STAT_OFFSET;
 677                        val = bcmgenet_umac_readl(priv,
 678                                                  UMAC_MIB_START + j + offset);
 679                        break;
 680                case BCMGENET_STAT_MISC:
 681                        val = bcmgenet_umac_readl(priv, s->reg_offset);
 682                        /* clear if overflowed */
 683                        if (val == ~0)
 684                                bcmgenet_umac_writel(priv, 0, s->reg_offset);
 685                        break;
 686                }
 687
 688                j += s->stat_sizeof;
 689                p = (char *)priv + s->stat_offset;
 690                *(u32 *)p = val;
 691        }
 692}
 693
 694static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 695                                       struct ethtool_stats *stats,
 696                                       u64 *data)
 697{
 698        struct bcmgenet_priv *priv = netdev_priv(dev);
 699        int i;
 700
 701        if (netif_running(dev))
 702                bcmgenet_update_mib_counters(priv);
 703
 704        for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 705                const struct bcmgenet_stats *s;
 706                char *p;
 707
 708                s = &bcmgenet_gstrings_stats[i];
 709                if (s->type == BCMGENET_STAT_NETDEV)
 710                        p = (char *)&dev->stats;
 711                else
 712                        p = (char *)priv;
 713                p += s->stat_offset;
 714                data[i] = *(u32 *)p;
 715        }
 716}
 717
 718static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 719{
 720        struct bcmgenet_priv *priv = netdev_priv(dev);
 721        u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 722        u32 reg;
 723
 724        if (enable && !priv->clk_eee_enabled) {
 725                clk_prepare_enable(priv->clk_eee);
 726                priv->clk_eee_enabled = true;
 727        }
 728
 729        reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 730        if (enable)
 731                reg |= EEE_EN;
 732        else
 733                reg &= ~EEE_EN;
 734        bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 735
 736        /* Enable EEE and switch to a 27Mhz clock automatically */
 737        reg = __raw_readl(priv->base + off);
 738        if (enable)
 739                reg |= TBUF_EEE_EN | TBUF_PM_EN;
 740        else
 741                reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 742        __raw_writel(reg, priv->base + off);
 743
 744        /* Do the same for thing for RBUF */
 745        reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 746        if (enable)
 747                reg |= RBUF_EEE_EN | RBUF_PM_EN;
 748        else
 749                reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 750        bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 751
 752        if (!enable && priv->clk_eee_enabled) {
 753                clk_disable_unprepare(priv->clk_eee);
 754                priv->clk_eee_enabled = false;
 755        }
 756
 757        priv->eee.eee_enabled = enable;
 758        priv->eee.eee_active = enable;
 759}
 760
 761static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 762{
 763        struct bcmgenet_priv *priv = netdev_priv(dev);
 764        struct ethtool_eee *p = &priv->eee;
 765
 766        if (GENET_IS_V1(priv))
 767                return -EOPNOTSUPP;
 768
 769        e->eee_enabled = p->eee_enabled;
 770        e->eee_active = p->eee_active;
 771        e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 772
 773        return phy_ethtool_get_eee(priv->phydev, e);
 774}
 775
 776static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 777{
 778        struct bcmgenet_priv *priv = netdev_priv(dev);
 779        struct ethtool_eee *p = &priv->eee;
 780        int ret = 0;
 781
 782        if (GENET_IS_V1(priv))
 783                return -EOPNOTSUPP;
 784
 785        p->eee_enabled = e->eee_enabled;
 786
 787        if (!p->eee_enabled) {
 788                bcmgenet_eee_enable_set(dev, false);
 789        } else {
 790                ret = phy_init_eee(priv->phydev, 0);
 791                if (ret) {
 792                        netif_err(priv, hw, dev, "EEE initialization failed\n");
 793                        return ret;
 794                }
 795
 796                bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 797                bcmgenet_eee_enable_set(dev, true);
 798        }
 799
 800        return phy_ethtool_set_eee(priv->phydev, e);
 801}
 802
 803static int bcmgenet_nway_reset(struct net_device *dev)
 804{
 805        struct bcmgenet_priv *priv = netdev_priv(dev);
 806
 807        return genphy_restart_aneg(priv->phydev);
 808}
 809
 810/* standard ethtool support functions. */
 811static struct ethtool_ops bcmgenet_ethtool_ops = {
 812        .get_strings            = bcmgenet_get_strings,
 813        .get_sset_count         = bcmgenet_get_sset_count,
 814        .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 815        .get_settings           = bcmgenet_get_settings,
 816        .set_settings           = bcmgenet_set_settings,
 817        .get_drvinfo            = bcmgenet_get_drvinfo,
 818        .get_link               = ethtool_op_get_link,
 819        .get_msglevel           = bcmgenet_get_msglevel,
 820        .set_msglevel           = bcmgenet_set_msglevel,
 821        .get_wol                = bcmgenet_get_wol,
 822        .set_wol                = bcmgenet_set_wol,
 823        .get_eee                = bcmgenet_get_eee,
 824        .set_eee                = bcmgenet_set_eee,
 825        .nway_reset             = bcmgenet_nway_reset,
 826};
 827
 828/* Power down the unimac, based on mode. */
 829static void bcmgenet_power_down(struct bcmgenet_priv *priv,
 830                                enum bcmgenet_power_mode mode)
 831{
 832        u32 reg;
 833
 834        switch (mode) {
 835        case GENET_POWER_CABLE_SENSE:
 836                phy_detach(priv->phydev);
 837                break;
 838
 839        case GENET_POWER_WOL_MAGIC:
 840                bcmgenet_wol_power_down_cfg(priv, mode);
 841                break;
 842
 843        case GENET_POWER_PASSIVE:
 844                /* Power down LED */
 845                if (priv->hw_params->flags & GENET_HAS_EXT) {
 846                        reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 847                        reg |= (EXT_PWR_DOWN_PHY |
 848                                EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
 849                        bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 850                }
 851                break;
 852        default:
 853                break;
 854        }
 855}
 856
 857static void bcmgenet_power_up(struct bcmgenet_priv *priv,
 858                              enum bcmgenet_power_mode mode)
 859{
 860        u32 reg;
 861
 862        if (!(priv->hw_params->flags & GENET_HAS_EXT))
 863                return;
 864
 865        reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
 866
 867        switch (mode) {
 868        case GENET_POWER_PASSIVE:
 869                reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
 870                                EXT_PWR_DOWN_BIAS);
 871                /* fallthrough */
 872        case GENET_POWER_CABLE_SENSE:
 873                /* enable APD */
 874                reg |= EXT_PWR_DN_EN_LD;
 875                break;
 876        case GENET_POWER_WOL_MAGIC:
 877                bcmgenet_wol_power_up_cfg(priv, mode);
 878                return;
 879        default:
 880                break;
 881        }
 882
 883        bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
 884
 885        if (mode == GENET_POWER_PASSIVE)
 886                bcmgenet_mii_reset(priv->dev);
 887}
 888
 889/* ioctl handle special commands that are not present in ethtool. */
 890static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 891{
 892        struct bcmgenet_priv *priv = netdev_priv(dev);
 893        int val = 0;
 894
 895        if (!netif_running(dev))
 896                return -EINVAL;
 897
 898        switch (cmd) {
 899        case SIOCGMIIPHY:
 900        case SIOCGMIIREG:
 901        case SIOCSMIIREG:
 902                if (!priv->phydev)
 903                        val = -ENODEV;
 904                else
 905                        val = phy_mii_ioctl(priv->phydev, rq, cmd);
 906                break;
 907
 908        default:
 909                val = -EINVAL;
 910                break;
 911        }
 912
 913        return val;
 914}
 915
 916static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
 917                                         struct bcmgenet_tx_ring *ring)
 918{
 919        struct enet_cb *tx_cb_ptr;
 920
 921        tx_cb_ptr = ring->cbs;
 922        tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
 923        tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE;
 924        /* Advancing local write pointer */
 925        if (ring->write_ptr == ring->end_ptr)
 926                ring->write_ptr = ring->cb_ptr;
 927        else
 928                ring->write_ptr++;
 929
 930        return tx_cb_ptr;
 931}
 932
 933/* Simple helper to free a control block's resources */
 934static void bcmgenet_free_cb(struct enet_cb *cb)
 935{
 936        dev_kfree_skb_any(cb->skb);
 937        cb->skb = NULL;
 938        dma_unmap_addr_set(cb, dma_addr, 0);
 939}
 940
 941static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv,
 942                                                  struct bcmgenet_tx_ring *ring)
 943{
 944        bcmgenet_intrl2_0_writel(priv,
 945                                 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 946                                 INTRL2_CPU_MASK_SET);
 947}
 948
 949static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv,
 950                                                 struct bcmgenet_tx_ring *ring)
 951{
 952        bcmgenet_intrl2_0_writel(priv,
 953                                 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE,
 954                                 INTRL2_CPU_MASK_CLEAR);
 955}
 956
 957static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv,
 958                                               struct bcmgenet_tx_ring *ring)
 959{
 960        bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 961                                 INTRL2_CPU_MASK_CLEAR);
 962        priv->int1_mask &= ~(1 << ring->index);
 963}
 964
 965static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv,
 966                                                struct bcmgenet_tx_ring *ring)
 967{
 968        bcmgenet_intrl2_1_writel(priv, (1 << ring->index),
 969                                 INTRL2_CPU_MASK_SET);
 970        priv->int1_mask |= (1 << ring->index);
 971}
 972
 973/* Unlocked version of the reclaim routine */
 974static void __bcmgenet_tx_reclaim(struct net_device *dev,
 975                                  struct bcmgenet_tx_ring *ring)
 976{
 977        struct bcmgenet_priv *priv = netdev_priv(dev);
 978        int last_tx_cn, last_c_index, num_tx_bds;
 979        struct enet_cb *tx_cb_ptr;
 980        struct netdev_queue *txq;
 981        unsigned int bds_compl;
 982        unsigned int c_index;
 983
 984        /* Compute how many buffers are transmitted since last xmit call */
 985        c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
 986        txq = netdev_get_tx_queue(dev, ring->queue);
 987
 988        last_c_index = ring->c_index;
 989        num_tx_bds = ring->size;
 990
 991        c_index &= (num_tx_bds - 1);
 992
 993        if (c_index >= last_c_index)
 994                last_tx_cn = c_index - last_c_index;
 995        else
 996                last_tx_cn = num_tx_bds - last_c_index + c_index;
 997
 998        netif_dbg(priv, tx_done, dev,
 999                  "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
1000                  __func__, ring->index,
1001                  c_index, last_tx_cn, last_c_index);
1002
1003        /* Reclaim transmitted buffers */
1004        while (last_tx_cn-- > 0) {
1005                tx_cb_ptr = ring->cbs + last_c_index;
1006                bds_compl = 0;
1007                if (tx_cb_ptr->skb) {
1008                        bds_compl = skb_shinfo(tx_cb_ptr->skb)->nr_frags + 1;
1009                        dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1010                        dma_unmap_single(&dev->dev,
1011                                         dma_unmap_addr(tx_cb_ptr, dma_addr),
1012                                         tx_cb_ptr->skb->len,
1013                                         DMA_TO_DEVICE);
1014                        bcmgenet_free_cb(tx_cb_ptr);
1015                } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1016                        dev->stats.tx_bytes +=
1017                                dma_unmap_len(tx_cb_ptr, dma_len);
1018                        dma_unmap_page(&dev->dev,
1019                                       dma_unmap_addr(tx_cb_ptr, dma_addr),
1020                                       dma_unmap_len(tx_cb_ptr, dma_len),
1021                                       DMA_TO_DEVICE);
1022                        dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1023                }
1024                dev->stats.tx_packets++;
1025                ring->free_bds += bds_compl;
1026
1027                last_c_index++;
1028                last_c_index &= (num_tx_bds - 1);
1029        }
1030
1031        if (ring->free_bds > (MAX_SKB_FRAGS + 1))
1032                ring->int_disable(priv, ring);
1033
1034        if (netif_tx_queue_stopped(txq))
1035                netif_tx_wake_queue(txq);
1036
1037        ring->c_index = c_index;
1038}
1039
1040static void bcmgenet_tx_reclaim(struct net_device *dev,
1041                                struct bcmgenet_tx_ring *ring)
1042{
1043        unsigned long flags;
1044
1045        spin_lock_irqsave(&ring->lock, flags);
1046        __bcmgenet_tx_reclaim(dev, ring);
1047        spin_unlock_irqrestore(&ring->lock, flags);
1048}
1049
1050static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1051{
1052        struct bcmgenet_priv *priv = netdev_priv(dev);
1053        int i;
1054
1055        if (netif_is_multiqueue(dev)) {
1056                for (i = 0; i < priv->hw_params->tx_queues; i++)
1057                        bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1058        }
1059
1060        bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1061}
1062
1063/* Transmits a single SKB (either head of a fragment or a single SKB)
1064 * caller must hold priv->lock
1065 */
1066static int bcmgenet_xmit_single(struct net_device *dev,
1067                                struct sk_buff *skb,
1068                                u16 dma_desc_flags,
1069                                struct bcmgenet_tx_ring *ring)
1070{
1071        struct bcmgenet_priv *priv = netdev_priv(dev);
1072        struct device *kdev = &priv->pdev->dev;
1073        struct enet_cb *tx_cb_ptr;
1074        unsigned int skb_len;
1075        dma_addr_t mapping;
1076        u32 length_status;
1077        int ret;
1078
1079        tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1080
1081        if (unlikely(!tx_cb_ptr))
1082                BUG();
1083
1084        tx_cb_ptr->skb = skb;
1085
1086        skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1087
1088        mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1089        ret = dma_mapping_error(kdev, mapping);
1090        if (ret) {
1091                priv->mib.tx_dma_failed++;
1092                netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1093                dev_kfree_skb(skb);
1094                return ret;
1095        }
1096
1097        dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1098        dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1099        length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1100                        (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1101                        DMA_TX_APPEND_CRC;
1102
1103        if (skb->ip_summed == CHECKSUM_PARTIAL)
1104                length_status |= DMA_TX_DO_CSUM;
1105
1106        dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1107
1108        /* Decrement total BD count and advance our write pointer */
1109        ring->free_bds -= 1;
1110        ring->prod_index += 1;
1111        ring->prod_index &= DMA_P_INDEX_MASK;
1112
1113        return 0;
1114}
1115
1116/* Transmit a SKB fragment */
1117static int bcmgenet_xmit_frag(struct net_device *dev,
1118                              skb_frag_t *frag,
1119                              u16 dma_desc_flags,
1120                              struct bcmgenet_tx_ring *ring)
1121{
1122        struct bcmgenet_priv *priv = netdev_priv(dev);
1123        struct device *kdev = &priv->pdev->dev;
1124        struct enet_cb *tx_cb_ptr;
1125        dma_addr_t mapping;
1126        int ret;
1127
1128        tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1129
1130        if (unlikely(!tx_cb_ptr))
1131                BUG();
1132        tx_cb_ptr->skb = NULL;
1133
1134        mapping = skb_frag_dma_map(kdev, frag, 0,
1135                                   skb_frag_size(frag), DMA_TO_DEVICE);
1136        ret = dma_mapping_error(kdev, mapping);
1137        if (ret) {
1138                priv->mib.tx_dma_failed++;
1139                netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1140                          __func__);
1141                return ret;
1142        }
1143
1144        dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1145        dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1146
1147        dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1148                    (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1149                    (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1150
1151
1152        ring->free_bds -= 1;
1153        ring->prod_index += 1;
1154        ring->prod_index &= DMA_P_INDEX_MASK;
1155
1156        return 0;
1157}
1158
1159/* Reallocate the SKB to put enough headroom in front of it and insert
1160 * the transmit checksum offsets in the descriptors
1161 */
1162static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1163                                            struct sk_buff *skb)
1164{
1165        struct status_64 *status = NULL;
1166        struct sk_buff *new_skb;
1167        u16 offset;
1168        u8 ip_proto;
1169        u16 ip_ver;
1170        u32 tx_csum_info;
1171
1172        if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1173                /* If 64 byte status block enabled, must make sure skb has
1174                 * enough headroom for us to insert 64B status block.
1175                 */
1176                new_skb = skb_realloc_headroom(skb, sizeof(*status));
1177                dev_kfree_skb(skb);
1178                if (!new_skb) {
1179                        dev->stats.tx_errors++;
1180                        dev->stats.tx_dropped++;
1181                        return NULL;
1182                }
1183                skb = new_skb;
1184        }
1185
1186        skb_push(skb, sizeof(*status));
1187        status = (struct status_64 *)skb->data;
1188
1189        if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1190                ip_ver = htons(skb->protocol);
1191                switch (ip_ver) {
1192                case ETH_P_IP:
1193                        ip_proto = ip_hdr(skb)->protocol;
1194                        break;
1195                case ETH_P_IPV6:
1196                        ip_proto = ipv6_hdr(skb)->nexthdr;
1197                        break;
1198                default:
1199                        return skb;
1200                }
1201
1202                offset = skb_checksum_start_offset(skb) - sizeof(*status);
1203                tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1204                                (offset + skb->csum_offset);
1205
1206                /* Set the length valid bit for TCP and UDP and just set
1207                 * the special UDP flag for IPv4, else just set to 0.
1208                 */
1209                if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1210                        tx_csum_info |= STATUS_TX_CSUM_LV;
1211                        if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1212                                tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1213                } else {
1214                        tx_csum_info = 0;
1215                }
1216
1217                status->tx_csum_info = tx_csum_info;
1218        }
1219
1220        return skb;
1221}
1222
1223static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1224{
1225        struct bcmgenet_priv *priv = netdev_priv(dev);
1226        struct bcmgenet_tx_ring *ring = NULL;
1227        struct netdev_queue *txq;
1228        unsigned long flags = 0;
1229        int nr_frags, index;
1230        u16 dma_desc_flags;
1231        int ret;
1232        int i;
1233
1234        index = skb_get_queue_mapping(skb);
1235        /* Mapping strategy:
1236         * queue_mapping = 0, unclassified, packet xmited through ring16
1237         * queue_mapping = 1, goes to ring 0. (highest priority queue
1238         * queue_mapping = 2, goes to ring 1.
1239         * queue_mapping = 3, goes to ring 2.
1240         * queue_mapping = 4, goes to ring 3.
1241         */
1242        if (index == 0)
1243                index = DESC_INDEX;
1244        else
1245                index -= 1;
1246
1247        nr_frags = skb_shinfo(skb)->nr_frags;
1248        ring = &priv->tx_rings[index];
1249        txq = netdev_get_tx_queue(dev, ring->queue);
1250
1251        spin_lock_irqsave(&ring->lock, flags);
1252        if (ring->free_bds <= nr_frags + 1) {
1253                netif_tx_stop_queue(txq);
1254                netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1255                           __func__, index, ring->queue);
1256                ret = NETDEV_TX_BUSY;
1257                goto out;
1258        }
1259
1260        if (skb_padto(skb, ETH_ZLEN)) {
1261                ret = NETDEV_TX_OK;
1262                goto out;
1263        }
1264
1265        /* set the SKB transmit checksum */
1266        if (priv->desc_64b_en) {
1267                skb = bcmgenet_put_tx_csum(dev, skb);
1268                if (!skb) {
1269                        ret = NETDEV_TX_OK;
1270                        goto out;
1271                }
1272        }
1273
1274        dma_desc_flags = DMA_SOP;
1275        if (nr_frags == 0)
1276                dma_desc_flags |= DMA_EOP;
1277
1278        /* Transmit single SKB or head of fragment list */
1279        ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1280        if (ret) {
1281                ret = NETDEV_TX_OK;
1282                goto out;
1283        }
1284
1285        /* xmit fragment */
1286        for (i = 0; i < nr_frags; i++) {
1287                ret = bcmgenet_xmit_frag(dev,
1288                                         &skb_shinfo(skb)->frags[i],
1289                                         (i == nr_frags - 1) ? DMA_EOP : 0,
1290                                         ring);
1291                if (ret) {
1292                        ret = NETDEV_TX_OK;
1293                        goto out;
1294                }
1295        }
1296
1297        skb_tx_timestamp(skb);
1298
1299        /* we kept a software copy of how much we should advance the TDMA
1300         * producer index, now write it down to the hardware
1301         */
1302        bcmgenet_tdma_ring_writel(priv, ring->index,
1303                                  ring->prod_index, TDMA_PROD_INDEX);
1304
1305        if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) {
1306                netif_tx_stop_queue(txq);
1307                ring->int_enable(priv, ring);
1308        }
1309
1310out:
1311        spin_unlock_irqrestore(&ring->lock, flags);
1312
1313        return ret;
1314}
1315
1316
1317static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb)
1318{
1319        struct device *kdev = &priv->pdev->dev;
1320        struct sk_buff *skb;
1321        dma_addr_t mapping;
1322        int ret;
1323
1324        skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1325        if (!skb)
1326                return -ENOMEM;
1327
1328        /* a caller did not release this control block */
1329        WARN_ON(cb->skb != NULL);
1330        cb->skb = skb;
1331        mapping = dma_map_single(kdev, skb->data,
1332                                 priv->rx_buf_len, DMA_FROM_DEVICE);
1333        ret = dma_mapping_error(kdev, mapping);
1334        if (ret) {
1335                priv->mib.rx_dma_failed++;
1336                bcmgenet_free_cb(cb);
1337                netif_err(priv, rx_err, priv->dev,
1338                          "%s DMA map failed\n", __func__);
1339                return ret;
1340        }
1341
1342        dma_unmap_addr_set(cb, dma_addr, mapping);
1343        /* assign packet, prepare descriptor, and advance pointer */
1344
1345        dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping);
1346
1347        /* turn on the newly assigned BD for DMA to use */
1348        priv->rx_bd_assign_index++;
1349        priv->rx_bd_assign_index &= (priv->num_rx_bds - 1);
1350
1351        priv->rx_bd_assign_ptr = priv->rx_bds +
1352                (priv->rx_bd_assign_index * DMA_DESC_SIZE);
1353
1354        return 0;
1355}
1356
1357/* bcmgenet_desc_rx - descriptor based rx process.
1358 * this could be called from bottom half, or from NAPI polling method.
1359 */
1360static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv,
1361                                     unsigned int budget)
1362{
1363        struct net_device *dev = priv->dev;
1364        struct enet_cb *cb;
1365        struct sk_buff *skb;
1366        u32 dma_length_status;
1367        unsigned long dma_flag;
1368        int len, err;
1369        unsigned int rxpktprocessed = 0, rxpkttoprocess;
1370        unsigned int p_index;
1371        unsigned int chksum_ok = 0;
1372
1373        p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX);
1374        p_index &= DMA_P_INDEX_MASK;
1375
1376        if (p_index < priv->rx_c_index)
1377                rxpkttoprocess = (DMA_C_INDEX_MASK + 1) -
1378                        priv->rx_c_index + p_index;
1379        else
1380                rxpkttoprocess = p_index - priv->rx_c_index;
1381
1382        netif_dbg(priv, rx_status, dev,
1383                  "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1384
1385        while ((rxpktprocessed < rxpkttoprocess) &&
1386               (rxpktprocessed < budget)) {
1387                cb = &priv->rx_cbs[priv->rx_read_ptr];
1388                skb = cb->skb;
1389
1390                /* We do not have a backing SKB, so we do not have a
1391                 * corresponding DMA mapping for this incoming packet since
1392                 * bcmgenet_rx_refill always either has both skb and mapping or
1393                 * none.
1394                 */
1395                if (unlikely(!skb)) {
1396                        dev->stats.rx_dropped++;
1397                        dev->stats.rx_errors++;
1398                        goto refill;
1399                }
1400
1401                /* Unmap the packet contents such that we can use the
1402                 * RSV from the 64 bytes descriptor when enabled and save
1403                 * a 32-bits register read
1404                 */
1405                dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr),
1406                                 priv->rx_buf_len, DMA_FROM_DEVICE);
1407
1408                if (!priv->desc_64b_en) {
1409                        dma_length_status =
1410                                dmadesc_get_length_status(priv,
1411                                                          priv->rx_bds +
1412                                                          (priv->rx_read_ptr *
1413                                                           DMA_DESC_SIZE));
1414                } else {
1415                        struct status_64 *status;
1416
1417                        status = (struct status_64 *)skb->data;
1418                        dma_length_status = status->length_status;
1419                }
1420
1421                /* DMA flags and length are still valid no matter how
1422                 * we got the Receive Status Vector (64B RSB or register)
1423                 */
1424                dma_flag = dma_length_status & 0xffff;
1425                len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1426
1427                netif_dbg(priv, rx_status, dev,
1428                          "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1429                          __func__, p_index, priv->rx_c_index,
1430                          priv->rx_read_ptr, dma_length_status);
1431
1432                if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1433                        netif_err(priv, rx_status, dev,
1434                                  "dropping fragmented packet!\n");
1435                        dev->stats.rx_dropped++;
1436                        dev->stats.rx_errors++;
1437                        dev_kfree_skb_any(cb->skb);
1438                        cb->skb = NULL;
1439                        goto refill;
1440                }
1441                /* report errors */
1442                if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1443                                                DMA_RX_OV |
1444                                                DMA_RX_NO |
1445                                                DMA_RX_LG |
1446                                                DMA_RX_RXER))) {
1447                        netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1448                                  (unsigned int)dma_flag);
1449                        if (dma_flag & DMA_RX_CRC_ERROR)
1450                                dev->stats.rx_crc_errors++;
1451                        if (dma_flag & DMA_RX_OV)
1452                                dev->stats.rx_over_errors++;
1453                        if (dma_flag & DMA_RX_NO)
1454                                dev->stats.rx_frame_errors++;
1455                        if (dma_flag & DMA_RX_LG)
1456                                dev->stats.rx_length_errors++;
1457                        dev->stats.rx_dropped++;
1458                        dev->stats.rx_errors++;
1459
1460                        /* discard the packet and advance consumer index.*/
1461                        dev_kfree_skb_any(cb->skb);
1462                        cb->skb = NULL;
1463                        goto refill;
1464                } /* error packet */
1465
1466                chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1467                             priv->desc_rxchk_en;
1468
1469                skb_put(skb, len);
1470                if (priv->desc_64b_en) {
1471                        skb_pull(skb, 64);
1472                        len -= 64;
1473                }
1474
1475                if (likely(chksum_ok))
1476                        skb->ip_summed = CHECKSUM_UNNECESSARY;
1477
1478                /* remove hardware 2bytes added for IP alignment */
1479                skb_pull(skb, 2);
1480                len -= 2;
1481
1482                if (priv->crc_fwd_en) {
1483                        skb_trim(skb, len - ETH_FCS_LEN);
1484                        len -= ETH_FCS_LEN;
1485                }
1486
1487                /*Finish setting up the received SKB and send it to the kernel*/
1488                skb->protocol = eth_type_trans(skb, priv->dev);
1489                dev->stats.rx_packets++;
1490                dev->stats.rx_bytes += len;
1491                if (dma_flag & DMA_RX_MULT)
1492                        dev->stats.multicast++;
1493
1494                /* Notify kernel */
1495                napi_gro_receive(&priv->napi, skb);
1496                cb->skb = NULL;
1497                netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1498
1499                /* refill RX path on the current control block */
1500refill:
1501                err = bcmgenet_rx_refill(priv, cb);
1502                if (err) {
1503                        priv->mib.alloc_rx_buff_failed++;
1504                        netif_err(priv, rx_err, dev, "Rx refill failed\n");
1505                }
1506
1507                rxpktprocessed++;
1508                priv->rx_read_ptr++;
1509                priv->rx_read_ptr &= (priv->num_rx_bds - 1);
1510        }
1511
1512        return rxpktprocessed;
1513}
1514
1515/* Assign skb to RX DMA descriptor. */
1516static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv)
1517{
1518        struct enet_cb *cb;
1519        int ret = 0;
1520        int i;
1521
1522        netif_dbg(priv, hw, priv->dev, "%s:\n", __func__);
1523
1524        /* loop here for each buffer needing assign */
1525        for (i = 0; i < priv->num_rx_bds; i++) {
1526                cb = &priv->rx_cbs[priv->rx_bd_assign_index];
1527                if (cb->skb)
1528                        continue;
1529
1530                ret = bcmgenet_rx_refill(priv, cb);
1531                if (ret)
1532                        break;
1533        }
1534
1535        return ret;
1536}
1537
1538static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1539{
1540        struct enet_cb *cb;
1541        int i;
1542
1543        for (i = 0; i < priv->num_rx_bds; i++) {
1544                cb = &priv->rx_cbs[i];
1545
1546                if (dma_unmap_addr(cb, dma_addr)) {
1547                        dma_unmap_single(&priv->dev->dev,
1548                                         dma_unmap_addr(cb, dma_addr),
1549                                         priv->rx_buf_len, DMA_FROM_DEVICE);
1550                        dma_unmap_addr_set(cb, dma_addr, 0);
1551                }
1552
1553                if (cb->skb)
1554                        bcmgenet_free_cb(cb);
1555        }
1556}
1557
1558static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1559{
1560        u32 reg;
1561
1562        reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1563        if (enable)
1564                reg |= mask;
1565        else
1566                reg &= ~mask;
1567        bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1568
1569        /* UniMAC stops on a packet boundary, wait for a full-size packet
1570         * to be processed
1571         */
1572        if (enable == 0)
1573                usleep_range(1000, 2000);
1574}
1575
1576static int reset_umac(struct bcmgenet_priv *priv)
1577{
1578        struct device *kdev = &priv->pdev->dev;
1579        unsigned int timeout = 0;
1580        u32 reg;
1581
1582        /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1583        bcmgenet_rbuf_ctrl_set(priv, 0);
1584        udelay(10);
1585
1586        /* disable MAC while updating its registers */
1587        bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1588
1589        /* issue soft reset, wait for it to complete */
1590        bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1591        while (timeout++ < 1000) {
1592                reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1593                if (!(reg & CMD_SW_RESET))
1594                        return 0;
1595
1596                udelay(1);
1597        }
1598
1599        if (timeout == 1000) {
1600                dev_err(kdev,
1601                        "timeout waiting for MAC to come out of reset\n");
1602                return -ETIMEDOUT;
1603        }
1604
1605        return 0;
1606}
1607
1608static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1609{
1610        /* Mask all interrupts.*/
1611        bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1612        bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1613        bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1614        bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1615        bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1616        bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1617}
1618
1619static int init_umac(struct bcmgenet_priv *priv)
1620{
1621        struct device *kdev = &priv->pdev->dev;
1622        int ret;
1623        u32 reg, cpu_mask_clear;
1624
1625        dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1626
1627        ret = reset_umac(priv);
1628        if (ret)
1629                return ret;
1630
1631        bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1632        /* clear tx/rx counter */
1633        bcmgenet_umac_writel(priv,
1634                             MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1635                             UMAC_MIB_CTRL);
1636        bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1637
1638        bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1639
1640        /* init rx registers, enable ip header optimization */
1641        reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1642        reg |= RBUF_ALIGN_2B;
1643        bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1644
1645        if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1646                bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1647
1648        bcmgenet_intr_disable(priv);
1649
1650        cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE;
1651
1652        dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__);
1653
1654        /* Monitor cable plug/unplugged event for internal PHY */
1655        if (phy_is_internal(priv->phydev)) {
1656                cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1657        } else if (priv->ext_phy) {
1658                cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP);
1659        } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1660                reg = bcmgenet_bp_mc_get(priv);
1661                reg |= BIT(priv->hw_params->bp_in_en_shift);
1662
1663                /* bp_mask: back pressure mask */
1664                if (netif_is_multiqueue(priv->dev))
1665                        reg |= priv->hw_params->bp_in_mask;
1666                else
1667                        reg &= ~priv->hw_params->bp_in_mask;
1668                bcmgenet_bp_mc_set(priv, reg);
1669        }
1670
1671        /* Enable MDIO interrupts on GENET v3+ */
1672        if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1673                cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR;
1674
1675        bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR);
1676
1677        /* Enable rx/tx engine.*/
1678        dev_dbg(kdev, "done init umac\n");
1679
1680        return 0;
1681}
1682
1683/* Initialize all house-keeping variables for a TX ring, along
1684 * with corresponding hardware registers
1685 */
1686static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1687                                  unsigned int index, unsigned int size,
1688                                  unsigned int write_ptr, unsigned int end_ptr)
1689{
1690        struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1691        u32 words_per_bd = WORDS_PER_BD(priv);
1692        u32 flow_period_val = 0;
1693        unsigned int first_bd;
1694
1695        spin_lock_init(&ring->lock);
1696        ring->index = index;
1697        if (index == DESC_INDEX) {
1698                ring->queue = 0;
1699                ring->int_enable = bcmgenet_tx_ring16_int_enable;
1700                ring->int_disable = bcmgenet_tx_ring16_int_disable;
1701        } else {
1702                ring->queue = index + 1;
1703                ring->int_enable = bcmgenet_tx_ring_int_enable;
1704                ring->int_disable = bcmgenet_tx_ring_int_disable;
1705        }
1706        ring->cbs = priv->tx_cbs + write_ptr;
1707        ring->size = size;
1708        ring->c_index = 0;
1709        ring->free_bds = size;
1710        ring->write_ptr = write_ptr;
1711        ring->cb_ptr = write_ptr;
1712        ring->end_ptr = end_ptr - 1;
1713        ring->prod_index = 0;
1714
1715        /* Set flow period for ring != 16 */
1716        if (index != DESC_INDEX)
1717                flow_period_val = ENET_MAX_MTU_SIZE << 16;
1718
1719        bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1720        bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1721        bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1722        /* Disable rate control for now */
1723        bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1724                                  TDMA_FLOW_PERIOD);
1725        /* Unclassified traffic goes to ring 16 */
1726        bcmgenet_tdma_ring_writel(priv, index,
1727                                  ((size << DMA_RING_SIZE_SHIFT) |
1728                                   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1729
1730        first_bd = write_ptr;
1731
1732        /* Set start and end address, read and write pointers */
1733        bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1734                                  DMA_START_ADDR);
1735        bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd,
1736                                  TDMA_READ_PTR);
1737        bcmgenet_tdma_ring_writel(priv, index, first_bd,
1738                                  TDMA_WRITE_PTR);
1739        bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1740                                  DMA_END_ADDR);
1741}
1742
1743/* Initialize a RDMA ring */
1744static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1745                                 unsigned int index, unsigned int size)
1746{
1747        u32 words_per_bd = WORDS_PER_BD(priv);
1748        int ret;
1749
1750        priv->num_rx_bds = TOTAL_DESC;
1751        priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
1752        priv->rx_bd_assign_ptr = priv->rx_bds;
1753        priv->rx_bd_assign_index = 0;
1754        priv->rx_c_index = 0;
1755        priv->rx_read_ptr = 0;
1756        priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
1757                               GFP_KERNEL);
1758        if (!priv->rx_cbs)
1759                return -ENOMEM;
1760
1761        ret = bcmgenet_alloc_rx_buffers(priv);
1762        if (ret) {
1763                kfree(priv->rx_cbs);
1764                return ret;
1765        }
1766
1767        bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR);
1768        bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1769        bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1770        bcmgenet_rdma_ring_writel(priv, index,
1771                                  ((size << DMA_RING_SIZE_SHIFT) |
1772                                   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1773        bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR);
1774        bcmgenet_rdma_ring_writel(priv, index,
1775                                  words_per_bd * size - 1, DMA_END_ADDR);
1776        bcmgenet_rdma_ring_writel(priv, index,
1777                                  (DMA_FC_THRESH_LO <<
1778                                   DMA_XOFF_THRESHOLD_SHIFT) |
1779                                   DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1780        bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR);
1781
1782        return ret;
1783}
1784
1785/* init multi xmit queues, only available for GENET2+
1786 * the queue is partitioned as follows:
1787 *
1788 * queue 0 - 3 is priority based, each one has 32 descriptors,
1789 * with queue 0 being the highest priority queue.
1790 *
1791 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1792 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1793 * descriptors.
1794 *
1795 * The transmit control block pool is then partitioned as following:
1796 * - tx_cbs[0...127] are for queue 16
1797 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1798 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1799 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1800 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1801 */
1802static void bcmgenet_init_multiq(struct net_device *dev)
1803{
1804        struct bcmgenet_priv *priv = netdev_priv(dev);
1805        unsigned int i, dma_enable;
1806        u32 reg, dma_ctrl, ring_cfg = 0;
1807        u32 dma_priority[3] = {0, 0, 0};
1808
1809        if (!netif_is_multiqueue(dev)) {
1810                netdev_warn(dev, "called with non multi queue aware HW\n");
1811                return;
1812        }
1813
1814        dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1815        dma_enable = dma_ctrl & DMA_EN;
1816        dma_ctrl &= ~DMA_EN;
1817        bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1818
1819        /* Enable strict priority arbiter mode */
1820        bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1821
1822        for (i = 0; i < priv->hw_params->tx_queues; i++) {
1823                /* first 64 tx_cbs are reserved for default tx queue
1824                 * (ring 16)
1825                 */
1826                bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt,
1827                                      i * priv->hw_params->bds_cnt,
1828                                      (i + 1) * priv->hw_params->bds_cnt);
1829
1830                /* Configure ring as descriptor ring and setup priority */
1831                ring_cfg |= 1 << i;
1832                dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT);
1833
1834                dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1835                        ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1836        }
1837
1838        /* Set ring 16 priority and program the hardware registers */
1839        dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1840                ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1841                 DMA_PRIO_REG_SHIFT(DESC_INDEX));
1842        bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
1843        bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
1844        bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
1845
1846        /* Enable rings */
1847        reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG);
1848        reg |= ring_cfg;
1849        bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG);
1850
1851        /* Configure ring as descriptor ring and re-enable DMA if enabled */
1852        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1853        reg |= dma_ctrl;
1854        if (dma_enable)
1855                reg |= DMA_EN;
1856        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1857}
1858
1859static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
1860{
1861        int ret = 0;
1862        int timeout = 0;
1863        u32 reg;
1864
1865        /* Disable TDMA to stop add more frames in TX DMA */
1866        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
1867        reg &= ~DMA_EN;
1868        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
1869
1870        /* Check TDMA status register to confirm TDMA is disabled */
1871        while (timeout++ < DMA_TIMEOUT_VAL) {
1872                reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
1873                if (reg & DMA_DISABLED)
1874                        break;
1875
1876                udelay(1);
1877        }
1878
1879        if (timeout == DMA_TIMEOUT_VAL) {
1880                netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
1881                ret = -ETIMEDOUT;
1882        }
1883
1884        /* Wait 10ms for packet drain in both tx and rx dma */
1885        usleep_range(10000, 20000);
1886
1887        /* Disable RDMA */
1888        reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
1889        reg &= ~DMA_EN;
1890        bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
1891
1892        timeout = 0;
1893        /* Check RDMA status register to confirm RDMA is disabled */
1894        while (timeout++ < DMA_TIMEOUT_VAL) {
1895                reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
1896                if (reg & DMA_DISABLED)
1897                        break;
1898
1899                udelay(1);
1900        }
1901
1902        if (timeout == DMA_TIMEOUT_VAL) {
1903                netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
1904                ret = -ETIMEDOUT;
1905        }
1906
1907        return ret;
1908}
1909
1910static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
1911{
1912        int i;
1913
1914        /* disable DMA */
1915        bcmgenet_dma_teardown(priv);
1916
1917        for (i = 0; i < priv->num_tx_bds; i++) {
1918                if (priv->tx_cbs[i].skb != NULL) {
1919                        dev_kfree_skb(priv->tx_cbs[i].skb);
1920                        priv->tx_cbs[i].skb = NULL;
1921                }
1922        }
1923
1924        bcmgenet_free_rx_buffers(priv);
1925        kfree(priv->rx_cbs);
1926        kfree(priv->tx_cbs);
1927}
1928
1929/* init_edma: Initialize DMA control register */
1930static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
1931{
1932        int ret;
1933
1934        netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n");
1935
1936        /* by default, enable ring 16 (descriptor based) */
1937        ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC);
1938        if (ret) {
1939                netdev_err(priv->dev, "failed to initialize RX ring\n");
1940                return ret;
1941        }
1942
1943        /* init rDma */
1944        bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1945
1946        /* Init tDma */
1947        bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
1948
1949        /* Initialize common TX ring structures */
1950        priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
1951        priv->num_tx_bds = TOTAL_DESC;
1952        priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
1953                               GFP_KERNEL);
1954        if (!priv->tx_cbs) {
1955                bcmgenet_fini_dma(priv);
1956                return -ENOMEM;
1957        }
1958
1959        /* initialize multi xmit queue */
1960        bcmgenet_init_multiq(priv->dev);
1961
1962        /* initialize special ring 16 */
1963        bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT,
1964                              priv->hw_params->tx_queues *
1965                              priv->hw_params->bds_cnt,
1966                              TOTAL_DESC);
1967
1968        return 0;
1969}
1970
1971/* NAPI polling method*/
1972static int bcmgenet_poll(struct napi_struct *napi, int budget)
1973{
1974        struct bcmgenet_priv *priv = container_of(napi,
1975                        struct bcmgenet_priv, napi);
1976        unsigned int work_done;
1977
1978        /* tx reclaim */
1979        bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
1980
1981        work_done = bcmgenet_desc_rx(priv, budget);
1982
1983        /* Advancing our consumer index*/
1984        priv->rx_c_index += work_done;
1985        priv->rx_c_index &= DMA_C_INDEX_MASK;
1986        bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
1987                                  priv->rx_c_index, RDMA_CONS_INDEX);
1988        if (work_done < budget) {
1989                napi_complete(napi);
1990                bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
1991                                         INTRL2_CPU_MASK_CLEAR);
1992        }
1993
1994        return work_done;
1995}
1996
1997/* Interrupt bottom half */
1998static void bcmgenet_irq_task(struct work_struct *work)
1999{
2000        struct bcmgenet_priv *priv = container_of(
2001                        work, struct bcmgenet_priv, bcmgenet_irq_work);
2002
2003        netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2004
2005        if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2006                priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2007                netif_dbg(priv, wol, priv->dev,
2008                          "magic packet detected, waking up\n");
2009                bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2010        }
2011
2012        /* Link UP/DOWN event */
2013        if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2014            (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) {
2015                phy_mac_interrupt(priv->phydev,
2016                                  priv->irq0_stat & UMAC_IRQ_LINK_UP);
2017                priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN);
2018        }
2019}
2020
2021/* bcmgenet_isr1: interrupt handler for ring buffer. */
2022static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2023{
2024        struct bcmgenet_priv *priv = dev_id;
2025        unsigned int index;
2026
2027        /* Save irq status for bottom-half processing. */
2028        priv->irq1_stat =
2029                bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2030                ~priv->int1_mask;
2031        /* clear interrupts */
2032        bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2033
2034        netif_dbg(priv, intr, priv->dev,
2035                  "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2036        /* Check the MBDONE interrupts.
2037         * packet is done, reclaim descriptors
2038         */
2039        if (priv->irq1_stat & 0x0000ffff) {
2040                index = 0;
2041                for (index = 0; index < 16; index++) {
2042                        if (priv->irq1_stat & (1 << index))
2043                                bcmgenet_tx_reclaim(priv->dev,
2044                                                    &priv->tx_rings[index]);
2045                }
2046        }
2047        return IRQ_HANDLED;
2048}
2049
2050/* bcmgenet_isr0: Handle various interrupts. */
2051static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2052{
2053        struct bcmgenet_priv *priv = dev_id;
2054
2055        /* Save irq status for bottom-half processing. */
2056        priv->irq0_stat =
2057                bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2058                ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2059        /* clear interrupts */
2060        bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2061
2062        netif_dbg(priv, intr, priv->dev,
2063                  "IRQ=0x%x\n", priv->irq0_stat);
2064
2065        if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) {
2066                /* We use NAPI(software interrupt throttling, if
2067                 * Rx Descriptor throttling is not used.
2068                 * Disable interrupt, will be enabled in the poll method.
2069                 */
2070                if (likely(napi_schedule_prep(&priv->napi))) {
2071                        bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE,
2072                                                 INTRL2_CPU_MASK_SET);
2073                        __napi_schedule(&priv->napi);
2074                }
2075        }
2076        if (priv->irq0_stat &
2077                        (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) {
2078                /* Tx reclaim */
2079                bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]);
2080        }
2081        if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2082                                UMAC_IRQ_PHY_DET_F |
2083                                UMAC_IRQ_LINK_UP |
2084                                UMAC_IRQ_LINK_DOWN |
2085                                UMAC_IRQ_HFB_SM |
2086                                UMAC_IRQ_HFB_MM |
2087                                UMAC_IRQ_MPD_R)) {
2088                /* all other interested interrupts handled in bottom half */
2089                schedule_work(&priv->bcmgenet_irq_work);
2090        }
2091
2092        if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2093            priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2094                priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2095                wake_up(&priv->wq);
2096        }
2097
2098        return IRQ_HANDLED;
2099}
2100
2101static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2102{
2103        struct bcmgenet_priv *priv = dev_id;
2104
2105        pm_wakeup_event(&priv->pdev->dev, 0);
2106
2107        return IRQ_HANDLED;
2108}
2109
2110static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2111{
2112        u32 reg;
2113
2114        reg = bcmgenet_rbuf_ctrl_get(priv);
2115        reg |= BIT(1);
2116        bcmgenet_rbuf_ctrl_set(priv, reg);
2117        udelay(10);
2118
2119        reg &= ~BIT(1);
2120        bcmgenet_rbuf_ctrl_set(priv, reg);
2121        udelay(10);
2122}
2123
2124static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2125                                 unsigned char *addr)
2126{
2127        bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2128                        (addr[2] << 8) | addr[3], UMAC_MAC0);
2129        bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2130}
2131
2132/* Returns a reusable dma control register value */
2133static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2134{
2135        u32 reg;
2136        u32 dma_ctrl;
2137
2138        /* disable DMA */
2139        dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2140        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2141        reg &= ~dma_ctrl;
2142        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2143
2144        reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2145        reg &= ~dma_ctrl;
2146        bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2147
2148        bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2149        udelay(10);
2150        bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2151
2152        return dma_ctrl;
2153}
2154
2155static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2156{
2157        u32 reg;
2158
2159        reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2160        reg |= dma_ctrl;
2161        bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2162
2163        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2164        reg |= dma_ctrl;
2165        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2166}
2167
2168static void bcmgenet_netif_start(struct net_device *dev)
2169{
2170        struct bcmgenet_priv *priv = netdev_priv(dev);
2171
2172        /* Start the network engine */
2173        napi_enable(&priv->napi);
2174
2175        umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2176
2177        if (phy_is_internal(priv->phydev))
2178                bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2179
2180        netif_tx_start_all_queues(dev);
2181
2182        phy_start(priv->phydev);
2183}
2184
2185static int bcmgenet_open(struct net_device *dev)
2186{
2187        struct bcmgenet_priv *priv = netdev_priv(dev);
2188        unsigned long dma_ctrl;
2189        u32 reg;
2190        int ret;
2191
2192        netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2193
2194        /* Turn on the clock */
2195        if (!IS_ERR(priv->clk))
2196                clk_prepare_enable(priv->clk);
2197
2198        /* take MAC out of reset */
2199        bcmgenet_umac_reset(priv);
2200
2201        ret = init_umac(priv);
2202        if (ret)
2203                goto err_clk_disable;
2204
2205        /* disable ethernet MAC while updating its registers */
2206        umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2207
2208        /* Make sure we reflect the value of CRC_CMD_FWD */
2209        reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2210        priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2211
2212        bcmgenet_set_hw_addr(priv, dev->dev_addr);
2213
2214        if (phy_is_internal(priv->phydev)) {
2215                reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2216                reg |= EXT_ENERGY_DET_MASK;
2217                bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2218        }
2219
2220        /* Disable RX/TX DMA and flush TX queues */
2221        dma_ctrl = bcmgenet_dma_disable(priv);
2222
2223        /* Reinitialize TDMA and RDMA and SW housekeeping */
2224        ret = bcmgenet_init_dma(priv);
2225        if (ret) {
2226                netdev_err(dev, "failed to initialize DMA\n");
2227                goto err_fini_dma;
2228        }
2229
2230        /* Always enable ring 16 - descriptor ring */
2231        bcmgenet_enable_dma(priv, dma_ctrl);
2232
2233        ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2234                          dev->name, priv);
2235        if (ret < 0) {
2236                netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2237                goto err_fini_dma;
2238        }
2239
2240        ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2241                          dev->name, priv);
2242        if (ret < 0) {
2243                netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2244                goto err_irq0;
2245        }
2246
2247        /* Re-configure the port multiplexer towards the PHY device */
2248        bcmgenet_mii_config(priv->dev, false);
2249
2250        phy_connect_direct(dev, priv->phydev, bcmgenet_mii_setup,
2251                           priv->phy_interface);
2252
2253        bcmgenet_netif_start(dev);
2254
2255        return 0;
2256
2257err_irq0:
2258        free_irq(priv->irq0, dev);
2259err_fini_dma:
2260        bcmgenet_fini_dma(priv);
2261err_clk_disable:
2262        if (!IS_ERR(priv->clk))
2263                clk_disable_unprepare(priv->clk);
2264        return ret;
2265}
2266
2267static void bcmgenet_netif_stop(struct net_device *dev)
2268{
2269        struct bcmgenet_priv *priv = netdev_priv(dev);
2270
2271        netif_tx_stop_all_queues(dev);
2272        napi_disable(&priv->napi);
2273        phy_stop(priv->phydev);
2274
2275        bcmgenet_intr_disable(priv);
2276
2277        /* Wait for pending work items to complete. Since interrupts are
2278         * disabled no new work will be scheduled.
2279         */
2280        cancel_work_sync(&priv->bcmgenet_irq_work);
2281
2282        priv->old_link = -1;
2283        priv->old_speed = -1;
2284        priv->old_duplex = -1;
2285        priv->old_pause = -1;
2286}
2287
2288static int bcmgenet_close(struct net_device *dev)
2289{
2290        struct bcmgenet_priv *priv = netdev_priv(dev);
2291        int ret;
2292
2293        netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2294
2295        bcmgenet_netif_stop(dev);
2296
2297        /* Really kill the PHY state machine and disconnect from it */
2298        phy_disconnect(priv->phydev);
2299
2300        /* Disable MAC receive */
2301        umac_enable_set(priv, CMD_RX_EN, false);
2302
2303        ret = bcmgenet_dma_teardown(priv);
2304        if (ret)
2305                return ret;
2306
2307        /* Disable MAC transmit. TX DMA disabled have to done before this */
2308        umac_enable_set(priv, CMD_TX_EN, false);
2309
2310        /* tx reclaim */
2311        bcmgenet_tx_reclaim_all(dev);
2312        bcmgenet_fini_dma(priv);
2313
2314        free_irq(priv->irq0, priv);
2315        free_irq(priv->irq1, priv);
2316
2317        if (phy_is_internal(priv->phydev))
2318                bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2319
2320        if (!IS_ERR(priv->clk))
2321                clk_disable_unprepare(priv->clk);
2322
2323        return 0;
2324}
2325
2326static void bcmgenet_timeout(struct net_device *dev)
2327{
2328        struct bcmgenet_priv *priv = netdev_priv(dev);
2329
2330        netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2331
2332        dev->trans_start = jiffies;
2333
2334        dev->stats.tx_errors++;
2335
2336        netif_tx_wake_all_queues(dev);
2337}
2338
2339#define MAX_MC_COUNT    16
2340
2341static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2342                                         unsigned char *addr,
2343                                         int *i,
2344                                         int *mc)
2345{
2346        u32 reg;
2347
2348        bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2349                             UMAC_MDF_ADDR + (*i * 4));
2350        bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2351                             addr[4] << 8 | addr[5],
2352                             UMAC_MDF_ADDR + ((*i + 1) * 4));
2353        reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2354        reg |= (1 << (MAX_MC_COUNT - *mc));
2355        bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2356        *i += 2;
2357        (*mc)++;
2358}
2359
2360static void bcmgenet_set_rx_mode(struct net_device *dev)
2361{
2362        struct bcmgenet_priv *priv = netdev_priv(dev);
2363        struct netdev_hw_addr *ha;
2364        int i, mc;
2365        u32 reg;
2366
2367        netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2368
2369        /* Promiscuous mode */
2370        reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2371        if (dev->flags & IFF_PROMISC) {
2372                reg |= CMD_PROMISC;
2373                bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2374                bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2375                return;
2376        } else {
2377                reg &= ~CMD_PROMISC;
2378                bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2379        }
2380
2381        /* UniMac doesn't support ALLMULTI */
2382        if (dev->flags & IFF_ALLMULTI) {
2383                netdev_warn(dev, "ALLMULTI is not supported\n");
2384                return;
2385        }
2386
2387        /* update MDF filter */
2388        i = 0;
2389        mc = 0;
2390        /* Broadcast */
2391        bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2392        /* my own address.*/
2393        bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2394        /* Unicast list*/
2395        if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2396                return;
2397
2398        if (!netdev_uc_empty(dev))
2399                netdev_for_each_uc_addr(ha, dev)
2400                        bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2401        /* Multicast */
2402        if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2403                return;
2404
2405        netdev_for_each_mc_addr(ha, dev)
2406                bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2407}
2408
2409/* Set the hardware MAC address. */
2410static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2411{
2412        struct sockaddr *addr = p;
2413
2414        /* Setting the MAC address at the hardware level is not possible
2415         * without disabling the UniMAC RX/TX enable bits.
2416         */
2417        if (netif_running(dev))
2418                return -EBUSY;
2419
2420        ether_addr_copy(dev->dev_addr, addr->sa_data);
2421
2422        return 0;
2423}
2424
2425static const struct net_device_ops bcmgenet_netdev_ops = {
2426        .ndo_open               = bcmgenet_open,
2427        .ndo_stop               = bcmgenet_close,
2428        .ndo_start_xmit         = bcmgenet_xmit,
2429        .ndo_tx_timeout         = bcmgenet_timeout,
2430        .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
2431        .ndo_set_mac_address    = bcmgenet_set_mac_addr,
2432        .ndo_do_ioctl           = bcmgenet_ioctl,
2433        .ndo_set_features       = bcmgenet_set_features,
2434};
2435
2436/* Array of GENET hardware parameters/characteristics */
2437static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2438        [GENET_V1] = {
2439                .tx_queues = 0,
2440                .rx_queues = 0,
2441                .bds_cnt = 0,
2442                .bp_in_en_shift = 16,
2443                .bp_in_mask = 0xffff,
2444                .hfb_filter_cnt = 16,
2445                .qtag_mask = 0x1F,
2446                .hfb_offset = 0x1000,
2447                .rdma_offset = 0x2000,
2448                .tdma_offset = 0x3000,
2449                .words_per_bd = 2,
2450        },
2451        [GENET_V2] = {
2452                .tx_queues = 4,
2453                .rx_queues = 4,
2454                .bds_cnt = 32,
2455                .bp_in_en_shift = 16,
2456                .bp_in_mask = 0xffff,
2457                .hfb_filter_cnt = 16,
2458                .qtag_mask = 0x1F,
2459                .tbuf_offset = 0x0600,
2460                .hfb_offset = 0x1000,
2461                .hfb_reg_offset = 0x2000,
2462                .rdma_offset = 0x3000,
2463                .tdma_offset = 0x4000,
2464                .words_per_bd = 2,
2465                .flags = GENET_HAS_EXT,
2466        },
2467        [GENET_V3] = {
2468                .tx_queues = 4,
2469                .rx_queues = 4,
2470                .bds_cnt = 32,
2471                .bp_in_en_shift = 17,
2472                .bp_in_mask = 0x1ffff,
2473                .hfb_filter_cnt = 48,
2474                .qtag_mask = 0x3F,
2475                .tbuf_offset = 0x0600,
2476                .hfb_offset = 0x8000,
2477                .hfb_reg_offset = 0xfc00,
2478                .rdma_offset = 0x10000,
2479                .tdma_offset = 0x11000,
2480                .words_per_bd = 2,
2481                .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2482        },
2483        [GENET_V4] = {
2484                .tx_queues = 4,
2485                .rx_queues = 4,
2486                .bds_cnt = 32,
2487                .bp_in_en_shift = 17,
2488                .bp_in_mask = 0x1ffff,
2489                .hfb_filter_cnt = 48,
2490                .qtag_mask = 0x3F,
2491                .tbuf_offset = 0x0600,
2492                .hfb_offset = 0x8000,
2493                .hfb_reg_offset = 0xfc00,
2494                .rdma_offset = 0x2000,
2495                .tdma_offset = 0x4000,
2496                .words_per_bd = 3,
2497                .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR,
2498        },
2499};
2500
2501/* Infer hardware parameters from the detected GENET version */
2502static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
2503{
2504        struct bcmgenet_hw_params *params;
2505        u32 reg;
2506        u8 major;
2507        u16 gphy_rev;
2508
2509        if (GENET_IS_V4(priv)) {
2510                bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2511                genet_dma_ring_regs = genet_dma_ring_regs_v4;
2512                priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2513                priv->version = GENET_V4;
2514        } else if (GENET_IS_V3(priv)) {
2515                bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
2516                genet_dma_ring_regs = genet_dma_ring_regs_v123;
2517                priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
2518                priv->version = GENET_V3;
2519        } else if (GENET_IS_V2(priv)) {
2520                bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
2521                genet_dma_ring_regs = genet_dma_ring_regs_v123;
2522                priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2523                priv->version = GENET_V2;
2524        } else if (GENET_IS_V1(priv)) {
2525                bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
2526                genet_dma_ring_regs = genet_dma_ring_regs_v123;
2527                priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
2528                priv->version = GENET_V1;
2529        }
2530
2531        /* enum genet_version starts at 1 */
2532        priv->hw_params = &bcmgenet_hw_params[priv->version];
2533        params = priv->hw_params;
2534
2535        /* Read GENET HW version */
2536        reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
2537        major = (reg >> 24 & 0x0f);
2538        if (major == 5)
2539                major = 4;
2540        else if (major == 0)
2541                major = 1;
2542        if (major != priv->version) {
2543                dev_err(&priv->pdev->dev,
2544                        "GENET version mismatch, got: %d, configured for: %d\n",
2545                        major, priv->version);
2546        }
2547
2548        /* Print the GENET core version */
2549        dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
2550                 major, (reg >> 16) & 0x0f, reg & 0xffff);
2551
2552        /* Store the integrated PHY revision for the MDIO probing function
2553         * to pass this information to the PHY driver. The PHY driver expects
2554         * to find the PHY major revision in bits 15:8 while the GENET register
2555         * stores that information in bits 7:0, account for that.
2556         *
2557         * On newer chips, starting with PHY revision G0, a new scheme is
2558         * deployed similar to the Starfighter 2 switch with GPHY major
2559         * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2560         * is reserved as well as special value 0x01ff, we have a small
2561         * heuristic to check for the new GPHY revision and re-arrange things
2562         * so the GPHY driver is happy.
2563         */
2564        gphy_rev = reg & 0xffff;
2565
2566        /* This is the good old scheme, just GPHY major, no minor nor patch */
2567        if ((gphy_rev & 0xf0) != 0)
2568                priv->gphy_rev = gphy_rev << 8;
2569
2570        /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2571        else if ((gphy_rev & 0xff00) != 0)
2572                priv->gphy_rev = gphy_rev;
2573
2574        /* This is reserved so should require special treatment */
2575        else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
2576                pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
2577                return;
2578        }
2579
2580#ifdef CONFIG_PHYS_ADDR_T_64BIT
2581        if (!(params->flags & GENET_HAS_40BITS))
2582                pr_warn("GENET does not support 40-bits PA\n");
2583#endif
2584
2585        pr_debug("Configuration for version: %d\n"
2586                "TXq: %1d, RXq: %1d, BDs: %1d\n"
2587                "BP << en: %2d, BP msk: 0x%05x\n"
2588                "HFB count: %2d, QTAQ msk: 0x%05x\n"
2589                "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2590                "RDMA: 0x%05x, TDMA: 0x%05x\n"
2591                "Words/BD: %d\n",
2592                priv->version,
2593                params->tx_queues, params->rx_queues, params->bds_cnt,
2594                params->bp_in_en_shift, params->bp_in_mask,
2595                params->hfb_filter_cnt, params->qtag_mask,
2596                params->tbuf_offset, params->hfb_offset,
2597                params->hfb_reg_offset,
2598                params->rdma_offset, params->tdma_offset,
2599                params->words_per_bd);
2600}
2601
2602static const struct of_device_id bcmgenet_match[] = {
2603        { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
2604        { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
2605        { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
2606        { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
2607        { },
2608};
2609
2610static int bcmgenet_probe(struct platform_device *pdev)
2611{
2612        struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
2613        struct device_node *dn = pdev->dev.of_node;
2614        const struct of_device_id *of_id = NULL;
2615        struct bcmgenet_priv *priv;
2616        struct net_device *dev;
2617        const void *macaddr;
2618        struct resource *r;
2619        int err = -EIO;
2620
2621        /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2622        dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1);
2623        if (!dev) {
2624                dev_err(&pdev->dev, "can't allocate net device\n");
2625                return -ENOMEM;
2626        }
2627
2628        if (dn) {
2629                of_id = of_match_node(bcmgenet_match, dn);
2630                if (!of_id)
2631                        return -EINVAL;
2632        }
2633
2634        priv = netdev_priv(dev);
2635        priv->irq0 = platform_get_irq(pdev, 0);
2636        priv->irq1 = platform_get_irq(pdev, 1);
2637        priv->wol_irq = platform_get_irq(pdev, 2);
2638        if (!priv->irq0 || !priv->irq1) {
2639                dev_err(&pdev->dev, "can't find IRQs\n");
2640                err = -EINVAL;
2641                goto err;
2642        }
2643
2644        if (dn) {
2645                macaddr = of_get_mac_address(dn);
2646                if (!macaddr) {
2647                        dev_err(&pdev->dev, "can't find MAC address\n");
2648                        err = -EINVAL;
2649                        goto err;
2650                }
2651        } else {
2652                macaddr = pd->mac_address;
2653        }
2654
2655        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2656        priv->base = devm_ioremap_resource(&pdev->dev, r);
2657        if (IS_ERR(priv->base)) {
2658                err = PTR_ERR(priv->base);
2659                goto err;
2660        }
2661
2662        SET_NETDEV_DEV(dev, &pdev->dev);
2663        dev_set_drvdata(&pdev->dev, dev);
2664        ether_addr_copy(dev->dev_addr, macaddr);
2665        dev->watchdog_timeo = 2 * HZ;
2666        dev->ethtool_ops = &bcmgenet_ethtool_ops;
2667        dev->netdev_ops = &bcmgenet_netdev_ops;
2668        netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64);
2669
2670        priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
2671
2672        /* Set hardware features */
2673        dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
2674                NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
2675
2676        /* Request the WOL interrupt and advertise suspend if available */
2677        priv->wol_irq_disabled = true;
2678        err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
2679                               dev->name, priv);
2680        if (!err)
2681                device_set_wakeup_capable(&pdev->dev, 1);
2682
2683        /* Set the needed headroom to account for any possible
2684         * features enabling/disabling at runtime
2685         */
2686        dev->needed_headroom += 64;
2687
2688        netdev_boot_setup_check(dev);
2689
2690        priv->dev = dev;
2691        priv->pdev = pdev;
2692        if (of_id)
2693                priv->version = (enum bcmgenet_version)of_id->data;
2694        else
2695                priv->version = pd->genet_version;
2696
2697        priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
2698        if (IS_ERR(priv->clk))
2699                dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
2700
2701        if (!IS_ERR(priv->clk))
2702                clk_prepare_enable(priv->clk);
2703
2704        bcmgenet_set_hw_params(priv);
2705
2706        /* Mii wait queue */
2707        init_waitqueue_head(&priv->wq);
2708        /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2709        priv->rx_buf_len = RX_BUF_LENGTH;
2710        INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
2711
2712        priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
2713        if (IS_ERR(priv->clk_wol))
2714                dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
2715
2716        priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
2717        if (IS_ERR(priv->clk_eee)) {
2718                dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
2719                priv->clk_eee = NULL;
2720        }
2721
2722        err = reset_umac(priv);
2723        if (err)
2724                goto err_clk_disable;
2725
2726        err = bcmgenet_mii_init(dev);
2727        if (err)
2728                goto err_clk_disable;
2729
2730        /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
2731         * just the ring 16 descriptor based TX
2732         */
2733        netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
2734        netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
2735
2736        /* libphy will determine the link state */
2737        netif_carrier_off(dev);
2738
2739        /* Turn off the main clock, WOL clock is handled separately */
2740        if (!IS_ERR(priv->clk))
2741                clk_disable_unprepare(priv->clk);
2742
2743        err = register_netdev(dev);
2744        if (err)
2745                goto err;
2746
2747        return err;
2748
2749err_clk_disable:
2750        if (!IS_ERR(priv->clk))
2751                clk_disable_unprepare(priv->clk);
2752err:
2753        free_netdev(dev);
2754        return err;
2755}
2756
2757static int bcmgenet_remove(struct platform_device *pdev)
2758{
2759        struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
2760
2761        dev_set_drvdata(&pdev->dev, NULL);
2762        unregister_netdev(priv->dev);
2763        bcmgenet_mii_exit(priv->dev);
2764        free_netdev(priv->dev);
2765
2766        return 0;
2767}
2768
2769#ifdef CONFIG_PM_SLEEP
2770static int bcmgenet_suspend(struct device *d)
2771{
2772        struct net_device *dev = dev_get_drvdata(d);
2773        struct bcmgenet_priv *priv = netdev_priv(dev);
2774        int ret;
2775
2776        if (!netif_running(dev))
2777                return 0;
2778
2779        bcmgenet_netif_stop(dev);
2780
2781        phy_suspend(priv->phydev);
2782
2783        netif_device_detach(dev);
2784
2785        /* Disable MAC receive */
2786        umac_enable_set(priv, CMD_RX_EN, false);
2787
2788        ret = bcmgenet_dma_teardown(priv);
2789        if (ret)
2790                return ret;
2791
2792        /* Disable MAC transmit. TX DMA disabled have to done before this */
2793        umac_enable_set(priv, CMD_TX_EN, false);
2794
2795        /* tx reclaim */
2796        bcmgenet_tx_reclaim_all(dev);
2797        bcmgenet_fini_dma(priv);
2798
2799        /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2800        if (device_may_wakeup(d) && priv->wolopts) {
2801                bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
2802                clk_prepare_enable(priv->clk_wol);
2803        }
2804
2805        /* Turn off the clocks */
2806        clk_disable_unprepare(priv->clk);
2807
2808        return 0;
2809}
2810
2811static int bcmgenet_resume(struct device *d)
2812{
2813        struct net_device *dev = dev_get_drvdata(d);
2814        struct bcmgenet_priv *priv = netdev_priv(dev);
2815        unsigned long dma_ctrl;
2816        int ret;
2817        u32 reg;
2818
2819        if (!netif_running(dev))
2820                return 0;
2821
2822        /* Turn on the clock */
2823        ret = clk_prepare_enable(priv->clk);
2824        if (ret)
2825                return ret;
2826
2827        bcmgenet_umac_reset(priv);
2828
2829        ret = init_umac(priv);
2830        if (ret)
2831                goto out_clk_disable;
2832
2833        /* From WOL-enabled suspend, switch to regular clock */
2834        if (priv->wolopts)
2835                clk_disable_unprepare(priv->clk_wol);
2836
2837        phy_init_hw(priv->phydev);
2838        /* Speed settings must be restored */
2839        bcmgenet_mii_config(priv->dev, false);
2840
2841        /* disable ethernet MAC while updating its registers */
2842        umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2843
2844        bcmgenet_set_hw_addr(priv, dev->dev_addr);
2845
2846        if (phy_is_internal(priv->phydev)) {
2847                reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2848                reg |= EXT_ENERGY_DET_MASK;
2849                bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2850        }
2851
2852        if (priv->wolopts)
2853                bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2854
2855        /* Disable RX/TX DMA and flush TX queues */
2856        dma_ctrl = bcmgenet_dma_disable(priv);
2857
2858        /* Reinitialize TDMA and RDMA and SW housekeeping */
2859        ret = bcmgenet_init_dma(priv);
2860        if (ret) {
2861                netdev_err(dev, "failed to initialize DMA\n");
2862                goto out_clk_disable;
2863        }
2864
2865        /* Always enable ring 16 - descriptor ring */
2866        bcmgenet_enable_dma(priv, dma_ctrl);
2867
2868        netif_device_attach(dev);
2869
2870        phy_resume(priv->phydev);
2871
2872        if (priv->eee.eee_enabled)
2873                bcmgenet_eee_enable_set(dev, true);
2874
2875        bcmgenet_netif_start(dev);
2876
2877        return 0;
2878
2879out_clk_disable:
2880        clk_disable_unprepare(priv->clk);
2881        return ret;
2882}
2883#endif /* CONFIG_PM_SLEEP */
2884
2885static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
2886
2887static struct platform_driver bcmgenet_driver = {
2888        .probe  = bcmgenet_probe,
2889        .remove = bcmgenet_remove,
2890        .driver = {
2891                .name   = "bcmgenet",
2892                .of_match_table = bcmgenet_match,
2893                .pm     = &bcmgenet_pm_ops,
2894        },
2895};
2896module_platform_driver(bcmgenet_driver);
2897
2898MODULE_AUTHOR("Broadcom Corporation");
2899MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2900MODULE_ALIAS("platform:bcmgenet");
2901MODULE_LICENSE("GPL");
2902
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