linux/drivers/net/ethernet/broadcom/genet/bcmgenet.c
<<
>>
Prefs
   1/*
   2 * Broadcom GENET (Gigabit Ethernet) controller driver
   3 *
   4 * Copyright (c) 2014 Broadcom Corporation
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#define pr_fmt(fmt)                             "bcmgenet: " fmt
  12
  13#include <linux/kernel.h>
  14#include <linux/module.h>
  15#include <linux/sched.h>
  16#include <linux/types.h>
  17#include <linux/fcntl.h>
  18#include <linux/interrupt.h>
  19#include <linux/string.h>
  20#include <linux/if_ether.h>
  21#include <linux/init.h>
  22#include <linux/errno.h>
  23#include <linux/delay.h>
  24#include <linux/platform_device.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/pm.h>
  27#include <linux/clk.h>
  28#include <linux/of.h>
  29#include <linux/of_address.h>
  30#include <linux/of_irq.h>
  31#include <linux/of_net.h>
  32#include <linux/of_platform.h>
  33#include <net/arp.h>
  34
  35#include <linux/mii.h>
  36#include <linux/ethtool.h>
  37#include <linux/netdevice.h>
  38#include <linux/inetdevice.h>
  39#include <linux/etherdevice.h>
  40#include <linux/skbuff.h>
  41#include <linux/in.h>
  42#include <linux/ip.h>
  43#include <linux/ipv6.h>
  44#include <linux/phy.h>
  45#include <linux/platform_data/bcmgenet.h>
  46
  47#include <asm/unaligned.h>
  48
  49#include "bcmgenet.h"
  50
  51/* Maximum number of hardware queues, downsized if needed */
  52#define GENET_MAX_MQ_CNT        4
  53
  54/* Default highest priority queue for multi queue support */
  55#define GENET_Q0_PRIORITY       0
  56
  57#define GENET_Q16_RX_BD_CNT     \
  58        (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
  59#define GENET_Q16_TX_BD_CNT     \
  60        (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
  61
  62#define RX_BUF_LENGTH           2048
  63#define SKB_ALIGNMENT           32
  64
  65/* Tx/Rx DMA register offset, skip 256 descriptors */
  66#define WORDS_PER_BD(p)         (p->hw_params->words_per_bd)
  67#define DMA_DESC_SIZE           (WORDS_PER_BD(priv) * sizeof(u32))
  68
  69#define GENET_TDMA_REG_OFF      (priv->hw_params->tdma_offset + \
  70                                TOTAL_DESC * DMA_DESC_SIZE)
  71
  72#define GENET_RDMA_REG_OFF      (priv->hw_params->rdma_offset + \
  73                                TOTAL_DESC * DMA_DESC_SIZE)
  74
  75static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
  76                                             void __iomem *d, u32 value)
  77{
  78        __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
  79}
  80
  81static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
  82                                            void __iomem *d)
  83{
  84        return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
  85}
  86
  87static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
  88                                    void __iomem *d,
  89                                    dma_addr_t addr)
  90{
  91        __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
  92
  93        /* Register writes to GISB bus can take couple hundred nanoseconds
  94         * and are done for each packet, save these expensive writes unless
  95         * the platform is explicitly configured for 64-bits/LPAE.
  96         */
  97#ifdef CONFIG_PHYS_ADDR_T_64BIT
  98        if (priv->hw_params->flags & GENET_HAS_40BITS)
  99                __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
 100#endif
 101}
 102
 103/* Combined address + length/status setter */
 104static inline void dmadesc_set(struct bcmgenet_priv *priv,
 105                               void __iomem *d, dma_addr_t addr, u32 val)
 106{
 107        dmadesc_set_addr(priv, d, addr);
 108        dmadesc_set_length_status(priv, d, val);
 109}
 110
 111static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
 112                                          void __iomem *d)
 113{
 114        dma_addr_t addr;
 115
 116        addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
 117
 118        /* Register writes to GISB bus can take couple hundred nanoseconds
 119         * and are done for each packet, save these expensive writes unless
 120         * the platform is explicitly configured for 64-bits/LPAE.
 121         */
 122#ifdef CONFIG_PHYS_ADDR_T_64BIT
 123        if (priv->hw_params->flags & GENET_HAS_40BITS)
 124                addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
 125#endif
 126        return addr;
 127}
 128
 129#define GENET_VER_FMT   "%1d.%1d EPHY: 0x%04x"
 130
 131#define GENET_MSG_DEFAULT       (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
 132                                NETIF_MSG_LINK)
 133
 134static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
 135{
 136        if (GENET_IS_V1(priv))
 137                return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
 138        else
 139                return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
 140}
 141
 142static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 143{
 144        if (GENET_IS_V1(priv))
 145                bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
 146        else
 147                bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
 148}
 149
 150/* These macros are defined to deal with register map change
 151 * between GENET1.1 and GENET2. Only those currently being used
 152 * by driver are defined.
 153 */
 154static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
 155{
 156        if (GENET_IS_V1(priv))
 157                return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
 158        else
 159                return __raw_readl(priv->base +
 160                                priv->hw_params->tbuf_offset + TBUF_CTRL);
 161}
 162
 163static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
 164{
 165        if (GENET_IS_V1(priv))
 166                bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
 167        else
 168                __raw_writel(val, priv->base +
 169                                priv->hw_params->tbuf_offset + TBUF_CTRL);
 170}
 171
 172static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
 173{
 174        if (GENET_IS_V1(priv))
 175                return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
 176        else
 177                return __raw_readl(priv->base +
 178                                priv->hw_params->tbuf_offset + TBUF_BP_MC);
 179}
 180
 181static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
 182{
 183        if (GENET_IS_V1(priv))
 184                bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
 185        else
 186                __raw_writel(val, priv->base +
 187                                priv->hw_params->tbuf_offset + TBUF_BP_MC);
 188}
 189
 190/* RX/TX DMA register accessors */
 191enum dma_reg {
 192        DMA_RING_CFG = 0,
 193        DMA_CTRL,
 194        DMA_STATUS,
 195        DMA_SCB_BURST_SIZE,
 196        DMA_ARB_CTRL,
 197        DMA_PRIORITY_0,
 198        DMA_PRIORITY_1,
 199        DMA_PRIORITY_2,
 200        DMA_INDEX2RING_0,
 201        DMA_INDEX2RING_1,
 202        DMA_INDEX2RING_2,
 203        DMA_INDEX2RING_3,
 204        DMA_INDEX2RING_4,
 205        DMA_INDEX2RING_5,
 206        DMA_INDEX2RING_6,
 207        DMA_INDEX2RING_7,
 208        DMA_RING0_TIMEOUT,
 209        DMA_RING1_TIMEOUT,
 210        DMA_RING2_TIMEOUT,
 211        DMA_RING3_TIMEOUT,
 212        DMA_RING4_TIMEOUT,
 213        DMA_RING5_TIMEOUT,
 214        DMA_RING6_TIMEOUT,
 215        DMA_RING7_TIMEOUT,
 216        DMA_RING8_TIMEOUT,
 217        DMA_RING9_TIMEOUT,
 218        DMA_RING10_TIMEOUT,
 219        DMA_RING11_TIMEOUT,
 220        DMA_RING12_TIMEOUT,
 221        DMA_RING13_TIMEOUT,
 222        DMA_RING14_TIMEOUT,
 223        DMA_RING15_TIMEOUT,
 224        DMA_RING16_TIMEOUT,
 225};
 226
 227static const u8 bcmgenet_dma_regs_v3plus[] = {
 228        [DMA_RING_CFG]          = 0x00,
 229        [DMA_CTRL]              = 0x04,
 230        [DMA_STATUS]            = 0x08,
 231        [DMA_SCB_BURST_SIZE]    = 0x0C,
 232        [DMA_ARB_CTRL]          = 0x2C,
 233        [DMA_PRIORITY_0]        = 0x30,
 234        [DMA_PRIORITY_1]        = 0x34,
 235        [DMA_PRIORITY_2]        = 0x38,
 236        [DMA_RING0_TIMEOUT]     = 0x2C,
 237        [DMA_RING1_TIMEOUT]     = 0x30,
 238        [DMA_RING2_TIMEOUT]     = 0x34,
 239        [DMA_RING3_TIMEOUT]     = 0x38,
 240        [DMA_RING4_TIMEOUT]     = 0x3c,
 241        [DMA_RING5_TIMEOUT]     = 0x40,
 242        [DMA_RING6_TIMEOUT]     = 0x44,
 243        [DMA_RING7_TIMEOUT]     = 0x48,
 244        [DMA_RING8_TIMEOUT]     = 0x4c,
 245        [DMA_RING9_TIMEOUT]     = 0x50,
 246        [DMA_RING10_TIMEOUT]    = 0x54,
 247        [DMA_RING11_TIMEOUT]    = 0x58,
 248        [DMA_RING12_TIMEOUT]    = 0x5c,
 249        [DMA_RING13_TIMEOUT]    = 0x60,
 250        [DMA_RING14_TIMEOUT]    = 0x64,
 251        [DMA_RING15_TIMEOUT]    = 0x68,
 252        [DMA_RING16_TIMEOUT]    = 0x6C,
 253        [DMA_INDEX2RING_0]      = 0x70,
 254        [DMA_INDEX2RING_1]      = 0x74,
 255        [DMA_INDEX2RING_2]      = 0x78,
 256        [DMA_INDEX2RING_3]      = 0x7C,
 257        [DMA_INDEX2RING_4]      = 0x80,
 258        [DMA_INDEX2RING_5]      = 0x84,
 259        [DMA_INDEX2RING_6]      = 0x88,
 260        [DMA_INDEX2RING_7]      = 0x8C,
 261};
 262
 263static const u8 bcmgenet_dma_regs_v2[] = {
 264        [DMA_RING_CFG]          = 0x00,
 265        [DMA_CTRL]              = 0x04,
 266        [DMA_STATUS]            = 0x08,
 267        [DMA_SCB_BURST_SIZE]    = 0x0C,
 268        [DMA_ARB_CTRL]          = 0x30,
 269        [DMA_PRIORITY_0]        = 0x34,
 270        [DMA_PRIORITY_1]        = 0x38,
 271        [DMA_PRIORITY_2]        = 0x3C,
 272        [DMA_RING0_TIMEOUT]     = 0x2C,
 273        [DMA_RING1_TIMEOUT]     = 0x30,
 274        [DMA_RING2_TIMEOUT]     = 0x34,
 275        [DMA_RING3_TIMEOUT]     = 0x38,
 276        [DMA_RING4_TIMEOUT]     = 0x3c,
 277        [DMA_RING5_TIMEOUT]     = 0x40,
 278        [DMA_RING6_TIMEOUT]     = 0x44,
 279        [DMA_RING7_TIMEOUT]     = 0x48,
 280        [DMA_RING8_TIMEOUT]     = 0x4c,
 281        [DMA_RING9_TIMEOUT]     = 0x50,
 282        [DMA_RING10_TIMEOUT]    = 0x54,
 283        [DMA_RING11_TIMEOUT]    = 0x58,
 284        [DMA_RING12_TIMEOUT]    = 0x5c,
 285        [DMA_RING13_TIMEOUT]    = 0x60,
 286        [DMA_RING14_TIMEOUT]    = 0x64,
 287        [DMA_RING15_TIMEOUT]    = 0x68,
 288        [DMA_RING16_TIMEOUT]    = 0x6C,
 289};
 290
 291static const u8 bcmgenet_dma_regs_v1[] = {
 292        [DMA_CTRL]              = 0x00,
 293        [DMA_STATUS]            = 0x04,
 294        [DMA_SCB_BURST_SIZE]    = 0x0C,
 295        [DMA_ARB_CTRL]          = 0x30,
 296        [DMA_PRIORITY_0]        = 0x34,
 297        [DMA_PRIORITY_1]        = 0x38,
 298        [DMA_PRIORITY_2]        = 0x3C,
 299        [DMA_RING0_TIMEOUT]     = 0x2C,
 300        [DMA_RING1_TIMEOUT]     = 0x30,
 301        [DMA_RING2_TIMEOUT]     = 0x34,
 302        [DMA_RING3_TIMEOUT]     = 0x38,
 303        [DMA_RING4_TIMEOUT]     = 0x3c,
 304        [DMA_RING5_TIMEOUT]     = 0x40,
 305        [DMA_RING6_TIMEOUT]     = 0x44,
 306        [DMA_RING7_TIMEOUT]     = 0x48,
 307        [DMA_RING8_TIMEOUT]     = 0x4c,
 308        [DMA_RING9_TIMEOUT]     = 0x50,
 309        [DMA_RING10_TIMEOUT]    = 0x54,
 310        [DMA_RING11_TIMEOUT]    = 0x58,
 311        [DMA_RING12_TIMEOUT]    = 0x5c,
 312        [DMA_RING13_TIMEOUT]    = 0x60,
 313        [DMA_RING14_TIMEOUT]    = 0x64,
 314        [DMA_RING15_TIMEOUT]    = 0x68,
 315        [DMA_RING16_TIMEOUT]    = 0x6C,
 316};
 317
 318/* Set at runtime once bcmgenet version is known */
 319static const u8 *bcmgenet_dma_regs;
 320
 321static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
 322{
 323        return netdev_priv(dev_get_drvdata(dev));
 324}
 325
 326static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
 327                                      enum dma_reg r)
 328{
 329        return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 330                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 331}
 332
 333static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
 334                                        u32 val, enum dma_reg r)
 335{
 336        __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 337                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 338}
 339
 340static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
 341                                      enum dma_reg r)
 342{
 343        return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 344                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 345}
 346
 347static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
 348                                        u32 val, enum dma_reg r)
 349{
 350        __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 351                        DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
 352}
 353
 354/* RDMA/TDMA ring registers and accessors
 355 * we merge the common fields and just prefix with T/D the registers
 356 * having different meaning depending on the direction
 357 */
 358enum dma_ring_reg {
 359        TDMA_READ_PTR = 0,
 360        RDMA_WRITE_PTR = TDMA_READ_PTR,
 361        TDMA_READ_PTR_HI,
 362        RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
 363        TDMA_CONS_INDEX,
 364        RDMA_PROD_INDEX = TDMA_CONS_INDEX,
 365        TDMA_PROD_INDEX,
 366        RDMA_CONS_INDEX = TDMA_PROD_INDEX,
 367        DMA_RING_BUF_SIZE,
 368        DMA_START_ADDR,
 369        DMA_START_ADDR_HI,
 370        DMA_END_ADDR,
 371        DMA_END_ADDR_HI,
 372        DMA_MBUF_DONE_THRESH,
 373        TDMA_FLOW_PERIOD,
 374        RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
 375        TDMA_WRITE_PTR,
 376        RDMA_READ_PTR = TDMA_WRITE_PTR,
 377        TDMA_WRITE_PTR_HI,
 378        RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
 379};
 380
 381/* GENET v4 supports 40-bits pointer addressing
 382 * for obvious reasons the LO and HI word parts
 383 * are contiguous, but this offsets the other
 384 * registers.
 385 */
 386static const u8 genet_dma_ring_regs_v4[] = {
 387        [TDMA_READ_PTR]                 = 0x00,
 388        [TDMA_READ_PTR_HI]              = 0x04,
 389        [TDMA_CONS_INDEX]               = 0x08,
 390        [TDMA_PROD_INDEX]               = 0x0C,
 391        [DMA_RING_BUF_SIZE]             = 0x10,
 392        [DMA_START_ADDR]                = 0x14,
 393        [DMA_START_ADDR_HI]             = 0x18,
 394        [DMA_END_ADDR]                  = 0x1C,
 395        [DMA_END_ADDR_HI]               = 0x20,
 396        [DMA_MBUF_DONE_THRESH]          = 0x24,
 397        [TDMA_FLOW_PERIOD]              = 0x28,
 398        [TDMA_WRITE_PTR]                = 0x2C,
 399        [TDMA_WRITE_PTR_HI]             = 0x30,
 400};
 401
 402static const u8 genet_dma_ring_regs_v123[] = {
 403        [TDMA_READ_PTR]                 = 0x00,
 404        [TDMA_CONS_INDEX]               = 0x04,
 405        [TDMA_PROD_INDEX]               = 0x08,
 406        [DMA_RING_BUF_SIZE]             = 0x0C,
 407        [DMA_START_ADDR]                = 0x10,
 408        [DMA_END_ADDR]                  = 0x14,
 409        [DMA_MBUF_DONE_THRESH]          = 0x18,
 410        [TDMA_FLOW_PERIOD]              = 0x1C,
 411        [TDMA_WRITE_PTR]                = 0x20,
 412};
 413
 414/* Set at runtime once GENET version is known */
 415static const u8 *genet_dma_ring_regs;
 416
 417static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
 418                                           unsigned int ring,
 419                                           enum dma_ring_reg r)
 420{
 421        return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
 422                        (DMA_RING_SIZE * ring) +
 423                        genet_dma_ring_regs[r]);
 424}
 425
 426static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
 427                                             unsigned int ring, u32 val,
 428                                             enum dma_ring_reg r)
 429{
 430        __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
 431                        (DMA_RING_SIZE * ring) +
 432                        genet_dma_ring_regs[r]);
 433}
 434
 435static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
 436                                           unsigned int ring,
 437                                           enum dma_ring_reg r)
 438{
 439        return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
 440                        (DMA_RING_SIZE * ring) +
 441                        genet_dma_ring_regs[r]);
 442}
 443
 444static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
 445                                             unsigned int ring, u32 val,
 446                                             enum dma_ring_reg r)
 447{
 448        __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
 449                        (DMA_RING_SIZE * ring) +
 450                        genet_dma_ring_regs[r]);
 451}
 452
 453static int bcmgenet_get_link_ksettings(struct net_device *dev,
 454                                       struct ethtool_link_ksettings *cmd)
 455{
 456        struct bcmgenet_priv *priv = netdev_priv(dev);
 457
 458        if (!netif_running(dev))
 459                return -EINVAL;
 460
 461        if (!priv->phydev)
 462                return -ENODEV;
 463
 464        return phy_ethtool_ksettings_get(priv->phydev, cmd);
 465}
 466
 467static int bcmgenet_set_link_ksettings(struct net_device *dev,
 468                                       const struct ethtool_link_ksettings *cmd)
 469{
 470        struct bcmgenet_priv *priv = netdev_priv(dev);
 471
 472        if (!netif_running(dev))
 473                return -EINVAL;
 474
 475        if (!priv->phydev)
 476                return -ENODEV;
 477
 478        return phy_ethtool_ksettings_set(priv->phydev, cmd);
 479}
 480
 481static int bcmgenet_set_rx_csum(struct net_device *dev,
 482                                netdev_features_t wanted)
 483{
 484        struct bcmgenet_priv *priv = netdev_priv(dev);
 485        u32 rbuf_chk_ctrl;
 486        bool rx_csum_en;
 487
 488        rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
 489
 490        rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
 491
 492        /* enable rx checksumming */
 493        if (rx_csum_en)
 494                rbuf_chk_ctrl |= RBUF_RXCHK_EN;
 495        else
 496                rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
 497        priv->desc_rxchk_en = rx_csum_en;
 498
 499        /* If UniMAC forwards CRC, we need to skip over it to get
 500         * a valid CHK bit to be set in the per-packet status word
 501        */
 502        if (rx_csum_en && priv->crc_fwd_en)
 503                rbuf_chk_ctrl |= RBUF_SKIP_FCS;
 504        else
 505                rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
 506
 507        bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
 508
 509        return 0;
 510}
 511
 512static int bcmgenet_set_tx_csum(struct net_device *dev,
 513                                netdev_features_t wanted)
 514{
 515        struct bcmgenet_priv *priv = netdev_priv(dev);
 516        bool desc_64b_en;
 517        u32 tbuf_ctrl, rbuf_ctrl;
 518
 519        tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
 520        rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
 521
 522        desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
 523
 524        /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
 525        if (desc_64b_en) {
 526                tbuf_ctrl |= RBUF_64B_EN;
 527                rbuf_ctrl |= RBUF_64B_EN;
 528        } else {
 529                tbuf_ctrl &= ~RBUF_64B_EN;
 530                rbuf_ctrl &= ~RBUF_64B_EN;
 531        }
 532        priv->desc_64b_en = desc_64b_en;
 533
 534        bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
 535        bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
 536
 537        return 0;
 538}
 539
 540static int bcmgenet_set_features(struct net_device *dev,
 541                                 netdev_features_t features)
 542{
 543        netdev_features_t changed = features ^ dev->features;
 544        netdev_features_t wanted = dev->wanted_features;
 545        int ret = 0;
 546
 547        if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
 548                ret = bcmgenet_set_tx_csum(dev, wanted);
 549        if (changed & (NETIF_F_RXCSUM))
 550                ret = bcmgenet_set_rx_csum(dev, wanted);
 551
 552        return ret;
 553}
 554
 555static u32 bcmgenet_get_msglevel(struct net_device *dev)
 556{
 557        struct bcmgenet_priv *priv = netdev_priv(dev);
 558
 559        return priv->msg_enable;
 560}
 561
 562static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
 563{
 564        struct bcmgenet_priv *priv = netdev_priv(dev);
 565
 566        priv->msg_enable = level;
 567}
 568
 569static int bcmgenet_get_coalesce(struct net_device *dev,
 570                                 struct ethtool_coalesce *ec)
 571{
 572        struct bcmgenet_priv *priv = netdev_priv(dev);
 573
 574        ec->tx_max_coalesced_frames =
 575                bcmgenet_tdma_ring_readl(priv, DESC_INDEX,
 576                                         DMA_MBUF_DONE_THRESH);
 577        ec->rx_max_coalesced_frames =
 578                bcmgenet_rdma_ring_readl(priv, DESC_INDEX,
 579                                         DMA_MBUF_DONE_THRESH);
 580        ec->rx_coalesce_usecs =
 581                bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT) * 8192 / 1000;
 582
 583        return 0;
 584}
 585
 586static int bcmgenet_set_coalesce(struct net_device *dev,
 587                                 struct ethtool_coalesce *ec)
 588{
 589        struct bcmgenet_priv *priv = netdev_priv(dev);
 590        unsigned int i;
 591        u32 reg;
 592
 593        /* Base system clock is 125Mhz, DMA timeout is this reference clock
 594         * divided by 1024, which yields roughly 8.192us, our maximum value
 595         * has to fit in the DMA_TIMEOUT_MASK (16 bits)
 596         */
 597        if (ec->tx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 598            ec->tx_max_coalesced_frames == 0 ||
 599            ec->rx_max_coalesced_frames > DMA_INTR_THRESHOLD_MASK ||
 600            ec->rx_coalesce_usecs > (DMA_TIMEOUT_MASK * 8) + 1)
 601                return -EINVAL;
 602
 603        if (ec->rx_coalesce_usecs == 0 && ec->rx_max_coalesced_frames == 0)
 604                return -EINVAL;
 605
 606        /* GENET TDMA hardware does not support a configurable timeout, but will
 607         * always generate an interrupt either after MBDONE packets have been
 608         * transmitted, or when the ring is emtpy.
 609         */
 610        if (ec->tx_coalesce_usecs || ec->tx_coalesce_usecs_high ||
 611            ec->tx_coalesce_usecs_irq || ec->tx_coalesce_usecs_low)
 612                return -EOPNOTSUPP;
 613
 614        /* Program all TX queues with the same values, as there is no
 615         * ethtool knob to do coalescing on a per-queue basis
 616         */
 617        for (i = 0; i < priv->hw_params->tx_queues; i++)
 618                bcmgenet_tdma_ring_writel(priv, i,
 619                                          ec->tx_max_coalesced_frames,
 620                                          DMA_MBUF_DONE_THRESH);
 621        bcmgenet_tdma_ring_writel(priv, DESC_INDEX,
 622                                  ec->tx_max_coalesced_frames,
 623                                  DMA_MBUF_DONE_THRESH);
 624
 625        for (i = 0; i < priv->hw_params->rx_queues; i++) {
 626                bcmgenet_rdma_ring_writel(priv, i,
 627                                          ec->rx_max_coalesced_frames,
 628                                          DMA_MBUF_DONE_THRESH);
 629
 630                reg = bcmgenet_rdma_readl(priv, DMA_RING0_TIMEOUT + i);
 631                reg &= ~DMA_TIMEOUT_MASK;
 632                reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 633                bcmgenet_rdma_writel(priv, reg, DMA_RING0_TIMEOUT + i);
 634        }
 635
 636        bcmgenet_rdma_ring_writel(priv, DESC_INDEX,
 637                                  ec->rx_max_coalesced_frames,
 638                                  DMA_MBUF_DONE_THRESH);
 639
 640        reg = bcmgenet_rdma_readl(priv, DMA_RING16_TIMEOUT);
 641        reg &= ~DMA_TIMEOUT_MASK;
 642        reg |= DIV_ROUND_UP(ec->rx_coalesce_usecs * 1000, 8192);
 643        bcmgenet_rdma_writel(priv, reg, DMA_RING16_TIMEOUT);
 644
 645        return 0;
 646}
 647
 648/* standard ethtool support functions. */
 649enum bcmgenet_stat_type {
 650        BCMGENET_STAT_NETDEV = -1,
 651        BCMGENET_STAT_MIB_RX,
 652        BCMGENET_STAT_MIB_TX,
 653        BCMGENET_STAT_RUNT,
 654        BCMGENET_STAT_MISC,
 655        BCMGENET_STAT_SOFT,
 656};
 657
 658struct bcmgenet_stats {
 659        char stat_string[ETH_GSTRING_LEN];
 660        int stat_sizeof;
 661        int stat_offset;
 662        enum bcmgenet_stat_type type;
 663        /* reg offset from UMAC base for misc counters */
 664        u16 reg_offset;
 665};
 666
 667#define STAT_NETDEV(m) { \
 668        .stat_string = __stringify(m), \
 669        .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
 670        .stat_offset = offsetof(struct net_device_stats, m), \
 671        .type = BCMGENET_STAT_NETDEV, \
 672}
 673
 674#define STAT_GENET_MIB(str, m, _type) { \
 675        .stat_string = str, \
 676        .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 677        .stat_offset = offsetof(struct bcmgenet_priv, m), \
 678        .type = _type, \
 679}
 680
 681#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
 682#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
 683#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
 684#define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
 685
 686#define STAT_GENET_MISC(str, m, offset) { \
 687        .stat_string = str, \
 688        .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
 689        .stat_offset = offsetof(struct bcmgenet_priv, m), \
 690        .type = BCMGENET_STAT_MISC, \
 691        .reg_offset = offset, \
 692}
 693
 694
 695/* There is a 0xC gap between the end of RX and beginning of TX stats and then
 696 * between the end of TX stats and the beginning of the RX RUNT
 697 */
 698#define BCMGENET_STAT_OFFSET    0xc
 699
 700/* Hardware counters must be kept in sync because the order/offset
 701 * is important here (order in structure declaration = order in hardware)
 702 */
 703static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
 704        /* general stats */
 705        STAT_NETDEV(rx_packets),
 706        STAT_NETDEV(tx_packets),
 707        STAT_NETDEV(rx_bytes),
 708        STAT_NETDEV(tx_bytes),
 709        STAT_NETDEV(rx_errors),
 710        STAT_NETDEV(tx_errors),
 711        STAT_NETDEV(rx_dropped),
 712        STAT_NETDEV(tx_dropped),
 713        STAT_NETDEV(multicast),
 714        /* UniMAC RSV counters */
 715        STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
 716        STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
 717        STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
 718        STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
 719        STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
 720        STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
 721        STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
 722        STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
 723        STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
 724        STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
 725        STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
 726        STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
 727        STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
 728        STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
 729        STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
 730        STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
 731        STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
 732        STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
 733        STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
 734        STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
 735        STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
 736        STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
 737        STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
 738        STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
 739        STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
 740        STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
 741        STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
 742        STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
 743        STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
 744        /* UniMAC TSV counters */
 745        STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
 746        STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
 747        STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
 748        STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
 749        STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
 750        STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
 751        STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
 752        STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
 753        STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
 754        STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
 755        STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
 756        STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
 757        STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
 758        STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
 759        STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
 760        STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
 761        STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
 762        STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
 763        STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
 764        STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
 765        STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
 766        STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
 767        STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
 768        STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
 769        STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
 770        STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
 771        STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
 772        STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
 773        STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
 774        /* UniMAC RUNT counters */
 775        STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
 776        STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
 777        STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
 778        STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
 779        /* Misc UniMAC counters */
 780        STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
 781                        UMAC_RBUF_OVFL_CNT),
 782        STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
 783        STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
 784        STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
 785        STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
 786        STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
 787};
 788
 789#define BCMGENET_STATS_LEN      ARRAY_SIZE(bcmgenet_gstrings_stats)
 790
 791static void bcmgenet_get_drvinfo(struct net_device *dev,
 792                                 struct ethtool_drvinfo *info)
 793{
 794        strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
 795        strlcpy(info->version, "v2.0", sizeof(info->version));
 796}
 797
 798static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
 799{
 800        switch (string_set) {
 801        case ETH_SS_STATS:
 802                return BCMGENET_STATS_LEN;
 803        default:
 804                return -EOPNOTSUPP;
 805        }
 806}
 807
 808static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
 809                                 u8 *data)
 810{
 811        int i;
 812
 813        switch (stringset) {
 814        case ETH_SS_STATS:
 815                for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 816                        memcpy(data + i * ETH_GSTRING_LEN,
 817                               bcmgenet_gstrings_stats[i].stat_string,
 818                               ETH_GSTRING_LEN);
 819                }
 820                break;
 821        }
 822}
 823
 824static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
 825{
 826        int i, j = 0;
 827
 828        for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 829                const struct bcmgenet_stats *s;
 830                u8 offset = 0;
 831                u32 val = 0;
 832                char *p;
 833
 834                s = &bcmgenet_gstrings_stats[i];
 835                switch (s->type) {
 836                case BCMGENET_STAT_NETDEV:
 837                case BCMGENET_STAT_SOFT:
 838                        continue;
 839                case BCMGENET_STAT_MIB_RX:
 840                case BCMGENET_STAT_MIB_TX:
 841                case BCMGENET_STAT_RUNT:
 842                        if (s->type != BCMGENET_STAT_MIB_RX)
 843                                offset = BCMGENET_STAT_OFFSET;
 844                        val = bcmgenet_umac_readl(priv,
 845                                                  UMAC_MIB_START + j + offset);
 846                        break;
 847                case BCMGENET_STAT_MISC:
 848                        val = bcmgenet_umac_readl(priv, s->reg_offset);
 849                        /* clear if overflowed */
 850                        if (val == ~0)
 851                                bcmgenet_umac_writel(priv, 0, s->reg_offset);
 852                        break;
 853                }
 854
 855                j += s->stat_sizeof;
 856                p = (char *)priv + s->stat_offset;
 857                *(u32 *)p = val;
 858        }
 859}
 860
 861static void bcmgenet_get_ethtool_stats(struct net_device *dev,
 862                                       struct ethtool_stats *stats,
 863                                       u64 *data)
 864{
 865        struct bcmgenet_priv *priv = netdev_priv(dev);
 866        int i;
 867
 868        if (netif_running(dev))
 869                bcmgenet_update_mib_counters(priv);
 870
 871        for (i = 0; i < BCMGENET_STATS_LEN; i++) {
 872                const struct bcmgenet_stats *s;
 873                char *p;
 874
 875                s = &bcmgenet_gstrings_stats[i];
 876                if (s->type == BCMGENET_STAT_NETDEV)
 877                        p = (char *)&dev->stats;
 878                else
 879                        p = (char *)priv;
 880                p += s->stat_offset;
 881                if (sizeof(unsigned long) != sizeof(u32) &&
 882                    s->stat_sizeof == sizeof(unsigned long))
 883                        data[i] = *(unsigned long *)p;
 884                else
 885                        data[i] = *(u32 *)p;
 886        }
 887}
 888
 889static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
 890{
 891        struct bcmgenet_priv *priv = netdev_priv(dev);
 892        u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
 893        u32 reg;
 894
 895        if (enable && !priv->clk_eee_enabled) {
 896                clk_prepare_enable(priv->clk_eee);
 897                priv->clk_eee_enabled = true;
 898        }
 899
 900        reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
 901        if (enable)
 902                reg |= EEE_EN;
 903        else
 904                reg &= ~EEE_EN;
 905        bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
 906
 907        /* Enable EEE and switch to a 27Mhz clock automatically */
 908        reg = __raw_readl(priv->base + off);
 909        if (enable)
 910                reg |= TBUF_EEE_EN | TBUF_PM_EN;
 911        else
 912                reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
 913        __raw_writel(reg, priv->base + off);
 914
 915        /* Do the same for thing for RBUF */
 916        reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
 917        if (enable)
 918                reg |= RBUF_EEE_EN | RBUF_PM_EN;
 919        else
 920                reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
 921        bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
 922
 923        if (!enable && priv->clk_eee_enabled) {
 924                clk_disable_unprepare(priv->clk_eee);
 925                priv->clk_eee_enabled = false;
 926        }
 927
 928        priv->eee.eee_enabled = enable;
 929        priv->eee.eee_active = enable;
 930}
 931
 932static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
 933{
 934        struct bcmgenet_priv *priv = netdev_priv(dev);
 935        struct ethtool_eee *p = &priv->eee;
 936
 937        if (GENET_IS_V1(priv))
 938                return -EOPNOTSUPP;
 939
 940        e->eee_enabled = p->eee_enabled;
 941        e->eee_active = p->eee_active;
 942        e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
 943
 944        return phy_ethtool_get_eee(priv->phydev, e);
 945}
 946
 947static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
 948{
 949        struct bcmgenet_priv *priv = netdev_priv(dev);
 950        struct ethtool_eee *p = &priv->eee;
 951        int ret = 0;
 952
 953        if (GENET_IS_V1(priv))
 954                return -EOPNOTSUPP;
 955
 956        p->eee_enabled = e->eee_enabled;
 957
 958        if (!p->eee_enabled) {
 959                bcmgenet_eee_enable_set(dev, false);
 960        } else {
 961                ret = phy_init_eee(priv->phydev, 0);
 962                if (ret) {
 963                        netif_err(priv, hw, dev, "EEE initialization failed\n");
 964                        return ret;
 965                }
 966
 967                bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
 968                bcmgenet_eee_enable_set(dev, true);
 969        }
 970
 971        return phy_ethtool_set_eee(priv->phydev, e);
 972}
 973
 974/* standard ethtool support functions. */
 975static const struct ethtool_ops bcmgenet_ethtool_ops = {
 976        .get_strings            = bcmgenet_get_strings,
 977        .get_sset_count         = bcmgenet_get_sset_count,
 978        .get_ethtool_stats      = bcmgenet_get_ethtool_stats,
 979        .get_drvinfo            = bcmgenet_get_drvinfo,
 980        .get_link               = ethtool_op_get_link,
 981        .get_msglevel           = bcmgenet_get_msglevel,
 982        .set_msglevel           = bcmgenet_set_msglevel,
 983        .get_wol                = bcmgenet_get_wol,
 984        .set_wol                = bcmgenet_set_wol,
 985        .get_eee                = bcmgenet_get_eee,
 986        .set_eee                = bcmgenet_set_eee,
 987        .nway_reset             = phy_ethtool_nway_reset,
 988        .get_coalesce           = bcmgenet_get_coalesce,
 989        .set_coalesce           = bcmgenet_set_coalesce,
 990        .get_link_ksettings     = bcmgenet_get_link_ksettings,
 991        .set_link_ksettings     = bcmgenet_set_link_ksettings,
 992};
 993
 994/* Power down the unimac, based on mode. */
 995static int bcmgenet_power_down(struct bcmgenet_priv *priv,
 996                                enum bcmgenet_power_mode mode)
 997{
 998        int ret = 0;
 999        u32 reg;
1000
1001        switch (mode) {
1002        case GENET_POWER_CABLE_SENSE:
1003                phy_detach(priv->phydev);
1004                break;
1005
1006        case GENET_POWER_WOL_MAGIC:
1007                ret = bcmgenet_wol_power_down_cfg(priv, mode);
1008                break;
1009
1010        case GENET_POWER_PASSIVE:
1011                /* Power down LED */
1012                if (priv->hw_params->flags & GENET_HAS_EXT) {
1013                        reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1014                        reg |= (EXT_PWR_DOWN_PHY |
1015                                EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
1016                        bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1017
1018                        bcmgenet_phy_power_set(priv->dev, false);
1019                }
1020                break;
1021        default:
1022                break;
1023        }
1024
1025        return 0;
1026}
1027
1028static void bcmgenet_power_up(struct bcmgenet_priv *priv,
1029                              enum bcmgenet_power_mode mode)
1030{
1031        u32 reg;
1032
1033        if (!(priv->hw_params->flags & GENET_HAS_EXT))
1034                return;
1035
1036        reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
1037
1038        switch (mode) {
1039        case GENET_POWER_PASSIVE:
1040                reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
1041                                EXT_PWR_DOWN_BIAS);
1042                /* fallthrough */
1043        case GENET_POWER_CABLE_SENSE:
1044                /* enable APD */
1045                reg |= EXT_PWR_DN_EN_LD;
1046                break;
1047        case GENET_POWER_WOL_MAGIC:
1048                bcmgenet_wol_power_up_cfg(priv, mode);
1049                return;
1050        default:
1051                break;
1052        }
1053
1054        bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
1055        if (mode == GENET_POWER_PASSIVE) {
1056                bcmgenet_phy_power_set(priv->dev, true);
1057                bcmgenet_mii_reset(priv->dev);
1058        }
1059}
1060
1061/* ioctl handle special commands that are not present in ethtool. */
1062static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1063{
1064        struct bcmgenet_priv *priv = netdev_priv(dev);
1065        int val = 0;
1066
1067        if (!netif_running(dev))
1068                return -EINVAL;
1069
1070        switch (cmd) {
1071        case SIOCGMIIPHY:
1072        case SIOCGMIIREG:
1073        case SIOCSMIIREG:
1074                if (!priv->phydev)
1075                        val = -ENODEV;
1076                else
1077                        val = phy_mii_ioctl(priv->phydev, rq, cmd);
1078                break;
1079
1080        default:
1081                val = -EINVAL;
1082                break;
1083        }
1084
1085        return val;
1086}
1087
1088static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
1089                                         struct bcmgenet_tx_ring *ring)
1090{
1091        struct enet_cb *tx_cb_ptr;
1092
1093        tx_cb_ptr = ring->cbs;
1094        tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
1095
1096        /* Advancing local write pointer */
1097        if (ring->write_ptr == ring->end_ptr)
1098                ring->write_ptr = ring->cb_ptr;
1099        else
1100                ring->write_ptr++;
1101
1102        return tx_cb_ptr;
1103}
1104
1105/* Simple helper to free a control block's resources */
1106static void bcmgenet_free_cb(struct enet_cb *cb)
1107{
1108        dev_kfree_skb_any(cb->skb);
1109        cb->skb = NULL;
1110        dma_unmap_addr_set(cb, dma_addr, 0);
1111}
1112
1113static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
1114{
1115        bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1116                                 INTRL2_CPU_MASK_SET);
1117}
1118
1119static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
1120{
1121        bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
1122                                 INTRL2_CPU_MASK_CLEAR);
1123}
1124
1125static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
1126{
1127        bcmgenet_intrl2_1_writel(ring->priv,
1128                                 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1129                                 INTRL2_CPU_MASK_SET);
1130}
1131
1132static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
1133{
1134        bcmgenet_intrl2_1_writel(ring->priv,
1135                                 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
1136                                 INTRL2_CPU_MASK_CLEAR);
1137}
1138
1139static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
1140{
1141        bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1142                                 INTRL2_CPU_MASK_SET);
1143}
1144
1145static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1146{
1147        bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1148                                 INTRL2_CPU_MASK_CLEAR);
1149}
1150
1151static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1152{
1153        bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1154                                 INTRL2_CPU_MASK_CLEAR);
1155}
1156
1157static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1158{
1159        bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1160                                 INTRL2_CPU_MASK_SET);
1161}
1162
1163/* Unlocked version of the reclaim routine */
1164static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1165                                          struct bcmgenet_tx_ring *ring)
1166{
1167        struct bcmgenet_priv *priv = netdev_priv(dev);
1168        struct device *kdev = &priv->pdev->dev;
1169        struct enet_cb *tx_cb_ptr;
1170        struct netdev_queue *txq;
1171        unsigned int pkts_compl = 0;
1172        unsigned int bytes_compl = 0;
1173        unsigned int c_index;
1174        unsigned int txbds_ready;
1175        unsigned int txbds_processed = 0;
1176
1177        /* Compute how many buffers are transmitted since last xmit call */
1178        c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1179        c_index &= DMA_C_INDEX_MASK;
1180
1181        if (likely(c_index >= ring->c_index))
1182                txbds_ready = c_index - ring->c_index;
1183        else
1184                txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1185
1186        netif_dbg(priv, tx_done, dev,
1187                  "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1188                  __func__, ring->index, ring->c_index, c_index, txbds_ready);
1189
1190        /* Reclaim transmitted buffers */
1191        while (txbds_processed < txbds_ready) {
1192                tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1193                if (tx_cb_ptr->skb) {
1194                        pkts_compl++;
1195                        bytes_compl += GENET_CB(tx_cb_ptr->skb)->bytes_sent;
1196                        dma_unmap_single(kdev,
1197                                         dma_unmap_addr(tx_cb_ptr, dma_addr),
1198                                         dma_unmap_len(tx_cb_ptr, dma_len),
1199                                         DMA_TO_DEVICE);
1200                        bcmgenet_free_cb(tx_cb_ptr);
1201                } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1202                        dma_unmap_page(kdev,
1203                                       dma_unmap_addr(tx_cb_ptr, dma_addr),
1204                                       dma_unmap_len(tx_cb_ptr, dma_len),
1205                                       DMA_TO_DEVICE);
1206                        dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1207                }
1208
1209                txbds_processed++;
1210                if (likely(ring->clean_ptr < ring->end_ptr))
1211                        ring->clean_ptr++;
1212                else
1213                        ring->clean_ptr = ring->cb_ptr;
1214        }
1215
1216        ring->free_bds += txbds_processed;
1217        ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1218
1219        dev->stats.tx_packets += pkts_compl;
1220        dev->stats.tx_bytes += bytes_compl;
1221
1222        txq = netdev_get_tx_queue(dev, ring->queue);
1223        netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
1224
1225        if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1226                if (netif_tx_queue_stopped(txq))
1227                        netif_tx_wake_queue(txq);
1228        }
1229
1230        return pkts_compl;
1231}
1232
1233static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1234                                struct bcmgenet_tx_ring *ring)
1235{
1236        unsigned int released;
1237        unsigned long flags;
1238
1239        spin_lock_irqsave(&ring->lock, flags);
1240        released = __bcmgenet_tx_reclaim(dev, ring);
1241        spin_unlock_irqrestore(&ring->lock, flags);
1242
1243        return released;
1244}
1245
1246static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1247{
1248        struct bcmgenet_tx_ring *ring =
1249                container_of(napi, struct bcmgenet_tx_ring, napi);
1250        unsigned int work_done = 0;
1251
1252        work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1253
1254        if (work_done == 0) {
1255                napi_complete(napi);
1256                ring->int_enable(ring);
1257
1258                return 0;
1259        }
1260
1261        return budget;
1262}
1263
1264static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1265{
1266        struct bcmgenet_priv *priv = netdev_priv(dev);
1267        int i;
1268
1269        if (netif_is_multiqueue(dev)) {
1270                for (i = 0; i < priv->hw_params->tx_queues; i++)
1271                        bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1272        }
1273
1274        bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1275}
1276
1277/* Transmits a single SKB (either head of a fragment or a single SKB)
1278 * caller must hold priv->lock
1279 */
1280static int bcmgenet_xmit_single(struct net_device *dev,
1281                                struct sk_buff *skb,
1282                                u16 dma_desc_flags,
1283                                struct bcmgenet_tx_ring *ring)
1284{
1285        struct bcmgenet_priv *priv = netdev_priv(dev);
1286        struct device *kdev = &priv->pdev->dev;
1287        struct enet_cb *tx_cb_ptr;
1288        unsigned int skb_len;
1289        dma_addr_t mapping;
1290        u32 length_status;
1291        int ret;
1292
1293        tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1294
1295        if (unlikely(!tx_cb_ptr))
1296                BUG();
1297
1298        tx_cb_ptr->skb = skb;
1299
1300        skb_len = skb_headlen(skb);
1301
1302        mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1303        ret = dma_mapping_error(kdev, mapping);
1304        if (ret) {
1305                priv->mib.tx_dma_failed++;
1306                netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1307                dev_kfree_skb(skb);
1308                return ret;
1309        }
1310
1311        dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1312        dma_unmap_len_set(tx_cb_ptr, dma_len, skb_len);
1313        length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1314                        (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1315                        DMA_TX_APPEND_CRC;
1316
1317        if (skb->ip_summed == CHECKSUM_PARTIAL)
1318                length_status |= DMA_TX_DO_CSUM;
1319
1320        dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1321
1322        return 0;
1323}
1324
1325/* Transmit a SKB fragment */
1326static int bcmgenet_xmit_frag(struct net_device *dev,
1327                              skb_frag_t *frag,
1328                              u16 dma_desc_flags,
1329                              struct bcmgenet_tx_ring *ring)
1330{
1331        struct bcmgenet_priv *priv = netdev_priv(dev);
1332        struct device *kdev = &priv->pdev->dev;
1333        struct enet_cb *tx_cb_ptr;
1334        unsigned int frag_size;
1335        dma_addr_t mapping;
1336        int ret;
1337
1338        tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1339
1340        if (unlikely(!tx_cb_ptr))
1341                BUG();
1342
1343        tx_cb_ptr->skb = NULL;
1344
1345        frag_size = skb_frag_size(frag);
1346
1347        mapping = skb_frag_dma_map(kdev, frag, 0, frag_size, DMA_TO_DEVICE);
1348        ret = dma_mapping_error(kdev, mapping);
1349        if (ret) {
1350                priv->mib.tx_dma_failed++;
1351                netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1352                          __func__);
1353                return ret;
1354        }
1355
1356        dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1357        dma_unmap_len_set(tx_cb_ptr, dma_len, frag_size);
1358
1359        dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1360                    (frag_size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1361                    (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1362
1363        return 0;
1364}
1365
1366/* Reallocate the SKB to put enough headroom in front of it and insert
1367 * the transmit checksum offsets in the descriptors
1368 */
1369static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1370                                            struct sk_buff *skb)
1371{
1372        struct status_64 *status = NULL;
1373        struct sk_buff *new_skb;
1374        u16 offset;
1375        u8 ip_proto;
1376        u16 ip_ver;
1377        u32 tx_csum_info;
1378
1379        if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1380                /* If 64 byte status block enabled, must make sure skb has
1381                 * enough headroom for us to insert 64B status block.
1382                 */
1383                new_skb = skb_realloc_headroom(skb, sizeof(*status));
1384                dev_kfree_skb(skb);
1385                if (!new_skb) {
1386                        dev->stats.tx_dropped++;
1387                        return NULL;
1388                }
1389                skb = new_skb;
1390        }
1391
1392        skb_push(skb, sizeof(*status));
1393        status = (struct status_64 *)skb->data;
1394
1395        if (skb->ip_summed  == CHECKSUM_PARTIAL) {
1396                ip_ver = htons(skb->protocol);
1397                switch (ip_ver) {
1398                case ETH_P_IP:
1399                        ip_proto = ip_hdr(skb)->protocol;
1400                        break;
1401                case ETH_P_IPV6:
1402                        ip_proto = ipv6_hdr(skb)->nexthdr;
1403                        break;
1404                default:
1405                        return skb;
1406                }
1407
1408                offset = skb_checksum_start_offset(skb) - sizeof(*status);
1409                tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1410                                (offset + skb->csum_offset);
1411
1412                /* Set the length valid bit for TCP and UDP and just set
1413                 * the special UDP flag for IPv4, else just set to 0.
1414                 */
1415                if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1416                        tx_csum_info |= STATUS_TX_CSUM_LV;
1417                        if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1418                                tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1419                } else {
1420                        tx_csum_info = 0;
1421                }
1422
1423                status->tx_csum_info = tx_csum_info;
1424        }
1425
1426        return skb;
1427}
1428
1429static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1430{
1431        struct bcmgenet_priv *priv = netdev_priv(dev);
1432        struct bcmgenet_tx_ring *ring = NULL;
1433        struct netdev_queue *txq;
1434        unsigned long flags = 0;
1435        int nr_frags, index;
1436        u16 dma_desc_flags;
1437        int ret;
1438        int i;
1439
1440        index = skb_get_queue_mapping(skb);
1441        /* Mapping strategy:
1442         * queue_mapping = 0, unclassified, packet xmited through ring16
1443         * queue_mapping = 1, goes to ring 0. (highest priority queue
1444         * queue_mapping = 2, goes to ring 1.
1445         * queue_mapping = 3, goes to ring 2.
1446         * queue_mapping = 4, goes to ring 3.
1447         */
1448        if (index == 0)
1449                index = DESC_INDEX;
1450        else
1451                index -= 1;
1452
1453        ring = &priv->tx_rings[index];
1454        txq = netdev_get_tx_queue(dev, ring->queue);
1455
1456        nr_frags = skb_shinfo(skb)->nr_frags;
1457
1458        spin_lock_irqsave(&ring->lock, flags);
1459        if (ring->free_bds <= (nr_frags + 1)) {
1460                if (!netif_tx_queue_stopped(txq)) {
1461                        netif_tx_stop_queue(txq);
1462                        netdev_err(dev,
1463                                   "%s: tx ring %d full when queue %d awake\n",
1464                                   __func__, index, ring->queue);
1465                }
1466                ret = NETDEV_TX_BUSY;
1467                goto out;
1468        }
1469
1470        if (skb_padto(skb, ETH_ZLEN)) {
1471                ret = NETDEV_TX_OK;
1472                goto out;
1473        }
1474
1475        /* Retain how many bytes will be sent on the wire, without TSB inserted
1476         * by transmit checksum offload
1477         */
1478        GENET_CB(skb)->bytes_sent = skb->len;
1479
1480        /* set the SKB transmit checksum */
1481        if (priv->desc_64b_en) {
1482                skb = bcmgenet_put_tx_csum(dev, skb);
1483                if (!skb) {
1484                        ret = NETDEV_TX_OK;
1485                        goto out;
1486                }
1487        }
1488
1489        dma_desc_flags = DMA_SOP;
1490        if (nr_frags == 0)
1491                dma_desc_flags |= DMA_EOP;
1492
1493        /* Transmit single SKB or head of fragment list */
1494        ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1495        if (ret) {
1496                ret = NETDEV_TX_OK;
1497                goto out;
1498        }
1499
1500        /* xmit fragment */
1501        for (i = 0; i < nr_frags; i++) {
1502                ret = bcmgenet_xmit_frag(dev,
1503                                         &skb_shinfo(skb)->frags[i],
1504                                         (i == nr_frags - 1) ? DMA_EOP : 0,
1505                                         ring);
1506                if (ret) {
1507                        ret = NETDEV_TX_OK;
1508                        goto out;
1509                }
1510        }
1511
1512        skb_tx_timestamp(skb);
1513
1514        /* Decrement total BD count and advance our write pointer */
1515        ring->free_bds -= nr_frags + 1;
1516        ring->prod_index += nr_frags + 1;
1517        ring->prod_index &= DMA_P_INDEX_MASK;
1518
1519        netdev_tx_sent_queue(txq, GENET_CB(skb)->bytes_sent);
1520
1521        if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1522                netif_tx_stop_queue(txq);
1523
1524        if (!skb->xmit_more || netif_xmit_stopped(txq))
1525                /* Packets are ready, update producer index */
1526                bcmgenet_tdma_ring_writel(priv, ring->index,
1527                                          ring->prod_index, TDMA_PROD_INDEX);
1528out:
1529        spin_unlock_irqrestore(&ring->lock, flags);
1530
1531        return ret;
1532}
1533
1534static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1535                                          struct enet_cb *cb)
1536{
1537        struct device *kdev = &priv->pdev->dev;
1538        struct sk_buff *skb;
1539        struct sk_buff *rx_skb;
1540        dma_addr_t mapping;
1541
1542        /* Allocate a new Rx skb */
1543        skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1544        if (!skb) {
1545                priv->mib.alloc_rx_buff_failed++;
1546                netif_err(priv, rx_err, priv->dev,
1547                          "%s: Rx skb allocation failed\n", __func__);
1548                return NULL;
1549        }
1550
1551        /* DMA-map the new Rx skb */
1552        mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1553                                 DMA_FROM_DEVICE);
1554        if (dma_mapping_error(kdev, mapping)) {
1555                priv->mib.rx_dma_failed++;
1556                dev_kfree_skb_any(skb);
1557                netif_err(priv, rx_err, priv->dev,
1558                          "%s: Rx skb DMA mapping failed\n", __func__);
1559                return NULL;
1560        }
1561
1562        /* Grab the current Rx skb from the ring and DMA-unmap it */
1563        rx_skb = cb->skb;
1564        if (likely(rx_skb))
1565                dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1566                                 priv->rx_buf_len, DMA_FROM_DEVICE);
1567
1568        /* Put the new Rx skb on the ring */
1569        cb->skb = skb;
1570        dma_unmap_addr_set(cb, dma_addr, mapping);
1571        dmadesc_set_addr(priv, cb->bd_addr, mapping);
1572
1573        /* Return the current Rx skb to caller */
1574        return rx_skb;
1575}
1576
1577/* bcmgenet_desc_rx - descriptor based rx process.
1578 * this could be called from bottom half, or from NAPI polling method.
1579 */
1580static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1581                                     unsigned int budget)
1582{
1583        struct bcmgenet_priv *priv = ring->priv;
1584        struct net_device *dev = priv->dev;
1585        struct enet_cb *cb;
1586        struct sk_buff *skb;
1587        u32 dma_length_status;
1588        unsigned long dma_flag;
1589        int len;
1590        unsigned int rxpktprocessed = 0, rxpkttoprocess;
1591        unsigned int p_index;
1592        unsigned int discards;
1593        unsigned int chksum_ok = 0;
1594
1595        p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1596
1597        discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1598                   DMA_P_INDEX_DISCARD_CNT_MASK;
1599        if (discards > ring->old_discards) {
1600                discards = discards - ring->old_discards;
1601                dev->stats.rx_missed_errors += discards;
1602                dev->stats.rx_errors += discards;
1603                ring->old_discards += discards;
1604
1605                /* Clear HW register when we reach 75% of maximum 0xFFFF */
1606                if (ring->old_discards >= 0xC000) {
1607                        ring->old_discards = 0;
1608                        bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1609                                                  RDMA_PROD_INDEX);
1610                }
1611        }
1612
1613        p_index &= DMA_P_INDEX_MASK;
1614
1615        if (likely(p_index >= ring->c_index))
1616                rxpkttoprocess = p_index - ring->c_index;
1617        else
1618                rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1619                                 p_index;
1620
1621        netif_dbg(priv, rx_status, dev,
1622                  "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1623
1624        while ((rxpktprocessed < rxpkttoprocess) &&
1625               (rxpktprocessed < budget)) {
1626                cb = &priv->rx_cbs[ring->read_ptr];
1627                skb = bcmgenet_rx_refill(priv, cb);
1628
1629                if (unlikely(!skb)) {
1630                        dev->stats.rx_dropped++;
1631                        goto next;
1632                }
1633
1634                if (!priv->desc_64b_en) {
1635                        dma_length_status =
1636                                dmadesc_get_length_status(priv, cb->bd_addr);
1637                } else {
1638                        struct status_64 *status;
1639
1640                        status = (struct status_64 *)skb->data;
1641                        dma_length_status = status->length_status;
1642                }
1643
1644                /* DMA flags and length are still valid no matter how
1645                 * we got the Receive Status Vector (64B RSB or register)
1646                 */
1647                dma_flag = dma_length_status & 0xffff;
1648                len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1649
1650                netif_dbg(priv, rx_status, dev,
1651                          "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1652                          __func__, p_index, ring->c_index,
1653                          ring->read_ptr, dma_length_status);
1654
1655                if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1656                        netif_err(priv, rx_status, dev,
1657                                  "dropping fragmented packet!\n");
1658                        dev->stats.rx_errors++;
1659                        dev_kfree_skb_any(skb);
1660                        goto next;
1661                }
1662
1663                /* report errors */
1664                if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1665                                                DMA_RX_OV |
1666                                                DMA_RX_NO |
1667                                                DMA_RX_LG |
1668                                                DMA_RX_RXER))) {
1669                        netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1670                                  (unsigned int)dma_flag);
1671                        if (dma_flag & DMA_RX_CRC_ERROR)
1672                                dev->stats.rx_crc_errors++;
1673                        if (dma_flag & DMA_RX_OV)
1674                                dev->stats.rx_over_errors++;
1675                        if (dma_flag & DMA_RX_NO)
1676                                dev->stats.rx_frame_errors++;
1677                        if (dma_flag & DMA_RX_LG)
1678                                dev->stats.rx_length_errors++;
1679                        dev->stats.rx_errors++;
1680                        dev_kfree_skb_any(skb);
1681                        goto next;
1682                } /* error packet */
1683
1684                chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1685                             priv->desc_rxchk_en;
1686
1687                skb_put(skb, len);
1688                if (priv->desc_64b_en) {
1689                        skb_pull(skb, 64);
1690                        len -= 64;
1691                }
1692
1693                if (likely(chksum_ok))
1694                        skb->ip_summed = CHECKSUM_UNNECESSARY;
1695
1696                /* remove hardware 2bytes added for IP alignment */
1697                skb_pull(skb, 2);
1698                len -= 2;
1699
1700                if (priv->crc_fwd_en) {
1701                        skb_trim(skb, len - ETH_FCS_LEN);
1702                        len -= ETH_FCS_LEN;
1703                }
1704
1705                /*Finish setting up the received SKB and send it to the kernel*/
1706                skb->protocol = eth_type_trans(skb, priv->dev);
1707                dev->stats.rx_packets++;
1708                dev->stats.rx_bytes += len;
1709                if (dma_flag & DMA_RX_MULT)
1710                        dev->stats.multicast++;
1711
1712                /* Notify kernel */
1713                napi_gro_receive(&ring->napi, skb);
1714                netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1715
1716next:
1717                rxpktprocessed++;
1718                if (likely(ring->read_ptr < ring->end_ptr))
1719                        ring->read_ptr++;
1720                else
1721                        ring->read_ptr = ring->cb_ptr;
1722
1723                ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1724                bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1725        }
1726
1727        return rxpktprocessed;
1728}
1729
1730/* Rx NAPI polling method */
1731static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1732{
1733        struct bcmgenet_rx_ring *ring = container_of(napi,
1734                        struct bcmgenet_rx_ring, napi);
1735        unsigned int work_done;
1736
1737        work_done = bcmgenet_desc_rx(ring, budget);
1738
1739        if (work_done < budget) {
1740                napi_complete_done(napi, work_done);
1741                ring->int_enable(ring);
1742        }
1743
1744        return work_done;
1745}
1746
1747/* Assign skb to RX DMA descriptor. */
1748static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1749                                     struct bcmgenet_rx_ring *ring)
1750{
1751        struct enet_cb *cb;
1752        struct sk_buff *skb;
1753        int i;
1754
1755        netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1756
1757        /* loop here for each buffer needing assign */
1758        for (i = 0; i < ring->size; i++) {
1759                cb = ring->cbs + i;
1760                skb = bcmgenet_rx_refill(priv, cb);
1761                if (skb)
1762                        dev_kfree_skb_any(skb);
1763                if (!cb->skb)
1764                        return -ENOMEM;
1765        }
1766
1767        return 0;
1768}
1769
1770static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1771{
1772        struct device *kdev = &priv->pdev->dev;
1773        struct enet_cb *cb;
1774        int i;
1775
1776        for (i = 0; i < priv->num_rx_bds; i++) {
1777                cb = &priv->rx_cbs[i];
1778
1779                if (dma_unmap_addr(cb, dma_addr)) {
1780                        dma_unmap_single(kdev,
1781                                         dma_unmap_addr(cb, dma_addr),
1782                                         priv->rx_buf_len, DMA_FROM_DEVICE);
1783                        dma_unmap_addr_set(cb, dma_addr, 0);
1784                }
1785
1786                if (cb->skb)
1787                        bcmgenet_free_cb(cb);
1788        }
1789}
1790
1791static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1792{
1793        u32 reg;
1794
1795        reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1796        if (enable)
1797                reg |= mask;
1798        else
1799                reg &= ~mask;
1800        bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1801
1802        /* UniMAC stops on a packet boundary, wait for a full-size packet
1803         * to be processed
1804         */
1805        if (enable == 0)
1806                usleep_range(1000, 2000);
1807}
1808
1809static int reset_umac(struct bcmgenet_priv *priv)
1810{
1811        struct device *kdev = &priv->pdev->dev;
1812        unsigned int timeout = 0;
1813        u32 reg;
1814
1815        /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1816        bcmgenet_rbuf_ctrl_set(priv, 0);
1817        udelay(10);
1818
1819        /* disable MAC while updating its registers */
1820        bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1821
1822        /* issue soft reset, wait for it to complete */
1823        bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1824        while (timeout++ < 1000) {
1825                reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1826                if (!(reg & CMD_SW_RESET))
1827                        return 0;
1828
1829                udelay(1);
1830        }
1831
1832        if (timeout == 1000) {
1833                dev_err(kdev,
1834                        "timeout waiting for MAC to come out of reset\n");
1835                return -ETIMEDOUT;
1836        }
1837
1838        return 0;
1839}
1840
1841static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1842{
1843        /* Mask all interrupts.*/
1844        bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1845        bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1846        bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1847        bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1848        bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1849        bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1850}
1851
1852static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1853{
1854        u32 int0_enable = 0;
1855
1856        /* Monitor cable plug/unplugged event for internal PHY, external PHY
1857         * and MoCA PHY
1858         */
1859        if (priv->internal_phy) {
1860                int0_enable |= UMAC_IRQ_LINK_EVENT;
1861        } else if (priv->ext_phy) {
1862                int0_enable |= UMAC_IRQ_LINK_EVENT;
1863        } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1864                if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1865                        int0_enable |= UMAC_IRQ_LINK_EVENT;
1866        }
1867        bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1868}
1869
1870static int init_umac(struct bcmgenet_priv *priv)
1871{
1872        struct device *kdev = &priv->pdev->dev;
1873        int ret;
1874        u32 reg;
1875        u32 int0_enable = 0;
1876        u32 int1_enable = 0;
1877        int i;
1878
1879        dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1880
1881        ret = reset_umac(priv);
1882        if (ret)
1883                return ret;
1884
1885        bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1886        /* clear tx/rx counter */
1887        bcmgenet_umac_writel(priv,
1888                             MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1889                             UMAC_MIB_CTRL);
1890        bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1891
1892        bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1893
1894        /* init rx registers, enable ip header optimization */
1895        reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1896        reg |= RBUF_ALIGN_2B;
1897        bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1898
1899        if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1900                bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1901
1902        bcmgenet_intr_disable(priv);
1903
1904        /* Enable Rx default queue 16 interrupts */
1905        int0_enable |= UMAC_IRQ_RXDMA_DONE;
1906
1907        /* Enable Tx default queue 16 interrupts */
1908        int0_enable |= UMAC_IRQ_TXDMA_DONE;
1909
1910        /* Configure backpressure vectors for MoCA */
1911        if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1912                reg = bcmgenet_bp_mc_get(priv);
1913                reg |= BIT(priv->hw_params->bp_in_en_shift);
1914
1915                /* bp_mask: back pressure mask */
1916                if (netif_is_multiqueue(priv->dev))
1917                        reg |= priv->hw_params->bp_in_mask;
1918                else
1919                        reg &= ~priv->hw_params->bp_in_mask;
1920                bcmgenet_bp_mc_set(priv, reg);
1921        }
1922
1923        /* Enable MDIO interrupts on GENET v3+ */
1924        if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1925                int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1926
1927        /* Enable Rx priority queue interrupts */
1928        for (i = 0; i < priv->hw_params->rx_queues; ++i)
1929                int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1930
1931        /* Enable Tx priority queue interrupts */
1932        for (i = 0; i < priv->hw_params->tx_queues; ++i)
1933                int1_enable |= (1 << i);
1934
1935        bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1936        bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1937
1938        /* Enable rx/tx engine.*/
1939        dev_dbg(kdev, "done init umac\n");
1940
1941        return 0;
1942}
1943
1944/* Initialize a Tx ring along with corresponding hardware registers */
1945static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1946                                  unsigned int index, unsigned int size,
1947                                  unsigned int start_ptr, unsigned int end_ptr)
1948{
1949        struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1950        u32 words_per_bd = WORDS_PER_BD(priv);
1951        u32 flow_period_val = 0;
1952
1953        spin_lock_init(&ring->lock);
1954        ring->priv = priv;
1955        ring->index = index;
1956        if (index == DESC_INDEX) {
1957                ring->queue = 0;
1958                ring->int_enable = bcmgenet_tx_ring16_int_enable;
1959                ring->int_disable = bcmgenet_tx_ring16_int_disable;
1960        } else {
1961                ring->queue = index + 1;
1962                ring->int_enable = bcmgenet_tx_ring_int_enable;
1963                ring->int_disable = bcmgenet_tx_ring_int_disable;
1964        }
1965        ring->cbs = priv->tx_cbs + start_ptr;
1966        ring->size = size;
1967        ring->clean_ptr = start_ptr;
1968        ring->c_index = 0;
1969        ring->free_bds = size;
1970        ring->write_ptr = start_ptr;
1971        ring->cb_ptr = start_ptr;
1972        ring->end_ptr = end_ptr - 1;
1973        ring->prod_index = 0;
1974
1975        /* Set flow period for ring != 16 */
1976        if (index != DESC_INDEX)
1977                flow_period_val = ENET_MAX_MTU_SIZE << 16;
1978
1979        bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1980        bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1981        bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1982        /* Disable rate control for now */
1983        bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1984                                  TDMA_FLOW_PERIOD);
1985        bcmgenet_tdma_ring_writel(priv, index,
1986                                  ((size << DMA_RING_SIZE_SHIFT) |
1987                                   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1988
1989        /* Set start and end address, read and write pointers */
1990        bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1991                                  DMA_START_ADDR);
1992        bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1993                                  TDMA_READ_PTR);
1994        bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1995                                  TDMA_WRITE_PTR);
1996        bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1997                                  DMA_END_ADDR);
1998}
1999
2000/* Initialize a RDMA ring */
2001static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
2002                                 unsigned int index, unsigned int size,
2003                                 unsigned int start_ptr, unsigned int end_ptr)
2004{
2005        struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
2006        u32 words_per_bd = WORDS_PER_BD(priv);
2007        int ret;
2008
2009        ring->priv = priv;
2010        ring->index = index;
2011        if (index == DESC_INDEX) {
2012                ring->int_enable = bcmgenet_rx_ring16_int_enable;
2013                ring->int_disable = bcmgenet_rx_ring16_int_disable;
2014        } else {
2015                ring->int_enable = bcmgenet_rx_ring_int_enable;
2016                ring->int_disable = bcmgenet_rx_ring_int_disable;
2017        }
2018        ring->cbs = priv->rx_cbs + start_ptr;
2019        ring->size = size;
2020        ring->c_index = 0;
2021        ring->read_ptr = start_ptr;
2022        ring->cb_ptr = start_ptr;
2023        ring->end_ptr = end_ptr - 1;
2024
2025        ret = bcmgenet_alloc_rx_buffers(priv, ring);
2026        if (ret)
2027                return ret;
2028
2029        bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
2030        bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
2031        bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
2032        bcmgenet_rdma_ring_writel(priv, index,
2033                                  ((size << DMA_RING_SIZE_SHIFT) |
2034                                   RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
2035        bcmgenet_rdma_ring_writel(priv, index,
2036                                  (DMA_FC_THRESH_LO <<
2037                                   DMA_XOFF_THRESHOLD_SHIFT) |
2038                                   DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
2039
2040        /* Set start and end address, read and write pointers */
2041        bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2042                                  DMA_START_ADDR);
2043        bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2044                                  RDMA_READ_PTR);
2045        bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
2046                                  RDMA_WRITE_PTR);
2047        bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
2048                                  DMA_END_ADDR);
2049
2050        return ret;
2051}
2052
2053static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
2054{
2055        unsigned int i;
2056        struct bcmgenet_tx_ring *ring;
2057
2058        for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2059                ring = &priv->tx_rings[i];
2060                netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2061        }
2062
2063        ring = &priv->tx_rings[DESC_INDEX];
2064        netif_tx_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
2065}
2066
2067static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
2068{
2069        unsigned int i;
2070        struct bcmgenet_tx_ring *ring;
2071
2072        for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2073                ring = &priv->tx_rings[i];
2074                napi_enable(&ring->napi);
2075        }
2076
2077        ring = &priv->tx_rings[DESC_INDEX];
2078        napi_enable(&ring->napi);
2079}
2080
2081static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
2082{
2083        unsigned int i;
2084        struct bcmgenet_tx_ring *ring;
2085
2086        for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2087                ring = &priv->tx_rings[i];
2088                napi_disable(&ring->napi);
2089        }
2090
2091        ring = &priv->tx_rings[DESC_INDEX];
2092        napi_disable(&ring->napi);
2093}
2094
2095static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
2096{
2097        unsigned int i;
2098        struct bcmgenet_tx_ring *ring;
2099
2100        for (i = 0; i < priv->hw_params->tx_queues; ++i) {
2101                ring = &priv->tx_rings[i];
2102                netif_napi_del(&ring->napi);
2103        }
2104
2105        ring = &priv->tx_rings[DESC_INDEX];
2106        netif_napi_del(&ring->napi);
2107}
2108
2109/* Initialize Tx queues
2110 *
2111 * Queues 0-3 are priority-based, each one has 32 descriptors,
2112 * with queue 0 being the highest priority queue.
2113 *
2114 * Queue 16 is the default Tx queue with
2115 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
2116 *
2117 * The transmit control block pool is then partitioned as follows:
2118 * - Tx queue 0 uses tx_cbs[0..31]
2119 * - Tx queue 1 uses tx_cbs[32..63]
2120 * - Tx queue 2 uses tx_cbs[64..95]
2121 * - Tx queue 3 uses tx_cbs[96..127]
2122 * - Tx queue 16 uses tx_cbs[128..255]
2123 */
2124static void bcmgenet_init_tx_queues(struct net_device *dev)
2125{
2126        struct bcmgenet_priv *priv = netdev_priv(dev);
2127        u32 i, dma_enable;
2128        u32 dma_ctrl, ring_cfg;
2129        u32 dma_priority[3] = {0, 0, 0};
2130
2131        dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
2132        dma_enable = dma_ctrl & DMA_EN;
2133        dma_ctrl &= ~DMA_EN;
2134        bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2135
2136        dma_ctrl = 0;
2137        ring_cfg = 0;
2138
2139        /* Enable strict priority arbiter mode */
2140        bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
2141
2142        /* Initialize Tx priority queues */
2143        for (i = 0; i < priv->hw_params->tx_queues; i++) {
2144                bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
2145                                      i * priv->hw_params->tx_bds_per_q,
2146                                      (i + 1) * priv->hw_params->tx_bds_per_q);
2147                ring_cfg |= (1 << i);
2148                dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2149                dma_priority[DMA_PRIO_REG_INDEX(i)] |=
2150                        ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
2151        }
2152
2153        /* Initialize Tx default queue 16 */
2154        bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
2155                              priv->hw_params->tx_queues *
2156                              priv->hw_params->tx_bds_per_q,
2157                              TOTAL_DESC);
2158        ring_cfg |= (1 << DESC_INDEX);
2159        dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2160        dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
2161                ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
2162                 DMA_PRIO_REG_SHIFT(DESC_INDEX));
2163
2164        /* Set Tx queue priorities */
2165        bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2166        bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2167        bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2168
2169        /* Initialize Tx NAPI */
2170        bcmgenet_init_tx_napi(priv);
2171
2172        /* Enable Tx queues */
2173        bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2174
2175        /* Enable Tx DMA */
2176        if (dma_enable)
2177                dma_ctrl |= DMA_EN;
2178        bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2179}
2180
2181static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2182{
2183        unsigned int i;
2184        struct bcmgenet_rx_ring *ring;
2185
2186        for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2187                ring = &priv->rx_rings[i];
2188                netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2189        }
2190
2191        ring = &priv->rx_rings[DESC_INDEX];
2192        netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2193}
2194
2195static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2196{
2197        unsigned int i;
2198        struct bcmgenet_rx_ring *ring;
2199
2200        for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2201                ring = &priv->rx_rings[i];
2202                napi_enable(&ring->napi);
2203        }
2204
2205        ring = &priv->rx_rings[DESC_INDEX];
2206        napi_enable(&ring->napi);
2207}
2208
2209static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2210{
2211        unsigned int i;
2212        struct bcmgenet_rx_ring *ring;
2213
2214        for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2215                ring = &priv->rx_rings[i];
2216                napi_disable(&ring->napi);
2217        }
2218
2219        ring = &priv->rx_rings[DESC_INDEX];
2220        napi_disable(&ring->napi);
2221}
2222
2223static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2224{
2225        unsigned int i;
2226        struct bcmgenet_rx_ring *ring;
2227
2228        for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2229                ring = &priv->rx_rings[i];
2230                netif_napi_del(&ring->napi);
2231        }
2232
2233        ring = &priv->rx_rings[DESC_INDEX];
2234        netif_napi_del(&ring->napi);
2235}
2236
2237/* Initialize Rx queues
2238 *
2239 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2240 * used to direct traffic to these queues.
2241 *
2242 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2243 */
2244static int bcmgenet_init_rx_queues(struct net_device *dev)
2245{
2246        struct bcmgenet_priv *priv = netdev_priv(dev);
2247        u32 i;
2248        u32 dma_enable;
2249        u32 dma_ctrl;
2250        u32 ring_cfg;
2251        int ret;
2252
2253        dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2254        dma_enable = dma_ctrl & DMA_EN;
2255        dma_ctrl &= ~DMA_EN;
2256        bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2257
2258        dma_ctrl = 0;
2259        ring_cfg = 0;
2260
2261        /* Initialize Rx priority queues */
2262        for (i = 0; i < priv->hw_params->rx_queues; i++) {
2263                ret = bcmgenet_init_rx_ring(priv, i,
2264                                            priv->hw_params->rx_bds_per_q,
2265                                            i * priv->hw_params->rx_bds_per_q,
2266                                            (i + 1) *
2267                                            priv->hw_params->rx_bds_per_q);
2268                if (ret)
2269                        return ret;
2270
2271                ring_cfg |= (1 << i);
2272                dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2273        }
2274
2275        /* Initialize Rx default queue 16 */
2276        ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2277                                    priv->hw_params->rx_queues *
2278                                    priv->hw_params->rx_bds_per_q,
2279                                    TOTAL_DESC);
2280        if (ret)
2281                return ret;
2282
2283        ring_cfg |= (1 << DESC_INDEX);
2284        dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2285
2286        /* Initialize Rx NAPI */
2287        bcmgenet_init_rx_napi(priv);
2288
2289        /* Enable rings */
2290        bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2291
2292        /* Configure ring as descriptor ring and re-enable DMA if enabled */
2293        if (dma_enable)
2294                dma_ctrl |= DMA_EN;
2295        bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2296
2297        return 0;
2298}
2299
2300static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2301{
2302        int ret = 0;
2303        int timeout = 0;
2304        u32 reg;
2305        u32 dma_ctrl;
2306        int i;
2307
2308        /* Disable TDMA to stop add more frames in TX DMA */
2309        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2310        reg &= ~DMA_EN;
2311        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2312
2313        /* Check TDMA status register to confirm TDMA is disabled */
2314        while (timeout++ < DMA_TIMEOUT_VAL) {
2315                reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2316                if (reg & DMA_DISABLED)
2317                        break;
2318
2319                udelay(1);
2320        }
2321
2322        if (timeout == DMA_TIMEOUT_VAL) {
2323                netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2324                ret = -ETIMEDOUT;
2325        }
2326
2327        /* Wait 10ms for packet drain in both tx and rx dma */
2328        usleep_range(10000, 20000);
2329
2330        /* Disable RDMA */
2331        reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2332        reg &= ~DMA_EN;
2333        bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2334
2335        timeout = 0;
2336        /* Check RDMA status register to confirm RDMA is disabled */
2337        while (timeout++ < DMA_TIMEOUT_VAL) {
2338                reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2339                if (reg & DMA_DISABLED)
2340                        break;
2341
2342                udelay(1);
2343        }
2344
2345        if (timeout == DMA_TIMEOUT_VAL) {
2346                netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2347                ret = -ETIMEDOUT;
2348        }
2349
2350        dma_ctrl = 0;
2351        for (i = 0; i < priv->hw_params->rx_queues; i++)
2352                dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2353        reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2354        reg &= ~dma_ctrl;
2355        bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2356
2357        dma_ctrl = 0;
2358        for (i = 0; i < priv->hw_params->tx_queues; i++)
2359                dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2360        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2361        reg &= ~dma_ctrl;
2362        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2363
2364        return ret;
2365}
2366
2367static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2368{
2369        int i;
2370        struct netdev_queue *txq;
2371
2372        bcmgenet_fini_rx_napi(priv);
2373        bcmgenet_fini_tx_napi(priv);
2374
2375        /* disable DMA */
2376        bcmgenet_dma_teardown(priv);
2377
2378        for (i = 0; i < priv->num_tx_bds; i++) {
2379                if (priv->tx_cbs[i].skb != NULL) {
2380                        dev_kfree_skb(priv->tx_cbs[i].skb);
2381                        priv->tx_cbs[i].skb = NULL;
2382                }
2383        }
2384
2385        for (i = 0; i < priv->hw_params->tx_queues; i++) {
2386                txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[i].queue);
2387                netdev_tx_reset_queue(txq);
2388        }
2389
2390        txq = netdev_get_tx_queue(priv->dev, priv->tx_rings[DESC_INDEX].queue);
2391        netdev_tx_reset_queue(txq);
2392
2393        bcmgenet_free_rx_buffers(priv);
2394        kfree(priv->rx_cbs);
2395        kfree(priv->tx_cbs);
2396}
2397
2398/* init_edma: Initialize DMA control register */
2399static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2400{
2401        int ret;
2402        unsigned int i;
2403        struct enet_cb *cb;
2404
2405        netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2406
2407        /* Initialize common Rx ring structures */
2408        priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2409        priv->num_rx_bds = TOTAL_DESC;
2410        priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2411                               GFP_KERNEL);
2412        if (!priv->rx_cbs)
2413                return -ENOMEM;
2414
2415        for (i = 0; i < priv->num_rx_bds; i++) {
2416                cb = priv->rx_cbs + i;
2417                cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2418        }
2419
2420        /* Initialize common TX ring structures */
2421        priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2422        priv->num_tx_bds = TOTAL_DESC;
2423        priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2424                               GFP_KERNEL);
2425        if (!priv->tx_cbs) {
2426                kfree(priv->rx_cbs);
2427                return -ENOMEM;
2428        }
2429
2430        for (i = 0; i < priv->num_tx_bds; i++) {
2431                cb = priv->tx_cbs + i;
2432                cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2433        }
2434
2435        /* Init rDma */
2436        bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2437
2438        /* Initialize Rx queues */
2439        ret = bcmgenet_init_rx_queues(priv->dev);
2440        if (ret) {
2441                netdev_err(priv->dev, "failed to initialize Rx queues\n");
2442                bcmgenet_free_rx_buffers(priv);
2443                kfree(priv->rx_cbs);
2444                kfree(priv->tx_cbs);
2445                return ret;
2446        }
2447
2448        /* Init tDma */
2449        bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2450
2451        /* Initialize Tx queues */
2452        bcmgenet_init_tx_queues(priv->dev);
2453
2454        return 0;
2455}
2456
2457/* Interrupt bottom half */
2458static void bcmgenet_irq_task(struct work_struct *work)
2459{
2460        struct bcmgenet_priv *priv = container_of(
2461                        work, struct bcmgenet_priv, bcmgenet_irq_work);
2462
2463        netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2464
2465        if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2466                priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2467                netif_dbg(priv, wol, priv->dev,
2468                          "magic packet detected, waking up\n");
2469                bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2470        }
2471
2472        /* Link UP/DOWN event */
2473        if (priv->irq0_stat & UMAC_IRQ_LINK_EVENT) {
2474                phy_mac_interrupt(priv->phydev,
2475                                  !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2476                priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2477        }
2478}
2479
2480/* bcmgenet_isr1: handle Rx and Tx priority queues */
2481static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2482{
2483        struct bcmgenet_priv *priv = dev_id;
2484        struct bcmgenet_rx_ring *rx_ring;
2485        struct bcmgenet_tx_ring *tx_ring;
2486        unsigned int index;
2487
2488        /* Save irq status for bottom-half processing. */
2489        priv->irq1_stat =
2490                bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2491                ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2492
2493        /* clear interrupts */
2494        bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2495
2496        netif_dbg(priv, intr, priv->dev,
2497                  "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2498
2499        /* Check Rx priority queue interrupts */
2500        for (index = 0; index < priv->hw_params->rx_queues; index++) {
2501                if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2502                        continue;
2503
2504                rx_ring = &priv->rx_rings[index];
2505
2506                if (likely(napi_schedule_prep(&rx_ring->napi))) {
2507                        rx_ring->int_disable(rx_ring);
2508                        __napi_schedule_irqoff(&rx_ring->napi);
2509                }
2510        }
2511
2512        /* Check Tx priority queue interrupts */
2513        for (index = 0; index < priv->hw_params->tx_queues; index++) {
2514                if (!(priv->irq1_stat & BIT(index)))
2515                        continue;
2516
2517                tx_ring = &priv->tx_rings[index];
2518
2519                if (likely(napi_schedule_prep(&tx_ring->napi))) {
2520                        tx_ring->int_disable(tx_ring);
2521                        __napi_schedule_irqoff(&tx_ring->napi);
2522                }
2523        }
2524
2525        return IRQ_HANDLED;
2526}
2527
2528/* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2529static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2530{
2531        struct bcmgenet_priv *priv = dev_id;
2532        struct bcmgenet_rx_ring *rx_ring;
2533        struct bcmgenet_tx_ring *tx_ring;
2534
2535        /* Save irq status for bottom-half processing. */
2536        priv->irq0_stat =
2537                bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2538                ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2539
2540        /* clear interrupts */
2541        bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2542
2543        netif_dbg(priv, intr, priv->dev,
2544                  "IRQ=0x%x\n", priv->irq0_stat);
2545
2546        if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2547                rx_ring = &priv->rx_rings[DESC_INDEX];
2548
2549                if (likely(napi_schedule_prep(&rx_ring->napi))) {
2550                        rx_ring->int_disable(rx_ring);
2551                        __napi_schedule_irqoff(&rx_ring->napi);
2552                }
2553        }
2554
2555        if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2556                tx_ring = &priv->tx_rings[DESC_INDEX];
2557
2558                if (likely(napi_schedule_prep(&tx_ring->napi))) {
2559                        tx_ring->int_disable(tx_ring);
2560                        __napi_schedule_irqoff(&tx_ring->napi);
2561                }
2562        }
2563
2564        if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2565                                UMAC_IRQ_PHY_DET_F |
2566                                UMAC_IRQ_LINK_EVENT |
2567                                UMAC_IRQ_HFB_SM |
2568                                UMAC_IRQ_HFB_MM |
2569                                UMAC_IRQ_MPD_R)) {
2570                /* all other interested interrupts handled in bottom half */
2571                schedule_work(&priv->bcmgenet_irq_work);
2572        }
2573
2574        if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2575            priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2576                priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2577                wake_up(&priv->wq);
2578        }
2579
2580        return IRQ_HANDLED;
2581}
2582
2583static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2584{
2585        struct bcmgenet_priv *priv = dev_id;
2586
2587        pm_wakeup_event(&priv->pdev->dev, 0);
2588
2589        return IRQ_HANDLED;
2590}
2591
2592#ifdef CONFIG_NET_POLL_CONTROLLER
2593static void bcmgenet_poll_controller(struct net_device *dev)
2594{
2595        struct bcmgenet_priv *priv = netdev_priv(dev);
2596
2597        /* Invoke the main RX/TX interrupt handler */
2598        disable_irq(priv->irq0);
2599        bcmgenet_isr0(priv->irq0, priv);
2600        enable_irq(priv->irq0);
2601
2602        /* And the interrupt handler for RX/TX priority queues */
2603        disable_irq(priv->irq1);
2604        bcmgenet_isr1(priv->irq1, priv);
2605        enable_irq(priv->irq1);
2606}
2607#endif
2608
2609static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2610{
2611        u32 reg;
2612
2613        reg = bcmgenet_rbuf_ctrl_get(priv);
2614        reg |= BIT(1);
2615        bcmgenet_rbuf_ctrl_set(priv, reg);
2616        udelay(10);
2617
2618        reg &= ~BIT(1);
2619        bcmgenet_rbuf_ctrl_set(priv, reg);
2620        udelay(10);
2621}
2622
2623static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2624                                 unsigned char *addr)
2625{
2626        bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2627                        (addr[2] << 8) | addr[3], UMAC_MAC0);
2628        bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2629}
2630
2631/* Returns a reusable dma control register value */
2632static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2633{
2634        u32 reg;
2635        u32 dma_ctrl;
2636
2637        /* disable DMA */
2638        dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2639        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2640        reg &= ~dma_ctrl;
2641        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2642
2643        reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2644        reg &= ~dma_ctrl;
2645        bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2646
2647        bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2648        udelay(10);
2649        bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2650
2651        return dma_ctrl;
2652}
2653
2654static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2655{
2656        u32 reg;
2657
2658        reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2659        reg |= dma_ctrl;
2660        bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2661
2662        reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2663        reg |= dma_ctrl;
2664        bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2665}
2666
2667/* bcmgenet_hfb_clear
2668 *
2669 * Clear Hardware Filter Block and disable all filtering.
2670 */
2671static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2672{
2673        u32 i;
2674
2675        bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2676        bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2677        bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2678
2679        for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2680                bcmgenet_rdma_writel(priv, 0x0, i);
2681
2682        for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2683                bcmgenet_hfb_reg_writel(priv, 0x0,
2684                                        HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2685
2686        for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2687                        priv->hw_params->hfb_filter_size; i++)
2688                bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2689}
2690
2691static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2692{
2693        if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2694                return;
2695
2696        bcmgenet_hfb_clear(priv);
2697}
2698
2699static void bcmgenet_netif_start(struct net_device *dev)
2700{
2701        struct bcmgenet_priv *priv = netdev_priv(dev);
2702
2703        /* Start the network engine */
2704        bcmgenet_enable_rx_napi(priv);
2705        bcmgenet_enable_tx_napi(priv);
2706
2707        umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2708
2709        netif_tx_start_all_queues(dev);
2710
2711        /* Monitor link interrupts now */
2712        bcmgenet_link_intr_enable(priv);
2713
2714        phy_start(priv->phydev);
2715}
2716
2717static int bcmgenet_open(struct net_device *dev)
2718{
2719        struct bcmgenet_priv *priv = netdev_priv(dev);
2720        unsigned long dma_ctrl;
2721        u32 reg;
2722        int ret;
2723
2724        netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2725
2726        /* Turn on the clock */
2727        clk_prepare_enable(priv->clk);
2728
2729        /* If this is an internal GPHY, power it back on now, before UniMAC is
2730         * brought out of reset as absolutely no UniMAC activity is allowed
2731         */
2732        if (priv->internal_phy)
2733                bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2734
2735        /* take MAC out of reset */
2736        bcmgenet_umac_reset(priv);
2737
2738        ret = init_umac(priv);
2739        if (ret)
2740                goto err_clk_disable;
2741
2742        /* disable ethernet MAC while updating its registers */
2743        umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2744
2745        /* Make sure we reflect the value of CRC_CMD_FWD */
2746        reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2747        priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2748
2749        bcmgenet_set_hw_addr(priv, dev->dev_addr);
2750
2751        if (priv->internal_phy) {
2752                reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2753                reg |= EXT_ENERGY_DET_MASK;
2754                bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2755        }
2756
2757        /* Disable RX/TX DMA and flush TX queues */
2758        dma_ctrl = bcmgenet_dma_disable(priv);
2759
2760        /* Reinitialize TDMA and RDMA and SW housekeeping */
2761        ret = bcmgenet_init_dma(priv);
2762        if (ret) {
2763                netdev_err(dev, "failed to initialize DMA\n");
2764                goto err_clk_disable;
2765        }
2766
2767        /* Always enable ring 16 - descriptor ring */
2768        bcmgenet_enable_dma(priv, dma_ctrl);
2769
2770        /* HFB init */
2771        bcmgenet_hfb_init(priv);
2772
2773        ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2774                          dev->name, priv);
2775        if (ret < 0) {
2776                netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2777                goto err_fini_dma;
2778        }
2779
2780        ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2781                          dev->name, priv);
2782        if (ret < 0) {
2783                netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2784                goto err_irq0;
2785        }
2786
2787        ret = bcmgenet_mii_probe(dev);
2788        if (ret) {
2789                netdev_err(dev, "failed to connect to PHY\n");
2790                goto err_irq1;
2791        }
2792
2793        bcmgenet_netif_start(dev);
2794
2795        return 0;
2796
2797err_irq1:
2798        free_irq(priv->irq1, priv);
2799err_irq0:
2800        free_irq(priv->irq0, priv);
2801err_fini_dma:
2802        bcmgenet_fini_dma(priv);
2803err_clk_disable:
2804        clk_disable_unprepare(priv->clk);
2805        return ret;
2806}
2807
2808static void bcmgenet_netif_stop(struct net_device *dev)
2809{
2810        struct bcmgenet_priv *priv = netdev_priv(dev);
2811
2812        netif_tx_stop_all_queues(dev);
2813        phy_stop(priv->phydev);
2814        bcmgenet_intr_disable(priv);
2815        bcmgenet_disable_rx_napi(priv);
2816        bcmgenet_disable_tx_napi(priv);
2817
2818        /* Wait for pending work items to complete. Since interrupts are
2819         * disabled no new work will be scheduled.
2820         */
2821        cancel_work_sync(&priv->bcmgenet_irq_work);
2822
2823        priv->old_link = -1;
2824        priv->old_speed = -1;
2825        priv->old_duplex = -1;
2826        priv->old_pause = -1;
2827}
2828
2829static int bcmgenet_close(struct net_device *dev)
2830{
2831        struct bcmgenet_priv *priv = netdev_priv(dev);
2832        int ret;
2833
2834        netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2835
2836        bcmgenet_netif_stop(dev);
2837
2838        /* Really kill the PHY state machine and disconnect from it */
2839        phy_disconnect(priv->phydev);
2840
2841        /* Disable MAC receive */
2842        umac_enable_set(priv, CMD_RX_EN, false);
2843
2844        ret = bcmgenet_dma_teardown(priv);
2845        if (ret)
2846                return ret;
2847
2848        /* Disable MAC transmit. TX DMA disabled have to done before this */
2849        umac_enable_set(priv, CMD_TX_EN, false);
2850
2851        /* tx reclaim */
2852        bcmgenet_tx_reclaim_all(dev);
2853        bcmgenet_fini_dma(priv);
2854
2855        free_irq(priv->irq0, priv);
2856        free_irq(priv->irq1, priv);
2857
2858        if (priv->internal_phy)
2859                ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2860
2861        clk_disable_unprepare(priv->clk);
2862
2863        return ret;
2864}
2865
2866static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2867{
2868        struct bcmgenet_priv *priv = ring->priv;
2869        u32 p_index, c_index, intsts, intmsk;
2870        struct netdev_queue *txq;
2871        unsigned int free_bds;
2872        unsigned long flags;
2873        bool txq_stopped;
2874
2875        if (!netif_msg_tx_err(priv))
2876                return;
2877
2878        txq = netdev_get_tx_queue(priv->dev, ring->queue);
2879
2880        spin_lock_irqsave(&ring->lock, flags);
2881        if (ring->index == DESC_INDEX) {
2882                intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2883                intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2884        } else {
2885                intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2886                intmsk = 1 << ring->index;
2887        }
2888        c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2889        p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2890        txq_stopped = netif_tx_queue_stopped(txq);
2891        free_bds = ring->free_bds;
2892        spin_unlock_irqrestore(&ring->lock, flags);
2893
2894        netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2895                  "TX queue status: %s, interrupts: %s\n"
2896                  "(sw)free_bds: %d (sw)size: %d\n"
2897                  "(sw)p_index: %d (hw)p_index: %d\n"
2898                  "(sw)c_index: %d (hw)c_index: %d\n"
2899                  "(sw)clean_p: %d (sw)write_p: %d\n"
2900                  "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2901                  ring->index, ring->queue,
2902                  txq_stopped ? "stopped" : "active",
2903                  intsts & intmsk ? "enabled" : "disabled",
2904                  free_bds, ring->size,
2905                  ring->prod_index, p_index & DMA_P_INDEX_MASK,
2906                  ring->c_index, c_index & DMA_C_INDEX_MASK,
2907                  ring->clean_ptr, ring->write_ptr,
2908                  ring->cb_ptr, ring->end_ptr);
2909}
2910
2911static void bcmgenet_timeout(struct net_device *dev)
2912{
2913        struct bcmgenet_priv *priv = netdev_priv(dev);
2914        u32 int0_enable = 0;
2915        u32 int1_enable = 0;
2916        unsigned int q;
2917
2918        netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2919
2920        for (q = 0; q < priv->hw_params->tx_queues; q++)
2921                bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2922        bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2923
2924        bcmgenet_tx_reclaim_all(dev);
2925
2926        for (q = 0; q < priv->hw_params->tx_queues; q++)
2927                int1_enable |= (1 << q);
2928
2929        int0_enable = UMAC_IRQ_TXDMA_DONE;
2930
2931        /* Re-enable TX interrupts if disabled */
2932        bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2933        bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2934
2935        netif_trans_update(dev);
2936
2937        dev->stats.tx_errors++;
2938
2939        netif_tx_wake_all_queues(dev);
2940}
2941
2942#define MAX_MC_COUNT    16
2943
2944static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2945                                         unsigned char *addr,
2946                                         int *i,
2947                                         int *mc)
2948{
2949        u32 reg;
2950
2951        bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2952                             UMAC_MDF_ADDR + (*i * 4));
2953        bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2954                             addr[4] << 8 | addr[5],
2955                             UMAC_MDF_ADDR + ((*i + 1) * 4));
2956        reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2957        reg |= (1 << (MAX_MC_COUNT - *mc));
2958        bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2959        *i += 2;
2960        (*mc)++;
2961}
2962
2963static void bcmgenet_set_rx_mode(struct net_device *dev)
2964{
2965        struct bcmgenet_priv *priv = netdev_priv(dev);
2966        struct netdev_hw_addr *ha;
2967        int i, mc;
2968        u32 reg;
2969
2970        netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2971
2972        /* Promiscuous mode */
2973        reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2974        if (dev->flags & IFF_PROMISC) {
2975                reg |= CMD_PROMISC;
2976                bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2977                bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2978                return;
2979        } else {
2980                reg &= ~CMD_PROMISC;
2981                bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2982        }
2983
2984        /* UniMac doesn't support ALLMULTI */
2985        if (dev->flags & IFF_ALLMULTI) {
2986                netdev_warn(dev, "ALLMULTI is not supported\n");
2987                return;
2988        }
2989
2990        /* update MDF filter */
2991        i = 0;
2992        mc = 0;
2993        /* Broadcast */
2994        bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2995        /* my own address.*/
2996        bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2997        /* Unicast list*/
2998        if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2999                return;
3000
3001        if (!netdev_uc_empty(dev))
3002                netdev_for_each_uc_addr(ha, dev)
3003                        bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3004        /* Multicast */
3005        if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
3006                return;
3007
3008        netdev_for_each_mc_addr(ha, dev)
3009                bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
3010}
3011
3012/* Set the hardware MAC address. */
3013static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
3014{
3015        struct sockaddr *addr = p;
3016
3017        /* Setting the MAC address at the hardware level is not possible
3018         * without disabling the UniMAC RX/TX enable bits.
3019         */
3020        if (netif_running(dev))
3021                return -EBUSY;
3022
3023        ether_addr_copy(dev->dev_addr, addr->sa_data);
3024
3025        return 0;
3026}
3027
3028static const struct net_device_ops bcmgenet_netdev_ops = {
3029        .ndo_open               = bcmgenet_open,
3030        .ndo_stop               = bcmgenet_close,
3031        .ndo_start_xmit         = bcmgenet_xmit,
3032        .ndo_tx_timeout         = bcmgenet_timeout,
3033        .ndo_set_rx_mode        = bcmgenet_set_rx_mode,
3034        .ndo_set_mac_address    = bcmgenet_set_mac_addr,
3035        .ndo_do_ioctl           = bcmgenet_ioctl,
3036        .ndo_set_features       = bcmgenet_set_features,
3037#ifdef CONFIG_NET_POLL_CONTROLLER
3038        .ndo_poll_controller    = bcmgenet_poll_controller,
3039#endif
3040};
3041
3042/* Array of GENET hardware parameters/characteristics */
3043static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
3044        [GENET_V1] = {
3045                .tx_queues = 0,
3046                .tx_bds_per_q = 0,
3047                .rx_queues = 0,
3048                .rx_bds_per_q = 0,
3049                .bp_in_en_shift = 16,
3050                .bp_in_mask = 0xffff,
3051                .hfb_filter_cnt = 16,
3052                .qtag_mask = 0x1F,
3053                .hfb_offset = 0x1000,
3054                .rdma_offset = 0x2000,
3055                .tdma_offset = 0x3000,
3056                .words_per_bd = 2,
3057        },
3058        [GENET_V2] = {
3059                .tx_queues = 4,
3060                .tx_bds_per_q = 32,
3061                .rx_queues = 0,
3062                .rx_bds_per_q = 0,
3063                .bp_in_en_shift = 16,
3064                .bp_in_mask = 0xffff,
3065                .hfb_filter_cnt = 16,
3066                .qtag_mask = 0x1F,
3067                .tbuf_offset = 0x0600,
3068                .hfb_offset = 0x1000,
3069                .hfb_reg_offset = 0x2000,
3070                .rdma_offset = 0x3000,
3071                .tdma_offset = 0x4000,
3072                .words_per_bd = 2,
3073                .flags = GENET_HAS_EXT,
3074        },
3075        [GENET_V3] = {
3076                .tx_queues = 4,
3077                .tx_bds_per_q = 32,
3078                .rx_queues = 0,
3079                .rx_bds_per_q = 0,
3080                .bp_in_en_shift = 17,
3081                .bp_in_mask = 0x1ffff,
3082                .hfb_filter_cnt = 48,
3083                .hfb_filter_size = 128,
3084                .qtag_mask = 0x3F,
3085                .tbuf_offset = 0x0600,
3086                .hfb_offset = 0x8000,
3087                .hfb_reg_offset = 0xfc00,
3088                .rdma_offset = 0x10000,
3089                .tdma_offset = 0x11000,
3090                .words_per_bd = 2,
3091                .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3092                         GENET_HAS_MOCA_LINK_DET,
3093        },
3094        [GENET_V4] = {
3095                .tx_queues = 4,
3096                .tx_bds_per_q = 32,
3097                .rx_queues = 0,
3098                .rx_bds_per_q = 0,
3099                .bp_in_en_shift = 17,
3100                .bp_in_mask = 0x1ffff,
3101                .hfb_filter_cnt = 48,
3102                .hfb_filter_size = 128,
3103                .qtag_mask = 0x3F,
3104                .tbuf_offset = 0x0600,
3105                .hfb_offset = 0x8000,
3106                .hfb_reg_offset = 0xfc00,
3107                .rdma_offset = 0x2000,
3108                .tdma_offset = 0x4000,
3109                .words_per_bd = 3,
3110                .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3111                         GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3112        },
3113};
3114
3115/* Infer hardware parameters from the detected GENET version */
3116static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3117{
3118        struct bcmgenet_hw_params *params;
3119        u32 reg;
3120        u8 major;
3121        u16 gphy_rev;
3122
3123        if (GENET_IS_V4(priv)) {
3124                bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3125                genet_dma_ring_regs = genet_dma_ring_regs_v4;
3126                priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3127                priv->version = GENET_V4;
3128        } else if (GENET_IS_V3(priv)) {
3129                bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3130                genet_dma_ring_regs = genet_dma_ring_regs_v123;
3131                priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3132                priv->version = GENET_V3;
3133        } else if (GENET_IS_V2(priv)) {
3134                bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3135                genet_dma_ring_regs = genet_dma_ring_regs_v123;
3136                priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3137                priv->version = GENET_V2;
3138        } else if (GENET_IS_V1(priv)) {
3139                bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3140                genet_dma_ring_regs = genet_dma_ring_regs_v123;
3141                priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3142                priv->version = GENET_V1;
3143        }
3144
3145        /* enum genet_version starts at 1 */
3146        priv->hw_params = &bcmgenet_hw_params[priv->version];
3147        params = priv->hw_params;
3148
3149        /* Read GENET HW version */
3150        reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3151        major = (reg >> 24 & 0x0f);
3152        if (major == 5)
3153                major = 4;
3154        else if (major == 0)
3155                major = 1;
3156        if (major != priv->version) {
3157                dev_err(&priv->pdev->dev,
3158                        "GENET version mismatch, got: %d, configured for: %d\n",
3159                        major, priv->version);
3160        }
3161
3162        /* Print the GENET core version */
3163        dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3164                 major, (reg >> 16) & 0x0f, reg & 0xffff);
3165
3166        /* Store the integrated PHY revision for the MDIO probing function
3167         * to pass this information to the PHY driver. The PHY driver expects
3168         * to find the PHY major revision in bits 15:8 while the GENET register
3169         * stores that information in bits 7:0, account for that.
3170         *
3171         * On newer chips, starting with PHY revision G0, a new scheme is
3172         * deployed similar to the Starfighter 2 switch with GPHY major
3173         * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3174         * is reserved as well as special value 0x01ff, we have a small
3175         * heuristic to check for the new GPHY revision and re-arrange things
3176         * so the GPHY driver is happy.
3177         */
3178        gphy_rev = reg & 0xffff;
3179
3180        /* This is the good old scheme, just GPHY major, no minor nor patch */
3181        if ((gphy_rev & 0xf0) != 0)
3182                priv->gphy_rev = gphy_rev << 8;
3183
3184        /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3185        else if ((gphy_rev & 0xff00) != 0)
3186                priv->gphy_rev = gphy_rev;
3187
3188        /* This is reserved so should require special treatment */
3189        else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3190                pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3191                return;
3192        }
3193
3194#ifdef CONFIG_PHYS_ADDR_T_64BIT
3195        if (!(params->flags & GENET_HAS_40BITS))
3196                pr_warn("GENET does not support 40-bits PA\n");
3197#endif
3198
3199        pr_debug("Configuration for version: %d\n"
3200                "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3201                "BP << en: %2d, BP msk: 0x%05x\n"
3202                "HFB count: %2d, QTAQ msk: 0x%05x\n"
3203                "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3204                "RDMA: 0x%05x, TDMA: 0x%05x\n"
3205                "Words/BD: %d\n",
3206                priv->version,
3207                params->tx_queues, params->tx_bds_per_q,
3208                params->rx_queues, params->rx_bds_per_q,
3209                params->bp_in_en_shift, params->bp_in_mask,
3210                params->hfb_filter_cnt, params->qtag_mask,
3211                params->tbuf_offset, params->hfb_offset,
3212                params->hfb_reg_offset,
3213                params->rdma_offset, params->tdma_offset,
3214                params->words_per_bd);
3215}
3216
3217static const struct of_device_id bcmgenet_match[] = {
3218        { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3219        { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3220        { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3221        { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3222        { },
3223};
3224MODULE_DEVICE_TABLE(of, bcmgenet_match);
3225
3226static int bcmgenet_probe(struct platform_device *pdev)
3227{
3228        struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3229        struct device_node *dn = pdev->dev.of_node;
3230        const struct of_device_id *of_id = NULL;
3231        struct bcmgenet_priv *priv;
3232        struct net_device *dev;
3233        const void *macaddr;
3234        struct resource *r;
3235        int err = -EIO;
3236
3237        /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3238        dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3239                                 GENET_MAX_MQ_CNT + 1);
3240        if (!dev) {
3241                dev_err(&pdev->dev, "can't allocate net device\n");
3242                return -ENOMEM;
3243        }
3244
3245        if (dn) {
3246                of_id = of_match_node(bcmgenet_match, dn);
3247                if (!of_id)
3248                        return -EINVAL;
3249        }
3250
3251        priv = netdev_priv(dev);
3252        priv->irq0 = platform_get_irq(pdev, 0);
3253        priv->irq1 = platform_get_irq(pdev, 1);
3254        priv->wol_irq = platform_get_irq(pdev, 2);
3255        if (!priv->irq0 || !priv->irq1) {
3256                dev_err(&pdev->dev, "can't find IRQs\n");
3257                err = -EINVAL;
3258                goto err;
3259        }
3260
3261        if (dn) {
3262                macaddr = of_get_mac_address(dn);
3263                if (!macaddr) {
3264                        dev_err(&pdev->dev, "can't find MAC address\n");
3265                        err = -EINVAL;
3266                        goto err;
3267                }
3268        } else {
3269                macaddr = pd->mac_address;
3270        }
3271
3272        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3273        priv->base = devm_ioremap_resource(&pdev->dev, r);
3274        if (IS_ERR(priv->base)) {
3275                err = PTR_ERR(priv->base);
3276                goto err;
3277        }
3278
3279        SET_NETDEV_DEV(dev, &pdev->dev);
3280        dev_set_drvdata(&pdev->dev, dev);
3281        ether_addr_copy(dev->dev_addr, macaddr);
3282        dev->watchdog_timeo = 2 * HZ;
3283        dev->ethtool_ops = &bcmgenet_ethtool_ops;
3284        dev->netdev_ops = &bcmgenet_netdev_ops;
3285
3286        priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3287
3288        /* Set hardware features */
3289        dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3290                NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3291
3292        /* Request the WOL interrupt and advertise suspend if available */
3293        priv->wol_irq_disabled = true;
3294        err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3295                               dev->name, priv);
3296        if (!err)
3297                device_set_wakeup_capable(&pdev->dev, 1);
3298
3299        /* Set the needed headroom to account for any possible
3300         * features enabling/disabling at runtime
3301         */
3302        dev->needed_headroom += 64;
3303
3304        netdev_boot_setup_check(dev);
3305
3306        priv->dev = dev;
3307        priv->pdev = pdev;
3308        if (of_id)
3309                priv->version = (enum bcmgenet_version)of_id->data;
3310        else
3311                priv->version = pd->genet_version;
3312
3313        priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3314        if (IS_ERR(priv->clk)) {
3315                dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3316                priv->clk = NULL;
3317        }
3318
3319        clk_prepare_enable(priv->clk);
3320
3321        bcmgenet_set_hw_params(priv);
3322
3323        /* Mii wait queue */
3324        init_waitqueue_head(&priv->wq);
3325        /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3326        priv->rx_buf_len = RX_BUF_LENGTH;
3327        INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3328
3329        priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3330        if (IS_ERR(priv->clk_wol)) {
3331                dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3332                priv->clk_wol = NULL;
3333        }
3334
3335        priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3336        if (IS_ERR(priv->clk_eee)) {
3337                dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3338                priv->clk_eee = NULL;
3339        }
3340
3341        err = reset_umac(priv);
3342        if (err)
3343                goto err_clk_disable;
3344
3345        err = bcmgenet_mii_init(dev);
3346        if (err)
3347                goto err_clk_disable;
3348
3349        /* setup number of real queues  + 1 (GENET_V1 has 0 hardware queues
3350         * just the ring 16 descriptor based TX
3351         */
3352        netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3353        netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3354
3355        /* libphy will determine the link state */
3356        netif_carrier_off(dev);
3357
3358        /* Turn off the main clock, WOL clock is handled separately */
3359        clk_disable_unprepare(priv->clk);
3360
3361        err = register_netdev(dev);
3362        if (err)
3363                goto err;
3364
3365        return err;
3366
3367err_clk_disable:
3368        clk_disable_unprepare(priv->clk);
3369err:
3370        free_netdev(dev);
3371        return err;
3372}
3373
3374static int bcmgenet_remove(struct platform_device *pdev)
3375{
3376        struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3377
3378        dev_set_drvdata(&pdev->dev, NULL);
3379        unregister_netdev(priv->dev);
3380        bcmgenet_mii_exit(priv->dev);
3381        free_netdev(priv->dev);
3382
3383        return 0;
3384}
3385
3386#ifdef CONFIG_PM_SLEEP
3387static int bcmgenet_suspend(struct device *d)
3388{
3389        struct net_device *dev = dev_get_drvdata(d);
3390        struct bcmgenet_priv *priv = netdev_priv(dev);
3391        int ret;
3392
3393        if (!netif_running(dev))
3394                return 0;
3395
3396        bcmgenet_netif_stop(dev);
3397
3398        phy_suspend(priv->phydev);
3399
3400        netif_device_detach(dev);
3401
3402        /* Disable MAC receive */
3403        umac_enable_set(priv, CMD_RX_EN, false);
3404
3405        ret = bcmgenet_dma_teardown(priv);
3406        if (ret)
3407                return ret;
3408
3409        /* Disable MAC transmit. TX DMA disabled have to done before this */
3410        umac_enable_set(priv, CMD_TX_EN, false);
3411
3412        /* tx reclaim */
3413        bcmgenet_tx_reclaim_all(dev);
3414        bcmgenet_fini_dma(priv);
3415
3416        /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3417        if (device_may_wakeup(d) && priv->wolopts) {
3418                ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3419                clk_prepare_enable(priv->clk_wol);
3420        } else if (priv->internal_phy) {
3421                ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3422        }
3423
3424        /* Turn off the clocks */
3425        clk_disable_unprepare(priv->clk);
3426
3427        return ret;
3428}
3429
3430static int bcmgenet_resume(struct device *d)
3431{
3432        struct net_device *dev = dev_get_drvdata(d);
3433        struct bcmgenet_priv *priv = netdev_priv(dev);
3434        unsigned long dma_ctrl;
3435        int ret;
3436        u32 reg;
3437
3438        if (!netif_running(dev))
3439                return 0;
3440
3441        /* Turn on the clock */
3442        ret = clk_prepare_enable(priv->clk);
3443        if (ret)
3444                return ret;
3445
3446        /* If this is an internal GPHY, power it back on now, before UniMAC is
3447         * brought out of reset as absolutely no UniMAC activity is allowed
3448         */
3449        if (priv->internal_phy)
3450                bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3451
3452        bcmgenet_umac_reset(priv);
3453
3454        ret = init_umac(priv);
3455        if (ret)
3456                goto out_clk_disable;
3457
3458        /* From WOL-enabled suspend, switch to regular clock */
3459        if (priv->wolopts)
3460                clk_disable_unprepare(priv->clk_wol);
3461
3462        phy_init_hw(priv->phydev);
3463        /* Speed settings must be restored */
3464        bcmgenet_mii_config(priv->dev);
3465
3466        /* disable ethernet MAC while updating its registers */
3467        umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3468
3469        bcmgenet_set_hw_addr(priv, dev->dev_addr);
3470
3471        if (priv->internal_phy) {
3472                reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3473                reg |= EXT_ENERGY_DET_MASK;
3474                bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3475        }
3476
3477        if (priv->wolopts)
3478                bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3479
3480        /* Disable RX/TX DMA and flush TX queues */
3481        dma_ctrl = bcmgenet_dma_disable(priv);
3482
3483        /* Reinitialize TDMA and RDMA and SW housekeeping */
3484        ret = bcmgenet_init_dma(priv);
3485        if (ret) {
3486                netdev_err(dev, "failed to initialize DMA\n");
3487                goto out_clk_disable;
3488        }
3489
3490        /* Always enable ring 16 - descriptor ring */
3491        bcmgenet_enable_dma(priv, dma_ctrl);
3492
3493        netif_device_attach(dev);
3494
3495        phy_resume(priv->phydev);
3496
3497        if (priv->eee.eee_enabled)
3498                bcmgenet_eee_enable_set(dev, true);
3499
3500        bcmgenet_netif_start(dev);
3501
3502        return 0;
3503
3504out_clk_disable:
3505        clk_disable_unprepare(priv->clk);
3506        return ret;
3507}
3508#endif /* CONFIG_PM_SLEEP */
3509
3510static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3511
3512static struct platform_driver bcmgenet_driver = {
3513        .probe  = bcmgenet_probe,
3514        .remove = bcmgenet_remove,
3515        .driver = {
3516                .name   = "bcmgenet",
3517                .of_match_table = bcmgenet_match,
3518                .pm     = &bcmgenet_pm_ops,
3519        },
3520};
3521module_platform_driver(bcmgenet_driver);
3522
3523MODULE_AUTHOR("Broadcom Corporation");
3524MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3525MODULE_ALIAS("platform:bcmgenet");
3526MODULE_LICENSE("GPL");
3527
lxr.linux.no kindly hosted by Redpill Linpro AS, provider of Linux consulting and operations services since 1995.