linux/drivers/net/ethernet/allwinner/sun4i-emac.c
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   1/*
   2 * Allwinner EMAC Fast Ethernet driver for Linux.
   3 *
   4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
   5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
   6 *
   7 * Based on the Linux driver provided by Allwinner:
   8 * Copyright (C) 1997  Sten Wang
   9 *
  10 * This file is licensed under the terms of the GNU General Public
  11 * License version 2. This program is licensed "as is" without any
  12 * warranty of any kind, whether express or implied.
  13 */
  14
  15#include <linux/clk.h>
  16#include <linux/etherdevice.h>
  17#include <linux/ethtool.h>
  18#include <linux/gpio.h>
  19#include <linux/interrupt.h>
  20#include <linux/irq.h>
  21#include <linux/mii.h>
  22#include <linux/module.h>
  23#include <linux/netdevice.h>
  24#include <linux/of_address.h>
  25#include <linux/of_irq.h>
  26#include <linux/of_mdio.h>
  27#include <linux/of_net.h>
  28#include <linux/of_platform.h>
  29#include <linux/platform_device.h>
  30#include <linux/phy.h>
  31#include <linux/soc/sunxi/sunxi_sram.h>
  32
  33#include "sun4i-emac.h"
  34
  35#define DRV_NAME                "sun4i-emac"
  36#define DRV_VERSION             "1.02"
  37
  38#define EMAC_MAX_FRAME_LEN      0x0600
  39
  40/* Transmit timeout, default 5 seconds. */
  41static int watchdog = 5000;
  42module_param(watchdog, int, 0400);
  43MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
  44
  45/* EMAC register address locking.
  46 *
  47 * The EMAC uses an address register to control where data written
  48 * to the data register goes. This means that the address register
  49 * must be preserved over interrupts or similar calls.
  50 *
  51 * During interrupt and other critical calls, a spinlock is used to
  52 * protect the system, but the calls themselves save the address
  53 * in the address register in case they are interrupting another
  54 * access to the device.
  55 *
  56 * For general accesses a lock is provided so that calls which are
  57 * allowed to sleep are serialised so that the address register does
  58 * not need to be saved. This lock also serves to serialise access
  59 * to the EEPROM and PHY access registers which are shared between
  60 * these two devices.
  61 */
  62
  63/* The driver supports the original EMACE, and now the two newer
  64 * devices, EMACA and EMACB.
  65 */
  66
  67struct emac_board_info {
  68        struct clk              *clk;
  69        struct device           *dev;
  70        struct platform_device  *pdev;
  71        spinlock_t              lock;
  72        void __iomem            *membase;
  73        u32                     msg_enable;
  74        struct net_device       *ndev;
  75        struct sk_buff          *skb_last;
  76        u16                     tx_fifo_stat;
  77
  78        int                     emacrx_completed_flag;
  79
  80        struct phy_device       *phy_dev;
  81        struct device_node      *phy_node;
  82        unsigned int            link;
  83        unsigned int            speed;
  84        unsigned int            duplex;
  85
  86        phy_interface_t         phy_interface;
  87};
  88
  89static void emac_update_speed(struct net_device *dev)
  90{
  91        struct emac_board_info *db = netdev_priv(dev);
  92        unsigned int reg_val;
  93
  94        /* set EMAC SPEED, depend on PHY  */
  95        reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
  96        reg_val &= ~(0x1 << 8);
  97        if (db->speed == SPEED_100)
  98                reg_val |= 1 << 8;
  99        writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
 100}
 101
 102static void emac_update_duplex(struct net_device *dev)
 103{
 104        struct emac_board_info *db = netdev_priv(dev);
 105        unsigned int reg_val;
 106
 107        /* set duplex depend on phy */
 108        reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
 109        reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
 110        if (db->duplex)
 111                reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
 112        writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
 113}
 114
 115static void emac_handle_link_change(struct net_device *dev)
 116{
 117        struct emac_board_info *db = netdev_priv(dev);
 118        struct phy_device *phydev = db->phy_dev;
 119        unsigned long flags;
 120        int status_change = 0;
 121
 122        if (phydev->link) {
 123                if (db->speed != phydev->speed) {
 124                        spin_lock_irqsave(&db->lock, flags);
 125                        db->speed = phydev->speed;
 126                        emac_update_speed(dev);
 127                        spin_unlock_irqrestore(&db->lock, flags);
 128                        status_change = 1;
 129                }
 130
 131                if (db->duplex != phydev->duplex) {
 132                        spin_lock_irqsave(&db->lock, flags);
 133                        db->duplex = phydev->duplex;
 134                        emac_update_duplex(dev);
 135                        spin_unlock_irqrestore(&db->lock, flags);
 136                        status_change = 1;
 137                }
 138        }
 139
 140        if (phydev->link != db->link) {
 141                if (!phydev->link) {
 142                        db->speed = 0;
 143                        db->duplex = -1;
 144                }
 145                db->link = phydev->link;
 146
 147                status_change = 1;
 148        }
 149
 150        if (status_change)
 151                phy_print_status(phydev);
 152}
 153
 154static int emac_mdio_probe(struct net_device *dev)
 155{
 156        struct emac_board_info *db = netdev_priv(dev);
 157
 158        /* to-do: PHY interrupts are currently not supported */
 159
 160        /* attach the mac to the phy */
 161        db->phy_dev = of_phy_connect(db->ndev, db->phy_node,
 162                                     &emac_handle_link_change, 0,
 163                                     db->phy_interface);
 164        if (!db->phy_dev) {
 165                netdev_err(db->ndev, "could not find the PHY\n");
 166                return -ENODEV;
 167        }
 168
 169        /* mask with MAC supported features */
 170        db->phy_dev->supported &= PHY_BASIC_FEATURES;
 171        db->phy_dev->advertising = db->phy_dev->supported;
 172
 173        db->link = 0;
 174        db->speed = 0;
 175        db->duplex = -1;
 176
 177        return 0;
 178}
 179
 180static void emac_mdio_remove(struct net_device *dev)
 181{
 182        struct emac_board_info *db = netdev_priv(dev);
 183
 184        phy_disconnect(db->phy_dev);
 185        db->phy_dev = NULL;
 186}
 187
 188static void emac_reset(struct emac_board_info *db)
 189{
 190        dev_dbg(db->dev, "resetting device\n");
 191
 192        /* RESET device */
 193        writel(0, db->membase + EMAC_CTL_REG);
 194        udelay(200);
 195        writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
 196        udelay(200);
 197}
 198
 199static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
 200{
 201        writesl(reg, data, round_up(count, 4) / 4);
 202}
 203
 204static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
 205{
 206        readsl(reg, data, round_up(count, 4) / 4);
 207}
 208
 209static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 210{
 211        struct emac_board_info *dm = netdev_priv(dev);
 212        struct phy_device *phydev = dm->phy_dev;
 213
 214        if (!netif_running(dev))
 215                return -EINVAL;
 216
 217        if (!phydev)
 218                return -ENODEV;
 219
 220        return phy_mii_ioctl(phydev, rq, cmd);
 221}
 222
 223/* ethtool ops */
 224static void emac_get_drvinfo(struct net_device *dev,
 225                              struct ethtool_drvinfo *info)
 226{
 227        strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME));
 228        strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION));
 229        strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
 230}
 231
 232static int emac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 233{
 234        struct emac_board_info *dm = netdev_priv(dev);
 235        struct phy_device *phydev = dm->phy_dev;
 236
 237        if (!phydev)
 238                return -ENODEV;
 239
 240        return phy_ethtool_gset(phydev, cmd);
 241}
 242
 243static int emac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 244{
 245        struct emac_board_info *dm = netdev_priv(dev);
 246        struct phy_device *phydev = dm->phy_dev;
 247
 248        if (!phydev)
 249                return -ENODEV;
 250
 251        return phy_ethtool_sset(phydev, cmd);
 252}
 253
 254static const struct ethtool_ops emac_ethtool_ops = {
 255        .get_drvinfo    = emac_get_drvinfo,
 256        .get_settings   = emac_get_settings,
 257        .set_settings   = emac_set_settings,
 258        .get_link       = ethtool_op_get_link,
 259};
 260
 261static unsigned int emac_setup(struct net_device *ndev)
 262{
 263        struct emac_board_info *db = netdev_priv(ndev);
 264        unsigned int reg_val;
 265
 266        /* set up TX */
 267        reg_val = readl(db->membase + EMAC_TX_MODE_REG);
 268
 269        writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
 270                db->membase + EMAC_TX_MODE_REG);
 271
 272        /* set MAC */
 273        /* set MAC CTL0 */
 274        reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
 275        writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
 276                EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
 277                db->membase + EMAC_MAC_CTL0_REG);
 278
 279        /* set MAC CTL1 */
 280        reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
 281        reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
 282        reg_val |= EMAC_MAC_CTL1_CRC_EN;
 283        reg_val |= EMAC_MAC_CTL1_PAD_EN;
 284        writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
 285
 286        /* set up IPGT */
 287        writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
 288
 289        /* set up IPGR */
 290        writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
 291                db->membase + EMAC_MAC_IPGR_REG);
 292
 293        /* set up Collison window */
 294        writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
 295                db->membase + EMAC_MAC_CLRT_REG);
 296
 297        /* set up Max Frame Length */
 298        writel(EMAC_MAX_FRAME_LEN,
 299                db->membase + EMAC_MAC_MAXF_REG);
 300
 301        return 0;
 302}
 303
 304static void emac_set_rx_mode(struct net_device *ndev)
 305{
 306        struct emac_board_info *db = netdev_priv(ndev);
 307        unsigned int reg_val;
 308
 309        /* set up RX */
 310        reg_val = readl(db->membase + EMAC_RX_CTL_REG);
 311
 312        if (ndev->flags & IFF_PROMISC)
 313                reg_val |= EMAC_RX_CTL_PASS_ALL_EN;
 314        else
 315                reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN;
 316
 317        writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
 318                EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
 319                EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
 320                EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
 321                db->membase + EMAC_RX_CTL_REG);
 322}
 323
 324static unsigned int emac_powerup(struct net_device *ndev)
 325{
 326        struct emac_board_info *db = netdev_priv(ndev);
 327        unsigned int reg_val;
 328
 329        /* initial EMAC */
 330        /* flush RX FIFO */
 331        reg_val = readl(db->membase + EMAC_RX_CTL_REG);
 332        reg_val |= 0x8;
 333        writel(reg_val, db->membase + EMAC_RX_CTL_REG);
 334        udelay(1);
 335
 336        /* initial MAC */
 337        /* soft reset MAC */
 338        reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
 339        reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
 340        writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
 341
 342        /* set MII clock */
 343        reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
 344        reg_val &= (~(0xf << 2));
 345        reg_val |= (0xD << 2);
 346        writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
 347
 348        /* clear RX counter */
 349        writel(0x0, db->membase + EMAC_RX_FBC_REG);
 350
 351        /* disable all interrupt and clear interrupt status */
 352        writel(0, db->membase + EMAC_INT_CTL_REG);
 353        reg_val = readl(db->membase + EMAC_INT_STA_REG);
 354        writel(reg_val, db->membase + EMAC_INT_STA_REG);
 355
 356        udelay(1);
 357
 358        /* set up EMAC */
 359        emac_setup(ndev);
 360
 361        /* set mac_address to chip */
 362        writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
 363               dev_addr[2], db->membase + EMAC_MAC_A1_REG);
 364        writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
 365               dev_addr[5], db->membase + EMAC_MAC_A0_REG);
 366
 367        mdelay(1);
 368
 369        return 0;
 370}
 371
 372static int emac_set_mac_address(struct net_device *dev, void *p)
 373{
 374        struct sockaddr *addr = p;
 375        struct emac_board_info *db = netdev_priv(dev);
 376
 377        if (netif_running(dev))
 378                return -EBUSY;
 379
 380        memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
 381
 382        writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
 383               dev_addr[2], db->membase + EMAC_MAC_A1_REG);
 384        writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
 385               dev_addr[5], db->membase + EMAC_MAC_A0_REG);
 386
 387        return 0;
 388}
 389
 390/* Initialize emac board */
 391static void emac_init_device(struct net_device *dev)
 392{
 393        struct emac_board_info *db = netdev_priv(dev);
 394        unsigned long flags;
 395        unsigned int reg_val;
 396
 397        spin_lock_irqsave(&db->lock, flags);
 398
 399        emac_update_speed(dev);
 400        emac_update_duplex(dev);
 401
 402        /* enable RX/TX */
 403        reg_val = readl(db->membase + EMAC_CTL_REG);
 404        writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
 405                db->membase + EMAC_CTL_REG);
 406
 407        /* enable RX/TX0/RX Hlevel interrup */
 408        reg_val = readl(db->membase + EMAC_INT_CTL_REG);
 409        reg_val |= (0xf << 0) | (0x01 << 8);
 410        writel(reg_val, db->membase + EMAC_INT_CTL_REG);
 411
 412        spin_unlock_irqrestore(&db->lock, flags);
 413}
 414
 415/* Our watchdog timed out. Called by the networking layer */
 416static void emac_timeout(struct net_device *dev)
 417{
 418        struct emac_board_info *db = netdev_priv(dev);
 419        unsigned long flags;
 420
 421        if (netif_msg_timer(db))
 422                dev_err(db->dev, "tx time out.\n");
 423
 424        /* Save previous register address */
 425        spin_lock_irqsave(&db->lock, flags);
 426
 427        netif_stop_queue(dev);
 428        emac_reset(db);
 429        emac_init_device(dev);
 430        /* We can accept TX packets again */
 431        netif_trans_update(dev);
 432        netif_wake_queue(dev);
 433
 434        /* Restore previous register address */
 435        spin_unlock_irqrestore(&db->lock, flags);
 436}
 437
 438/* Hardware start transmission.
 439 * Send a packet to media from the upper layer.
 440 */
 441static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 442{
 443        struct emac_board_info *db = netdev_priv(dev);
 444        unsigned long channel;
 445        unsigned long flags;
 446
 447        channel = db->tx_fifo_stat & 3;
 448        if (channel == 3)
 449                return 1;
 450
 451        channel = (channel == 1 ? 1 : 0);
 452
 453        spin_lock_irqsave(&db->lock, flags);
 454
 455        writel(channel, db->membase + EMAC_TX_INS_REG);
 456
 457        emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
 458                        skb->data, skb->len);
 459        dev->stats.tx_bytes += skb->len;
 460
 461        db->tx_fifo_stat |= 1 << channel;
 462        /* TX control: First packet immediately send, second packet queue */
 463        if (channel == 0) {
 464                /* set TX len */
 465                writel(skb->len, db->membase + EMAC_TX_PL0_REG);
 466                /* start translate from fifo to phy */
 467                writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
 468                       db->membase + EMAC_TX_CTL0_REG);
 469
 470                /* save the time stamp */
 471                netif_trans_update(dev);
 472        } else if (channel == 1) {
 473                /* set TX len */
 474                writel(skb->len, db->membase + EMAC_TX_PL1_REG);
 475                /* start translate from fifo to phy */
 476                writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
 477                       db->membase + EMAC_TX_CTL1_REG);
 478
 479                /* save the time stamp */
 480                netif_trans_update(dev);
 481        }
 482
 483        if ((db->tx_fifo_stat & 3) == 3) {
 484                /* Second packet */
 485                netif_stop_queue(dev);
 486        }
 487
 488        spin_unlock_irqrestore(&db->lock, flags);
 489
 490        /* free this SKB */
 491        dev_consume_skb_any(skb);
 492
 493        return NETDEV_TX_OK;
 494}
 495
 496/* EMAC interrupt handler
 497 * receive the packet to upper layer, free the transmitted packet
 498 */
 499static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
 500                          unsigned int tx_status)
 501{
 502        /* One packet sent complete */
 503        db->tx_fifo_stat &= ~(tx_status & 3);
 504        if (3 == (tx_status & 3))
 505                dev->stats.tx_packets += 2;
 506        else
 507                dev->stats.tx_packets++;
 508
 509        if (netif_msg_tx_done(db))
 510                dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
 511
 512        netif_wake_queue(dev);
 513}
 514
 515/* Received a packet and pass to upper layer
 516 */
 517static void emac_rx(struct net_device *dev)
 518{
 519        struct emac_board_info *db = netdev_priv(dev);
 520        struct sk_buff *skb;
 521        u8 *rdptr;
 522        bool good_packet;
 523        static int rxlen_last;
 524        unsigned int reg_val;
 525        u32 rxhdr, rxstatus, rxcount, rxlen;
 526
 527        /* Check packet ready or not */
 528        while (1) {
 529                /* race warning: the first packet might arrive with
 530                 * the interrupts disabled, but the second will fix
 531                 * it
 532                 */
 533                rxcount = readl(db->membase + EMAC_RX_FBC_REG);
 534
 535                if (netif_msg_rx_status(db))
 536                        dev_dbg(db->dev, "RXCount: %x\n", rxcount);
 537
 538                if ((db->skb_last != NULL) && (rxlen_last > 0)) {
 539                        dev->stats.rx_bytes += rxlen_last;
 540
 541                        /* Pass to upper layer */
 542                        db->skb_last->protocol = eth_type_trans(db->skb_last,
 543                                                                dev);
 544                        netif_rx(db->skb_last);
 545                        dev->stats.rx_packets++;
 546                        db->skb_last = NULL;
 547                        rxlen_last = 0;
 548
 549                        reg_val = readl(db->membase + EMAC_RX_CTL_REG);
 550                        reg_val &= ~EMAC_RX_CTL_DMA_EN;
 551                        writel(reg_val, db->membase + EMAC_RX_CTL_REG);
 552                }
 553
 554                if (!rxcount) {
 555                        db->emacrx_completed_flag = 1;
 556                        reg_val = readl(db->membase + EMAC_INT_CTL_REG);
 557                        reg_val |= (0xf << 0) | (0x01 << 8);
 558                        writel(reg_val, db->membase + EMAC_INT_CTL_REG);
 559
 560                        /* had one stuck? */
 561                        rxcount = readl(db->membase + EMAC_RX_FBC_REG);
 562                        if (!rxcount)
 563                                return;
 564                }
 565
 566                reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
 567                if (netif_msg_rx_status(db))
 568                        dev_dbg(db->dev, "receive header: %x\n", reg_val);
 569                if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
 570                        /* disable RX */
 571                        reg_val = readl(db->membase + EMAC_CTL_REG);
 572                        writel(reg_val & ~EMAC_CTL_RX_EN,
 573                               db->membase + EMAC_CTL_REG);
 574
 575                        /* Flush RX FIFO */
 576                        reg_val = readl(db->membase + EMAC_RX_CTL_REG);
 577                        writel(reg_val | (1 << 3),
 578                               db->membase + EMAC_RX_CTL_REG);
 579
 580                        do {
 581                                reg_val = readl(db->membase + EMAC_RX_CTL_REG);
 582                        } while (reg_val & (1 << 3));
 583
 584                        /* enable RX */
 585                        reg_val = readl(db->membase + EMAC_CTL_REG);
 586                        writel(reg_val | EMAC_CTL_RX_EN,
 587                               db->membase + EMAC_CTL_REG);
 588                        reg_val = readl(db->membase + EMAC_INT_CTL_REG);
 589                        reg_val |= (0xf << 0) | (0x01 << 8);
 590                        writel(reg_val, db->membase + EMAC_INT_CTL_REG);
 591
 592                        db->emacrx_completed_flag = 1;
 593
 594                        return;
 595                }
 596
 597                /* A packet ready now  & Get status/length */
 598                good_packet = true;
 599
 600                emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
 601                                &rxhdr, sizeof(rxhdr));
 602
 603                if (netif_msg_rx_status(db))
 604                        dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
 605
 606                rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
 607                rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
 608
 609                if (netif_msg_rx_status(db))
 610                        dev_dbg(db->dev, "RX: status %02x, length %04x\n",
 611                                rxstatus, rxlen);
 612
 613                /* Packet Status check */
 614                if (rxlen < 0x40) {
 615                        good_packet = false;
 616                        if (netif_msg_rx_err(db))
 617                                dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
 618                }
 619
 620                if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
 621                        good_packet = false;
 622
 623                        if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
 624                                if (netif_msg_rx_err(db))
 625                                        dev_dbg(db->dev, "crc error\n");
 626                                dev->stats.rx_crc_errors++;
 627                        }
 628
 629                        if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
 630                                if (netif_msg_rx_err(db))
 631                                        dev_dbg(db->dev, "length error\n");
 632                                dev->stats.rx_length_errors++;
 633                        }
 634                }
 635
 636                /* Move data from EMAC */
 637                if (good_packet) {
 638                        skb = netdev_alloc_skb(dev, rxlen + 4);
 639                        if (!skb)
 640                                continue;
 641                        skb_reserve(skb, 2);
 642                        rdptr = (u8 *) skb_put(skb, rxlen - 4);
 643
 644                        /* Read received packet from RX SRAM */
 645                        if (netif_msg_rx_status(db))
 646                                dev_dbg(db->dev, "RxLen %x\n", rxlen);
 647
 648                        emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
 649                                        rdptr, rxlen);
 650                        dev->stats.rx_bytes += rxlen;
 651
 652                        /* Pass to upper layer */
 653                        skb->protocol = eth_type_trans(skb, dev);
 654                        netif_rx(skb);
 655                        dev->stats.rx_packets++;
 656                }
 657        }
 658}
 659
 660static irqreturn_t emac_interrupt(int irq, void *dev_id)
 661{
 662        struct net_device *dev = dev_id;
 663        struct emac_board_info *db = netdev_priv(dev);
 664        int int_status;
 665        unsigned long flags;
 666        unsigned int reg_val;
 667
 668        /* A real interrupt coming */
 669
 670        /* holders of db->lock must always block IRQs */
 671        spin_lock_irqsave(&db->lock, flags);
 672
 673        /* Disable all interrupts */
 674        writel(0, db->membase + EMAC_INT_CTL_REG);
 675
 676        /* Got EMAC interrupt status */
 677        /* Got ISR */
 678        int_status = readl(db->membase + EMAC_INT_STA_REG);
 679        /* Clear ISR status */
 680        writel(int_status, db->membase + EMAC_INT_STA_REG);
 681
 682        if (netif_msg_intr(db))
 683                dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
 684
 685        /* Received the coming packet */
 686        if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
 687                /* carrier lost */
 688                db->emacrx_completed_flag = 0;
 689                emac_rx(dev);
 690        }
 691
 692        /* Transmit Interrupt check */
 693        if (int_status & (0x01 | 0x02))
 694                emac_tx_done(dev, db, int_status);
 695
 696        if (int_status & (0x04 | 0x08))
 697                netdev_info(dev, " ab : %x\n", int_status);
 698
 699        /* Re-enable interrupt mask */
 700        if (db->emacrx_completed_flag == 1) {
 701                reg_val = readl(db->membase + EMAC_INT_CTL_REG);
 702                reg_val |= (0xf << 0) | (0x01 << 8);
 703                writel(reg_val, db->membase + EMAC_INT_CTL_REG);
 704        }
 705        spin_unlock_irqrestore(&db->lock, flags);
 706
 707        return IRQ_HANDLED;
 708}
 709
 710#ifdef CONFIG_NET_POLL_CONTROLLER
 711/*
 712 * Used by netconsole
 713 */
 714static void emac_poll_controller(struct net_device *dev)
 715{
 716        disable_irq(dev->irq);
 717        emac_interrupt(dev->irq, dev);
 718        enable_irq(dev->irq);
 719}
 720#endif
 721
 722/*  Open the interface.
 723 *  The interface is opened whenever "ifconfig" actives it.
 724 */
 725static int emac_open(struct net_device *dev)
 726{
 727        struct emac_board_info *db = netdev_priv(dev);
 728        int ret;
 729
 730        if (netif_msg_ifup(db))
 731                dev_dbg(db->dev, "enabling %s\n", dev->name);
 732
 733        if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev))
 734                return -EAGAIN;
 735
 736        /* Initialize EMAC board */
 737        emac_reset(db);
 738        emac_init_device(dev);
 739
 740        ret = emac_mdio_probe(dev);
 741        if (ret < 0) {
 742                free_irq(dev->irq, dev);
 743                netdev_err(dev, "cannot probe MDIO bus\n");
 744                return ret;
 745        }
 746
 747        phy_start(db->phy_dev);
 748        netif_start_queue(dev);
 749
 750        return 0;
 751}
 752
 753static void emac_shutdown(struct net_device *dev)
 754{
 755        unsigned int reg_val;
 756        struct emac_board_info *db = netdev_priv(dev);
 757
 758        /* Disable all interrupt */
 759        writel(0, db->membase + EMAC_INT_CTL_REG);
 760
 761        /* clear interrupt status */
 762        reg_val = readl(db->membase + EMAC_INT_STA_REG);
 763        writel(reg_val, db->membase + EMAC_INT_STA_REG);
 764
 765        /* Disable RX/TX */
 766        reg_val = readl(db->membase + EMAC_CTL_REG);
 767        reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
 768        writel(reg_val, db->membase + EMAC_CTL_REG);
 769}
 770
 771/* Stop the interface.
 772 * The interface is stopped when it is brought.
 773 */
 774static int emac_stop(struct net_device *ndev)
 775{
 776        struct emac_board_info *db = netdev_priv(ndev);
 777
 778        if (netif_msg_ifdown(db))
 779                dev_dbg(db->dev, "shutting down %s\n", ndev->name);
 780
 781        netif_stop_queue(ndev);
 782        netif_carrier_off(ndev);
 783
 784        phy_stop(db->phy_dev);
 785
 786        emac_mdio_remove(ndev);
 787
 788        emac_shutdown(ndev);
 789
 790        free_irq(ndev->irq, ndev);
 791
 792        return 0;
 793}
 794
 795static const struct net_device_ops emac_netdev_ops = {
 796        .ndo_open               = emac_open,
 797        .ndo_stop               = emac_stop,
 798        .ndo_start_xmit         = emac_start_xmit,
 799        .ndo_tx_timeout         = emac_timeout,
 800        .ndo_set_rx_mode        = emac_set_rx_mode,
 801        .ndo_do_ioctl           = emac_ioctl,
 802        .ndo_change_mtu         = eth_change_mtu,
 803        .ndo_validate_addr      = eth_validate_addr,
 804        .ndo_set_mac_address    = emac_set_mac_address,
 805#ifdef CONFIG_NET_POLL_CONTROLLER
 806        .ndo_poll_controller    = emac_poll_controller,
 807#endif
 808};
 809
 810/* Search EMAC board, allocate space and register it
 811 */
 812static int emac_probe(struct platform_device *pdev)
 813{
 814        struct device_node *np = pdev->dev.of_node;
 815        struct emac_board_info *db;
 816        struct net_device *ndev;
 817        int ret = 0;
 818        const char *mac_addr;
 819
 820        ndev = alloc_etherdev(sizeof(struct emac_board_info));
 821        if (!ndev) {
 822                dev_err(&pdev->dev, "could not allocate device.\n");
 823                return -ENOMEM;
 824        }
 825
 826        SET_NETDEV_DEV(ndev, &pdev->dev);
 827
 828        db = netdev_priv(ndev);
 829        memset(db, 0, sizeof(*db));
 830
 831        db->dev = &pdev->dev;
 832        db->ndev = ndev;
 833        db->pdev = pdev;
 834
 835        spin_lock_init(&db->lock);
 836
 837        db->membase = of_iomap(np, 0);
 838        if (!db->membase) {
 839                dev_err(&pdev->dev, "failed to remap registers\n");
 840                ret = -ENOMEM;
 841                goto out;
 842        }
 843
 844        /* fill in parameters for net-dev structure */
 845        ndev->base_addr = (unsigned long)db->membase;
 846        ndev->irq = irq_of_parse_and_map(np, 0);
 847        if (ndev->irq == -ENXIO) {
 848                netdev_err(ndev, "No irq resource\n");
 849                ret = ndev->irq;
 850                goto out_iounmap;
 851        }
 852
 853        db->clk = devm_clk_get(&pdev->dev, NULL);
 854        if (IS_ERR(db->clk)) {
 855                ret = PTR_ERR(db->clk);
 856                goto out_iounmap;
 857        }
 858
 859        ret = clk_prepare_enable(db->clk);
 860        if (ret) {
 861                dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret);
 862                goto out_iounmap;
 863        }
 864
 865        ret = sunxi_sram_claim(&pdev->dev);
 866        if (ret) {
 867                dev_err(&pdev->dev, "Error couldn't map SRAM to device\n");
 868                goto out_clk_disable_unprepare;
 869        }
 870
 871        db->phy_node = of_parse_phandle(np, "phy", 0);
 872        if (!db->phy_node) {
 873                dev_err(&pdev->dev, "no associated PHY\n");
 874                ret = -ENODEV;
 875                goto out_release_sram;
 876        }
 877
 878        /* Read MAC-address from DT */
 879        mac_addr = of_get_mac_address(np);
 880        if (mac_addr)
 881                memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
 882
 883        /* Check if the MAC address is valid, if not get a random one */
 884        if (!is_valid_ether_addr(ndev->dev_addr)) {
 885                eth_hw_addr_random(ndev);
 886                dev_warn(&pdev->dev, "using random MAC address %pM\n",
 887                         ndev->dev_addr);
 888        }
 889
 890        db->emacrx_completed_flag = 1;
 891        emac_powerup(ndev);
 892        emac_reset(db);
 893
 894        ndev->netdev_ops = &emac_netdev_ops;
 895        ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
 896        ndev->ethtool_ops = &emac_ethtool_ops;
 897
 898        platform_set_drvdata(pdev, ndev);
 899
 900        /* Carrier starts down, phylib will bring it up */
 901        netif_carrier_off(ndev);
 902
 903        ret = register_netdev(ndev);
 904        if (ret) {
 905                dev_err(&pdev->dev, "Registering netdev failed!\n");
 906                ret = -ENODEV;
 907                goto out_release_sram;
 908        }
 909
 910        dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
 911                 ndev->name, db->membase, ndev->irq, ndev->dev_addr);
 912
 913        return 0;
 914
 915out_release_sram:
 916        sunxi_sram_release(&pdev->dev);
 917out_clk_disable_unprepare:
 918        clk_disable_unprepare(db->clk);
 919out_iounmap:
 920        iounmap(db->membase);
 921out:
 922        dev_err(db->dev, "not found (%d).\n", ret);
 923
 924        free_netdev(ndev);
 925
 926        return ret;
 927}
 928
 929static int emac_remove(struct platform_device *pdev)
 930{
 931        struct net_device *ndev = platform_get_drvdata(pdev);
 932        struct emac_board_info *db = netdev_priv(ndev);
 933
 934        unregister_netdev(ndev);
 935        sunxi_sram_release(&pdev->dev);
 936        clk_disable_unprepare(db->clk);
 937        iounmap(db->membase);
 938        free_netdev(ndev);
 939
 940        dev_dbg(&pdev->dev, "released and freed device\n");
 941        return 0;
 942}
 943
 944static int emac_suspend(struct platform_device *dev, pm_message_t state)
 945{
 946        struct net_device *ndev = platform_get_drvdata(dev);
 947
 948        netif_carrier_off(ndev);
 949        netif_device_detach(ndev);
 950        emac_shutdown(ndev);
 951
 952        return 0;
 953}
 954
 955static int emac_resume(struct platform_device *dev)
 956{
 957        struct net_device *ndev = platform_get_drvdata(dev);
 958        struct emac_board_info *db = netdev_priv(ndev);
 959
 960        emac_reset(db);
 961        emac_init_device(ndev);
 962        netif_device_attach(ndev);
 963
 964        return 0;
 965}
 966
 967static const struct of_device_id emac_of_match[] = {
 968        {.compatible = "allwinner,sun4i-a10-emac",},
 969
 970        /* Deprecated */
 971        {.compatible = "allwinner,sun4i-emac",},
 972        {},
 973};
 974
 975MODULE_DEVICE_TABLE(of, emac_of_match);
 976
 977static struct platform_driver emac_driver = {
 978        .driver = {
 979                .name = "sun4i-emac",
 980                .of_match_table = emac_of_match,
 981        },
 982        .probe = emac_probe,
 983        .remove = emac_remove,
 984        .suspend = emac_suspend,
 985        .resume = emac_resume,
 986};
 987
 988module_platform_driver(emac_driver);
 989
 990MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
 991MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
 992MODULE_DESCRIPTION("Allwinner A10 emac network driver");
 993MODULE_LICENSE("GPL");
 994
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