linux/drivers/net/can/mscan/mpc5xxx_can.c
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   1/*
   2 * CAN bus driver for the Freescale MPC5xxx embedded CPU.
   3 *
   4 * Copyright (C) 2004-2005 Andrey Volkov <avolkov@varma-el.com>,
   5 *                         Varma Electronics Oy
   6 * Copyright (C) 2008-2009 Wolfgang Grandegger <wg@grandegger.com>
   7 * Copyright (C) 2009 Wolfram Sang, Pengutronix <w.sang@pengutronix.de>
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the version 2 of the GNU General Public License
  11 * as published by the Free Software Foundation
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, see <http://www.gnu.org/licenses/>.
  20 */
  21
  22#include <linux/kernel.h>
  23#include <linux/module.h>
  24#include <linux/interrupt.h>
  25#include <linux/platform_device.h>
  26#include <linux/netdevice.h>
  27#include <linux/can/dev.h>
  28#include <linux/of_platform.h>
  29#include <sysdev/fsl_soc.h>
  30#include <linux/clk.h>
  31#include <linux/io.h>
  32#include <asm/mpc52xx.h>
  33
  34#include "mscan.h"
  35
  36#define DRV_NAME "mpc5xxx_can"
  37
  38struct mpc5xxx_can_data {
  39        unsigned int type;
  40        u32 (*get_clock)(struct platform_device *ofdev, const char *clock_name,
  41                         int *mscan_clksrc);
  42        void (*put_clock)(struct platform_device *ofdev);
  43};
  44
  45#ifdef CONFIG_PPC_MPC52xx
  46static struct of_device_id mpc52xx_cdm_ids[] = {
  47        { .compatible = "fsl,mpc5200-cdm", },
  48        {}
  49};
  50
  51static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
  52                                 const char *clock_name, int *mscan_clksrc)
  53{
  54        unsigned int pvr;
  55        struct mpc52xx_cdm  __iomem *cdm;
  56        struct device_node *np_cdm;
  57        unsigned int freq;
  58        u32 val;
  59
  60        pvr = mfspr(SPRN_PVR);
  61
  62        /*
  63         * Either the oscillator clock (SYS_XTAL_IN) or the IP bus clock
  64         * (IP_CLK) can be selected as MSCAN clock source. According to
  65         * the MPC5200 user's manual, the oscillator clock is the better
  66         * choice as it has less jitter. For this reason, it is selected
  67         * by default. Unfortunately, it can not be selected for the old
  68         * MPC5200 Rev. A chips due to a hardware bug (check errata).
  69         */
  70        if (clock_name && strcmp(clock_name, "ip") == 0)
  71                *mscan_clksrc = MSCAN_CLKSRC_BUS;
  72        else
  73                *mscan_clksrc = MSCAN_CLKSRC_XTAL;
  74
  75        freq = mpc5xxx_get_bus_frequency(ofdev->dev.of_node);
  76        if (!freq)
  77                return 0;
  78
  79        if (*mscan_clksrc == MSCAN_CLKSRC_BUS || pvr == 0x80822011)
  80                return freq;
  81
  82        /* Determine SYS_XTAL_IN frequency from the clock domain settings */
  83        np_cdm = of_find_matching_node(NULL, mpc52xx_cdm_ids);
  84        if (!np_cdm) {
  85                dev_err(&ofdev->dev, "can't get clock node!\n");
  86                return 0;
  87        }
  88        cdm = of_iomap(np_cdm, 0);
  89
  90        if (in_8(&cdm->ipb_clk_sel) & 0x1)
  91                freq *= 2;
  92        val = in_be32(&cdm->rstcfg);
  93
  94        freq *= (val & (1 << 5)) ? 8 : 4;
  95        freq /= (val & (1 << 6)) ? 12 : 16;
  96
  97        of_node_put(np_cdm);
  98        iounmap(cdm);
  99
 100        return freq;
 101}
 102#else /* !CONFIG_PPC_MPC52xx */
 103static u32 mpc52xx_can_get_clock(struct platform_device *ofdev,
 104                                 const char *clock_name, int *mscan_clksrc)
 105{
 106        return 0;
 107}
 108#endif /* CONFIG_PPC_MPC52xx */
 109
 110#ifdef CONFIG_PPC_MPC512x
 111static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
 112                                 const char *clock_source, int *mscan_clksrc)
 113{
 114        struct device_node *np;
 115        u32 clockdiv;
 116        enum {
 117                CLK_FROM_AUTO,
 118                CLK_FROM_IPS,
 119                CLK_FROM_SYS,
 120                CLK_FROM_REF,
 121        } clk_from;
 122        struct clk *clk_in, *clk_can;
 123        unsigned long freq_calc;
 124        struct mscan_priv *priv;
 125        struct clk *clk_ipg;
 126
 127        /* the caller passed in the clock source spec that was read from
 128         * the device tree, get the optional clock divider as well
 129         */
 130        np = ofdev->dev.of_node;
 131        clockdiv = 1;
 132        of_property_read_u32(np, "fsl,mscan-clock-divider", &clockdiv);
 133        dev_dbg(&ofdev->dev, "device tree specs: clk src[%s] div[%d]\n",
 134                clock_source ? clock_source : "<NULL>", clockdiv);
 135
 136        /* when clock-source is 'ip', the CANCTL1[CLKSRC] bit needs to
 137         * get set, and the 'ips' clock is the input to the MSCAN
 138         * component
 139         *
 140         * for clock-source values of 'ref' or 'sys' the CANCTL1[CLKSRC]
 141         * bit needs to get cleared, an optional clock-divider may have
 142         * been specified (the default value is 1), the appropriate
 143         * MSCAN related MCLK is the input to the MSCAN component
 144         *
 145         * in the absence of a clock-source spec, first an optimal clock
 146         * gets determined based on the 'sys' clock, if that fails the
 147         * 'ref' clock is used
 148         */
 149        clk_from = CLK_FROM_AUTO;
 150        if (clock_source) {
 151                /* interpret the device tree's spec for the clock source */
 152                if (!strcmp(clock_source, "ip"))
 153                        clk_from = CLK_FROM_IPS;
 154                else if (!strcmp(clock_source, "sys"))
 155                        clk_from = CLK_FROM_SYS;
 156                else if (!strcmp(clock_source, "ref"))
 157                        clk_from = CLK_FROM_REF;
 158                else
 159                        goto err_invalid;
 160                dev_dbg(&ofdev->dev, "got a clk source spec[%d]\n", clk_from);
 161        }
 162        if (clk_from == CLK_FROM_AUTO) {
 163                /* no spec so far, try the 'sys' clock; round to the
 164                 * next MHz and see if we can get a multiple of 16MHz
 165                 */
 166                dev_dbg(&ofdev->dev, "no clk source spec, trying SYS\n");
 167                clk_in = devm_clk_get(&ofdev->dev, "sys");
 168                if (IS_ERR(clk_in))
 169                        goto err_notavail;
 170                freq_calc = clk_get_rate(clk_in);
 171                freq_calc +=  499999;
 172                freq_calc /= 1000000;
 173                freq_calc *= 1000000;
 174                if ((freq_calc % 16000000) == 0) {
 175                        clk_from = CLK_FROM_SYS;
 176                        clockdiv = freq_calc / 16000000;
 177                        dev_dbg(&ofdev->dev,
 178                                "clk fit, sys[%lu] div[%d] freq[%lu]\n",
 179                                freq_calc, clockdiv, freq_calc / clockdiv);
 180                }
 181        }
 182        if (clk_from == CLK_FROM_AUTO) {
 183                /* no spec so far, use the 'ref' clock */
 184                dev_dbg(&ofdev->dev, "no clk source spec, trying REF\n");
 185                clk_in = devm_clk_get(&ofdev->dev, "ref");
 186                if (IS_ERR(clk_in))
 187                        goto err_notavail;
 188                clk_from = CLK_FROM_REF;
 189                freq_calc = clk_get_rate(clk_in);
 190                dev_dbg(&ofdev->dev,
 191                        "clk fit, ref[%lu] (no div) freq[%lu]\n",
 192                        freq_calc, freq_calc);
 193        }
 194
 195        /* select IPS or MCLK as the MSCAN input (returned to the caller),
 196         * setup the MCLK mux source and rate if applicable, apply the
 197         * optionally specified or derived above divider, and determine
 198         * the actual resulting clock rate to return to the caller
 199         */
 200        switch (clk_from) {
 201        case CLK_FROM_IPS:
 202                clk_can = devm_clk_get(&ofdev->dev, "ips");
 203                if (IS_ERR(clk_can))
 204                        goto err_notavail;
 205                priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 206                priv->clk_can = clk_can;
 207                freq_calc = clk_get_rate(clk_can);
 208                *mscan_clksrc = MSCAN_CLKSRC_IPS;
 209                dev_dbg(&ofdev->dev, "clk from IPS, clksrc[%d] freq[%lu]\n",
 210                        *mscan_clksrc, freq_calc);
 211                break;
 212        case CLK_FROM_SYS:
 213        case CLK_FROM_REF:
 214                clk_can = devm_clk_get(&ofdev->dev, "mclk");
 215                if (IS_ERR(clk_can))
 216                        goto err_notavail;
 217                priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 218                priv->clk_can = clk_can;
 219                if (clk_from == CLK_FROM_SYS)
 220                        clk_in = devm_clk_get(&ofdev->dev, "sys");
 221                if (clk_from == CLK_FROM_REF)
 222                        clk_in = devm_clk_get(&ofdev->dev, "ref");
 223                if (IS_ERR(clk_in))
 224                        goto err_notavail;
 225                clk_set_parent(clk_can, clk_in);
 226                freq_calc = clk_get_rate(clk_in);
 227                freq_calc /= clockdiv;
 228                clk_set_rate(clk_can, freq_calc);
 229                freq_calc = clk_get_rate(clk_can);
 230                *mscan_clksrc = MSCAN_CLKSRC_BUS;
 231                dev_dbg(&ofdev->dev, "clk from MCLK, clksrc[%d] freq[%lu]\n",
 232                        *mscan_clksrc, freq_calc);
 233                break;
 234        default:
 235                goto err_invalid;
 236        }
 237
 238        /* the above clk_can item is used for the bitrate, access to
 239         * the peripheral's register set needs the clk_ipg item
 240         */
 241        clk_ipg = devm_clk_get(&ofdev->dev, "ipg");
 242        if (IS_ERR(clk_ipg))
 243                goto err_notavail_ipg;
 244        if (clk_prepare_enable(clk_ipg))
 245                goto err_notavail_ipg;
 246        priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 247        priv->clk_ipg = clk_ipg;
 248
 249        /* return the determined clock source rate */
 250        return freq_calc;
 251
 252err_invalid:
 253        dev_err(&ofdev->dev, "invalid clock source specification\n");
 254        /* clock source rate could not get determined */
 255        return 0;
 256
 257err_notavail:
 258        dev_err(&ofdev->dev, "cannot acquire or setup bitrate clock source\n");
 259        /* clock source rate could not get determined */
 260        return 0;
 261
 262err_notavail_ipg:
 263        dev_err(&ofdev->dev, "cannot acquire or setup register clock\n");
 264        /* clock source rate could not get determined */
 265        return 0;
 266}
 267
 268static void mpc512x_can_put_clock(struct platform_device *ofdev)
 269{
 270        struct mscan_priv *priv;
 271
 272        priv = netdev_priv(dev_get_drvdata(&ofdev->dev));
 273        if (priv->clk_ipg)
 274                clk_disable_unprepare(priv->clk_ipg);
 275}
 276#else /* !CONFIG_PPC_MPC512x */
 277static u32 mpc512x_can_get_clock(struct platform_device *ofdev,
 278                                 const char *clock_name, int *mscan_clksrc)
 279{
 280        return 0;
 281}
 282#define mpc512x_can_put_clock NULL
 283#endif /* CONFIG_PPC_MPC512x */
 284
 285static const struct of_device_id mpc5xxx_can_table[];
 286static int mpc5xxx_can_probe(struct platform_device *ofdev)
 287{
 288        const struct of_device_id *match;
 289        const struct mpc5xxx_can_data *data;
 290        struct device_node *np = ofdev->dev.of_node;
 291        struct net_device *dev;
 292        struct mscan_priv *priv;
 293        void __iomem *base;
 294        const char *clock_name = NULL;
 295        int irq, mscan_clksrc = 0;
 296        int err = -ENOMEM;
 297
 298        match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
 299        if (!match)
 300                return -EINVAL;
 301        data = match->data;
 302
 303        base = of_iomap(np, 0);
 304        if (!base) {
 305                dev_err(&ofdev->dev, "couldn't ioremap\n");
 306                return err;
 307        }
 308
 309        irq = irq_of_parse_and_map(np, 0);
 310        if (!irq) {
 311                dev_err(&ofdev->dev, "no irq found\n");
 312                err = -ENODEV;
 313                goto exit_unmap_mem;
 314        }
 315
 316        dev = alloc_mscandev();
 317        if (!dev)
 318                goto exit_dispose_irq;
 319        platform_set_drvdata(ofdev, dev);
 320        SET_NETDEV_DEV(dev, &ofdev->dev);
 321
 322        priv = netdev_priv(dev);
 323        priv->reg_base = base;
 324        dev->irq = irq;
 325
 326        clock_name = of_get_property(np, "fsl,mscan-clock-source", NULL);
 327
 328        BUG_ON(!data);
 329        priv->type = data->type;
 330        priv->can.clock.freq = data->get_clock(ofdev, clock_name,
 331                                               &mscan_clksrc);
 332        if (!priv->can.clock.freq) {
 333                dev_err(&ofdev->dev, "couldn't get MSCAN clock properties\n");
 334                goto exit_free_mscan;
 335        }
 336
 337        err = register_mscandev(dev, mscan_clksrc);
 338        if (err) {
 339                dev_err(&ofdev->dev, "registering %s failed (err=%d)\n",
 340                        DRV_NAME, err);
 341                goto exit_free_mscan;
 342        }
 343
 344        dev_info(&ofdev->dev, "MSCAN at 0x%p, irq %d, clock %d Hz\n",
 345                 priv->reg_base, dev->irq, priv->can.clock.freq);
 346
 347        return 0;
 348
 349exit_free_mscan:
 350        free_candev(dev);
 351exit_dispose_irq:
 352        irq_dispose_mapping(irq);
 353exit_unmap_mem:
 354        iounmap(base);
 355
 356        return err;
 357}
 358
 359static int mpc5xxx_can_remove(struct platform_device *ofdev)
 360{
 361        const struct of_device_id *match;
 362        const struct mpc5xxx_can_data *data;
 363        struct net_device *dev = platform_get_drvdata(ofdev);
 364        struct mscan_priv *priv = netdev_priv(dev);
 365
 366        match = of_match_device(mpc5xxx_can_table, &ofdev->dev);
 367        data = match ? match->data : NULL;
 368
 369        unregister_mscandev(dev);
 370        if (data && data->put_clock)
 371                data->put_clock(ofdev);
 372        iounmap(priv->reg_base);
 373        irq_dispose_mapping(dev->irq);
 374        free_candev(dev);
 375
 376        return 0;
 377}
 378
 379#ifdef CONFIG_PM
 380static struct mscan_regs saved_regs;
 381static int mpc5xxx_can_suspend(struct platform_device *ofdev, pm_message_t state)
 382{
 383        struct net_device *dev = platform_get_drvdata(ofdev);
 384        struct mscan_priv *priv = netdev_priv(dev);
 385        struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
 386
 387        _memcpy_fromio(&saved_regs, regs, sizeof(*regs));
 388
 389        return 0;
 390}
 391
 392static int mpc5xxx_can_resume(struct platform_device *ofdev)
 393{
 394        struct net_device *dev = platform_get_drvdata(ofdev);
 395        struct mscan_priv *priv = netdev_priv(dev);
 396        struct mscan_regs *regs = (struct mscan_regs *)priv->reg_base;
 397
 398        regs->canctl0 |= MSCAN_INITRQ;
 399        while (!(regs->canctl1 & MSCAN_INITAK))
 400                udelay(10);
 401
 402        regs->canctl1 = saved_regs.canctl1;
 403        regs->canbtr0 = saved_regs.canbtr0;
 404        regs->canbtr1 = saved_regs.canbtr1;
 405        regs->canidac = saved_regs.canidac;
 406
 407        /* restore masks, buffers etc. */
 408        _memcpy_toio(&regs->canidar1_0, (void *)&saved_regs.canidar1_0,
 409                     sizeof(*regs) - offsetof(struct mscan_regs, canidar1_0));
 410
 411        regs->canctl0 &= ~MSCAN_INITRQ;
 412        regs->cantbsel = saved_regs.cantbsel;
 413        regs->canrier = saved_regs.canrier;
 414        regs->cantier = saved_regs.cantier;
 415        regs->canctl0 = saved_regs.canctl0;
 416
 417        return 0;
 418}
 419#endif
 420
 421static const struct mpc5xxx_can_data mpc5200_can_data = {
 422        .type = MSCAN_TYPE_MPC5200,
 423        .get_clock = mpc52xx_can_get_clock,
 424        /* .put_clock not applicable */
 425};
 426
 427static const struct mpc5xxx_can_data mpc5121_can_data = {
 428        .type = MSCAN_TYPE_MPC5121,
 429        .get_clock = mpc512x_can_get_clock,
 430        .put_clock = mpc512x_can_put_clock,
 431};
 432
 433static const struct of_device_id mpc5xxx_can_table[] = {
 434        { .compatible = "fsl,mpc5200-mscan", .data = &mpc5200_can_data, },
 435        /* Note that only MPC5121 Rev. 2 (and later) is supported */
 436        { .compatible = "fsl,mpc5121-mscan", .data = &mpc5121_can_data, },
 437        {},
 438};
 439MODULE_DEVICE_TABLE(of, mpc5xxx_can_table);
 440
 441static struct platform_driver mpc5xxx_can_driver = {
 442        .driver = {
 443                .name = "mpc5xxx_can",
 444                .owner = THIS_MODULE,
 445                .of_match_table = mpc5xxx_can_table,
 446        },
 447        .probe = mpc5xxx_can_probe,
 448        .remove = mpc5xxx_can_remove,
 449#ifdef CONFIG_PM
 450        .suspend = mpc5xxx_can_suspend,
 451        .resume = mpc5xxx_can_resume,
 452#endif
 453};
 454
 455module_platform_driver(mpc5xxx_can_driver);
 456
 457MODULE_AUTHOR("Wolfgang Grandegger <wg@grandegger.com>");
 458MODULE_DESCRIPTION("Freescale MPC5xxx CAN driver");
 459MODULE_LICENSE("GPL v2");
 460
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